Siemens SAB-C167CR-16RM, SAF-C167CR-16RM, SAK-C167CR-16RM Datasheet

Microcomputer Components

16-Bit CMOS Single-Chip Microcontrollers

C167CR-16RM

Data Sheet 12.96 (Advance Information)

C167CR-16RM
Revision History: Original Version 12.96 (Advance Inf ormation)

Previous Releases: ­Page Subjects (compared to Data Sheet C167CR, 06.95)
21 Incremental Interface Mode added.
22 T3 capture trigger for CAPREL added.

Controller Area Network (CAN): License of Robert Bosch GmbH

Edition 12.96

Published by Siemens AG, Bereich Halbleiter, Marketing-Komm un ikation
Balanstraße 73, D-81541 M ün chen.

© Siemens AG 1996. All Rights Reserved.
As far as patents or other rights of third parties are concerned, liability is only assumed for

components per se, not for applications, processes and circuits implemented within components or
assemblies.

The information describes the type of component and shall not be considered as assured
characteristics.

Terms of delivery a nd rights to change design reserved.
For questions on technology, delivery and prices please contact the Offices of Siemens

Aktiengesellschaft in Germany or the Siemens Companies and Representatives worldwide.
Due to technical requirements components may contain dangerous substances. For information on

the type in question please contact your nearest Siemens Office, Components Group.
Siemens AG is an approved CECC manufacturer.

C16x-Family of

C167CR-16RM

High-Perfo rman ce CMO S 16-Bit Microc on t rolle rs

Advance Information
C167CR-16RM 16-Bit Microcontroller

● High Performance 16-bit CPU with 4-Stage Pipeline

● 100 ns Instruction Cycle Time at 20 MHz CPU Clock

● 500 ns Multiplication (16 × 16 bit), 1 µ s D ivision (32 / 16 bit)

● Enhanced Boolean Bit Manipulation F acilities

● Additional Instructions to Su pport HLL and Oper ating Systems

● Register-Based Design with Multiple Variable Register Banks

● Single-Cycle Context Switching Support

● Clock Generation via on- chip PLL or via direct clock i nput

● Up to 16 MBytes Linear Addres s Space for Code and Data

● 2 KBytes On-Chip Internal RAM (IRAM)

● 2 KBytes On-Chi p Extension RAM (XRAM)

● 128 KBytes On-Chip ROM

● Programmable External Bus Characteristics for Different Address Ranges

● 8-Bit or 16-Bit External Data Bus

● Multiplexed or Dem ultiplexed External Address/Data Buses

● Five Programmable Chip-Select Signals

● Hold- and Hold-Acknowledge Bus Arbitration Support

● 1024 Bytes On-Chip Special F unction Register Area

● Idle and Power Down Modes

● 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event

Controller (PEC)

● 16-Priority-Level Interrupt System with 56 Sourc es, Sample-Rate down to 50 ns

● 16-Channel 10-bit A/D Converter with 9.7µs Conversion Time

● Two 16-Channel Capture/Compare Units

● 4-Channel PWM Unit

● Two Multi-Functional General Purpose Timer Units with 5 Timers

● Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

● On-Chip CAN Inter face with 15 Message Objects (F ull-CAN/Basic-CAN)

● Programmable Watchdog Timer

● Up to 111 General Purpose I/O Lines, partly wi th Selectable Input Thresholds and Hysteresis

● Supported by a Wealt h of Development Tools like C-Com pilers, Macro-Assembler Packages,

Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,
Programming Boards

● On-Chip Bootstrap Loader

● 144-Pin MQFP Package (EIAJ)

This document describes th e SAB-C167CR -16R M and the SAK-C167CR-16RM. For simplicity all
versions are re ferred to by the term C167CR-16RM throughout this document.

1 12.96

C167CR-16RM

Introduction

The C167CR-16RM is a new derivative of the Siemens C16x F amily of full featured singl e-chip
CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per
second) with high peripheral functionality and enhanced IO-capabil ities. It also provides on-chip
ROM, on-chip high-speed RAM and clock generation via PLL.

20Dec96@09:25h Intermediate Version

C167CR-

16RM

Figure 1
Logic Symbol

Ordering Information
Type Ordering Code Package Function

SAB-C167CR-16RM Q67121-D... P-MQFP-144-1 16-bit microcontroller with

2 * 2 KByte RAM
Temperature ran ge 0 to +70 °C

SAF-C167CR-16RM Q67121-D... P-MQFP-144-1 16-bit microcontroller with

2 * 2 KByte RAM
Temperature ran ge -40 to +85 °C

SAK-C167CR-16RM Q67121-D... P-MQFP-144-1 16-bit microcontroller with

2 * 2 KByte RAM
Temperature ran ge -40 to +125 °C

Semiconductor Group 2

20Dec96 @09 :25h In ter med iate Version

C167CR-16RM

Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product

after verifiction of the respective ROM code.

Pin Configuration

(top view)

Figure 2

C167CR-16RM

A22/CAN_TxD

/CAN_RxD

3 Semiconductor Group

C167CR-16RM

Pin Definitions and Functio ns

20Dec96@09:25h Intermediate Version

Symbol Pin

Number

P6.0 –
P6.7

P8.0 –
P8.7

1 ­8

1
...
5
6
7
8

9 ­16

9
...
16

Input (I)
Output (O)

I/O

O
...
O
I
O
O

I/O

I/O
...
I/O

Function

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 6 outputs can be configured as push/
pull or open drain drivers.
The following Port 6 pins also serve for alternate functions:
P6.0 CS0

... ... ...

P6.4 CS4
P6.5 HOLD
P6.6 HLDA
P6.7 BREQ

Port 8 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 8 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 8 is
selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out

... ... ...

P8.7 CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out

Chip Select 0 Output

Chip Select 4 Output
External Master Hold Request Input
Hold Acknowledge Output
Bus Request Output

P7.0 –
P7.7

19 ­26

19
...
22
23
...
26

I/O

O
...
O
I/O
...
I/O

Port 7 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 7 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 7 is
selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
P7.0 POUT0 PWM Channel 0 Output

... ... ...

P7.3 POUT3 PWM Channel 3 Output
P7.4 CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out

... ... ...

P7.7 CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out

Semiconductor Group 4

20Dec96 @09 :25h In ter med iate Version

Pin Definitions and Functio ns (cont’d)

C167CR-16RM

Symbol Pin

Number

P5.0 –
P5.15

P2.0 –
P2.15

27 – 36
39 – 44

39
40
41
42
43
44

47 – 54
57 - 64

47
...
54
57

...
64

Input (I)
Output (O)

I
I

I
I
I
I
I
I

I/O

I/O
...
I/O
I/O
I
...
I/O
I
I

Function

Port 5 is a 16-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serv e as the (up to 16)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog in put channel x), or they serve as timer
inputs:
P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input
P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input
P5.12 T6IN GPT2 Timer T6 Count Input
P5.13 T5IN GPT2 Timer T5 Count Input
P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input
P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input

Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state. Port 2 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 2 is
selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out

... ... ...

P2.7 CC7IO CAPCOM: CC7 Cap.-In/Comp.Out
P2.8 CC8IO CAPCOM: CC8 Cap.-In/Comp.Out,

EX0IN Fast External Interrupt 0 Input

... ... ...

P2.15 CC15IO CAPCOM : CC15 Cap.-In/Comp.Out,

EX7IN Fast External Interrupt 7 Input

T7IN CAPCOM2 Timer T7 Count Input

5 Semiconductor Group

C167CR-16RM

Pin Definitions and Functio ns (cont’d)

20Dec96@09:25h Intermediate Version

Symbol Pin

Number

P3.0 –
P3.13,
P3.15

65 – 70,
73 – 80,
81

65
66
67
68
69
70

73
74

75
76
77
78
79

80
81

Input (I)
Output (O)

I/O
I/O
I/O

I
O
I
O
I
I

I
I

I/O
I/O
O
I/O
O
O
I/O
O

Function

Port 3 is a 15-bit (P3.14 is missing) bidirecti onal I/O port. It is
bit-wise programmable for input or output via direction bits.
For a pin configured as input, the output driver is put into high­impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
P3.0 T0IN CAPCOM Timer T0 Count Input
P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output
P3.2 CAPIN GPT2 Register CAPREL Capture Input
P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output
P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input
P3.5 T4IN GPT1 Timer T4 Input for

Count/Gate/Reload/Capture
P3.6 T3IN GPT1 Timer T3 Count/Gate Input
P3.7 T2IN GPT1 Timer T2 Input for

Count/Gate/Reload/Capture
P3.8 MRST SSC Master-Rec./Slave-Transmit I/O
P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I
P3.10 T×D0 ASC0 Clock/Data Output (Asyn./Syn.)
P3.11 R×D0 ASC0 Data Input (Asyn.) or I/O (Syn.)
P3.12 BHE

WRH
P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp.
P3.15 CLKOUT System Clock Output (=CPU Clock)

Ext. Memory High Byte Enable Signal,
Ext. Memory High Byte Write Strobe

P4.0 –
P4.7

RD

Semiconductor Group 6

85 - 92

85
...
89
90

91

92
95 O External Memory Read Strobe. RD is activated for every

I/O

O
...
O
O
I
O
O
O

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0 A16 Least Significant Segment Addr. Line

... ... ...

P4.4 A20 Segment Address Line
P4.5 A21 Segment Address Line,

CAN_RxD CAN Receive Data Input
P4.6 A22 Segment Address Line,

CAN_TxD CAN Transmit Data Output
P4.7 A23 Most Significant Segment Addr. Li ne

external instruction or data read access.

20Dec96 @09 :25h In ter med iate Version

Pin Definitions and Functio ns (cont’d)

C167CR-16RM

Symbol Pin

Number

WR/
WRL

READY

ALE 98 O Address Latch Enable Output. Can be used for latching the

EA

96 O External Memory Write Strobe. In WR-mode this pin is

97 I Ready Input. When the Ready function is enabled, a high

99 I External Access Enable pin. A low level at this pin during and

Input (I)
Output (O)

Function

activated for every external d ata write access. In WRL
this pin is activated for low byte data write accesses on a 16­bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.

level at this pin duri ng an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.

address into external memory or an address latch in the
multiplexed bus modes.

after Reset forces the C167CR-16RM to begin instruction
execution out of external memory. A high level forces
execution out of the internal ROM. ROMless versions must
have this pin tied to ‘0’.

-mode

PORT0:
P0L.0 –
P0L.7,
P0H.0 ­P0H.7

100 –
107
108,
111-117

I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed bus
modes and as the data (D) bus in dem ultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 - D7
P0H.0 – P0H.7: I/O D8 - D15

Multipl exed bus modes:

Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7: A8 - A15 AD8 - AD15

7 Semiconductor Group

C167CR-16RM

20Dec96@09:25h Intermediate Version

Pin Definitions and Functio ns (cont’d)
Symbol Pin

Number

PORT1:
P1L.0 –
P1L.7,
P1H.0 ­P1H.7

118 –
125
128 –
135

132
133
134
135

XTAL1

XTAL2

138

137

Input (I)
Output (O)

I/O

I
I
I
I

I

O

Function

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after
switching from a demultiplexed bus mode to a multiplexed bus
mode.
The following PORT1 pins also serve for alternate functions:
P1H.4 CC24IO CAPCOM2: CC24 Capture Input
P1H.5 CC25IO CAPCOM2: CC25 Capture Input
P1H.6 CC26IO CAPCOM2: CC26 Capture Input
P1H.7 CC27IO CAPCOM2: CC27 Capture Input

XTAL1: Input to the oscillator amplifier and input to the

internal clock generator
XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC Characteristics
must be observed.

RSTIN

RSTOUT

NMI

V

AREF

V

AGND

V

PP

140 I Reset Input with Schmitt-Trigger characteristics. A low level at

this pin for a specified dur ation while the oscillator is r unning
resets the C167CR-16RM . An internal pullup resistor permits

V

power-on reset using only a capacitor connected to

SS

.

141 O Internal Reset Indication Output. This pi n is set to a low lev el

when the part is executing either a hardware-, a software- or a
watchdog timer reset. RSTOUT

remains low until the EINIT

(end of initialization) instructi on is executed.

142 I Non-Maskable Interrupt Input. A high to low transi tion at this

pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C167CR-16RM to go into
power down mode. If NMI

is high, when PWRDN is executed,
the part will continue to run in normal m ode.
If not used, pin NMI

should be pulled high externally.
37 - Reference voltage for the A/D converter.
38 - Reference ground for the A/D converter.
84 - Flash programming voltage. This pin accepts the

programming voltage for flash versions of the C167CR-16RM.
Note: This pin is not connected (NC) on non-flash versions.

Semiconductor Group 8

20Dec96 @09 :25h In ter med iate Version

Pin Definitions and Functio ns (cont’d)

C167CR-16RM

Symbol Pin

Number

V

CC

17, 46,
56, 72,
82, 93,
109,
126,
136, 144

V

SS

18, 45,
55, 71,
83, 94,
110,
127,
139, 143

Input (I)

Function

Output (O)

- Digital Supply Voltage:
+ 5 V during normal operation and idle m ode.
≥ 2.5 V during power down m ode.

- Digital Ground.

9 Semiconductor Group

C167CR-16RM

Functional Description

The architecture of the C167CR-16RM combines advantages of both RISC and CISC processors
and of advanced peripheral subsystems in a very well-balanced way. The following block diagram
gives an overview of the different on-chip components and of the advanced, high ban dwidth internal
bus structure of the C167CR-16RM .

Note:All time specifications refer to a CPU clock of 20 MHz

(see definition in the AC Characteristics section).

20Dec96@09:25h Intermediate Version

Figure 3
Block Diagram

Semiconductor Group 10

20Dec96 @09 :25h In ter med iate Version

Memory Organization

The memory space of the C167CR-16RM is configured in a Von Neumann architecture which
means that code memory, data memory, r egisters and I/O ports are organized within the same
linear address space which includes 16 MBytes. The entire memory space can be accessed
bytewise or wordwise. Particular portions of the on-chip memory have additionally been made
directly bitaddressable.

The C167CR-16RM contains 128 KBytes of on-chip mask-programmable ROM for code or
constant data. The lower 32 KBytes of the on-chip ROM can be mapped either to segment 0 or
segment 1.

2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the
system stack, general purpose register banks and even for code. A register bank can consist of up
to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose
Registers (GPRs).

1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space a nd ESFR s pace). SF Rs ar e wordw ide regi sters which ar e used for contr olli n g
and monitoring functions of the different on-chip units. Unused SF R addresses are reserv ed for
future members of the C16x family.

C167CR-16RM

2 KBytes of on-chip Extension RAM (XRAM) are provi ded to store user data, user stacks or code.
The XRAM is accessed like external memory and therefore cannot be used for the system stack or
for register banks and is not bitadressable. The XRAM allows 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided on chip, up
to 16 MBytes of external RAM a nd/or RO M can be connected to the microcontroller.

11 Semiconductor Group

C167CR-16RM

External Bus Con troller

All of the external memory accesses are performed by a partic ular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexe d
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on

PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for
input/output.

Important timing char acteristics of the exter nal bus interface (Mem ory Cycle Time, Memory Tri­State Time, Length of ALE an d Read Write Delay) have been made programmable to allow the user
the adaption of a wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx /
BUSCONx) which allow to access different resources with different bus characteristics. These
address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and
BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows
are controlled by BUSCON0.
Up to 5 external CS
logic. Access to very slow memories is supported via a particular ‘Ready’ function.

20Dec96@09:25h Intermediate Version

signals (4 windows plus default) can be generated in order to save external glue

A HOLD
other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSC ON . After
setting HLDEN once, pins P6.7...P6.5 (BREQ
EBC. In Master Mode (default after reset) the HLDA
Slave Mode is selected where pin HLD A
slave controller to another master controller without glue logic.

For applications whic h require less than 16 MBytes of ex ternal memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 8 address lines, if an address s pace of 16 MBytes is used.

Note: When the on-chip CAN Module is to be used the segment address output on Port 4 must be

/HLDA protocol i s available for bus arbitration and allows to share external resources with

, HLDA, HOLD) are automatically controlled by t he

pin is an output. By setting bit DP6.7 to ’1’ the

is switched to input. This allows to directly connect the

limited to 4 bits (ie. A19...A16) in order to enable the alternate function of the CAN interface
pins.

Semiconductor Group 12

20Dec96 @09 :25h In ter med iate Version

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C167CR-16RM’s instructions can be executed in
just one machine cycle which requires 100 ns at 20- MHz CPU clock. For example, shift and rotate
instructions are alw ays pr ocesse d duri ng o ne mac hine cy cle i ndependent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast
as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

C167CR-16RM

Figure 4
CPU Block Diagram

13 Semiconductor Group

C167CR-16RM

The CPU disposes of an actual register context consisting of up to 16 w ordwide GPR s which are
physically allocated w ithin the on-chip RAM area. A Context P ointer (CP) r egister determines the
base address of the active register bank to be acces sed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.

A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack
is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient C167CR-16RM instruction set which includes the following
instruction classes:

– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instr uctions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions

20Dec96@09:25h Intermediate Version

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of di rect, indirect or immedi ate addressing modes are provided to specify the required
operands.

Semiconductor Group 14

20Dec96 @09 :25h In ter med iate Version

Interrupt System

With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal
program execution), the C167CR-16RM is capable of reacting very fast to the occurence of non­deterministic events.

The architecture of the C167CR-16RM supports several mechanisms for fast and flexible response
to service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt s ervice w here the c urrent program execution i s s uspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implic ity decremented for each PEC service excep t
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is perform ed to the corr esponding source r elated vector location. PEC servic es are very
well suited, for example, for supporting the transmission or reception of blocks of data. The
C167CR-16RM has 8 PEC channels each of which offers such fast interrupt-driven data transfer
capabilities.

C167CR-16RM

A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be progr ammed to one of sixteen interrupt prior ity level s. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the poss ible interrupt sources has a dedicated vector
location.

Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling
edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.

The following table shows all of the possible C167CR-16RM interrupt sources and the
corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt)
numbers:

Note: Three nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from

integrated X-Bus peripherals. Nodes , where no X- Peripheral s are c onnecte d, may be use d
to generate software controlled interrupt requests by setting the respective XPnIR bit.

15 Semiconductor Group

C167CR-16RM

20Dec96@09:25h Intermediate Version

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040
CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044
CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048
CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004C
CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050
CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054
CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058
CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005C
CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060
CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064
CAPCOM Regi ster 10 CC10IR CC10IE CC10INT 00’0068
CAPCOM Regi ster 11 CC11IR CC11IE CC11INT 00’006C
CAPCOM Regi ster 12 CC12IR CC12IE CC12INT 00’0070
CAPCOM Regi ster 13 CC13IR CC13IE CC13INT 00’0074
CAPCOM Regi ster 14 CC14IR CC14IE CC14INT 00’0078
CAPCOM Regi ster 15 CC15IR CC15IE CC15INT 00’007C
CAPCOM Regi ster 16 CC16IR CC16IE CC16INT 00’00C0
CAPCOM Regi ster 17 CC17IR CC17IE CC17INT 00’00C4
CAPCOM Regi ster 18 CC18IR CC18IE CC18INT 00’00C8
CAPCOM Regi ster 19 CC19IR CC19IE CC19INT 00’00CC
CAPCOM Regi ster 20 CC20IR CC20IE CC20INT 00’00D0
CAPCOM Regi ster 21 CC21IR CC21IE CC21INT 00’00D4
CAPCOM Regi ster 22 CC22IR CC22IE CC22INT 00’00D8
CAPCOM Regi ster 23 CC23IR CC23IE CC23INT 00’00DC
CAPCOM Regi ster 24 CC24IR CC24IE CC24INT 00’00E0
CAPCOM Regi ster 25 CC25IR CC25IE CC25INT 00’00E4
CAPCOM Regi ster 26 CC26IR CC26IE CC26INT 00’00E8
CAPCOM Regi ster 27 CC27IR CC27IE CC27INT 00’00EC
CAPCOM Regi ster 28 CC28IR CC28IE CC28INT 00’00E0
CAPCOM Regi ster 29 CC29IR CC29IE CC29INT 00’0110
CAPCOM Regi ster 30 CC30IR CC30IE CC30INT 00’0114
CAPCOM Regi ster 31 CC31IR CC31IE CC31INT 00’0118
CAPCOM Timer 0 T0IR T0IE T0INT 00’0080

Trap
Number

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H
H

10

H

11

H

12

H

13

H

H

H

H
H
H
H

H
H
H
H

H
H
H
H

H
H

14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
44
45
46
20

H
H
H
H
H
H
H

H
H

H
H

H
H
H
H
H
H
H
H
H
H
H
H

H

H

H
H
H
H
H

Semiconductor Group 16

20Dec96 @09 :25h In ter med iate Version

C167CR-16RM

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

CAPCOM Timer 1 T1IR T1IE T1INT 00’0084
CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8
GPT1 Timer 2 T2IR T2 IE T2INT 00’0088
GPT1 Timer 3 T3IR T3 IE T3INT 00’008C
GPT1 Timer 4 T4IR T4 IE T4INT 00’0090
GPT2 Timer 5 T5IR T5 IE T5INT 00’0094
GPT2 Timer 6 T6IR T6 IE T6INT 00’0098
GPT2 CAPREL Regis ter CRIR CRIE CRINT 00’009C
A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0
A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C
ASC0 Receive S0RIR S0RIE S0RINT 00’00AC
ASC0 Error S0EIR S0EIE S0EINT 00’00B0
SSC Transmit SCTIR SCTIE SCTINT 00’00B4
SSC Receive SCRIR SCRIE SCRINT 00’00B8
SSC Error SCEIR SCE IE SCEINT 00’00BC
PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FC
CAN Interface XP0IR XP0IE XP0INT 00’0100
X-Peripheral Node XP1IR X P1IE XP1INT 00’0104
X-Peripheral Node XP2IR X P2IE XP2INT 00’0108
PLL Unlock XP3IR XP3IE XP3INT 00’010C

Trap
Number

H

H

H
H
H

H
H
H

21

H

3D

H
H

H

H
H
H
H
H

H
H
H
H

H

H

H

3E
22
23
24
25
26
27
28
29
2A
47
2B
2C
2D
2E
2F
3F
40
41
42
43

H

H
H
H
H
H
H
H
H
H

H
H

H

H
H

H
H
H
H
H
H
H

17 Semiconductor Group

C167CR-16RM

20Dec96@09:25h Intermediate Version

The C167CR-16RM also provides an excellent mechanism to identify and to process exceptions or
error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause
immediate non-maskable system reaction which is similar to a standard interrupt service (branching
to a dedicated vector t able locati on). Th e occur ence of a hardware tr ap is ad ditionally signified by
an individual bit in the trap flag register (TFR). Exce pt when another higher priori tized trap ser vice
is in progress, a hardwar e trap will interrupt any actual pr ogram exec ution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise during run­time:

Exception Condition Trap

Flag

Trap
Vector

Vector
Location

Reset Functions:

Hardware Reset
Software Reset
Watchdog Timer Overflow

RESET
RESET
RESET

00’0000
00’0000
00’0000

Class A Hardware Traps:

Non-Maskable Interrupt
Stack Overflow
Stack Underflow

NMI
STKOF
STKUF

NMITRAP
STOTRAP
STUTRAP

00’0008
00’0010
00’0018

Class B Hardware Traps:

Undefined Opcode
Protected Instruction

UNDOPC
PRTFLT

BTRAP
BTRAP

00’0028

00’0028
Fault
Illegal Word Operand

ILLOPA

BTRAP

00’0028
Access
Illegal Instruction Access
Illegal External Bus

ILLINA
ILLBUS

BTRAP
BTRAP

00’0028

00’0028
Access

Reserved [2C
Software Traps

TRAP Instruction

Any

[00’0000

00’01FC

in steps

of 4

Trap
Number

H
H
H

H
H
H

H
H

H

H
H

– 3CH][0BH – 0FH]

H

00
00
00

02
04
06

0A
0A

0A

0A
0A

H
H
H

H
H
H

H
H

H

H
H

Any

–

H

]

H

H

[00

– 7FH]

H

Trap
Priority

III
III
III

II
II
II

I
I

I

I
I

Current
CPU
Priority

Semiconductor Group 18

20Dec96 @09 :25h In ter med iate Version

Capture/Compare (CAPCOM) Units

The CAPCOM units support generation and control of timing sequences on up to 32 channels with
a maximum resoluti on of 4 00 ns (at 20-MH z sys tem clock) . The CAPC OM units are typic ally use d
to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion, softwar e timing, or time recordin g relative to external
events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the
capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal system
clock, or may be derived from an overflow /underflow of timer T6 in modul e GPT2. Thi s provi des a
wide range of vari ation for the timer period and resoluti on and allows preci se adjustments to the
application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7
allow event scheduling for the capture/compare registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8,
respectively), and programmed for capture or compare function. Each register has one port pin
associated with it which serves as an input pin for triggering the capture function, or as an output pin
(except for CC24...CC27) to indicate the occur ence of a compare event.

C167CR-16RM

When a capture/compare register h as been selected for capture mode, the current contents of the
allocated timer will be latched (‘capture’d) into the capture/compare register in response to an
external event at the port pin which is associ ated with this register . In a ddition, a specific i nterr upt
request for this capture/compare register is generated. Either a positive, a negative, or both a
positive and a negative external signal transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes are
continuously compared with the contents of the allocated timers. When a match occurs between the
timer value and the value in a capture/compare register, specific actions will be taken based on the
selected compare mo de.

Compare Modes Funct ion

Mode 0 Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1 Pin toggles on each compare match;

several compare events per timer period are possible

Mode 2 Interrupt-only compare mode;

only one compare interrupt per timer period is generated

Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double
Register Mode

Two registers operate on one pin; pin toggles on each compare match;
several compare events per timer period are possible.

19 Semiconductor Group