Siemens HYB3164165T-50, HYB3164165T-60, HYB3164165TL-50, HYB3164165TL-60, HYB3165165T-50 Datasheet

4M x 16-Bit Dynamic RAM
(4k & 8k Refresh, EDO-version)

HYB 3164165T(L) -50/-60
HYB 3165165T(L) -50/-60

Preliminary Information

• 4 194 304 words by 16-bit organization

• 0 to 70 ˚C operating temperature

• Fast access and cycle time

RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
84 ns (-50 version)
104 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)

• Hyper page mode (EDO) cycle time

20 ns (-50 version)
25 ns (-60 version)

• Single + 3.3 V (± 0.3V) power supply

• Low power dissipation

max. 396 active mW ( HYB 3164165T(L)-50)
max. 360 active mW ( HYB 3164165T(L)-60)
max. 504 active mW ( HYB 3165165T(L)-50)
max. 432 active mW ( HYB 3165165T(L)-60)

7.2 mW standby (TTL)
720 W standby (MOS)

14.4 mW Self Refresh (L-version only)

• Read, write, read-modify-write, CAS-before-RAS refresh (CBR),

RAS-only refresh, hidden refresh and self refresh modes

• Hyper page mode (EDO) capability

• 2 CAS / 1 WE byte control

• 8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164165T(L))

• 4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165165T(L))

• Plastic Package:

P-TSOPII-54-1 500 mil HYB 3164(5)165T(L)

Semiconductor Group 31

HYB3164(5)165T(L)-50/-60

4M x 16 EDO-DRAM

This HYB3164(5)165 is a 64 MBit dynamic RAM organized 4 194 304 x 16 bits. The device is
fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process
technology. The circuit and process design allow this device to achieve high performance and low
power dissipation. The HYB3164(5)165 operates with a single 3.3 +/-0.3V power supply and
interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the
HYB3164(5)165 to be packaged in a 500mil wide TSOPII-54 plastic package. These packages
provide high system bit densities and are compatible with commonly used automatic testing and
insertion equipment.The HYB3164(5)165TL parts have a very low power „sleep mode“ supported
by Self Refresh.

Ordering Information
Type Ordering

Package Descriptions

Code

HYB 3164165T-50 on request P-TSOPII-54-1 500 mil EDO-DRAM (access time 50 ns)
HYB 3164165T-60 on request P-TSOPII-54-1 500 mil EDO-DRAM (access time 60 ns)
HYB 3164165TL-50 on request P-TSOPII-54-1 500 mil EDO-DRAM (access time 50 ns)
HYB 3164165TL-60 on request P-TSOPII-54-1 500 mil EDO-DRAM (access time 60 ns)
HYB 3165165T-50 on request P-TSOPII-54-1 500 mil EDO-DRAM (access time 50 ns)
HYB 3165165T-60 on request P-TSOPII-54-1 500 mil EDO-DRAM (access time 60 ns)
HYB 3165165TL-50 on request P-TSOPII-54-1 500 mil EDO-DRAM (access time 50 ns)
HYB 3165165TL-60 on request P-TSOPII-54-1 500 mil EDO-DRAM (access time 60 ns)

Pin Names

A0-A12 Address Inputs for HYB 3164165T(L)
A0-A11 Address Inputs for HYB 3165165T(L)
RAS Row Address Strobe
OE Output Enable
I/O1-I/O16 Data Input/Output
UCAS, LCAS Column Address Strobe
WRITE Read/Write Input
Vcc Power Supply ( + 3.3V)
Vss Ground

Semiconductor Group 32

P-TSOPII-54-1 (500 mil)

HYB3164(5)165T(L)-50/-60

4M x 16 EDO-DRAM

* Pin 35 is A12 for HYB 3164165T(L) and N.C. for HYB 3165165T(L)

Pin Configuration

Semiconductor Group 33

TRUTH TABLE

HYB3164(5)165T(L)-50/-60

4M x 16 EDO-DRAM

FUNCTION

Standby
Read:Word
Read:Lower Byte

Read:Upper Byte

Write:Word
(Early-Write)

Write:Lower Byte
(Early-Write)

Write:Upper Byte
(Early Write)

Read-Modify­Write

Hyper Page Mode
Read (Word)

Hyper Page Mode
Read (Word)

1st

Cycle

2nd

Cycle

RAS LCAS UCASWRITEOE ROW

ADD

COL

ADD
H H - X H - X X X X X
L L H H L ROW COL
L L H H L ROW COL

L H L H L ROW COL

L L L L X ROW COL

L L H L X ROW COL

L H L L X ROW COL

L L L H - L L - H ROW COL

L H - L H - L H L ROW COL

L H - L H - L H L n/a COL

I/O1­I/O16

High Impedance
Data Out
Lower Byte:Data Out

Upper-Byte:High-Z
Lower Byte:High-Z

Upper Byte:Data Out
Data In

Lower Byte:Data Out
Upper-Byte:High-Z

Lower Byte:High-Z
Upper Byte:Data Out

Data Out, Data In

Data Out

Data Out

Hyper Page Mode
Early Write(Word)

Hyper Page Mode
Early Write(Word)

Hyper Page Mode
RMW

Hyper Page Mode
RMW

RAS only refresh
CAS-before-RAS

refresh
Test Mode Entry

Hidden Refresh
(Read)

Hidden Refresh
(Write)

Self Refresh
(L-version only)

1st

Cycle

2nd

Cycle

1st

Cycle

2st

Cycle

L H - L H - L L X ROW COL

L H - L H - L L X n/a COL

L H - L H - L H - L L - H ROW COL

L H - L H - L H - L L - H n/a COL

L H H X X ROW n/a
H - L L L H X X n/a

H - L L L L X X n/a
L-H-LL L H L ROW COL

L-H-LL L L X ROW COL

H-L L H X X X X

Data In

Data In

Data Out, Data In

Data Out, Data In

High Impedance
High Impedance

High Impedance
Data Out

Data In

High Impedance

Semiconductor Group 34

HYB3164(5)165T(L)-50/-60

4M x 16 EDO-DRAM

Block Diagram for HYB 3164165T(L)

Semiconductor Group 35

HYB3164(5)165T(L)-50/-60

4M x 16 EDO-DRAM

Block Diagram for HYB 3165165T(L)

Semiconductor Group 36

HYB3164(5)165T(L)-50/-60

4M x 16 EDO-DRAM

Absolute Maximum Ratings

Operating temperature range..............................................................................................0 to 70 ˚C

Storage temperature range.........................................................................................– 55 to 150 ˚C

Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V

Power supply voltage....................................................................................................-0.5V to 4.6 V

Power dissipation......................................................................................................................1.0 W

Data out current (short circuit)..................................................................................................50 mA

Note

Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.

DC Characteristics

T

= 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165165J/T)

A

Parameter Symbol Limit Values Unit Note

min. max.

Input high voltage
Input low voltage
Output high voltage (LVTTL)

V

IH

V

IL

V

OH

2.0 Vcc+0.3 V 1)
– 0.3 0.8 V 1)

2.4 – V

Output „H“ level voltage (Iout = -2mA)
Output low voltage (LVTTL)

V

OL

– 0.4 V

Output „L“level voltage (Iout = +2mA)
Output high voltage (LVCMOS)

V

OH

Vcc-0.2 - V

Output „H“ level voltage (Iout = -100uA)
Ouput low voltage (LVCMOS)

V

OL

- 0.2 V

Output „L“ level voltage (Iout = +100uA)
Input leakage current,any input

(0 V < Vin < Vcc , all other pins = 0 V

Output leakage current

(DO is disabled, 0 V < Vout < Vcc )

I

I

I(L)

O(L)

– 2 2 µA

– 2 2 µA

Average Vcc supply current:

-50 ns version

-60 ns version

(RAS, CAS, address cycling: tRC = tRC min.)

Standby Vcc supply current

(RAS=CAS= Vih)

Semiconductor Group 37

I

I

CC1

CC2

–
–

110 (140)
100 (120)mAmA

– 2 mA –

2) 3) 4)

HYB3164(5)165T(L)-50/-60

4M x 16 EDO-DRAM

DC Characteristics

T

= 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165165J/T)

A

(cont’d)

Parameter Symbol Limit Values Unit Note

min. max.

Average Vcc supply current, during RAS-only
refresh cycles: -50 ns version

-60 ns version

(RAS cycling: CAS = VIH: tRC = tRC min.)

Average Vcc supply current,

Hyper page mode (EDO): -50 ns version

-60 ns version

(RAS = VIL, CAS, address cycling: tHPC=tHPC min.)

Standby Vcc supply current

(RAS=CAS= Vcc-0.2V)

Average Vcc supply current, during

CAS-before-

RAS refresh mode: -50 ns version

-60 ns version

(RAS, CAS cycling: tRC = tRC min.)

Self Refresh Current (L-version only)

Average Power Supply Current during Self Refresh.
(CBR cycle with tRAS>TRASSmin,

WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

CAS held low,

I

I

I

I

I

CC3

CC4

CC5

CC6

CC7

–
–

–
–

110 (140)
100 (120)mAmA

115 (150)
100 (120)mAmA

– 200 A –

–
–

110 (140)
100 (120)mAmA

– 400 A

2) 4)

2) 3) 4)

2) 4)

Capacitance

T

= 0 to 70 ˚C,VCC = 3.3 V ± 0.3 V, f = 1 MHz

A

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A11,A12)
Input capacitance (

RAS, CAS, WRITE, OE) C

I/O capacitance (I/O1-I/O16)

C

I1

I2

C

IO

–5pF
–7pF
–7pF

Semiconductor Group 38

HYB3164(5)165T(L)-50/-60

4M x 16 EDO-DRAM

AC Characteristics

T

= 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns

A

5)6)

Parameter

common parameters

Random read or write cycle time t
RAS precharge time t
RAS pulse width t
CAS pulse width t
Row address setup time t
Row address hold time t
Column address setup time t
Column address hold time t
RAS to CAS delay time t
RAS to column address delay time t
RAS hold time t
CAS hold time t
CAS to RAS precharge time t
Transition time (rise and fall) t
Refresh period for HYB3164165 t
Refresh period for HYB3165165 t

Symbol

RC

RP

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

RSH

CSH

CRP

T

REF

REF

Limit Values

Unit Note

-50 -60

min. max. min. max.

84 – 104 – ns
30 – 40 – ns
50 100k 60 100k ns
8 10k 10 10k ns
0–0– ns
8–10– ns
0–0– ns
8–10– ns
12 37 14 45 ns
10 25 12 30 ns
810–ns
45 50 – ns
5–5– ns
1 50 1 50 ns 7
– 128 – 128 ms
– 64 – 64 ms

Read Cycle

Access time from RAS t
Access time from

CAS t
Access time from column address t
OE access time t
Column address to

RAS lead time t
Read command setup time t
Read command hold time t
Read command hold time referenced to

RAC

CAC

AA

OEA

RAL

RCS

RCH

t

RRH

RAS
CAS to output in low-Z t

CLZ

Semiconductor Group 39

– 50 – 60 ns 8, 9
– 13 – 15 ns 8, 9
– 25 – 30 ns 8,10
– 13 – 15 ns
25 – 30 – ns
0–0– ns
0–0– ns11
0–0– ns11

0–0– ns8