Siemens C515C User Guide

C515C

8-Bit CMOS Microcontroller

User's Manual 10.97

http://www.siemens.de/

Semiconductor/

Edition 10.97 Published by Siemens AG,

Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

Siemens AG 1997.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or

the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components systems

1 A critical component is a component used in a life-support device or system whose failure can reasonably be

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or

with the express written approval of the Semiconductor Group of Siemens AG.

expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or

C515C User’s Manual Revision History : 10.97

Previous Releases : 06.96 (Original Version)

General Information

C515C

Page (new version)

general C515C-8E OTP version included (new chapter 10)

1-1 1-9 Table 1-1 2-2 3-2 3-3, 3-11, 4-4, 6-4, Tab.3-2/3-3 Tab.3-2 / 3-3, pg.9-2 3-17

4-2, 4-5 4-3 4-10 - 4-12 4-11 4-12 6-6 6-10, 6-11 6-18 6-39, 6-43 6-57 6-72 6-105, 6-106 6-108 6-109 7-2 9-6, 9-7 9-7 9-8 9-15 Chapter 10 11-1 11-4 - 11-6

Page (prev. version)

1-1 1-9 Table 1-1 2-2 3-2 3-3, 3-11, 4-4, 6-4, Tab.3-2/3-3 Tab.3-2 / 3-3, pg.9-2 3-17

4-2, 4-5 4-3 4-10 - 4-12 4-11 4-12 6-6 6-10, 6-11 6-18 6-39, 6-43 6-57 6-72 6-105, 6-106 6-108

7-2 9-6, 9-7 9-7 9-8 9-15

10-1 10-3

Subjects (changes since last revision)

C515C AC/DC characteristics are now in chapter 11 Description of the new features of the C515C-8E; figure 1-1 modified

PSEN Ports 1 to 5 and 7 descriptions are corrected to quasi-bidirectional Figure 2-1 modified for C515C-8E Section 3.1 : C515C-8E version included Description of SYSCON : bit CSWO and C515C-8E reset value added

Description of PCON1 : bit WS and C515C-8E reset value added

Reset value of P4 and table entry for bit P7.0 (INT7) corrected; Version registers for C515C-8E added Figure 4-1 and 4-2 corrected 3rd paragraph of chapter 4.1.3 removed Chapter 4.7 “ROM Protection...“ enhanced for OTP verification Figure 4-5 corrected Figure 4-5 : OTP version reference added Figure 6-4 and text : delay part corrected Figures 6-7 and 6-8 : delay part corrected Figure 6-14 corrected Figure 6-22 and 6-26 : figure content exchanged

6.4.3.: first paragraph, divider range corrected Baudrate selection bits corrected multiple formulas corrected

last paragraph added Chapter 6.5.8 (CAN switch-off capability) added Figure 7-1 : bit address for bit RXIE added Adding P4.7/RXDC wake-up capability to the description Figure 9-1 corrected Additional text in last paragraph before 9.5 Note below figure 9-5 added New chapter : describes OTP programming of the C515C-8E Minimum value for ambient temperature under bias corrected to –40˚C Improved and extended Icc specification

and ALE are activated every three (and not six) osc. periods

Semiconductor Group

C515C User’s Manual Revision History (cont’d) : 10.97

Previous Releases : 06.96 (Original Version)

General Information

C515C

Page (new version)

11-10 11-11 11-14 to 11-17

Page (prev. version)

10-8 10-10

Subjects (changes since last revision)

SSC timing parameter

(master mode) and

SCLK

improved

Wrong figure “External Clock Cycle“ exchanged with correct figure Programming interface characteristics added

Semiconductor Group

General Information

C515C

Table of Contents Page

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2 Pin Definitions and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 Data Memory, "Data Space". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.3 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.4 XRAM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4.1 XRAM/CAN Controller Access Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode). . . . . . . . . . . . . . . . 3-5

3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode). . . . . . . . . 3-5

3.4.4 Reset Operation of the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.4.5 Behaviour of Port0 and Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.5 Special Function Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

4 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Accessing External Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.2 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.1.3 External Program Memory Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2 PSEN

4.3 Overlapping External Data and Program Memory Spaces. . . . . . . . . . . . . . . . . . . . 4-3

4.4 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.5 Enhanced Hooks Emulation Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.6 Eight Datapointers for Faster External Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.6.1 The Importance of Additional Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.6.2 How the eight Datapointers of the C515C are realized . . . . . . . . . . . . . . . . . . . . . . 4-6

4.6.3 Advantages of Multiple Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.6.4 Application Example and Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.7 ROM/OTP Protection for the C515C-8R / C515C-8E . . . . . . . . . . . . . . . . . . . . . . 4-10

4.7.1 Unprotected ROM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.7.2 Protected ROM/OTP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

5 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Hardware Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Hardware Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.3 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.4 Oscillator and Clock Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.5 System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

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General Information

C515C

Table of Contents Page

6.1.1.1 Port Structure Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.1.1.2 Quasi-Bidirectional Port Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.1.1.2.1 Basic Port Circuirty of Port 1 to 5 and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.1.1.2.2 Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.1.1.2.3 Port 0 and Port 2 used as Address/Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.1.1.2.4 SSC Port Pins of Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.1.1.3 Bidirectional (CMOS) Port Structure of Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

6.1.1.3.1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

6.1.1.3.2 Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

6.1.1.3.3 Hardware Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

6.1.2 Alternate Functions of Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

6.1.3 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

6.1.3.1 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

6.1.3.2 Port Loading and Interfacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19

6.1.3.3 Read-Modify-Write Feature of Ports 1 to 5 and 7. . . . . . . . . . . . . . . . . . . . . . . . . . 6-19

6.2 Timers/Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

6.2.1 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

6.2.1.1 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

6.2.1.2 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25

6.2.1.3 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26

6.2.1.4 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27

6.2.1.5 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

6.2.2 Timer/Counter 2 with Additional Compare/Capture/Reload . . . . . . . . . . . . . . . . . . 6-29

6.2.2.1 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31

6.2.2.2 Timer 2 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36

6.2.2.3 Compare Function of Registers CRC, CC1 to CC3 . . . . . . . . . . . . . . . . . . . . . . . . 6-38

6.2.2.3.1 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38

6.2.2.3.2 Modulation Range in Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40

6.2.2.3.3 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42

6.2.2.4 Using Interrupts in Combination with the Compare Function . . . . . . . . . . . . . . . . . 6-44

6.2.2.5 Capture Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46

6.3 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48

6.3.1 Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49

6.3.2 Serial Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49

6.3.3 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51

6.3.3.1 Baud Rate in Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52

6.3.3.2 Baud Rate in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52

6.3.3.3 Baud Rate in Mode 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53

6.3.3.3.1 Using the Internal Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53

6.3.3.3.2 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55

6.3.4 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-56

6.3.5 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59

6.3.6 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62

6.4 SSC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65

6.4.1 General Operation of the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66

Semiconductor Group I-2 1997-10-01

General Information

C515C

Table of Contents Page

6.4.2 Enable/Disable Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66

6.4.3 Baudrate Generation (Master Mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67

6.4.4 Write Collision Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67

6.4.5 Master/Slave Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68

6.4.6 Data/Clock Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69

6.4.6.1 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69

6.4.6.2 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70

6.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-71

6.5 The On-Chip CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76

6.5.1 Basic CAN Controller Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-77

6.5.2 CAN Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81

6.5.2.1 General Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81

6.5.2.2 The Message Object Registers / Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91

6.5.3 Handling of Message Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97

6.5.4 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-104

6.5.5 Configuration of the Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-105

6.5.5.1 Hard Synchronization and Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106

6.5.5.2 Calculation of the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106

6.5.6 CAN Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-107

6.5.7 CAN Controller in Power Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-108

6.5.8 Switch-off Capability of the CAN Controller (C515C-8E only) . . . . . . . . . . . . . . . 6-109

6.5.9 Configuration Examples of a Transmission Object. . . . . . . . . . . . . . . . . . . . . . . . 6-110

6.5.10 Configuration Examples of a Reception Object . . . . . . . . . . . . . . . . . . . . . . . . . . 6-111

6.5.11 The CAN Application Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-112

6.6 A/D Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-113

6.6.1 A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-113

6.6.2 A/D Converter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-115

6.6.3 A/D Converter Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-119

6.6.4 A/D Conversion Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-120

6.6.5 A/D Converter Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-124

7 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.1.1 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.1.2 Interrupt Request / Control Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.1.3 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

7.2 Interrupt Priority Level Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

7.3 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

7.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

7.5 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20

8 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1 Programmable Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1.1 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.1.2 Watchdog Timer Control / Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.1.3 Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Semiconductor Group I-3 1997-10-01

General Information

C515C

Table of Contents Page

8.1.3.1 The First Possibility of Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.1.3.2 The Second Possibility of Starting the Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . 8-4

8.1.4 Refreshing the Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.1.5 Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.2 Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

9 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1 Power Saving Mode Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.3 Slow Down Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.4 Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.4.1 Invoking Software Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.4.2 Exit from Software Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.5 State of Pins in Software Initiated Power Saving Modes . . . . . . . . . . . . . . . . . . . . . 9-8

9.6 Hardware Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.7 Hardware Power Down Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11

9.8 CPUR Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15

10 OTP Memory Operation (C515C-8E only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.3 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.4 Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.1 Basic Programming Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.2 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.5 Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

10.6 Lock Bits Programming / Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

10.7 Access of Version Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

11 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.3 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

11.4 AC Characteristics for C515C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

11.5 OTP Memory Programming Mode Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 11-14

11.6 ROM/OTP Verification Characteristics for C515C-8R / C515C-8E . . . . . . . . . . 11-18

11.7 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21

12 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

Semiconductor Group I-4 1997-10-01

Introduction

C515C

1 Introduction

The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller which additionally provides a full CAN interface, a SPI compatible synchronous serial interface, extended power save provisions, additional on-chip RAM, 64K byte of on-chip program memory, two new external interrupts and RFI related improvements. With a maximum external clock rate of 10 MHz it achieves a 600 ns instruction cycle time (1

The C515C-8R contains a non-volatile 64k byte read-only program memory. The C515C-L is identical to the C515C-8R, except that it lacks the on-chip program memory The C515C-8E is the OTP version in the C515C microcontroller with a 64k byte one-time programmable (OTP) program memory. With the C515C-8E fast programming cycles are achieved (1 byte in 100 several levels of OTP memory protection can be selected. If compared to the C515C-8R and C515C-L, the C515C-8E OTP version additionally provides two features :

s at 6 MHz).

sec). Also

– the wake-up from software power down mode can, additionally to the external pin P3.2/INT0

wake-up capability, also be triggered alternatively by a second pin P4.7/RXDC.

– for power consumption reasons the on-chip CAN controller can be switched off

The term C515C refers to all versions within this documentation unless otherwise noted.

Figure 1-1 shows the different functional units of the C515C and figure 1-2 shows the simplified

logic symbol of the C515C.

SSC (SPI)

Interface

Oscillator Watchdog

Power

Save Modes

Idle /

Power down

Slow down

On-Chip Emulation Support Module

Full-CAN

Controller

10-bit ADC

(8 inputs)

Timer 2

Capture/Compare

Unit

Port 4Port 5Port 6Port 7

XRAM

2K × 8

CPU

8 Datapointer

Program Memory

C515C-8R : 64k x 8 ROM

C515C-8E : 64k x 8 OTP

RAM

256 × 8

8-bit USART

Port 0

Port 1

Port 2

Port 3

I/O

Analog /

I/O

Digital

Input

Figure 1-1 C515C Functional Units

Semiconductor Group 1-1 1997-10-01

I/O

Listed below is a summary of the main features of the C515C:

•

Full upward compatibility with SAB 80C515A

•

On-chip program memory (with optional memory protection) – C515C-8R : 64k byte on-chip ROM – C515C-8E : 64k byte on-chip OTP – alternatively up to 64k byte external program memory

•

64k byte on-chip ROM (external program execution is possible)

•

256 byte on-chip RAM

•

2K byte on-chip XRAM

•

Up to 64K byte external data memory

•

Superset of the 8051 architecture with 8 datapointers

•

Up to 10 MHz external operating frequency – without clock prescaler (1

•

On-chip emulation support logic (Enhanced Hooks Technology

•

Current optimized oscillator circuit

•

Eight ports: 48 + 1 digital I/O lines, 8 analog inputs – Quasi-bidirectional port structure (8051 compatible) – Port 5 selectable for bidirectional port structure (CMOS voltage levels)

•

Three 16-bit timer/counters – Timer 2 can be used for compare/capture functions

•

10-bit A/D converter with multiplexed inputs and Built-in self calibration

•

Full duplex serial interface with programmable baudrate generator (USART)

•

SSC synchronous serial interface (SPI compatible) – Master and slave capable – Programmable clock polarity / clock-edge to data phase relation – LSB/MSB first selectable – 1.25 MHz transfer rate at 10 MHz operating frequency Full-CAN Module

•

– 256 register/data bytes are located in external data memory area – max.1 MBaud at 10 MHz operating frequency Seventeen interrupt vectors, at four priority levels selectable

•

Extended watchdog facilities

•

– 15-bit programmable watchdog timer – Oscillator watchdog Power saving modes

•

– Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake-up capability through INT0 – Hardware power-down mode CPU running condition output pin

•

ALE can be switched off

•

Multiple separate VCC/VSS pin pairs

•

P-MQFP-80 package

•

Temperature Ranges: SAB-C515C

•

s instruction cycle time at 6 MHz external clock)

= 0 to 70 ° C

SAF-C515C SAH-C515C

= - 40 to 85 ° C

= - 40 to 110 ° C

)

Introduction

or RXDC pin

C515C

Semiconductor Group 1-2 1997-10-01

Introduction

C515C

Figure 1-2 Logic Symbol

Semiconductor Group 1-3 1997-10-01

Introduction

1.1 Pin Configuration

This section describes the pin configuration of the C515C in the P-MQFP-80 package.

C515C

Figure 1-3 Pin Configuration (top view)

Semiconductor Group 1-4 1997-10-01

1.2 Pin Definitions and Functions

This section describes all external signals of the C515C with its function.

Table 1-1 Pin Deﬁnitions and Functions

)

Symbol Pin Number I/O*

Function

P-MQFP-80

Introduction

C515C

P4.0-P4.7 72-74, 76-80

72 73

74 76 77 78 79 80

I/O Port 4

is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I characteristics) because of the internal pull-up resistors. P4 also contains the external A/D converter control pin, the SSC pins, the CAN controller input/output lines, and the external interrupt 8 input. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The alternate functions are assigned to port 4 as follows: P4.0 ADST External A/D converter start pin P4.1 SCLK SSC Master Clock Output /

P4.2 SRI SSC Receive Input P4.3 STO SSC Transmit Output P4.4 SLS Slave Select Input P4.5 INT8 External interrupt 8 input P4.6 TXDC Transmitter output of the CAN controller P4.7 RXDC Receiver input of the CAN controller

SSC Slave Clock Input

, in the DC

/SWD 75 I Power saving mode enable / Start watchdog timer

A low level on this pin allows the software to enter the power down, idle and slow down mode. In case the low level is also seen during reset, the watchdog timer function is off on default. Use of the software controlled power saving modes is blocked, when this pin is held on high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor.

RESET

1IRESET

A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C515C. A small internal pullup resistor permits power-on reset using only a capacitor connected to VSS.

*) I = Input

O = Output

Semiconductor Group 1-5 1997-10-01

Table 1-1 Pin Deﬁnitions and Functions (cont’d)

Symbol Pin Number I/O*)Function

P-MQFP-80

VAREF 3 – Reference voltage for the A/D converter VAGND 4 – Reference ground for the A/D converter P6.7-P6.0 5-12 I Port 6

is an 8-bit unidirectional input port to the A/D converter. Port pins can be used for digital input, if voltage levels simultaneously meet the specifications high/low input voltages and for the eight multiplexed analog inputs.

Introduction

C515C

P3.0-P3.7 15-22

19 20 21

I/O Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 RXD Receiver data input (asynch.) or

P3.1 TXD Transmitter data output (asynch.) or

P3.2 INT0

P3.3 INT1 External interrupt 1 input / timer 1

P3.4 T0 Timer 0 counter input P3.5 T1 Timer 1 counter input P3.6 WR WR control output; latches the data

P3.7 RD RD control output; enables the

, in the DC

data input/output (synch.) of serial interface

clock output (synch.) of serial interface External interrupt 0 input / timer 0 gate control input

gate control input

byte from port 0 into the external data memory

external data memory

*) I = Input

O = Output

Semiconductor Group 1-6 1997-10-01

Table 1-1 Pin Deﬁnitions and Functions (cont’d)

Symbol Pin Number I/O*)Function

P-MQFP-80

P7.0 23 I/O Port 7

is an 1-bit quasi-bidirectional I/O port with internal pull-up resistor. When a 1 is written to P7.0 it is pulled high by an internal pull-up resistor, and in that state can be used as input. As input, P7.0 being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistor. If P7.0 is used as interrupt input, its output latch must be programmed to a one (1). The secondary function is assigned to the port 7 pin as follows: P7.0 INT7 Interrupt 7 input

Introduction

C515C

P1.0 - P1.7 31-24

27 26

25 24

I/O Port 1

is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I characteristics) because of the internal pullup resistors. The port is used for the low-order address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows: P1.0 INT3

P1.1 INT4 CC1 Interrupt 4 input / compare 1 output /

P1.2 INT5 CC2 Interrupt 5 input / compare 2 output /

P1.3 INT6 CC3 Interrupt 6 input / compare 3 output /

P1.4 INT2 Interrupt 2 input P1.5 T2EX Timer 2 external reload / trigger

P1.6 CLKOUT System clock output P1.7 T2 Counter 2 input

, in the DC

CC0 Interrupt 3 input / compare 0 output /

capture 0 input

capture 1 input

capture 2 input

capture 3 input

input

*) I = Input

O = Output

Semiconductor Group 1-7 1997-10-01

Table 1-1 Pin Deﬁnitions and Functions (cont’d)

Symbol Pin Number I/O*)Function

P-MQFP-80

XTAL2 36 – XTAL2

Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed.

XTAL1 37 – XTAL1

Output of the inverting oscillator amplifier.

Introduction

C515C

P2.0-P2.7 38-45 I/O Port 2

is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register.

CPUR

46 O CPU running condition

This output pin is at low level when the CPU is running and program fetches or data accesses in the external data memory area are executed. In idle mode, hardware and software power down mode, and with an active RESET signal CPUR is set to high level. CPUR can be typically used for switching external memory devices into power saving modes.

, in the DC

*) I = Input

O = Output

Semiconductor Group 1-8 1997-10-01

Table 1-1 Pin Deﬁnitions and Functions (cont’d)

Symbol Pin Number I/O*)Function

P-MQFP-80

PSEN 47 O The Program Store Enable

output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods, except during external data memory accesses. The signal remains high during internal program execution.

ALE 48 O The Address Latch enable

output is used for latching the address into external memory during normal operation. It is activated every three oscillator periods, except during an external data memory access. ALE can be switched off when the program is executed internally.

Introduction

C515C

EA 49 I External Access Enable

When held high, the C515C executes instructions always from internal program memory. When EA is held low, all instructions are fetched from external program memory. EA should not be driven during reset operation

P0.0-P0.7 52-59 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C515C-8E. External pullup resistors are required during program.

P5.7-P5.0 60-67 I/O Port 5

is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (I characteristics) because of the internal pullup resistors. Port 5 can also be switched into a bidirectional mode, in which CMOS levels are provided. In this bidirectional mode, each port 5 pin can be programmed individually as input or output.

, in the DC

*) I = Input

O = Output

Semiconductor Group 1-9 1997-10-01

Table 1-1 Pin Deﬁnitions and Functions (cont’d)

Symbol Pin Number I/O*)Function

P-MQFP-80

Introduction

C515C

HWPD

VCC1 33 – Supply voltage for internal logic

VSS1 34 – Ground (0 V) for internal logic

VCCE1 VCCE2

VSSE1 VSSE2

VCCEXT 50 – Supply voltage for external access pins

69 I Hardware Power Down

A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C515C. A low level for a longer period will force the part to power down mode with the pins floating.

This pins is used for the power supply of the internal logic circuits during normal, idle, and power down mode.

This pin is used for the ground connection of the internal logic circuits during normal, idle, and power down mode.

32 68

35 70

– Supply voltage for I/O ports

These pins are used for power supply of the I/O ports during normal, idle, and power-down mode.

– Ground (0 V) for I/O ports

These pins are used for ground connections of the I/O ports during normal, idle, and power-down mode.

This pin is used for power supply of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN

, P3.6/WR, and P3.7/RD).

VSSEXT 51 – Ground (0 V) for external access pins

This pin is used for the ground connection of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN P3.7/RD).

VCCCLK 14 – Supply voltage for on-chip oscillator

This pin is used for power supply of the on-chip oscillator circuit.

VSSCLK 13 – Ground (0 V) for on-chip oscillator

This pin is used for ground connection of the on-chip oscillator circuit.

N.C. 2, 71 – Not connected

These pins should not be connected.

*) I = Input

O = Output

Semiconductor Group 1-10 1997-10-01

, P3.6/WR, and

Fundamental Structure

C515C

2 Fundamental Structure

The C515C is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining all architectural and operational characteristics of the C501, the C515C incorporates a CPU with 8 datapointers, a genuine 10-bit A/D converter, a capture/compare unit, a Full-CAN controller unit, a SSC synchronous serial interface, a USART serial interface, a XRAM data memory as well as some enhancements in the Fail Save Mechanism Unit. Figure 2-1 shows a block diagram of the C515C.

Semiconductor Group 2-1 1997-10-01

C515C

Fundamental Structure

C515C

XTAL1 XTAL2

ALE

PSEN

CPUR

PE/SWD

HWPD

RESET

Oscillator Watchdog

OSC & Timing

CPU

8 Datapointers

Programmable

Watchdog Timer

Timer 0

Timer 1

Timer 2

Capture/Compare

Unit

XRAM

2k x 8

RAM

256 x 8

ROM/

OTP

64k x 8

Emulation

Support

Logic

Port 0

Port 1

Port 2

multiple

Vcc/Vss Lines

Port 0 8-bit digit. I/O

Port 1

8-bit digit. I/O

Port 2 8-bit digit. I/O

USART

Baud Rate Generator

SSC (SPI) Interface

Full-CAN

Controller

Interrupt Unit

AGND

AREF

A/D Converter

10-Bit

S&H

MUX

Figure 2-1 Block Diagram of the C515C

256 Byte

Reg./Data

Port 3

Port 4

Port 5

Port 7

Port 6

Port 3

8-bit digit. I/O

Port 4 8-bit digit. I/O

Port 5 8-bit digit. I/O

Port 7

1-bit digit. I/O

Port 6 8-bit analog / digital Input

Semiconductor Group 2-2 1997-10-01

Fundamental Structure

C515C

2.1 CPU

The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 6 MHz external clock, 58% of the instructions execute in 1.0 µs (10 MHz: 600 ns).

The CPU (Central Processing Unit) of the C515C consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing.

The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register.

The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jumpif-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag.

The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence.

Additionally to the CPU functionality of the C501/8051 standard microcontroller, the C515C contains 8 datapointers. For complex applications with peripherals located in the external data memory space (e.g. CAN controller) or extended data storage capacity this turned out to be a "bottle neck" for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages.

Accumulator

ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A.

Program Status Word

The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU.

Semiconductor Group 2-3 1997-10-01

Fundamental Structure

C515C

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

CY AC

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations. F0 General Purpose Flag RS1

RS0

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07 0 1 Bank 1 selected, data address 08H-0F 1 0 Bank 2 selected, data address 10H-17 1 1 Bank 3 selected, data address 18H-1F

PSW

OV Overflow Flag

Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

B Register

The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register.

Stack Pointer

The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control.

Semiconductor Group 2-4 1997-10-01

Fundamental Structure

C515C

2.2 CPU Timing

The C515C has no clock prescaler. Therefore, a machine cycle of the C515C consists of 6 states (6 oscillator periods). Each state is divided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 6 oscillator periods, numbered S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts one oscillator period. Typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2.

The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL1 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1.

Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2.

Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction.

Semiconductor Group 2-5 1997-10-01

Fundamental Structure

C515C

Figure 2-2 Fetch Execute Sequence

Semiconductor Group 2-6 1997-10-01

Memory Organization

3 Memory Organization

The C515C CPU manipulates operands in the following four address spaces:

– up to 64 Kbyte of internal/external program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – 256 bytes CAN controller registers / data memory – 2K bytes of internal XRAM data memory – a 128 byte special function register area

Figure 3-1 illustrates the memory address spaces of the C515C.

C515C

Figure 3-1 C515C Memory Map

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Memory Organization

C515C

3.1 Program Memory, "Code Space"

The C515C-8R provides 64 Kbytes of read-only program memory while the C515C-L has no internal program memory. The C515C-8E provides 64 Kbytes of OTP program memory.. For internal ROM/OTP program execution the EA pin must be put to high level. The 64K bytes program memory can also be located completely external. If the EA pin is held low, the C515C fetches all instructions from an external program memory.

3.2 Data Memory, "Data Space"

The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes.

The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address. The internal CAN controller and the internal XRAM are located in the external address memory area at addresses F700H to FFFFH. Using MOVX instruction with addresses pointing to this address area, alternatively XRAM and CAN controller registers or external XRAM are accessed.

3.3 General Purpose Registers

The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines.

The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0).

Reset initializes the stack pointer to location 07H and increments it once to start from location 08 which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage.

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Memory Organization

C515C

3.4 XRAM Operation

The XRAM in the C515C is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM.

3.4.1 XRAM/CAN Controller Access Control

Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to XRAM and the CAN controller. XMAP0 is a general access enable/disable control bit and XMAP1 controls the external signal generation during XRAM/CAN controller accesses.

Special Function Register SYSCON (Address B1H) Reset Value C515C-8R : X010XX01 Reset Value C515C-8E : X010X001

Bit No. MSB LSB

76543210

Bit Function

– Not implemented. Reserved for future use. XMAP1 XRAM/CAN controller visible access control

– PMOD

The function of the shaded bit is not described in this section.

Control bit for RD addresses are outside the XRAM/CAN controller address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0 : The signals RD and WR are not activated during accesses to

XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during

EALE RMAP –

/WR signals during XRAM/CAN Controller accesses. If

the XRAM/CAN Controller

accesses to XRAM/CAN Controller. In this mode, address and data information during XRAM/CAN Controller accesses are visible externally.

CSWO XMAP1

XMAP0

SYSCON

B B

XMAP0 Global XRAM/CAN controller access enable/disable control

XMAP0 = 0 : The access to XRAM and CAN controller is enabled. XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default

after reset!). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected.

When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM and CAN Controller RD and WR become active and port 0 and 2 drive the actual address/data information which is read/written from/to XRAM or CAN controller. This feature allows to check the internal data transfers to XRAM and CAN controller. When port 0 and 2 are used for I/O purposes, the XMAP1 bit should not be set. Otherwise the I/O function of the port 0 and port 2 lines is interrupted.

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Memory Organization

C515C

After a reset operation, bit XMAP0 is reset. This means that the accesses to XRAM and CAN controller are generally disabled. In this case, all accesses using MOVX instructions within the address range of F700H to FFFFH generate external data memory bus cycles. When XMAP0 is set, the access to XRAM and CAN controller is enabled and all accesses using MOVX instructions with an address in the range of F700H to FFFFH will access internal XRAM or CAN controller.

Bit XMAP0 is hardware protected. If it is reset once (XRAM and CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again. This hardware protection mechanism is done by an unsymmetric latch at XMAP0 bit. A unintentional disabling of XRAM and CAN controller could be dangerous since indeterminate values could be read from the external bus. To avoid this the XMAP0 bit is forced to '1' only by a reset operation. Additionally, during reset an internal capacitor is loaded. So the reset state is a disabled XRAM and CAN controller. Because of the load time of the capacitor, XMAP0 bit once written to '0' (that is, discharging the capacitor) cannot be set to '1' again by software. On the other hand any distortion (software hang up, noise,...) is not able to load this capacitor, too. That is, the stable status is XRAM and CAN controller enabled.

The clear instruction for the XMAP0 bit should be integrated in the program initialization routine before XRAM or CAN controller is used. In extremely noisy systems the user may have redundant clear instructions.

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Memory Organization

C515C

3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode)

The XRAM and CAN controller can be accessed by two read/write instructions, which use the 16bit DPTR for indirect addressing. These instructions are :

– MOVX A, @DPTR (Read) – MOVX @DPTR, A (Write)

For accessing the XRAM, the effective address stored in DPTR must be in the range of F800H to FFFFH. For accessing the CAN controller, the effective address stored in DPTR must be in the range of F700H to F7FFH.

3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode)

The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are:

MOVX A, @ Ri (Read) MOVX @Ri, A (Write)

As in the SAB 80C515A a special page register is implemented into the C515C to provide the possibility of accessing the XRAM or CAN controller also with the MOVX @Ri instructions, i.e. XPAGE serves the same function for the XRAM and CAN controller as Port 2 for external data memory.

Special Function Register XPAGE (Address 91H) Reset Value : 00

Bit No. MSB LSB

76543210

Bit Function

XPAGE.7-0 XRAM/CAN controller high address

XPAGE.7-0 is the address part A15-A8 when 8-bit MOVX instructions are used to access internal XRAM or CAN controller.

.5 .4 .3

.2 .1.7 .6 .0

XPAGE

Figures 3-2 to 3-4 show the dependencies of XPAGE- and Port 2 - addressing in order to explain

the differences in accessing XRAM/CAN controller, ext. RAM or what is to do when Port 2 is used as an I/O-port.

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Memory Organization

C515C

Port 0

XRAM

CAN-Controller

XPAGE

Write to

Port 2

Port 2 Page Address

Address/Data

MCS02761

Figure 3-2 Write Page Address to Port 2

“MOV P2,pageaddress“ will write the page address to Port 2 and the XPAGE-Register. When external RAM is to be accessed in the XRAM/CAN controller address range (F700H -

FFFFH), the XRAM/CAN controller has to be disabled. When additional external RAM is to be addressed in an address range < F700H, the XRAM/CAN controller may remain enabled and there is no need to overwrite XPAGE by a second move.

Semiconductor Group 3-6 1997-10-01

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