Siemens C504 User Guide

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C504

8-Bit CMOS Microcontroller

User's Manual 10.97

http://www.siemens.de/

Semiconductor/

Edition 1997-10-01

This edition was realized using the software system FrameMaker



Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

Siemens AG 1997.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or

the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components systems

with the express written approval of the Semiconductor Group of Siemens AG.

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or

1 A critical component is a component used in a life-support device or system whose failure can reasonably be

expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or

maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

C504 Data Sheet Revision History : 1997-10-01

Previous Releases : 06.96 (Original Version)

General Information

C504

Page (new version)

Page (prev. version)

Subjects (changes since last revision)

general C504-2E OTP version included (new chapter 10)

C504-2E AC/DC characteristics are now in chapter 11

1-1 1-4 1-6 2-1 3-3, 3-4 3-11 3-85-2 4-6 to 4-8 5-4 5-6, 5-7 6-7

1-1 1-4 1-6 2-1 4-6, 4-7 – 5-1 4-8 to 4-10 5-3 – 6-7

Figure 1-1 completed Figure 1-3 completed RESET pin desc. : “..for the duration of two machine cycl...“ corrected Figure 2-1 completed Chapter 3.4 “XRAM Operation“ moved from chapter 4 to chapter 3 Version register information added Figure 5-2 “Reset Circuitries“ added

Chapter 4.6/4.7 “ROM Protection ....“ enhanced for OTP verification

Figure 5-3/5-2 corrected Chapter 5.4 “Oscillator and Clock Circuit“ added Figure 6-5 corrected; modified sentence : “During this time, the P2

SFR remains unchanged while the P0 SFR has 1’s written to it.“ – 6-8

6-8 6-9

Figure 6-6 added

Figure 6-6/6-7 corrected; also text in paragraph “The pullup FET p1

of...“ 2nd sentence modified : “activated for one state...“ 6-14 6-18 6-26 6-33 6-36 6-42 6-41 6-45 6-50 6-51 6-52 6-58 6-70 Ch.6.3.4 6-80, 6-81 7-3 7-14 9-1 11-2 11-3, 11-4 11-15 to

6-13 – – 6-31 6-34 6-40 6-39 6-43 6-48 6-49 6-50 6-56 6-68 Ch.6.3.4 – 7-3 7-13 9-1 10-2 11-3 –

Figure 6-11/6-10 corrected

Timer 0/1 count register definitions added

Timer 2 count and reload/capture register definitions added

Figure 6-19 corrected

Figure 6-21 corrected

Sentence below table added

Invalid characters in formulas corrected (“x“)

Note in figure 6-26 below added

1. paragraph, 2nd line : ... or CCx and

COUTx .. added Description of the two new CMSEL1 bits ESMC and NMCS added CMSEL table : upper 4 lines “ or analog input pins...“ deleted, see note Paragraph with active/passive state definition moved from 6-70/6-68 Text in last but one paragraph modified New wording :“4-phase“ multi-channel PWM mode instead of “4-pole“.. New chapter 6.3.4.5 added Figure 7-2/7-1b: address of bit EA in corrected External interrupts : description of the TCON bits added Corrected text in 1st paragraph : PCON/PCON1 have differert addr.

specification added

New improved I

specification added

AC charcteristics of programming mode added

11-18 Ch.12 several

Ch.11 several

Improved index with bold page numbers for main reference pages Writing errors corrected

Semiconductor Group I-3

General Information

C504

Table of Contents Page

1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2 Pin Definitions and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

3 Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 Data Memory, "Data Space". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.3 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.4 XRAM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4.1 Reset Operation of the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode). . . . . . . . . . . . . . . . 3-4

3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode). . . . . . . . . 3-4

3.5 Special Function Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

4 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Accessing External Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 PSEN

4.3 Overlapping External Data and Program Memory Spaces. . . . . . . . . . . . . . . . . . . . 4-2

4.4 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.5 Enhanced Hooks Emulation Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.6 ROM/OTP Protection for C504-2R / C504-2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.6.1 Unprotected ROM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.6.2 Protected ROM/OTP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

5 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Hardware Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.3 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.4 Oscillator and Clock Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.2 Standard I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.1.2.1 Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.1.2.2 Port 1 and Port 3 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.1.2.3 Port 2 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.1.3 Detailed Output Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.1.3.1 Type B Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.1.3.2 Type C Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

6.1.3.3 Type D Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

6.1.3.4 Type E Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

6.1.4 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.1.5 Port Loading and Interfacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Semiconductor Group I-1 1997-10-01

General Information

C504

Table of Contents Page

6.1.6 Read-Modify-Write Feature of Ports 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

6.2 Timers/Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

6.2.1 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

6.2.1.1 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

6.2.1.2 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

6.2.1.3 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

6.2.1.4 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23

6.2.1.5 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24

6.2.2 Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25

6.2.2.1 Timer/Counter 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26

6.2.2.2 Auto-Reload (Up or Down Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

6.2.2.3 Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31

6.3 Capture / Compare Unit (CCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32

6.3.1 General Capture/Compare Unit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33

6.3.2 CAPCOM Unit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35

6.3.2.1 CAPCOM Unit Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35

6.3.2.2 CAPCOM Unit Operating Mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36

6.3.2.3 CAPCOM Unit Operating Mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39

6.3.2.4 CAPCOM Unit Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40

6.3.2.5 Burst Mode of CAPCOM / COMP Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42

6.3.2.6 CAPCOM Unit in Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43

6.3.2.7 Trap Function of the CAPCOM Unit in Compare Mode . . . . . . . . . . . . . . . . . . . . . 6-44

6.3.2.8 CAPCOM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46

6.3.3 Compare (COMP) Unit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-61

6.3.3.1 COMP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62

6.3.4 Combined Multi-Channel PWM Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67

6.3.4.1 Control Register BCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68

6.3.4.2 Signal Generation in Multi-Channel PWM Modes . . . . . . . . . . . . . . . . . . . . . . . . . 6-70

6.3.4.3 Block Commutation PWM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73

6.3.4.4 Compare Timer 1 Controlled Multi-Channel PWM Modes . . . . . . . . . . . . . . . . . . . 6-75

6.3.4.5 Software Controlled State Switching in Multi-Channel PWM Modes . . . . . . . . . . . 6-80

6.3.4.6 Trap Function in Multi-Channel Block Commutation Mode . . . . . . . . . . . . . . . . . . 6-81

6.4 Serial Interface (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-82

6.4.1 Multiprocessor Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83

6.4.2 Serial Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83

6.4.3 Baud Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-85

6.4.3.1 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-86

6.4.3.2 Using Timer 2 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87

6.4.4 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-89

6.4.5 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-92

6.4.6 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-95

6.5 10-bit A/D Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98

6.5.1 A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98

6.5.2 A/D Converter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-100

6.5.3 A/D Converter Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-103

Semiconductor Group I-2 1997-10-01

General Information

C504

Table of Contents Page

6.5.4 A/D Conversion Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-104

6.5.5 A/D Converter Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-108

6.5.6 A/D Converter Analog Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-109

7 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1 Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.2 Interrupt Sources and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.3 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.3.1 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.3.2 Interrupt Prioritiy Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.3.3 Interrupt Request Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

7.4 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

7.5 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

7.6 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

8 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1 Programmable Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1.1 Refreshing the Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.1.2 Watchdog Reset and Watchdog Status Flag (WDTS) . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.2 Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.2.1 Detailed Description of the Oscillator Watchdog Unit. . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.2.2 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

9 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2 Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.2.1 Invoking Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.2.2 Exit from Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

10 OTP Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.3 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.4 Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.1 Basic Programming Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.2 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.5 Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

10.6 Lock Bits Programming / Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

10.7 Access of Version Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

11 Device Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.3 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

11.4 AC Characteristics for C504-L / C504-2R / C504-2E . . . . . . . . . . . . . . . . . . . . . . . 11-8

11.5 AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 . . . . . . . . . . . . . . . . 11-10

11.6 AC Characteristics for C504-L40 / C504-2R40 / C504-2E40 . . . . . . . . . . . . . . . . 11-12

11.7 AC Characteristics of Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16

Semiconductor Group I-3 1997-10-01

General Information

C504

Table of Contents Page

11.8 ROM/OTP Verification Characteristics for C504-2R / C504-2E . . . . . . . . . . . . . . 11-20

11.9 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23

12 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

13 Microelectronics Training Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1

Information on Literature Semiconductor Group - Addresses

Semiconductor Group I-4 1997-10-01

Introduction

C504

1 Introduction

The C504 is a modified and extended version of the C501 Microcontroller. Its enhanced functionality, especially the capture compare unit (CCU), allows to use the MCU in motor control applications. Further, the C504 is compatible with the SAB 80C52/C501 microcontrollers and can replace it in existing applications.

The C504-2R contains a non-volatile 16K × 8 read-only program memory, a volatile on-chip 512 × 8 read/write data memory, four 8-bit wide ports, three 16-bit timers/counters, a 16-bit capture/ compare unit, a 10-bit compare timer, a twelve source, two priority level interrupt structure, a serial port, versatile fail save mechanisms, on-chip emulation support logic, and a genuine 10-bit A/D converter. The C504-L is identical to the C504-2R, except that it lacks the on-chip program memory The C504-2E is the OTP version in the C504 microcontroller with a 16Kx8 one-time programmable (OTP) program memory.The term C504 refers to all versions within this documentation unless otherwise noted.

Oscillator Watchdog

10-Bit ADC

Timer 2

16-Bit

Capture/Compare

Unit

10-Bit Compare Unit

On-Chip Emulation Support Module

Watchdog Timer

Figure 1-1 C504 Functional Units

256 x 8

XRAM

C500

Core

ROM/OTP

16 k x 8

RAM

256 x 8

8-Bit

USART

Port 0

Port 1

Port 2

Port 3

I/O

8-Bit Digital I/O 4-Bit Analog Inputs

I/O

8-Bit Digital I/O 4-Bit Analog Inputs

MCB02589

Semiconductor Group 1-1 1997-10-01

Listed below is a summary of the main features of the C504:

•

Fully compatible to standard 8051 microcontroller

•

Up to 40 MHz external operating frequency

•

16K byte on-chip program memory – C504-2R: ROM version (with optional ROM protection) – C504-2E: programmable OTP version – C504-L : without on-chip program memory) – alternatively up to 64K byte external program memory

•

256 × 8 RAM

•

256 × 8 XRAM

•

Four 8-bit ports, (2 ports with mixed analog/digital I/O capability)

•

Three 16-bit timers/counters (timer 2 with up/down counter feature)

•

Capture/compare unit for PWM signal generation and signal capturing

- 3-channel, 16-bit capture/compare unit

- 1-channel, 10-bit compare unit

•

USART

•

10-bit A/D Converter with 8 multiplexed inputs

•

Twelve interrupt sources with two priority levels

•

On-chip emulation support logic (Enhanced Hooks Technology

•

Programmable 15-bit Watchdog Timer

•

Oscillator Watchdog

•

Fast Power On Reset

•

Power Saving Modes

•

M-QFP-44 package

•

Temperature ranges: SAB-C504

SAF-C504 SAH-C504 SAK-C504

: 0 to 70 ° C

: – 40 to 85 ° C

: – 40 to 110 ° C (max. operating frequency.: TBD)

: – 40 to 125 ° C (max. operating frequency.: 12 MHz)

Introduction

C504

)

Semiconductor Group 1-2 1997-10-01

Introduction

C504

Figure 1-2 Logic Symbol

Semiconductor Group 1-3 1997-10-01

1.1 Pin Configuration

This section describes the pin configration of the C504 in the P-MQFP-44 package.

COUT3

P0.7 / AD7

C504-LM C504-2RM C504-2EM

ALE

P2.6 / A14

PSEN

P2.7 / A15

P2.5 / A13

21 20 19 18 17 16 15 14 13 12

1116

P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8

XTAL1 XTAL2 P3.7 / RD P3.6 / WR / INT2

P0.3 / AD3

P0.2 / AD2

P0.1 / AD1

P0.0 / AD0

AREF

GND

P1.0 / AN0 / T2

P1.1 / AN1 / T2EX

P1.2 / AN2 / CC0

P1.3 / AN3 / COUT0

P1.4 / CC1

P0.6 / AD6

P0.5 / AD5

P0.4 / AD4

33 31 30 29 282726 25242332 34 35 36 37 38 39 40 41 42 43 44

2345 78 109

Introduction

C504

Figure 1-3 Pin Configuration (top view)

RESET

P1.6 / CC2

P1.5 / COUT1

P3.0 / RxD

P1.7 / COUT2

CTRAP

P3.1 / TxD

P3.3 / AN5 / INT1

P3.2 / AN4 / INT0

P3.5 / AN7 / T1

P3.4 / AN6 / T0

MCP02532

Semiconductor Group 1-4 1997-10-01

1.2 Pin Definitions and Functions

This section describes all external signals of the C504 with its function.

Table 1-1 Pin Definitions and Functions

Introduction

C504

Symbol Pin Number

(P-MQFP-44)

P1.0-P1.7 40-44,

1-3

I/O *)

I/O

Function

Port 1

is an 8-bit bidirectional port. Port pins can be used for digital input/output. P1.0 - P1.3 can also be used as analog inputs of the A/D-converter. As secondary digital functions, port 1 contains the timer 2 pins and the capture/compare inputs/outputs. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. The functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / T2 Analog input channel 0 /

input to counter 2

P1.1 / AN1 / T2EX Analog input channel 1 /

capture/reload trigger of timer 2 / updown count

P1.2 / AN2 / CC0 Analog input channel 2 /

input/output of capture/compare channel 0

P1.3 / AN3 / COUT0 Analog input channel 3 /

output of capture/compare channel 0

P1.4 / CC1 Input/output of capture/compare

channel 1

P1.5 / COUT1 Output of capture/compare

channel 1

P1.6 / CC2 Input/output of capture/compare

channel 2

P1.7 / COUT2 Output of capture/compare

channel 2

RESET 4 I

RESET

A high level on this pin for the duration of two machine cycles while the oscillator is running resets the device. An internal diffused resistor to using only an external capacitor to

*) I = Input

O = Output

permits power-on reset

Semiconductor Group 1-5 1997-10-01

Table 1-1 Pin Definitions and Functions (cont’d)

Introduction

C504

Symbol Pin Number

(P-MQFP-44)

P3.0-P3.7 5, 7-13

I/O *)

I/O

Function

Port 3

is an 8-bit bidirectional port. P3.0 (R × D) and P3.1 (T × D) operate as defined for the C501. P3.2 to P3.7 contain the external interrupt inputs, timer inputs, input and as an additional optinal function four of the analog inputs of the A/D-converter. Port 3 pins are assigned to be used as analog inputs by the bits of SFR P3ANA. P3.6/WR can be assigned as a third interrupt input. The functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data

input/output (synch.) of serial interface

P3.1 / TxD Transmitter data output (asynch.) or

clock output (synch.) of serial interface

P3.2 / AN4 / INT0 Analog input channel 4 / external

interrupt 0 input / timer 0 gate control input

P3.3 / AN5 / INT1 Analog input channel 5 / external

interrupt 1 input / timer 1 gate control input

P3.4 / AN6 / T0 Analog input channel 6 / timer 0

counter input

P3.5 / AN7 / T1 Analog input channel 7 / timer 1

counter input

P3.6 / WR

P3.7 / RD RD control output; enables the

/ INT2 WR control output; latches the data

byte from port 0 into the external data memory / external interrupt 2 input

external data memory

CTRAP

*) I = Input

O = Output

Semiconductor Group 1-6 1997-10-01

CCU Trap Input

With CTRAP = low the compare outputs of the CAPCOM unit are switched to the logic level as defined in the COINI register (if they are enabled by the bits in SFR TRCON). CTRAP is an input pin with an internal pullup resistor. For power saving reasons, the signal source which drives the CTRAP input should be at high or floating level during power-down mode.

Table 1-1 Pin Definitions and Functions (cont’d)

Introduction

C504

Symbol Pin Number

(P-MQFP-44)

XTAL2 14 – XTAL2

XTAL1 15 – XTAL1

P2.0-P2.7 18-25 I/O Port 2

I/O *)

Function

Output of the inverting oscillator amplifier.

Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed.

is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current ( of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register.

There

, in the DC characteristics) because

PSEN

ALE 27 O The Address Latch Enable

*) I = Input

O = Output

Semiconductor Group 1-7 1997-10-01

26 O The Program Store Enable

output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periodes except during external data memory accesses. Remains high during internal program execution.

output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periodes except during an external data memory access. When instructions are executed from internal ROM (EA by bit EALE in SFR SYSCON.

=1) the ALE generation can be disabled

Table 1-1 Pin Definitions and Functions (cont’d)

Introduction

C504

Symbol Pin Number

(P-MQFP-44)

I/O *)

Function

COUT3 28 O 10-Bit compare channel output

This pin is used for the output signal of the 10-bit compare timer 2 unit. COUT3 can be disabled and set to a high or low state.

29 I External Access Enable

When held at high level, instructions are fetched from the internal ROM (C504-2R only) when the PC is less than 4000H.When held at low level, the C504 fetches all instructions from external program memory. For the C504-L this pin must be tied low.

P0.0-P0.7 30-37 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup resistors when issuing 1 s. Port 0 also outputs the code bytes during program verification in the C504-2R. External pullup resistors are required during program (ROM) verification.

AREF

AGND

*) I = Input

O = Output

38 – Reference voltage for the A/D converter. 39 – Reference ground for the A/D converter. 16 – Ground (0V) 17 – Power Supply (+5V)

Semiconductor Group 1-8 1997-10-01

Fundamental Structure

C504

2 Fundamental Structure

The C504 basically is fully compatible to the architecture of the standard 8051 microcontroller family. Especially it is functionally upward compatible with the SAB 80C52/C501 microcontrollers. While maintaining all architectural and operational characteristics of the SAB 80C52/C501, the C504 incorporates a genuine 10-bit A/D Converter, a capture/compare unit, a XRAM data memory as well as some enhancements in the Timer 2 and Fail Save Mechanism Unit. Figure 2-1 shows a block diagram of the C504.

XTAL1 XTAL2

Oscillator Watchdog

OSC & Timing

XRAM

256 x 8

RAM ROM/OTP

256 x 8

16 k x 8

RESET ALE PSEN EA

COUT3 CTRAP

AREF

AGND

CPU

Timer 0

Timer 1

Timer 2

Interrupt Unit

USART

Capture/Compare Unit

A/D Converter 10-Bit

S & H

MUX

Port 0

Port 1

Port 2

Port 3

Emulation

Support

Logic

Port 0

8-Bit Digital I/O

Port 1

8-Bit Digital I/O 4-Bit Analog Inputs

Port 2

8-Bit Digital I/O

Port 3

8-Bit Digital I/O 4-Bit Analog Inputs

MCB02591

Figure 2-1 Block Diagram of the C504

Semiconductor Group 2-1 1997-10-01

Fundamental Structure

C504

2.1 CPU

The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 12-MHz crystal, 58% of the instructions execute in 1.0 µs (40 MHz: 300 ns). The CPU (Central Processing Unit) of the C504 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, completement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence.

Accumulator

ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A.

Program Status Word

The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU.

Semiconductor Group 2-2 1997-10-01

Fundamental Structure

C504

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

CY AC

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations. F0 General Purpose Flag RS1

RS0

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07 0 1 Bank 1 selected, data address 08H-0F 1 0 Bank 2 selected, data address 10H-17 1 1 Bank 3 selected, data address 18H-1F

PSW

H H H H

OV Overflow Flag

Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

B Register

The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register.

Stack Pointer

The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control.

Semiconductor Group 2-3 1997-10-01

Fundamental Structure

C504

2.2 CPU Timing

A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbered S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and logically operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most C504 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-2 (c) and (d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction.

Semiconductor Group 2-4 1997-10-01

Fundamental Structure

C504

Figure 2-2 Fetch Execute Sequence

Semiconductor Group 2-5 1997-10-01

Memory Organization

3 Memory Organization

The C504 CPU manipulates operands in the following four address spaces:

– up to 64 Kbyte of internal/external program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – 256 bytes of internal XRAM data memory – a 128 byte special function register area

Figure 3-1 illustrates the memory address spaces of the C504.

C504

Figure 3-1 C504 Memory Map

Semiconductor Group 3-1 1997-10-01

Memory Organization

C504

3.1 Program Memory, "Code Space"

The C504-2R has 16 Kbytes of read-only program memory, while the C504-L has no internal program memory. The C504-2E provides 16 Kbytes of OTP program memory. The program memory can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C504 executes out of internal ROM unless the program counter address exceeds 3FFFH. Locations 4000H through FFFFH are then fetched from the external program memory. If the EA pin is held low, the C504 fetches all instructions from the external program memory.

3.2 Data Memory, "Data Space"

The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes.

The external data memory can be expanded up to 64 Kbytes and can be accessed by instructions that use a 16-bit or an 8-bit address.

3.3 General Purpose Registers

The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines.

The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0).

Reset initializes the stack pointer to location 07H and increments it once to start from location 08 which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage.

Semiconductor Group 3-2 1997-10-01

Memory Organization

C504

3.4 XRAM Operation

The XRAM in the C504 is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM.

The C504 maps 256 bytes of the external data space into the on-chip XRAM. Especially when using the 8-bit addressing modes this could prevent access to the external memory extension and might induce problems when porting software. Therefore, it is possible to enable and disable the on-chip XRAM using the bit XMAP in SFR SYSCON. When the XRAM is disabled (default after reset), all external data memory accesses will go to the external data memory area.

Special Function Register SYSCON (Address B1H) Reset Value : XX10XXX0

Bit No. MSB LSB

76543210

Bit Function

– Not implemented. Reserved for future use. XMAP Enable XRAM

––

The functions of the shaded bits are not described in this section.

XMAP=0 : XRAM disabled. XMAP=1 : XRAM enabled. If XRAM is enabled, 8-bit MOVX instructions using Ri always access the internal XRAM and do not generate external bus cycles. If XRAM is enabled, 16-bit MOVX instructions using DPTR, access the XRAM if the address is in the range of FF00H to FFFFH and do not generate external bus cycles in this address range.

EALE RMAP –

––

XMAP

SYSCON

3.4.1 Reset Operation of the XRAM

The content of the XRAM is not affected by a reset. After power-up the content is undefined, while it remains unchanged during and after a reset as long as the power supply is not turned off. If a reset occurs during a write operation to XRAM, the content of a XRAM memory location depends on the cycle in which the active reset signal is detected (MOVX is a 2-cycle instruction):

Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected. Reset during 2nd cycle : The old value in XRAM is overwritten by the new value.

After reset the access to the XRAM is disabled (bit XMAP of SYSCON = 0).

Semiconductor Group 3-3 1997-10-01

Memory Organization

C504

3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode)

The XRAM can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect addressing. These instructions are:

– MOVX A, @DPTR (Read) – MOVX @DPTR, A (Write)

Using these instructions with the XRAM disabled implies, that port 0 is used as address low/data bus, port 2 for high address output, and two lines of port 3 (P3.6/WR/INT2, P3.7/RD) for control to access up to 64 KB of external memory. If the XRAM is enabled and if the effective address stored in DPTR is in the range of 0000H to FEFFH, these instruction will access external memory.

If XRAM is enabled and if the address is within FF00H to FFFFH, the physically internal XRAM of the C504 will be accessed. External memory, which is located in this address range, cannot be accessed in this case because no external bus cycles will generated. Therefore port 0, 2 and 3 can be used as general purpose I/O if only the XRAM memory space is addressed by the user program.

3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode)

The C504 architecture provides also instructions for accesses to external data memory and XRAM which use an 8-bit address (indirect addressing with registers R0 or R1). These instructions are:

– MOVX A, @Ri (Read) – MOVX @Ri, A (Write)

Using these instructions with the XRAM disabled implies, that port 0 is used as address/data bus, port 2 for high address output, and two lines of port 3 (P3.6/WR/INT2, P3.7/RD) for control. Normally these instructions are used to access 256 byte pages of external memory.

If the XRAM is enabled these instruction will only access the internal XRAM. External memory cannot be accessed in this case because no external bus cycle will be generated. Therefore port 0, 2 and 3 can be used as standard I/O, if only the internal XRAM is used.

Semiconductor Group 3-4 1997-10-01

Memory Organization

C504

3.5 Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. Three special function registers of the C504 (PCON1, P1ANA, P3ANA) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers of the C504 are located in the standard special function register area.

Special Function Register SYSCON (Address B1H) Reset Value : XX10XXX0

Bit No. MSB LSB

76543210

Bit Function

– Not implemented. Reserved for future use. RMAP Special function register map bit

As long as bit RMAP is set, mapped special function registers can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each.

––

The functions of the shaded bits are not described in this section.

RMAP = 0 : The access to the non-mapped (standard) special function

RMAP = 1 : The access to the mapped special function register area is

EALE RMAP –

enabled.

––

XMAP

SYSCON

There are also 128 directly addressable bits available within each SFR area (standard and mapped SFR area). All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.

The 63 special function register (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C504 are listed in table 3-1 and table 3-2. In table 3-1 they are organized in groups which refer to the functional blocks of the C504. Table 3-2 illustrates the contents of the SFRs in numeric order of their addresses.

Semiconductor Group 3-5 1997-10-01

Memory Organization

C504

Table 3-1 Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B DPH DPL PSW SP

SYSCON

Interrupt System

IEN0 IEN1 CCIE IP0 IP1 ITCON

Ports P0

P1 P1ANA P2 P3 P3ANA

A/DConverter

ADCON0 ADCON1

ADDATH ADDATL P1ANA P3ANA

Serial Channels

PCON SBUF SCON

Timer 0/ Timer 1

TCON TH0 TH1 TL0 TL1 TMOD

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) X means that the value is undefined and the location is reserved

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer System Control Register

Interrupt Enable Register 0 Interrupt Enable Register 1

Capture/Compare Interrupt Enable Reg. Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Trigger Condition Register

Port 0 Port 1

Port 1 Analog Input Selection Register Port 2 Port 3

Port 3 Analog Input Selection Register A/D Converter Control Register 0

A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte

Port 1 Analog Input Selection Register

Port 3 Analog Input Selection Register

Power Control Register Serial Channel Buffer Register Serial Channel Control Register

Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register

E0 F0

83 82

81 B1

A9 D6

B9 9A

80 90 90 A0 B0 B0

DC D9 DA 90 B0

87 99

98 88

8C 8D 8A 8B 89

H H

H H H

H H

H H H H

1) 4)

XX10XXX0 0X000000

XX000000 00

XX000000 XX000000 00101010

XXXX1111 FF

XX1111XX XX000000

01XXX000 00

00XXXXXX XXXX1111 XX1111XX

000X0000

Semiconductor Group 3-6 1997-10-01

Memory Organization

C504

Table 3-1 Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Timer 2 T2CON

T2MOD RC2H RC2L TH2 TL2

Capture / Compare Unit

CT1CON CCPL CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 COINI TRCON CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 CCIR CCIE CT2CON CP2L CP2H CMP2L CMP2H BCON

Watchdog WDCON

WDTREL

Power Save Mode

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) X means that the value is undefined and the location is reserved

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

PCON PCON1

Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload Capture Register, High Byte Timer 2 Reload Capture Register, Low Byte Timer 2 High Byte Timer 2 Low Byte

Compare timer 1 control register Compare timer 1 period register, low byte Compare timer 1 period register, high byte Compare timer 1 offset register, low byte Compare timer 1 offset register, high byte Capture/compare mode select register 0 Capture/compare mode select register 1 Compare output initialization register Trap enable control register Capture/compare register 0, low byte Capture/compare register 0, high byte Capture/compare register 1, low byte Capture/compare register 1, high byte Capture/compare register 2, low byte Capture/compare register 2, high byte Capture/compare interrupt request flag reg.

Capture/compare interrupt enable register Compare timer 2 control register Compare timer 2 period register, low byte Compare timer 2 period register, high byte Compare timer 2 compare register, low byte Compare timer 2 compare register, high byte Block commutation control register

Watchdog Timer Control Register Watchdog Timer Reload Register

Power Control Register Power Control Register 1

C9 CB CA CD CC

E1 DE DF E6 E7 E3 E4 E2 CF C2 C3 C4 C5 C6 C7 E5 D6 C1 D2 D3 D4 D5 D7

86 87

H H

H H H H H H

H H H H H H H

H H

XXXXXXX0 00

00010000 00

XXXXXX00 00

XXXX0000 00

000X0000 0XXXXXXX

3))

Semiconductor Group 3-7 1997-10-01

Memory Organization

Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses

C504

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H H H H

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 WDT

.6 .5 .4 .3 .2 .1 .0

80 81 82 83 86

P0 FF

SP 07

DPL 00

DPH 00

WDTREL 00

Reset

PSEL

88 88

89 8A 8B 8C 8D 90 90

98 99 9A

A0 A8

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

PCON 000X-

TCON 00

2)3)

PCON1 0XXX-

TMOD 00

TL0 00

TL1 00

TH0 00

TH1 00

P1 FF

2)3)

P1ANA XXXX-

SCON 00

SBUF XX

ITCON 0010-

P2 FF

IEN0 0X00-

IEN1 XX00-

0000

XXXX

H H H H H

1111

1010

0000

SMOD PDS IDLS – GF1 GF0 PDE IDLE

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 EWPD – – – – – – –

GATE C/T

M1 M0 GATE C/T M1 M0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 T2EX T2 – – – – EAN3 EAN2 EAN1 EAN0

SM0 SM1 SM2 REN TB8 RB8 TI RI .7 .6 .5 .4 .3 .2 .1 .0 IT2 IE2 I2ETF I2ETR I1ETF I1ETR I0ETF I0ETR

.7 .6 .5 .4 .3 .2 .1 .0 EA – ET2 ES ET1 EX1 ET0 EX0

– – ECT1 ECCM ECT2 ECEM EX2 EADC

Semiconductor Group 3-8 1997-10-01

Memory Organization

Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C504

Addr Register Content

after

B H H H H H H H

B0 B0

C2 C3 C4 C5 C6 C7 C8

P3 FF

2)3)

P3ANA XX11-

SYSCON XX10-

IP0 XX00-

IP1 XX00-

WDCON

CT2CON 0001-

CCL0 00

CCH0 00

CCL1 00

CCH1 00

CCL2 00

CCH2 00

T2CON 00

Reset

11XX

XXX0

0000

0000 XXXX-

0000

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RD WR T1 T0 INT1 INT0 TxD RxD – – EAN7 EAN6 EAN5 EAN4 – –

– – EALE RMAP – – – XMAP

– – PT2 PS PT1 PX1 PT0 PX0

– – PCT1 PCCM PCT2 PCEM PX2 PADC

– – – – OWDS WDTS WDT SWDT

CT2P ECT2O STE2 CT2

CT2R CLK2 CLK1 CLK0

RES .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/

RL2

CA CB CC CD CF D0 D2

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

T2MOD XXXX-

RC2L 00

RC2H 00

TL2 00

TH2 00

TRCON 00

PSW 00

CP2L 00

XXX0

H H H H H H H

–––––––DCEN

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TREN0 CY AC F0 RS1 RS0 OV F1 P .7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 3-9 1997-10-01

Memory Organization

Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C504

Addr Register Content

after

B H H H

D4 D5

D9 DA

DE DF E0 E1

CP2H XXXX.

CMP2L 00

CMP2H XXXX.

CCIE 00

BCON 00

ADCON0 XX00-

ADDATH 00

ADDATL 00XX-

ADCON1 01XX-

CCPL 00

CCPH 00

ACC 00

CT1CON 0001-

COINI FF

Reset

XX00

0000

XXXX

X000

0000

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

––––––.1.0

.7 .6 .5 .4 .3 .2 .1 .0 ––––––.1.0

ECTP ECTC CC2

FEN

BCMP

PWM1 PWM0 EBCE

CC2 REN

CC1 FEN

BCERR

CC1 REN

CC0 FEN

CC0 REN

BCEN BCM1 BCM0

BCEM – – IADC BSY ADM MX2 MX1 MX0

.9 .8 .7 .6 .5 .4 .3 .2 .1.0––––––

ADCL1 ADCL0 – – – MX2 MX1 MX0

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 CTM ETRP STE1 CT1

CT1R CLK2 CLK1 CLK0

RES

COUT 3I

COUT XI

COUT 2I

CC2I COUT

CC1I COUT

CC0I

E5 E6 E7 F0

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

CMSEL0 00

CMSEL1 00

CCIR 00

CT1OFL 00

CT1OFH 00

B 00

H H H H

CMSEL 13

ESMC NMCS 0 0

CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0R .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0

CMSEL 12

CMSEL 11

CMSEL 10

CMSEL 03

CMSEL 23

CMSEL 02

CMSEL 22

CMSEL 01

CMSEL 21

CMSEL 00

CMSEL 20

Semiconductor Group 3-10 1997-10-01

Memory Organization

Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C504

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H H

11000101

0 1

0000100

.7 .6 .5 .4 .3 .2 .1 .0

Reset

3) 4)

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

4) These SFRs are read-only registers.

5) 04

6) The content of this SFR varies with the actual step of the C504 (see also table 10-4 in chapter 10).

VR0 C5

VR1 04

VR2

is valid for the C504-2R, 84H is valid for the C504-2E,

Semiconductor Group 3-11 1997-10-01

External Bus Interface

C504

4 External Bus Interface

The C504 allows for external memory expansion. To accomplish this, the external bus interface common to most 8051-based controllers is employed.

4.1 Accessing External Memory

It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described.

Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri).

Role of P0 and P2 as Data/Address Bus

When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors.

During any access to external memory, the CPU writes FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding.

Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register).

Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified.

If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods.

Semiconductor Group 4-1 1997-10-01

External Bus Interface

C504

Timing

The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustrated in figure 4-1 a) and b).

Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is

activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated.

Program memory: Signal PSEN functions as a read strobe.

External Program Memory Access

The external program memory is accessed under two conditions:

– whenever signal EA is active: or – whenever the program counter (PC) contains a number that is larger than 3FFFH.

This requires the ROM-less version C504-L to have EA wired low to allow the lower 16K program bytes to be fetched from external memory.

When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and may not be used for general-purpose I/O. The contents of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri).

Since the C504-L has no internal program memory, accesses to program memory are always external, and port 2 is at all times dedicated to output the high-order address byte. This means that port 0 and port 2 of the C504-L can never be used as general-purpose I/O. This also applies to the C504-2R or C504-2E when they operat only with an external program memory.

4.2 PSEN, Program Store Enable

The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external program memory, PSEN is activated twice every cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN including activation and deactivation of ALE and RD, takes 12 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN takes 6 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b).

is activated its timing is not the same as for RD. A complete RD cycle,

4.3 Overlapping External Data and Program Memory Spaces

In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C504 the external program and data memory spaces can be combined by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle.

Semiconductor Group 4-2 1997-10-01

External Bus Interface

C504

ALE

PSEN

One Machine Cycle One Machine Cycle

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

PCL OUT

valid

PCH OUT

INSTINPCL

OUT

PCL OUT

valid

PCH PCH OUT

INST

PCL OUT

valid

One Machine CycleOne Machine Cycle

PCH

INSTINPCL

PCH OUT

INST

PCL OUT

OUTOUT

OUT

PCL OUT

valid

(A) without MOVX

INST

ALE

PSEN

PCL OUT

valid

PCH OUT

INST

DPL or Ri

OUT

INST

PCL OUT

Figure 4-1 External Program Memory Execution

valid

DPH OUT OR

P2 OUT

DATA

PCL OUT

valid

S6S5S4S3S2S1S6S5S4S3S2S1

(B) with MOVX

PCHPCH OUT

INST

MCD02575

Semiconductor Group 4-3 1997-10-01

External Bus Interface

C504

4.4 ALE, Address Latch Enable

The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 into an external latch during fetches from external memory. The address byte is valid at the negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This activation takes place even if the cycle involves no external fetch. The only time no ALE pulse comes out is during an access to external data memory when RD/WR signals are active. The first ALE of the second cycle of a MOVX instruction is missing (see figure 4-1 b). Consequently, in any system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator frequency and can be used for external clocking or timing purposes.

The C504 allows to switch off the ALE output signal. If the internal ROM is used (EA=1) and ALE is switched off by EALE=0, ALE will only go active during external data memory accesses (MOVX instructions) and code memory accesses with an address greater than 3FFFH (external code memory fetches). If EA=0, the ALE generation is always enabled and the bit EALE has no effect.

After a hardware reset the ALE generation is enabled.

Special Function Register SYSCON (Address B1H) Reset Value : XX10XXX0

Bit No. MSB LSB

76543210

Bit Function

– Not implemented. Reserved for future use. EALE Enable ALE output

––

The function of the shaded bit is not described in this section.

EALE = 0 : ALE generation is disabled; disables ALE signal generation

EALE = 1 : ALE generation is enabled If EA=0, the ALE generation is always enabled and the bit EALE has no effect on the ALE generation.

EALE RMAP –

during internal code memory accesses (EA ALE is automatically generated at MOVX instructions and code memory accesses with an address greater 3FFFH.

––

XMAP

SYSCON

=1). With EA=1,

Semiconductor Group 4-4 1997-10-01

External Bus Interface

C504

4.5 Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical.

The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.

SYSCON

PCON TCON

Optional

I/O Ports

ICE-System Interface

to Emulation Hardware

RESET

ALE

PSEN

C500

MCU Interface Circuit

Port 3 Port 1

Port 0 Port 2

Target System Interface

RSYSCON

RPCON RTCON

Enhanced Hooks

RPort 0RPort 2

EH-IC

TEA TALE TPSEN

MCS02647

Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.

Semiconductor Group 4-5 1997-10-01

External Bus Interface

C504

4.6 ROM/OTP Protection for C504-2R / C504-2E

The C504-2R ROM version allows to protect the content of the internal ROM against read out by non authorized people. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a C504-2R ROM version has to define whether ROM protection has to be selected or not.

The C504-2E OTP version allows also program memory protection in several levels (see chapter

10.6). The program memory protection for the C504-2E can be activated after programming of the device.

The C504-2R devices, which operate from internal ROM, are always checked for correct ROM content during production test. Therefore, unprotected and also protected ROMs must provide a procedure to verify the ROM content. In ROM verification mode 1, which is used to verify unprotected ROMs, a ROM address is applied externally to the C504-2R and the ROM data byte is output at port 0. ROM verification mode 2, which is used to verify ROM protected devices, operates different: ROM addresses are generated internally and the expected data bytes must be applied externally to the device (by the manufacturer or by the customer) and are compared internally with the data bytes from the ROM. After 16 byte verify operations the state of the P3.5 pin shows whether the last 16 bytes have been verified correctly.

This mechanism provides a very high security of ROM protection. Only the owner of the ROM code and the manufacturer who know the content of the ROM can read out and verify it with less effort.

4.6.1 Unprotected ROM Mode

If the ROM is unprotected, the ROM verification mode 1 as shown in figure 4-3 is used to read out the content of the ROM (see also the AC specifications in chapter 10, not valid for C504-2E).

Figure 4-3 ROM Verification Mode 1

ROM verification mode 1 is selected if the inputs PSEN, ALE, EA, and RESET are put to the specified logic level. P2.6 and P2.7 must be held at low level. Whenever the 14-bit address of the internal ROM byte to be read is applied to the port 1 and port 2, after a delay time, port 0 outputs the content of the addressed internal program memory cell. In ROM verification mode 1, the C504-2R must be provided with a system clock at the XTAL pins and pullup resistors on the port 0 lines.

Semiconductor Group 4-6 1997-10-01

External Bus Interface

C504

4.6.2 Protected ROM/OTP Mode

If the C504-2R ROM is protected by mask (or C504-2E OTP in protection level 1), the ROM/OTP verification mode 2 as shown in figure 4-4 is used to verify the content of the ROM/OTP. The detailed timing characteristics of the ROM/OTP verification mode is shown in the AC specifications (chapter 11).

Figure 4-4 ROM Verification Mode 2

ROM/OTP verification mode 2 is selected if the inputs PSEN, EA, and ALE are put to the specified logic levels. With RESET going inactive, the ROM/OTP verification mode 2 sequence is started. The C504 outputs an ALE signal with a period of 12 t bytes at port 0 are assigned to the ROM addresses in the following way:

1. Data Byte = content of internal ROM/OTP address 0000

2. Data Byte = content of internal ROM/OTP address 0001

3. Data Byte = content of internal ROM/OTP address 0002 :

16. Data Byte= content of internal ROM/OTP address 000FH :

The C504 does not output any address information during the ROM/OTP verification mode 2. The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000 and must be put onto the data bus with the falling edge of RESET. With each following ALE pulse the ROM/OTP address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally.

and expects data bytes at port 0. The data

CLCL

H H H

Semiconductor Group 4-7 1997-10-01

External Bus Interface

C504

Between two ALE pulses the data at port 0 is latched (at 6 t

after ALE rising edge) and compared

CLCL

internally with the ROM/OTP content of the actual address. If an verify error is detected, the error condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. P3.5 is always set or cleared after each 16 byte block of the verify sequence. In ROM/OTP verification mode 2, the C504 must be provided with a system clock at the XTAL pins.

Figure 4-5 shows an application example of a external circuitry which allows to verify a protected ROM/OTP inside the C504 in ROM/OTP verification mode 2. With RESET going inactive, the C504 starts the ROM/OTP verify sequence. Its ALE is clocking an 14-bit address counter. This counter generates the addresses for an external EPROM which is programmed with the content of the internal (protected) ROM/OTP. The verify detect logic typically displays the state of the verify error output P3.5. P3.5 can be latched with the falling edge of ALE.

When the last byte of the internal ROM/OTP has been handled, the C504 starts generating a PSEN signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end of the internal ROM/OTP verification.

P3.5

Verify Detect Logic

ALE

C504-2R C504-2E

RESET

P2.7

PSEN

CLK

2kΩ

14-Bit Address

- A13

Counter

Compare Code

0Port

ROM

CS OE

MCB02595

Figure 4-5 ROM/OTP Verification Mode 2 - External Circuitry Example

Semiconductor Group 4-8 1997-10-01

Reset / System Reset

C504

5 Reset and System Clock Operation

5.1 Hardware Reset Operation

The hardware reset function incorporated in the C504 allows an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated.

Additionally to the hardware reset, which is applied externally to the C504, there are two internal reset sources, the watchdog timer and the oscillator watchdog. The chapter at hand only deals with the external hardware reset.

The reset input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycle (24 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again.

During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins).

At the reset pin, a pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the reset pin to VCC via a capacitor. After VCC has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset.

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Reset / System Reset

C504

The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is generated externally (figure 5-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive.

RESET

C504 C504

RESET

C504

RESET

MCS03352

Figure 5-1 Reset Circuitries

A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches of ports 0, 1, 2, and 3 default in FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1 to 3) output a one (1).

The contents of the internal RAM and XRAM of the C504 is not affected by a reset. After power-up the contents are undefined, while it remains unchanged during a reset if the power supply is not turned off.

Semiconductor Group 5-2 1997-10-01

Reset / System Reset

C504

5.2 Fast Internal Reset after Power-On

The C504 uses the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 5-1 shows the power-on sequence under control of the oscillator watchdog.

Normally the devices of the 8051 family enter their default reset state not before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 10 ms). During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins.

In the C504 the oscillator watchdog unit avoids this situation. In this case, after power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator's output. This allows correct resetting of the part and brings also all ports to the defined state (see figure 5-2).

Under worst case conditions (fast VCC rise time - e.g. 1µs, measured from VCC = 4.25 V up to stable port condition), the delay between power-on and the correct port reset state is:

– Typ.: 18 µs – Max.: 34 µs

The RC oscillator will already run at a VCC below 4.25V (lower specification limit). Therefore, at slower VCC rise times the delay time will be less than the two values given above.

After the on-chip oscillator has finally started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of max. 768 cycles of the RC oscillator clock in order to allow the oscillation of the on-chip oscillator to stabilize (figure 5-2, II). Subsequently the clock is supplied by the on-chip oscillator and the oscillator watchdog's reset request is released (figure 5-2, III). However, an externally applied reset still remains active (figure 5-2, IV) and the device does not start program execution (figure 5-2, V) before the external reset is also released.

Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up. The reasons are as follows:

– Termination of Software Power-Down Mode – Reset of the status flag OWDS that is set by the oscillator watchdog during the power up

sequence.

Using a crystal or ceramic resonator for clock generation, the external reset signal must be hold active at least until the on-chip oscillator has started and the internal watchdog reset phase is completed (after phase III in figure 5-2). When an external clock generator is used, phase II is very short. Therefore, an external reset time of typically 1 ms is sufficient in most applications.

Generally, for reset time generation at power-on an external capacitor can be applied to the RESET pin.

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Reset / System Reset

C504

Figure 5-2 Power-On Reset Timing of the C504

Semiconductor Group 5-4 1997-10-01

Reset / System Reset

C504

5.3 Hardware Reset Timing

This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase

2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (high level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. Note that this reset procedure is also performed if there is no clock available at the device. (This is done by the oscillator watchdog, which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins). The RESET signal must be active for at least one machine cycle; after this time the C504 remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase

2) the first falling edge at pin ALE occurs. Figure 5-3 shows this timing for a configuration with EA = 0 (external program memory). Thus,

between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles.

One Machine Cycle

S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2

P1 P2

RESET

ALE

PCL OUT

PCH OUT

Inst.

PCL

in OUT

MCT02092

PCH OUT

Figure 5-3 CPU Timing after Reset

Semiconductor Group 5-5 1997-10-01

Reset / System Reset

C504

5.4 Oscillator and Clock Circuit

XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components as a pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles.

Figure 5-4 shows the recommended oscillator circuit.

XTAL2

3.5 - 40 MHz

C = 20 pF 10 pF for crystal operation

Figure 5-4 Recommended Oscillator Circuit

In this application the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in figure 5-5). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors normally have different values depending on the oscillator frequency. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors.

C504

XTAL1

MCS03353

Semiconductor Group 5-6 1997-10-01

**)

Reset / System Reset

C504

To internal timing circuitry

XTAL2 XTAL1

C504

*) Crystal or ceramic resonator **) Resistor is only in the C504-2E

MCS03354

Figure 5-5 On-Chip Oscillator Circuiry

To drive the C504 with an external clock source, the external clock signal has to be applied to XTAL1, as shown in figure 5-6. XTAL2 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the V

IH2

specification of XTAL1.

C504

N.C.

XTAL2

External Clock

XTAL1

Signal

MCS03355

Figure 5-6 External Clock Source

Semiconductor Group 5-7 1997-10-01

On-Chip Peripheral Components

C504

6 On-Chip Peripheral Components

6.1 Parallel I/O

The C504 has four 8-bit I/O ports. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET.

6.1.1 Port Structures

The C504 generally allows digital I/O on 32 lines grouped into 4 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0-P3 are performed via their corresponding special function registers. Depending on the specific ports, multiple functions are assigned to the port pins. Therefore, the parallel I/O ports of the C504 can be grouped into five different types which are listed in table 6-1.

Table 6-1 C504 Port Structures

Type Description

A Standard digital I/O ports which can be also used for external address/data bus. B Standard multifunctional digital I/O port lines C Mixed digital/analog I/O port lines with programmable analog input function D Standard digital I/O port lines with push-pull drive capability E Mixed digital/analog I/O port lines with push-pull drive capability and programmable

analog input function

Type A and B port pins are standard C501 compatible I/O port lines, which can be used for digital I/O. The type A ports (port 0 and port 2) are also designed for accessing external data or program memory. Type B port lines are located at port 3 and provide alternate functions for the serial interface or are used as control outputs during external data memory accesses.

The C504 provides eight analog input lines which are realized as mixed digital/analog inputs. The 8 analog inputs are split into two groups of four inputs each. Four analog inputs AN0-AN3 are located at the port 1 pins P1.0 to P1.3 and the other four analog inputs AN4-AN7 are located at the port 3 pins P3.2 to P3.5 (type C and type E port lines). After reset, all analog inputs are disabled and the related pins of port 1 and 3 are configured as digital inputs. The analog function of the specific port 1 and port 3 pins is enabled by bits in the SFRs P1ANA and P3ANA. Writing a 0 to a bit position of P1ANA or P3ANA assigns the corresponding pin to operate as analog input.

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On-Chip Peripheral Components

C504

Note: P1ANA and P3ANA are mapped SFRs and can be only accessed if bit RMAP in SFR SYSCON is set (description see chapter 6.5.4).

Type D and E port lines can be switched to push-pull drive capability when they are used as compare outputs of the CAPCOM unit.

As already mentioned, port 1 and 3 are provided for multiple alternate functions. These second and third functions of the port 1 and 3 lines are listed in table 6-2:

Table 6-2 Alternate Functions of Port 1 and 3

Port Second / third

Function

P1.0 P1.1

P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0

P3.1

P3.2

P3.3

P3.4 P3.5 P3.6 P3.7

AN0 / T2 AN1 / T2EX

AN2 / CC0 AN3 / COUT0 CC1 COUT1 CC2 COUT2 RxD

TxD

AN4 / INT0

AN5 / INT1

AN6 / T0 AN7 / T1 WR / INT2 RD

Port Type

C C

E E D D D D B

C C B B

Function

Analog input channel 0 / input to counter 2 Analog input channel 1 / capture-reload trigger of timer 2 / up down count Analog input channel 2 / CAPCOM channel 0 input/output Analog input channel 3 / CAPCOM channel 0 output CAPCOM channel 1 input/output CAPCOM channel 1 output CAPCOM channel 2 input/output CAPCOM channel 2 output Serial port’s receiver data input (asynchronous) or data input/ output (synchronous) Serial port’s transmitter data output (asynchronous) or data clock output (synchronous) Analog input channel 4 / External interrupt 0 input, timer 0 gate control Analog input channel 5 / External interrupt 1 input, timer 1 gate control Analog input channel 6 / Timer 0 external counter input Analog input channel 7 / Timer 1 external counter input External data memory write strobe / External interrupt 2 input External data momory read strobe

Prior to the description of the port type specific port configurations the general port structure is described in the next section.

Semiconductor Group 6-2 1997-10-01

On-Chip Peripheral Components

C504

6.1.2 Standard I/O Port Circuitry Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each

of the four I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0, P2, P3) activate the "read-latch" signal, while others activate the "read-pin" signal.

Read Latch

Int. Bus

Write

Latch

Read

Figure 6-1 Basic Structure of a Port Circuitry

CLK

Port Latch

Port

Driver Circuit

MCS01822

Port Pin

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On-Chip Peripheral Components

C504

Port 1, 2 and 3 output drivers have internal pullup FET’s (see figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit must contain a one (1) (that means for figure 6-2: Q=0), which turns off the output driver FET n1. Then, for ports 1, 2 and 3, the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current (IIL or ITL). For this reason these ports are sometimes called "quasi-bidirectional".

Read Latch

Int. Bus

Write

Latch

Read

Bit Latch

CLK

Figure 6-2 Basic Output Driver Circuit of Ports 1, 2 and 3

Internal Pull Up Arrangement

MCS01823

Semiconductor Group 6-4 1997-10-01

On-Chip Peripheral Components

C504

6.1.2.1 Port 0 Circuitry

Port 0, in contrast to ports 1, 2 and 3, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-3) is used only when the port is emitting 1 s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a "1" to the port latch leaves both output FETs off and the pin floats. In that condition it can be used as high-impedance input. If port 0 is configured as general I/O port and has to emit logic high-level (1), external pullups are required.

Read Latch

Bus

Int.

Write to

Latch

Read Pin

CLK

Bit Latch

Addr./Data

Control

MUX

MCS02434

Port Pin

Figure 6-3 Port 0 Circuitry

Semiconductor Group 6-5 1997-10-01

On-Chip Peripheral Components

C504

6.1.2.2 Port 1 and Port 3 Circuitry

The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-2.

Figure 6-4 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1); otherwise the pulldown FET is on and the port pin is stuck at 0. After reset all port latches contain ones (1).

Read Latch

Int. Bus

Write

Latch

Read

CLK

Bit Latch

Alternate

Input

Function

Alternate

Output

Function

Internal Pull Up Arrangement

MCS01827

Figure 6-4 Ports 1 and 3

Semiconductor Group 6-6 1997-10-01

On-Chip Peripheral Components

C504

6.1.2.3 Port 2 Circuitry

As shown in figure 6-3 and below in figure 6-5, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P2 SFR remains unchanged while the P0 SFR has 1’s written to it. Being an address/data bus, port 0 uses a pullup FET as shown in figure 6-5. When a 16-bit address is used, port 2 uses the additional strong pullups p1 (figure 6-6) to emit 1’s for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity.

Read Latch

Int. Bus

Write to Latch

Read Pin

CLK

Bit

Latch

Addr.

MUX

Control

Internal

Pull Up

Arrangement

MCS03228

Port Pin

Figure 6-5 Port 2 Circuitry

If no external bus cycles are generated using data or code memory accesses, port 0 can be used for I/O functions. Note : during MOVX accesses to the internal XRAM no external bus cycles are generated.

Semiconductor Group 6-7 1997-10-01

On-Chip Peripheral Components

C504

Addr.

MUX

Input Data (Read Pin)

Delay

1 State

= 1

Control

p1 p2 p3

Port Pin

= 1= 1

MCS03229

Figure 6-6 Port 2 Pull-up Arrangement

Port 2 in I/O function works similar to the standard port driver circuitry whereas in address output function it works similar to Port 0 circuitry.

Semiconductor Group 6-8 1997-10-01

On-Chip Peripheral Components

C504

6.1.3 Detailed Output Driver Circuitry

In fact, the pullups mentioned before and included in figure 6-2, 6-4 and 6-5 are pullup arrangements. The differences of the port types available in the C504 is described in the next sections.

6.1.3.1 Type B Port Driver Circuitry Figure 6-7 shows the output driver circuit of the type B multifunctional digital I/O port lines. The

basic circuitry of these ports is shown in figure 6-4.The pullup arrangement of type B port lines has one n-channel pulldown FET and three pullup FETs:

Port Pin

MCS03230

Input Data (Read Pin)

Delay = 1 State

p1 p2 p3

=1=1

Figure 6-7 Driver Circuit of Type B Port Pins

– The pulldown FET n1 is of n-channel type. It is a very strong driver transistor which is capable

of sinking high currents (IOL); it is only activated if a "0" is programmed to the port pin. A short circuit to VCC must be avoided if the transistor is turned on, since the high current might destroy the FET. This also means that no “0“ must be programmed into the latch of a pin that is used as inpu.

– The pullup FET p1 is of p-channel type. It is activated for one state (S1) if a 0-to-1 transition

is programmed to the port pin, i.e. a "1" is programmed to the port latch which contained a "0". The extra pullup can drive a similar current as the pulldown FET n1. This provides a fast transition of the logic levels at the pin.

– The pullup FET p2 is of p-channel type. It is always activated when a "1" is in the port latch,

thus providing the logic high output level. This pullup FET sources a much lower current than p1; therefore the pin may also be tied to ground, e.g. when used as input with logic low input level.

Semiconductor Group 6-9 1997-10-01

On-Chip Peripheral Components

C504

– The pullup FET p3 is of p-channel type. It is only activated if the voltage at the port pin is

higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logic high level shall be output at the pin (and the voltage is not forced lower than approximately

1.0 to 1.5 V). However, this transistor is turned off if the pin is driven to a logic low level, e.g when used as input. In this configuration only the weak pullup FET p2 is active, which sources the current IIL . If, in addition, the pullup FET p3 is activated, a higher current can be sourced (ITL). Thus, an additional power consumption can be avoided if port pins are used as inputs with a low level applied. However, the driving capability is stronger if a logic high level is output.

The described activating and deactivating of the four different transistors translates into four states the pins can be:

– input low state (IL), p2 active only – input high state (IH) = steady output high state (SOH) p2 and p3 active – forced output high state (FOH), p1, p2 and p3 active – output low state (OL), n1 active

If a pin is used as input and a low level is applied, it will be in IL state, if a high level is applied, it will switch to IH state.

If the latch is loaded with "0", the pin will be in OL state. If the latch holds a "0" and is loaded with "1", the pin will enter FOH state for two cycles and then

switch to SOH state. If the latch holds a "1" and is reloaded with a "1" no state change will occur. At the beginning of power-on reset the pins will be in IL state (latch is set to "1", voltage level on pin

is below of the trip point of p3). Depending on the voltage level and load applied to the pin, it will remain in this state or will switch to IH (=SOH) state. If it is used as output, the weak pull-up p2 will pull the voltage level at the pin above p3’s trip point after some time and p3 will turn on and provide a strong "1". Note, however, that if the load exceeds

the drive capability of p2 ( first 0-to-1 transition on the latch occurs. Until this the output level might stay below the trip point of the external circuitry.

The same is true if a pin is used as bidirectional line and the external circuitry is switched from outpout to input when the pin is held at "0" and the load then exceeds the p2 drive capabilities.

If the load exceeds IIL the pin can be forced to "1" by writing a "0" followed by a "1" to the port pin.

), the pin might remain in the IL state and provide a week "1" until the

Semiconductor Group 6-10 1997-10-01

On-Chip Peripheral Components

C504

6.1.3.2 Type C Port Driver Circuitry Figure 6-8 shows the port driver circuit of the type C mixed digital/analog I/O port lines of the C504.

The analog function is selected by the bits in the SFRs P1ANA and P3ANA.

Figure 6-8 Driver Circuit of Type C Port Pins

Semiconductor Group 6-11 1997-10-01

On-Chip Peripheral Components

C504

6.1.3.3 Type D Port Driver Circuitry

The driver and control structure of the port pins used for compare output functions have a port structure which allows a true push-pull output driving capability (Type D). This output driver characteristic is only enabled/used when the corresponding port lines are used as compare outputs. The analog function is selected by the bits in the SFRs P1ANA and P3ANA.

The push-pull port structure is illustrated in figure 6-9.

Figure 6-9 Driver Circuit of Type D Port Pins

Semiconductor Group 6-12 1997-10-01

On-Chip Peripheral Components

C504

6.1.3.4 Type E Port Driver Circuitry

The type E ports are a combination of type C and type D port drivers. They combine push-pull driving characteristic with the capability to select the port pin for analog input function. The push-pull driver characteristic is only enabled/used when the corresponding port lines are used as compare outputs. The analog function is selected by the bits in the SFRs P1ANA and P3ANA.

The push-pull mixed digital/analog port structure is illustrated in figure 6-10.

Figure 6-10 Driver Circuit of Type E Port Pins

Semiconductor Group 6-13 1997-10-01

On-Chip Peripheral Components

C504

6.1.4 Port Timing

When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1). Consequently, the new value in the port latch will not appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle.

When an instruction reads a value from a port pin (e.g. MOV A, P1) the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions. Figure 6-11 illustrates this port timing. It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an "edge", e.g. when used as counter input. In this case an "edge" is detected when the sampled value differs from the value that was sampled the cycle before. Therefore, there must be met certain requirements on the pulse length of signals in order to avoid signal "edges" not being detected. The minimum time period of high and low level is one machine cycle, which guarantees that this logic level is noticed by the port at least once.

Figure 6-11 Port Timing

P1 P2

XTAL2

Input sampled: e.g. MOV A, P1

Port

S4 S5

Old Data

P2P1

P1 active for 1 State (driver transistor)

New Data

P2P1

MCT03231

Semiconductor Group 6-14 1997-10-01

On-Chip Peripheral Components

C504

6.1.5 Port Loading and Interfacing

The output buffers of ports 2 and 3 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be looked up in the DC characteristics in the Data Sheet of the C504. The corresponding parameters are VOL and VOH.

The same applies to port 0 output buffers. They do, however, require external pullups to drive floating inputs, except when being used as the address/data bus.

When used as inputs it must be noted that the ports 2 and 3 are not floating but have internal pullup transistors. The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin (the parameters ITL and IIL in the DC characteristics specify these currents). Port 0 as well as the input only port 1, however, have floating inputs when used for digital input.

Semiconductor Group 6-15 1997-10-01

On-Chip Peripheral Components

C504

6.1.6 Read-Modify-Write Feature of Ports 2 and 3

Some port-reading instructions read the latch and others read the pin. The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write"- instructions, which are listed in table 6-3. If the destination is a port or a port pin, these instructions read the latch rather than the pin. Note that all other instructions which can be used to read a port, exclusively read the port pin. In any case, reading from latch or pin, resp., is performed by reading the SFR P0, P2 and P3; for example, "MOV A, P3" reads the value from port 3 pins, while "ANL P3, #0AAH" reads from the latch, modifies the value and writes it back to the latch.

It is not obvious that the last three instructions in table 6-3 are read-modify-write instructions, but they are. The reason is that they read the port byte, all 8 bits, modify the addressed bit, then write the complete byte back to the latch.

Table 6-3 "Read-Modify-Write"-Instructions

Instruction Function

ANL Logic AND; e.g. ANL P1, A ORL Logic OR; e.g. ORL P2, A XRL Logic exclusive OR; e.g. XRL P3, A JBC Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL CPL Complement bit; e.g. CPL P3.0 INC Increment byte; e.g. INC P4 DEC Decrement byte; e.g. DEC P5 DJNZ Decrement and jump if not zero; e.g. DJNZ P3, EL MOV Px.y,C Move carry bit to bit y of port x CLR Px.y Clear bit y of port x SETB Px.y Set bit y of port x

The reason why read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "1" is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transitor (approx. 0.7 V, i.e. a logic low level!) and interpret it as "0". For example, when modifying a port bit by a SETB or CLR instruction, another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch. However, reading the latch rater than the pin will return the correct value of "1".

Semiconductor Group 6-16 1997-10-01

On-Chip Peripheral Components

C504

6.2 Timers/Counters

The C504 contains three 16-bit timers/counters which are useful in many applications for timing and counting.

In "timer" function, the register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the counter rate is 1/12 of the oscillator frequency.

In "counter" function, the register is incremented in response to a 1-to-0 transition (falling edge) at its corresponding external input pin, T0 or T1 (alternate functions of P3.4 and P3.5, resp.). In this function the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle.

6.2.1 Timer/Counter 0 and 1

Timer / counter 0 and 1 of the C504 are fully compatible with timer / counter 0 and 1 of the C501 and can be used in the same four operating modes:

Mode 0: 8-bit timer/counter with a divide-by-32 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; Timer/

counter 1 in this mode holds its count. The effect is the same as setting TR1 = 0.

External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements.

Each timer consists of two 8-bit registers (TH0 and TL0 for timer/counter 0, TH1 and TL1 for timer/ counter 1) which may be combined to one timer configuration depending on the mode that is established. The functions of the timers are controlled by two special function registers TCON and TMOD.

In the following descriptions the symbols TH0 and TL0 are used to specify the high-byte and the low-byte of timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for timer 0. If not explicitly noted, this applies also to timer 1.

Semiconductor Group 6-17 1997-10-01

On-Chip Peripheral Components

6.2.1.1 Timer/Counter 0 and 1 Registers

Totally six special function registers control the timer/counter 0 and 1 operation :

– TL0/TH0 and TL1/TH1 - counter registers, low and high part – TCON and TMOD - control and mode select registers

C504

Special Function Register TL0 (Address 8AH) Reset Value : 00 Special Function Register TH0 (Address 8CH) Reset Value : 00 Special Function Register TL1 (Address 8BH) Reset Value : 00 Special Function Register TH1 (Address 8DH) Reset Value : 00

Bit No.

MSB LSB

76543210

.7 .6 .5 .48A

.7 .6 .5 .48C

.7 .6 .5 .48B

.7 .6 .5 .48D

.3 .2 .1 .0

TL0

TH0.3 .2 .1 .0

TL1.3 .2 .1 .0

TH1.3 .2 .1 .0

H H H H

Bit Function

TLx.7-0 x=0-1

Timer/counter 0/1 low register

Operating Mode Description

0 "TLx" holds the 5-bit prescaler value. 1 "TLx" holds the lower 8-bit part of the 16-bit timer/counter value. 2 "TLx" holds the 8-bit timer/counter value. 3 TL0 holds the 8-bit timer/counter value; TL1 is not used.

THx.7-0 x=0-1

Timer/counter 0/1 high register

Operating Mode Description

0 "THx" holds the 8-bit timer/counter value. 1 "THx" holds the higher 8-bit part of the 16-bit timer/counter valu 2 "THx" holds the 8-bit reload value. 3 TH0 holds the 8-bit timer value; TH1 is not used.

Semiconductor Group 6-18 1997-10-01

On-Chip Peripheral Components

C504

Special Function Register TCON (Address 88H) Reset Value : 00

Bit No.

Bit Function

TR0 Timer 0 run control bit

TF0 Timer 0 overflow flag

TR1 Timer 1 run control bit

TF1 Timer 1 overflow flag

MSB LSB

76543210

TF1 TR1 TF0 TR088

The shaded bits are not used in controlling timer/counter 0 and 1.

Set/cleared by software to turn timer/counter 0 ON/OFF.

Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine.

Set/cleared by software to turn timer/counter 1 ON/OFF.

Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine.

IE1 IT1 IE0 IT0

TCON

Semiconductor Group 6-19 1997-10-01

On-Chip Peripheral Components

C504

Special Function Register TMOD (Address 89H) Reset Value : 00

Bit No.

MSB LSB

76543210

GATE C/T M1 M089

GATE C/T M1 M0

TMOD

Timer 1 Control Timer 0 Control

Bit Function

GATE Gating control

When set, timer/counter "x" is enabled only while "INT x" pin is high and "TRx" control bit is set. When cleared timer "x" is enabled whenever "TRx" control bit is set.

C/T

Counter or timer select bit Set for counter operation (input from "Tx" input pin). Cleared for timer operation (input from internal system clock).

M1 M0

Mode select bits

M1 M0 Function

0 0 8-bit timer/counter:

"THx" operates as 8-bit timer/counter "TLx" serves as 5-bit prescaler

0 1 16-bit timer/counter.

"THx" and "TLx" are cascaded; there is no prescaler

1 0 8-bit auto-reload timer/counter.

"THx" holds a value which is to be reloaded into "TLx" each time it overflows

1 1 Timer 0 :

TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only controlled by timer 1 control bits. Timer 1 : Timer/counter 1 stops

Semiconductor Group 6-20 1997-10-01

On-Chip Peripheral Components

C504

6.2.1.2 Mode 0

Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by-32 prescaler. Figure 6-12 shows the mode 0 operation.

In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1 (setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the special function register TCON; Gate is in TMOD.

The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers.

Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR0, TF0, TH0, TL0 and INT0 for the corresponding timer 1 signals in figure 6-12. There are two different gate bits, one for timer 1 (TMOD.7) and one for timer 0 (TMOD.3).

÷ 12

C/T = 0

C/T = 1

Control

TR0

P3.4/T0

Gate

P3.2/INTO

OSC

Figure 6-12 Timer/Counter 0, Mode 0: 13-Bit Timer/Counter

TL0 TH0

Bits) Bits)(8

TF0

Interrupt

MCS02583

Semiconductor Group 6-21 1997-10-01

On-Chip Peripheral Components

C504

6.2.1.3 Mode 1

Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure 6-13.

÷ 12

TR0

C/T = 0

C/T = 1

MCS02095

P3.4/T0

Gate

P3.2/INTO

OSC

Figure 6-13 Timer/Counter 0, Mode 1: 16-Bit Timer/Counter

Control

TL0 TH0

(8 Bits)

Interrupt

TF0

Semiconductor Group 6-22 1997-10-01

On-Chip Peripheral Components

C504

6.2.1.4 Mode 2

Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in figure 6-14. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged.

Figure 6-14 Timer/Counter 0,1, Mode 2: 8-Bit Timer/Counter with Auto-Reload

Semiconductor Group 6-23 1997-10-01

On-Chip Peripheral Components

C504

6.2.1.5 Mode 3

Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters. The logic for mode 3 on timer 0 is shown in figure 6-15. TL0 uses the timer 0 control bits: C/T, Gate, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the "timer 1" interrupt.

Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial channel as a baud rate generator, or in fact, in any application not requiring an interrupt from timer 1 itself.

P3.4/T0

Gate

P3.2/INT0

/12

OSC

TR1

OSC

÷ 12

TR1

C/T = 0

C/T = 1

OSC

/12

Control

TL0

(8 Bits)

TH0

(8 Bits)

Interrupt

TF0

Interrupt

TF1

MCS02096

Figure 6-15 Timer/Counter 0, Mode 3: Two 8-Bit Timers/Counters

Semiconductor Group 6-24 1997-10-01

On-Chip Peripheral Components

C504

6.2.2 Timer/Counter 2

Timer 2 is a 16-bit timer / counter which can operate as timer or counter. It has three operating modes:

– 16-bit auto-reload mode (up or down counting) – 16-bit capture mode – Baudrate generator (see 6.4.3 “Baud Rates“)

The modes are selected by bits in the SFR T2CON as shown in table 6-4:

Table 6-4 Timer/Counter 2 - Operating Modes

RCLK + TCLK CP/RL2 TR2 Mode

0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 X 1 Baud rate generator X X 0 (OFF)

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

In the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2 (P1.0). In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.

Semiconductor Group 6-25 1997-10-01

On-Chip Peripheral Components

6.2.2.1 Timer/Counter 2 Registers

Totally six special function registers control the timer/counter 0 and 1 operation :

– TL2/TH2 and RC2L/RC2H - counter and reload/capture registers, low and high part – T2CON and T2MOD - control and mode select registers

C504

Special Function Register TL2 (Address CCH) Reset Value : 00 Special Function Register TH2 (Address CDH) Reset Value : 00 Special Function Register RC2L (Address CAH) Reset Value : 00 Special Function Register RC2H (Address CBH) Reset Value : 00

Bit No.

MSB LSB

76543210

.7 .6 .5 .4CC

.7 .6 .5 .4CD

.7 .6 .5 .4CA

.7 .6 .5 .4CB

.3 .2 .1 .0

TL2

TH2.3 .2 .1 .0

RC2L.3 .2 .1 .0

RC2H.3 .2 .1 .0

H H H H

Bit Function

TL2.7-0 Timer 2 value low byte

The TL2 register holds the 8-bit low part of the 16-bit timer 2 count value.

TH2.7-0 Timer 2 value high byte

The TH2 register holds the 8-bit high part of the 16-bit timer 2 count value.

RC2L.7-0 Reload / capture timer 2 register low byte

RC2L holds the 8-bit low byte of the 16-bit timer 2 reload or capture value.

RC2H.7-0 Reload / capture timer 2 register high byte

RC2H holds the 8-bit high byte of the 16-bit timer 2 reload or capture value.

Semiconductor Group 6-26 1997-10-01

On-Chip Peripheral Components

C504

Special Function Register T2CON (Address C8H) Reset Value : 00

Bit No.

Bit Function

TF2 Timer 2 Overflow Flag

EXF2 Timer 2 External Flag

RCLK Receive Clock Enable

MSB LSB

76543210

TF2 EXF2 RCLK TCLKC8

Set by a timer 2 overflow. Must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1.

Set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1, SFR T2MOD)

When set, causes the serial port to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. RCLK = 0 causes timer 1 overflows to be used for the receive clock.

T2CONEXEN2 TR2 C/T2 CP/RL2

TCLK Transmit Clock Enable

When set, causes the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. TCLK = 0 causes timer 1 overflow to be used for the transmit clock.

EXEN2 Timer 2 External Enable

When set, allows a capture or reload to occur as a result of a negative transition on pin T2EX (P1.1) if timer 2 is not being used to clock the serial port. EXEN2 = 0 causes timer 2 to ignore events at T2EX.

TR2 Start / Stop Control for Timer 2

TR2 = 1 starts timer 2.

C/T2

CP/RL2

Timer or Counter Select for Timer 2 C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).

Capture /Reload Select CP/RL2 = 1 causes captures to occur an negative transitions at pin T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when timer 2 overflows or negative transitions occur at pin T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on timer 2 overflow.

Semiconductor Group 6-27 1997-10-01

On-Chip Peripheral Components

C504

Special Function Register T2MOD (Address C9H) Reset Value : XXXX XXX0

Bit No.

Bit Function

– Not implemented, reserved for future use. DCEN When set, this bit allows timer 2 to be configured as an up/down counter.

6.2.2.1 Auto-Reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by a bit named DCEN (Down Counter Enable, SFR T2MOD, 0C9H). When DCEN is set, timer 2 can count up or down depending on the value of pin T2EX (P1.1).

MSB LSB

76543210

––––C9

– – – DCEN

T2MOD

Figure 6-16 shows timer 2 automatically counting up when DCEN = 0. In this mode there are two

options selectable by bit EXEN2 in SFR T2CON.

Semiconductor Group 6-28 1997-10-01

On-Chip Peripheral Components

C504

Figure 6-16 Timer 2 Auto-Reload Mode (DCEN = 0)

If EXEN2 = 0, timer 2 counts up to FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RC2H and RC2L. The values in RC2H and RC2L are preset by software.

If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at the external input T2EX (P1.1). This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an timer 2 interrupt if enabled.

Setting the DCEN bit enables timer 2 to count up or down as shown in figure 6-17. In this mode the T2EX pin controls the direction of count.

Semiconductor Group 6-29 1997-10-01

On-Chip Peripheral Components

C504

Figure 6-17 Timer 2 Auto-Reload Mode (DCEN = 1)

A logic 1 at T2EX makes timer 2 count up. The timer will overflow at FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RC2H and RC2L to be reloaded into the timer registers, TH2 and TL2, respectively.

A logic 0 at T2EX makes timer 2 count down. Now the timer underflows when TH2 and TL2 equal the values stored in RC2H and RC2L. The underflow sets the TF2 bit and causes FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever timer 2 overflows or underflows. This bit can be used as a 17th bit of resolution if desired. In this operating mode, EXF2 does not flag an interrupt.

Note: P1.1/T2EX is sampled during S5P2 of every machine cycle. The next increment/decrement of timer 2 will be done during S3P1 in the next cycle.

Semiconductor Group 6-30 1997-10-01

On-Chip Peripheral Components

C504

6.2.2.2 Capture

In the capture mode there are two options selected by bit EXEN2 in SFR T2CON. If EXEN2 = 0, timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in SFR T2CON.

This bit can be used to generate an interrupt. If EXEN2 = 1, timer 2 still does the above, but with added feature that a 1-to-0 transition at external

input T2EX causes the current value in TH2 and TL2 to be captured into RC2H and RC2L, respectively. In addition, the transition at T2EX causes bit EXF2 in SFR T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in figure 6-18.

Figure 6-18 Timer 2 in Capture Mode

The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1 in SFR T2CON. It will be described in conjunction with the serial port.

Semiconductor Group 6-31 1997-10-01

On-Chip Peripheral Components

C504

6.3 Capture / Compare Unit (CCU)

The Capture / Compare Unit (CCU) of the C504 has been designed for applications which have a demand for digital signal generation and/or event capturing (e.g. pulse width modulation, pulse width measuring). It consists of a 16-bit 3-channel capture/compare unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP).

In compare mode, the CAPCOM unit provides two output signals per channel, which can have inverted signal polarity and non-overlapping pulse transitions. The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals. For motor control applications, both units (CAPCOM and COMP) may generate versatile multichannel PWM signals. For brushless DC motors dedicated control modes are supported which are either controlled by software or by hardware (hall sensors).

Figure 6-18 Block Diagram of the Capture/Compare Unit CCU

Semiconductor Group 6-32 1997-10-01

On-Chip Peripheral Components

C504

6.3.1 General Capture/Compare Unit Operation

The compare timer 1 and 2 are free running, processor clock coupled 16-bit / 10-bit timers which have each a count rate with a maximum of its possible compare output signal waveforms are shown in figure 6-19.

Compare Timer 1 Operating Mode 0 a) Standard PWM (Edge Aligned) b) Standard PWM (Single Edge Aligned)

OSC

/2 up to

/256. The compare timer operations with

OSC

with programmable dead time ( )

OFF

Period Value

Compare Value

0000

CC COUT

Compare Timer 1 Operating Mode 1

Symetrical PWM (Center Aligned)

Period Value

Compare Value

Offset

OFF

CC COUT

Symetrical PWM (Center Aligned)d) with programmable dead time ( )

OFF

Period Value

Compare Value

0000

CC COINI=0

COUT COINI=1

: Interrupts can be generated

Compare Value

Offset

CC COINI=0

COUT COINI=1

OFF

MCT03356

Figure 6-19 Basic Operating Modes of the CAPCOM Unit

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On-Chip Peripheral Components

C504

Both compare timers start counting upwards from 0000H up to a count value stored in the period registers. If the value stored in the period register is reached, they are reset (operating mode 0, both compare timers) or the count direction is changed from up-counting to down-counting (operating mode 1, only compare timer 1). Using operating mode 0, edge aligned PWM signals can be generated. Using operating mode 1, center aligned PWM signals can be generated. Compare timer 1 can be programmed for both operating modes while compare timer 2 always works in operating mode 0 with one output signal COUT3. Figure 6-19 a) and c) shows the function of these basic operating modes.

Compare timer 1 has an additional 16-bit offset register, which consists of the high byte stored in CT1OFH and the low byte stored in CT1OFL. If the value stored in CT1OFF is 0, the compare timer operates as shown in figure 6-19 a) and c). If the value stored in CT1OFF is not zero, the compare timer operates as shown in figure 6-19 b) and d). In operating mode 0, compare timer 1 is always reset after its value has been equal to the value stored in period register. In operating mode 1, the count direction of the compare timer is changed from up- to down-counting when its value has reached the value stored in the period register. The count direction is changed from down- to up-counting when the compare timer value has reached 0000H. Generally, the compare outputs CCx are always assigned to a match condition with the compare timer value directly while the compare outputs COUTx are assigned to a match condition with the compare timer value plus the offset value. Therefore, signal waveforms with non-overlapping signal transitions as shown in figure 6-19 b) and d) can be generated. Further, the initial logic output level of the CAPCOM channel outputs when used in compare mode can be selected. This allows to generate waveforms with inverting signal polarities. In capture mode of the CAPCOM unit, the value of compare timer 1 is stored in the capture registers if a signal transition occurs at pins CCx.

The compare unit COMP is a 10-bit compare unit which can be used to generate a pulse width modulated signal. This PWM output signal drives the output pin COUT3. In burst mode and in the PWM modes the output of the COMP unit can be switched to the COUTx outputs.

The block commutation control logic allows to generate versatile multi-channel PWM output signals. In one of theses modes, the block commutation mode, signal transitions at the three external interrupt inputs are used to trigger the PWM signal generation logic. Depending on these signal transitions, the six I/O lines of the CAPCOM unit, which are decoupled in block commutation mode from the three capture/compare channels, are driven as static or PWM modulated outputs. CAPCOM channel 0 can be used in block commutation mode for a capture operation (speed measurement) which is triggered by each transition at the external interrupt inputs. Further, the multi-channel PWM mode signal generation can be also triggered by the period of compare timer 1. These operating modes are referenced as multi-channel PWM modes.

Using the CTRAP passive state (defined in COINI register) and released again.

The CCU unit has four main interrupt sources with their specific interrupt vectors. Interrupts can be generated at the compare timer 1 period match or count-change events, at the compare timer 2 period match event, at a CAPCOM compare match or capture event, and at a CAPCOM emergency event. An emergency event occurs if an active CTRAP signal is detected or if an error condition in block commutation mode is detected. All interrupt sources can be enabled/disabled individually.

input signal of the C504, the compare outputs can be put immediately into their

Semiconductor Group 6-34 1997-10-01

On-Chip Peripheral Components

C504

6.3.2 CAPCOM Unit Operation

6.3.2.1 CAPCOM Unit Clocking Scheme

The CAPCOM unit is basically controlled by the 16-bit compare timer 1. Compare timer 1 is the timing base for all compare and capture capabilities of the CAPCOM unit. The input clock for compare timer 1 is directly coupled to the system clock of the C504. Its frequency can be selected via three bits of the CT1CON register in a range of

For the understanding of the following timing diagrams, figure 6-20 shows the internal clocking scheme of the CAPCOM unit. The internal input clock of the CAPCOM unit is a symmetrical clock with 50% duty cycle. The clock transitions (edges) of the CAPCOM internal input clock are used for different actions: at clock edge 1 the compare timer 1 is clocked to the next count value, and with clock edge 2 the compare outputs CCx and COUTx are toggled/set to the new logic level if required.

OSC

/2 up to

OSC

/256.

Figure 6-20 CAPCOM Unit Clocking Scheme

Generally, the CAPCOM clocking scheme shown above is also valid for the COMP (compare timer 2) unit.

Semiconductor Group 6-35 1997-10-01

On-Chip Peripheral Components

6.3.2.2 CAPCOM Unit Operating Mode 0 Figure 6-21 shows the CAPCOM unit timing in operating mode 0 in detail.

CT1 Value CCP = 7 Period Reg.

Offset Reg. CT1OFF = 0

Start of CT1 (CC = 0)

C504

Time

Duty Cycles: 100%

(CC = 1)

(CC = 4)

CC or COUT

COINI Bit is "0"

CC or COUT

COINI Bit is "1"

CC CCP CT1O

(CC = 7)

(Active High Signals)

(CC > 7) "0"

(CC = 0)

(CC = 1)

(CC = 4)

(CC = 7)

(Active Low Signals)

(CC > 7)

: Content of the CC H / CC L Compare Registers : Content of the CCPH / CCPL Period Register : Content of the CT1OFH / CT1OFL Offset Register

"1"

87.5%

50%

12.5%

100%

87.5%

50%

12.5%

MCT03357

Figure 6-21 Compare Timer 1 Mode 0

In the example above compare timer 1 counts from 0000H up to 0007H (value stored in CCPH/ CCPL). The offset registers CT1OFH/CT1OFL have a value of 0000H. If programmed in compare mode, two output signals are assigned to the related CAPCOM channel x : CCx and COUTx. The mode select bits in the SFRs CMSEL0 and CMSEL1 define which of these two outputs will be

Semiconductor Group 6-36 1997-10-01

On-Chip Peripheral Components

C504

controlled by the CAPCOM channel. In figure 6-21 only the CCx signal is shown, but the same or the inverted waveform can be generated at the COUTx outputs.

After reset all CCx/COUTx pins are at high level, driven by a weak pullup. With the programming of the CMSEL1 or CMSEL0 registers, all affected compare outputs are switched to push-pull mode and start driving an initial level which is defined by the bits in SFR COINI. In figure 6-21 the upper five waveforms are assigned to a CCx pin with the appropriate bit in COINI cleared while the lower five waveforms are assigned to a CCx pin with the appropriate bit in COINI set.

When the count value of the compare timer 1 is incremented and the new value matches with the value stored in the corresponding compare register, the related compare output changes its logic state. When the compare timer is reset to 0000H the related compare output changes its logic state again. With the scheme shown in figure 6-21 output waveforms with duty cycles between 0% and 100% can be generated. For a compare register value of 0000H the output will remain at high level (COINI bit = 0) or low level (COINI bit = 1) representing a duty cycle of 100%. If the value stored in the compare register is higher than the value of the period register, a low level (COINI bit = 0) or high level (COINI bit = 1) corresponds to a duty cycle of 0%.

Figure 6-22 shows the waveform generation in operating mode 0 when the offset register has a value which is not equal 0000H (example: CT1OFH/CT1OFL = 0002H). Using compare timer 1 with an offset value not equal 0 is used to generate single edge aligned signals with a constant delay between one of the two signal transitions.

Compare timer 1 always counts from 0000H up to the value stored in CCP, also if the value in the offset register is not equal 0. With reset (count value 0000H) of the compare timer 1 the CCx and COUTx will always change their logic state. During the up-counting phase CCx will change the logic state when the compare timer value is equal to the compare register value and COUTx will change the logic state when the compare timer value plus the offset value matches the value stored in the compare register.

In figure 6-22 the waveforms a) and b) show an example for a waveform of two signals with a constant delay of their rising edge. A compare register value of 3 is assumed. Using inverted signal polarity (SFR COINI), signal c) can be generated at COUTx. If the value in the offset register plus the value of the period register is less than or equal to the value stored in the compare register, a static “1“ or a static “0“ (depending on COINI content) will be generated at COUTx (see figure 6-22 d) and e)). Therefore, CCx will also stay at a static level if the compare register value is greater than the value stored in the period register.

Semiconductor Group 6-37 1997-10-01

On-Chip Peripheral Components

C504

Figure 6-22 Compare Timer 1 with Offset not equal 0 - Mode 0

Semiconductor Group 6-38 1997-10-01

On-Chip Peripheral Components

C504

6.3.2.3 CAPCOM Unit Operating Mode 1

Using compare timer 1 in operating mode 1, two symmetric output signals with constant dead time

at each signal transition can be generated per channel. Figure 6-23 shows the operating

OFF

mode 1 timing in detail.

Figure 6-23 Compare Timer 1 with Offset # 0 (Dead Time) - Mode 1

In the example above compare timer 1 counts from 0000H up to 0007H (value stored in period register CCPH/CCPL) and then counts down again to 0000H. The maximum and minimum (0000H) values of the compare timer 1 occur always once in the count value sequence. In the example shown in figure 6-23, the offset registers have a value of 0002H.

With the programming of the CMSEL1 or CMSEL0 registers, all affected compare outputs are switched to push-pull mode and start driving an initial level which is defined by the bits in SFR COINI.

Equal to operating mode 0, two compare output signals are assigned to the related CAPCOM channel: CCx and COUTx. The compare outputs CCx change their state if a match of compare timer 1 content and the corresponding compare register occurs. The compare outputs COUTx change their state when a match of compare timer 1 content plus the value stored in the offset registers and the corresponding compare register has occurred. If the value in the offset register plus the value of the period register is less than or equal to the value stored in the compare register, a static “1“ or a static “0“ (depending on COINI content) will be generated at COUTx. In the same way, CCx will also stay at a static level is the compare register value is greater than the value stored in the period register.

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On-Chip Peripheral Components

C504

6.3.2.4 CAPCOM Unit Timing Relationships

Depending on the operating mode of the compare timer 1, compare output signals can be generated with a maximum period and resolution as shown in figure 6-24. This example also demonstrates the reloading of the compare and period registers which occurs when compare timer 1 reaches the count value 0000H.

Figure 6-24 Maximum Period and Resolution of the Compare Timer 1 Unit

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C504

Table 6-5 shows the resolution and the period value range which depend on the selected compare

timer 1 input clock prescaler ratio.

Table 6-5 Resolution and Period of the Compare Timer 1 (at f

= 40 MHz)

OSC

Compare Timer 1

Operating Mode 0 Operating Mode 1 Resolution Period Resolution Period

Input Clock

OSC

/ 2 / 4 / 8 / 16 / 32 / 64 / 128 / 256

50 ns 100 ns 200 ns 400 ns 800 ns

1.6 µs

3.2 µs

6.4 µs

100ns - 3.28 ms 200 ns - 6.55 ms 400 ns - 13.11 ms 800 ns - 26.21 ms

1.6 µs - 52.43 ms

3.2 µs - 104.86 ms

6.4 µs - 209.72 ms

12.8 µs - 419.43 ms

50 ns 100 ns 200 ns 400 ns 800 ns

1.6 µs

3.2 µs

6.4 µs

200 ns - 6.55 ms 400 ns - 13.11 ms 800 ns - 26.21 ms

1.6 µs - 52.43 ms

3.2 µs - 104.86 ms

6.4 µs - 209.71 ms

12.8 µs - 419.42 ms

25.6 µs - 838.85 ms

Compare timer 1 period and duty cycle values can be calculated using the formulas below. In these formulas the following abbreviations are used :

pv = period value, stored in the period registers CCPH/CCPL ov = offset value, stored in the offset registers CT1OFH/CT1OFL cv = compare value, stored in the capture/compare registers CCHx/CCLx

Operating Mode 0 :

Duty cycle of CCx outputs =

Duty cycle of COUTx outputs =

Operating Mode 1 :

Duty cycle of CCx outputs =

Duty cycle of COUTx outputs =

Period value = pv + 1

Period value = 2 x pv

pv + 1

cv - ov pv + 1

cv - ov

x 100 %

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C504

6.3.2.5 Burst Mode of CAPCOM / COMP Unit

In the burst mode, both units of the CCU are combined in a way that the CAPCOM outputs COUTx or CCx and COUTx (controlled by bit BCMP in SFR BCON) are modulated by the output signal of the COMP unit. Using the burst mode, the CAPCOM unit operates in compare mode and the COMP unit provides a PWM signal which is switched to the COUTx outputs. This PWM signal typically has a higher frequency than the compare output signal of the CAPCOM unit. Figure 6-25 shows the waveform generation using the burst mode.

Figure 6-25 Burst Mode Operation

The burst mode of a COUTx output is enabled by the bit CMSELx3 which is located in the mode select registers CMSEL0 and CMSEL1. Figure 6-25 shows four CAPCOM output signals with different initial logic states with burst mode disabled (CMSELx3=0) and burst mode enabled (CMSELx3=1). Generally, the CCx outputs cannot operate in burst mode. Optionally, the signal at COUTx may have inverted polarity than the PWM signal which is available at pin COUT3.

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Depending on the corresponding initial compare output level bit in COINI, either a low or high level for the non-modulated state at the COUTx pins can be selected. Burst mode can be enabled in both operating modes of the compare timer 1. The burst mode as shown in figure 6-25 is only valid if the block commutation mode of the CCU is disabled (bit BCEN of SFR BCON cleared).

The modulation of the compare output signals at COUTx is switched on (COUT3 signal is switched to COUTx) when the compare timer 1 content plus the value stored in the compare timer 1 offset register is equal or greater than the value stored in the compare register of CAPCOM channel x.

6.3.2.6 CAPCOM Unit in Capture Mode

The three channels of the CAPCOM unit can be individually programmed to operate in capture mode. In capture mode each CAPCOM channel offers one capture input at pin CCx. Compare timer 1 runs either in operating mode 0 or 1. A rising or/and falling edge at CCx will copy the actual value of the compare timer 1 into the compare/capture registers. Interrupts can be generated selectively at each transition of the capture input signal.

The capture mode is selected by writing the mode select registers CMSEL1 and CMSEL0 with the appropriate values. The bit combinations in CMSEL0 and CMSEL1 also define the signal transition type (falling/rising edge) which generates a capture event. If a CAPCOM channel is enabled for capture mode, its CCx input is sampled with 2/t

Consecutive capture events, generated through signal transitions at a CCx capture input, overwrite the corresponding 16-bit compare/capture register contents. This must be regarded when successive signal transitions are processed.

CLCL

(= f

/2 = half external CPU clock rate).

OSC

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On-Chip Peripheral Components

C504

6.3.2.7 Trap Function of the CAPCOM Unit in Compare Mode

When a channel of the CAPCOM unit operates in compare mode its output lines can be decoupled in trap mode from the CAPCOM pulse generation. The trap mode is controlled by the external signal CTRAP. The CTRAP signal is sampled once each 2nd oscillator clock cycle. If a low is detected, the trap flag TRF of register TRCON is set and CCx or COUTx compare outputs are switched immediately to the logic (inactive) state as defined by the bits in COINI. If CT1RES = 0, compare timer 1 continues its operation but no compare output signal will be generated. If CT1RES = 1, compare timer 1 is reset when CTRAP becomes active. When CTRAP is sampled inactive (high) again, the compare channel outputs are synchronously switched to the compare channel output signal generation when compare timer 1 has reached the count value 0000H.

The trap function is controlled by bits in the TRCON register. The general enable function of the external CTRAP signal is controlled by one bit (TRPEN). Further, each CAPCOM compare channel output can be enabled/disabled selectively for trap function.

Figure 6-26 shows the trap function for the two outputs CCx and COUTx of one compare channel x. The timing diagram implies that the trap function is enabled at the CCx and COUTx outputs.

At reference point 1) in figure 6-26 CTRAP becomes active and at reference point 2) the trap state is released again synchronously to the compare timer 1 count state 0000H. If the trap function is enabled and CTRAP becomes active, bit TRF (trap flag) in SFR TRCON is set and a CCU emergency interrupt will be generated if the related interrupt enable bits are set. The flag TRF is level sensitive and must be cleared by software.

The trap function used in block commutation mode differs from the trap function described above. Especially the synchronization scheme is different (see section 6.3.4.6).

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Note : The state of the CCx and COUTx signals in trap state is defined by the

corresponding bits in COINI.

Figure 6-26 Trap Function of the CAPCOM Unit

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On-Chip Peripheral Components

C504

6.3.2.8 CAPCOM Registers

The CAPCOM unit of the C504 contains several special function registers. Table 6-6 gives an overview of the CAPCOM related registers.

Table 6-6 Special Function Registers of the CAPCOM Unit

Unit Symbol Description Address

CAPCOM Capture / Compare Unit

The following sections describe the CAPCOM registers in detail.

Writing the CAPCOM Period/Offset/Compare Registers on-the-Fly

CT1CON CCPL CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 CCIR CCIE COINI TRCON

Compare timer 1 control register Compare timer 1 period register, low byte Compare timer 1 period register, high byte Compare timer 1 offset register, low byte Compare timer 1 offset register, high byte Capture/compare mode select register 0 Capture/compare mode select register 1 Capture/compare register 0, low byte Capture/compare register 0, high byte Capture/compare register 1, low byte Capture/compare register 1, high byte Capture/compare register 2, low byte Capture/compare register 2, high byte Capture/compare interrupt request flag register Capture/compare interrupt enable register Compare output initialization register Trap enable register

E1 DE DF E6 E7 E3 E4 C2 C3 C4 C5 C6 C7 E5 D6 E2 CF

H H H H H H H H H H H H H H

If compare timer 1 is running, period, offset or compare registers can be written with modified values for generating new periods or duty cycles of the compare output signals. For proper synchronization purposes a special mechanism for updating of the 16-bit offset, period, and compare registers is implemented in the C504. This mechanism is based on shadow latches. When new values for offset, period, or compare registers have been written into the shadow latches, the real register update operation must be initiated by setting bit STE1 (shadow transfer enable) in SFR CT1CON. When this bit is set, the content of the shadow latches is transferred to the real registers under the following conditions:

– Compare timer 1 operating mode 0 : Compare timer 1 has reached the period value stored

in the CCPH/CCPL registers

– Compare timer 1 operating mode 1 : Compare timer 1 has reached the count value 0000

When the register transfer has been executed, STE1 is reset by hardware. So the software can recognize when the register transfer has occurred.

When compare timer 1 is started by setting the run bit CT1R the first time after reset, a shadow register transfer into the real registers is automatically executed. In this case STE1 must not be set.

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On-Chip Peripheral Components

C504

Compare Timer 1 Control Register

The 16-bit compare timer 1 is controlled by the bits of the CT1CON register. With this register the count mode, the trap interrupt enable, the compare timer start/stop and reset, and the timer input clock rate is controlled.

Special Function Register CT1CON (Address E1H) Reset Value : 00010000

Bit No. MSB LSB

76543210

CTM ETRP

STE1

CT1RES CT1R CLK2 CLK1 CLK0E1

CT1CON

Bit Function

CTM Compare timer 1 operating mode selection

CTM=0 selects operating mode 0 (up count) and CTM=1 selects operating mode 1 (up/down count) for compare timer 1.

ETRP CCU emergency trap interrupt enable

If ETRP = 1, the emergency interrupt for the CCU trap signal is enabled.

STE1 CAPCOM unit shadow latch transfer enable

When STE1 is set, the content of the compare timer 1 period, compare and offset registers (CCPH, CCPL, CCHx, CCLx, CT1OFH, CT1OFL) is transferred to its real registers when compare timer 1 reaches the next time the period value (operating mode 0) or value 0000H (operating mode 1). After the shadow transfer event, STE1 is reset by hardware.

CLK2 CLK1 CLK0

Compare timer 1 input clock selection The input clock for the compare timer 1 is derived from the clock rate

OSC

of the C504 via a programmable prescaler. The following table shows the programmable prescaler ratios.

CLK2 CLK1 CLK0 Function

0 0 0 Compare timer 1 input clock is 0 0 1 Compare timer 1 input clock is 0 1 0 Compare timer 1 input clock is 0 1 1 Compare timer 1 input clock is 1 0 0 Compare timer 1 input clock is 1 0 1 Compare timer 1 input clock is 1 1 0 Compare timer 1 input clock is 1 1 1 Compare timer 1 input clock is

f f f f f f f f

OSC

/2 /4 /8 /16 /32 /64 /128 /256

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Bit Function

On-Chip Peripheral Components

C504

CT1RES CT1R

Compare timer 1 reset control Compare timer 1 run/stop control These two bits control the start, stop, and reset function of compare timer 1. CT1RES is used to reset the compare timer and CT1R is used to start and stop the compare timer 1. The following table shows the functions of these two bits :

CT1RES CT1R Function

0 0 Compare timer 1 is stopped and holds its value; the

compare outputs stay in the logic state as they are.

1 0 Compare timer 1 is stopped and reset; compare

outputs are set to the logic state as defined in SFR COINI (default after reset).

→ 1 Compare timer 1 starts. Before CT1R is set the first

time, the CMSEL register should be programmed (enable capture/compare functions).

→ 1 Compare timer 1 starts running from count value

0000H; compare outputs are set to the logic state as defined in SFR COINI.

Note for capture mode : Setting CT1R=0 and CT1RES=1 after a capture event will destroy the value stored in the capture register CCx. Therefore, CT1RES should be set to 0 in capture mode. Reason : if CT1R=0 and CT1RES=1 all shadow registers are transparent (switched directly) to the real registers.

Note : When software power down mode is entered with CT1RES bit of SFR CT1CON set, the

compare timer 1 is reset after the execution of a wake-up from power-down mode procedure. When CT1RES is cleared before software power down mode is entered and a wake-up from power-down mode procedure has been executed, the compare timer 1 is not reset. Depending on the state of bit CT1R at power down mode entry, the compare timer 1 either stops (CT1R=0) or continues (CT1R=1) counting after a wake-up from power-down mode procedure. Further details of the power down mode are described in chapter 9.2 .

→ 0 Compare timer 1 is stopped and holds its value; the

compare outputs drive their actual logic state.

→ 0 Compare timer 1 is stopped and reset to 0000

compare outputs are set to the logic state as defined in SFR COINI.

;

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On-Chip Peripheral Components

C504

Compare Timer 1 Period Registers

The compare timer 1 period registers CCPH and CCPL store the 16-bit value for the compare timer 1 count period. CCPH holds the high byte of the 16-bit period value and CCPL holds the low byte. If CCPH/CCPL is written, always shadow latches are loaded. The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value (operating mode 0) or count value 0000H (operating mode 1). When the compare timer 1 period registers are read, always shadow latches are accessed.

Special Function Register CCPL (Address DEH) Reset Value : 00 Special Function Register CCPH (Address DFH) Reset Value : 00

Bit No. MSB LSB

76543210

Bit Function

CCPL.7 - 0 Compare timer 1 period value low byte

CCPH.7 - 0 Compare timer 1 period value high byte

.7 .6 .5 .4 .3 .2 .1 LSBDE

MSB .6 .5 .4 .3 .2 .1 .0DF

The 8-bit value in the CCPL register is the low byte of the 16-bit period value of compare timer 1 (shadow latch).

The 8-bit value in the CCPH register is the high byte of the 16-bit period value of compare timer 1 (shadow latch).

CCPL

CCPH

H H

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On-Chip Peripheral Components

C504

Compare Timer 1 Offset Registers

The CT1OFH and CT1OFL registers contain the value for the compare timer 1. CT1OFH holds the high byte of the 16-bit offset value and CT1OFL holds the low byte. For the detection of a compare match event, which results in changing polarity of a COUTx compare output signal, the content of CT1OFH/CT1OFL is always added to the actual value of the compare timer 1: The value stored in the offset registers has no effect on the signal generation at the CCx compare outputs.

If the compare timer 1 offset registers are written, always shadow latches are loaded. The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value (operating mode 0) or count value 0000H (operating mode 1). When the compare timer 1 offset registers are read, always shadow latches are accessed.

Special Function Register CT1OFL (Address E6H) Reset Value : 00 Special Function Register CT1OFH (Address E7H) Reset Value : 00

Bit No. MSB LSB

76543210

Bit Function

CT1OFL.7 - 0 8-bit compare timer 1 offset value low byte

CT1OFH.7 - 0 8-bit compare timer 1 offset value high byte

.7 .6 .5 .4 .3 .2 .1 LSBE6

MSB .6 .5 .4 .3 .2 .1 .0E7

The 8-bit value in the CT1OFL register is the low part of the offset value for compare timer 1 (shadow latch).

The 8-bit value in the CT1OFH register is the high part of the offset value for compare timer 1 (shadow latch).

CT1OFL

CT1OFH

H H

In order to generate correct dead times for PWM signals the offset value stored in CT1OFH/ CT1OFL must be lower than the values stored in the compare registers !

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On-Chip Peripheral Components

C504

Capture/Compare Channel Mode Select Registers

The capture/compare channels of the CAPCOM unit can operate individually either in compare mode or in capture mode. The CMSEL0 and CMSEL1 registers contain the mode select bits for the CAPCOM unit.

Special Function Register CMSEL0 (Address E3H) Reset Value : 00 Special Function Register CMSEL1 (Address E4H) Reset Value : 00

Bit No. MSB LSB

76543210

CMSEL

CMSEL CMSEL

12 11

CAPCOM

Channel 1

CMSEL10CMSEL

CMSEL CMSEL CMSEL

02 01 00

CAPCOM

Channel 0

CMSEL0

76543210

ESMC NMCS 0 0

CMSEL

CMSEL CMSEL CMSEL

22 21 20

CMSEL1

CAPCOM

Channel 2

Bit Function

ESMC Enable software controlled multi-channel PWM modes

If ESMC=0, switching of the follower state in 4-/5-/6-phase multi-channel PWM mode is controlled by compare timer 1 reaching its period value. If ESMC=1, switching of the follower state in 4-/5-/6-phase multi-channel PWM mode is controlled by bit NMCS.

H H

NMCS Next multi-channel PWM state

Setting bit NMCS (with ESMC set) will select the follower state in the 4-/5-/6phase multi-channel PWM mode, which is taken into account at the output pins, when compare timer 1 is 0. Bit NMCS is reset by hardware in the next clock cycle after it has been set.

CMSELx3 x=0-2

Switching compare timer 2 output signal to COUTx If CMSELx3 is set and compare mode is selected for the outputs COUTx, the output signal of the 10-bit compare unit, typically a higher frequency signal, is switched (modulated) to the COUTx pin. The state of the corresponding COINI bit at the start of compare timer 1 defines the logic level of the CAPCOM channel output signal at iwhich the COMP output signal is output to COUTx. COINI is set : The COMP output is switched to COUTx during the low phase

of the CAPCOM channel X signal.

COINI is cleared : The COMP output is switched to COUTx during the high phase

of the CAPCOM channel X signal.

Semiconductor Group 6-51 1997-10-01

Bit Function

On-Chip Peripheral Components

C504

CMSELx2- 0 x=0-2

CAPCOM capture / compare mode enable bits The CMSEL registers are used to select/enable the operating mode and the output/input pin configuration of the capture/compare channels. Each CAPCOM channel can be programmed individually either for compare or capture operation.

CMSELx2CMSELx1CMSELx0Mode

0 0 0 Compare outputs disabled;

No compare output signal is generated; CCx and COUTx are normal I/O pins.

0 0 1 Compare output on pin CCx enabled;

COUTx is normal I/O pin.

0 1 0 Compare output on pin COUTx enabled;

CCx is normal I/O pin.

0 1 1 Compare outputs on pins CCx and COUTx

enabled.

1 0 0 Capture mode enabled; signal transitions at CCx

do not generate a capture event; COUTx is a normal I/O pin or analog input pin.

1 0 1 Capture mode enabled; CCx is configured as a

capture input and a rising edge at CCx transfers compare timer 1 content into the capture register; COUTx is a normal I/O pin or analog input pin.

1 1 0 Capture mode enabled; CCx is configured as a

capture input and a falling edge at CCx transfers compare timer 1 content into the capture register; COUTx is a normal I/O pin or analog input pin.

1 1 1 Capture mode enabled; CCx is configured as a

capture input. Rising and falling edge at CCx transfer the compare timer 1 content into the capture register; COUTx is a normal I/O pin or analog input pin.

Note : only CC0 / COUT0 can be analog inputs if not selected as compare output.

In compare mode the two output signals of a CAPCOM channel can be enabled selectively. In capture mode the type of signal transition which will generate a capture event can be chosen.

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On-Chip Peripheral Components

C504

Capture / Compare Registers of CAPCOM Unit

The capture/compare registers are 16-bit registers, organized as two 8-bit byte-wide registers. Each of the three CAPCOM channels has one capture/compare register. In compare mode they hold a compare value which typically defines the duty cycle of the output signals. In capture mode, the actual compare timer 1 value is transferred into the capture/compare registers at a capture event.

If CCLx/CCHx is written, always shadow latches are loaded. The content of these shadow latches is transferred to the real registers when STE1 is set and the compare timer 1 reaches its period value (operating mode 0) or count value 0000H (operating mode 1). When the capture/compare registers are read, always the real registers are accessed because of capture mode.

Special Function Registers CCL0/CCH0 (Addresses C2H/C3H) Reset Value : 00 Special Function Registers CCL1/CCH1 (Addresses C4H/C5H) Reset Value : 00 Special Function Registers CCL2/CCH2 (Addresses C6H/C7H) Reset Value : 00

Bit No. MSB LSB

76543210

.7 .6 .5 .4 .3 .2 .1 LSBC2

MSB .6 .5 .4 .3 .2 .1 .0C3

.7 .6 .5 .4 .3 .2 .1 LSBC4

MSB .6 .5 .4 .3 .2 .1 .0C5

.7 .6 .5 .4 .3 .2 .1 LSBC6

CCL0

CCH0

CCL1

CCH1

CCL2

H H H

MSB .6 .5 .4 .3 .2 .1 .0C7

Bit Function

CCLx.7 - 0 x=0-2

CCHx.7 - 0 x=0-2

Semiconductor Group 6-53 1997-10-01

Capture/compare value low byte The 8-bit value in the CCLx register is the low part of the 16-bit capture/ compare value of channel x.

Capture/compare value high byte The 8-bit value in the CCHx register is the low part of the 16-bit capture/ compare value of channel x.

CCH2

On-Chip Peripheral Components

C504

Capture / Compare Interrupt Request Flags / Register

The interrupt flags of the CAPCOM capture/compare match and compare timer 1 interrupt are located in the register CCIR. All CAPCOM capture/compare match interrupt flags are set by hardware and must be cleared by software. A capture/compare match interrupt is generated with the setting of a CCxR bit (x=0-2) if the corresponding enable bits are set. The compare timer 1 interrupt is triggered by the CT1FP or CT1FC bits of SFR CCIR.

Special Function Register CCIR (Address E5H) Reset Value : 00

Bit No. MSB LSB

76543210

CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0RE5

CAPCOM

Channel 2

Bit Function

CT1FP Compare timer 1 period flag

Compare timer 1 operating mode 0 : CT1FP is set if compare timer 1 reaches the period value. Compare timer 1 operating mode 1 : CT1FP is set if compare timer 1 reaches the period value and changes the count direction from up- to down counting. Bit CT1FP must be cleared by software. If compare timer 1 interrupt is enabled, the setting of CT1FP will generate a compare timer 1 interrupt.

CT1FC Compare timer 1 count direction change flag

This flag can only be set if compare timer 1 runs in operating mode 1 (CTM=1). CT1FC is set when compare timer 1 reaches count value 0000H and changes the count direction from down- to up-counting. If compare timer 1 interrupt is enabled, the setting of CT1FC will generate a compare timer 1 interrupt. Bit CT1FC must be cleared by software.

CAPCOM

Channel 1

CAPCOM

Channel 0

CCIR

CCxR x=0-2

Semiconductor Group 6-54 1997-10-01

Capture/compare match on up-count flag Capture Mode : CCxR is set at a low-to-high transition (rising edge) of the corresponding CCx capture input signal. Compare Mode : CCxR is set if the compare timer 1 value matches the compare register CCx value during the up-count phase.

Siemens C504 User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Pin Configuration

1.2 Pin Definitions and Functions

2 Fundamental Structure

2.1 CPU

2.2 CPU Timing

3 Memory Organization

3.1 Program Memory, "Code Space"

3.2 Data Memory, "Data Space"

3.3 General Purpose Registers

3.4 XRAM Operation

3.4.1 Reset Operation of the XRAM

3.5 Special Function Registers

4 External Bus Interface

4.1 Accessing External Memory

4.2 PSEN, Program Store Enable

4.4 ALE, Address Latch Enable

4.5 Enhanced Hooks Emulation Concept

4.6 ROM/OTP Protection for C504-2R / C504-2E

4.6.1 Unprotected ROM Mode

4.6.2 Protected ROM/OTP Mode

5 Reset and System Clock Operation

5.1 Hardware Reset Operation

5.2 Fast Internal Reset after Power-On

5.3 Hardware Reset Timing

5.4 Oscillator and Clock Circuit

6 On-Chip Peripheral Components

6.1 Parallel I/O

6.1.1 Port Structures

6.1.2 Standard I/O Port Circuitry Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each

6.1.2.1 Port 0 Circuitry

6.1.2.2 Port 1 and Port 3 Circuitry

6.1.2.3 Port 2 Circuitry

6.1.3 Detailed Output Driver Circuitry

6.1.3.1 Type B Port Driver Circuitry Figure 6-7 shows the output driver circuit of the type B multifunctional digital I/O port lines. The

6.1.3.2 Type C Port Driver Circuitry Figure 6-8 shows the port driver circuit of the type C mixed digital/analog I/O port lines of the C504.

6.1.3.3 Type D Port Driver Circuitry

6.1.3.4 Type E Port Driver Circuitry

6.1.4 Port Timing

6.1.5 Port Loading and Interfacing

6.1.6 Read-Modify-Write Feature of Ports 2 and 3

6.2 Timers/Counters

6.2.1 Timer/Counter 0 and 1

6.2.1.1 Timer/Counter 0 and 1 Registers

6.2.1.2 Mode 0

6.2.1.3 Mode 1

6.2.1.4 Mode 2

6.2.1.5 Mode 3

6.2.2 Timer/Counter 2

6.2.2.1 Timer/Counter 2 Registers

6.2.2.1 Auto-Reload (Up or Down Counter)

6.2.2.2 Capture

6.3 Capture / Compare Unit (CCU)

6.3.1 General Capture/Compare Unit Operation

6.3.2 CAPCOM Unit Operation

6.3.2.1 CAPCOM Unit Clocking Scheme

6.3.2.2 CAPCOM Unit Operating Mode 0 Figure 6-21 shows the CAPCOM unit timing in operating mode 0 in detail.

6.3.2.3 CAPCOM Unit Operating Mode 1

6.3.2.4 CAPCOM Unit Timing Relationships

6.3.2.5 Burst Mode of CAPCOM / COMP Unit

6.3.2.6 CAPCOM Unit in Capture Mode

6.3.2.8 CAPCOM Registers