Siemens C504 User Guide

C504

8-Bit CMOS Microcontroller

User's Manual 10.97

http://www.siemens.de/

Semiconductor/

.

Edition 1997-10-01

This edition was realized using the software system FrameMaker



Published by Siemens AG,
Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
81541 München

Siemens AG 1997.

©

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or

the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components
systems

2

with the express written approval of the Semiconductor Group of Siemens AG.

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or

1 A critical component is a component used in a life-support device or system whose failure can reasonably be

expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or

maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endan­gered.

C504 Data Sheet
Revision History : 1997-10-01

Previous Releases : 06.96 (Original Version)

General Information

C504

Page (new
version)

Page (prev.
version)

Subjects (changes since last revision)

general C504-2E OTP version included (new chapter 10)

C504-2E AC/DC characteristics are now in chapter 11

1-1
1-4
1-6
2-1
3-3, 3-4
3-11
3-85-2
4-6 to 4-8
5-4
5-6, 5-7
6-7

1-1
1-4
1-6
2-1
4-6, 4-7
–
5-1
4-8 to 4-10
5-3
–
6-7

Figure 1-1 completed
Figure 1-3 completed
RESET pin desc. : “..for the duration of two machine cycl...“ corrected
Figure 2-1 completed
Chapter 3.4 “XRAM Operation“ moved from chapter 4 to chapter 3
Version register information added
Figure 5-2 “Reset Circuitries“ added

Chapter 4.6/4.7 “ROM Protection ....“ enhanced for OTP verification

Figure 5-3/5-2 corrected
Chapter 5.4 “Oscillator and Clock Circuit“ added
Figure 6-5 corrected; modified sentence : “During this time, the P2

SFR remains unchanged while the P0 SFR has 1’s written to it.“
–
6-8

6-8
6-9

Figure 6-6 added

Figure 6-6/6-7 corrected; also text in paragraph “The pullup FET p1

of...“ 2nd sentence modified : “activated for one state...“
6-14
6-18
6-26
6-33
6-36
6-42
6-41
6-45
6-50
6-51
6-52
6-58
6-70
Ch.6.3.4
6-80, 6-81
7-3
7-14
9-1
11-2
11-3, 11-4
11-15 to

6-13
–
–
6-31
6-34
6-40
6-39
6-43
6-48
6-49
6-50
6-56
6-68
Ch.6.3.4
–
7-3
7-13
9-1
10-2
11-3
–

Figure 6-11/6-10 corrected

Timer 0/1 count register definitions added

Timer 2 count and reload/capture register definitions added

Figure 6-19 corrected

Figure 6-21 corrected

Sentence below table added

Invalid characters in formulas corrected (“x“)

Note in figure 6-26 below added

1. paragraph, 2nd line : ... or CCx and

COUTx .. added
Description of the two new CMSEL1 bits ESMC and NMCS added
CMSEL table : upper 4 lines “ or analog input pins...“ deleted, see note
Paragraph with active/passive state definition moved from 6-70/6-68
Text in last but one paragraph modified
New wording :“4-phase“ multi-channel PWM mode instead of “4-pole“..
New chapter 6.3.4.5 added
Figure 7-2/7-1b: address of bit EA in corrected
External interrupts : description of the TCON bits added
Corrected text in 1st paragraph : PCON/PCON1 have differert addr.

specification added

V

PP

New improved I

specification added

CC

AC charcteristics of programming mode added

11-18
Ch.12
several

Ch.11
several

Improved index with bold page numbers for main reference pages
Writing errors corrected

Semiconductor Group I-3

General Information

C504

Table of Contents Page

1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2 Pin Definitions and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

3 Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 Data Memory, "Data Space". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.3 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.4 XRAM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4.1 Reset Operation of the XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode). . . . . . . . . . . . . . . . 3-4

3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode). . . . . . . . . 3-4

3.5 Special Function Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

4 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Accessing External Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 PSEN

4.3 Overlapping External Data and Program Memory Spaces. . . . . . . . . . . . . . . . . . . . 4-2

4.4 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.5 Enhanced Hooks Emulation Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.6 ROM/OTP Protection for C504-2R / C504-2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.6.1 Unprotected ROM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.6.2 Protected ROM/OTP Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

5 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Hardware Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.3 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.4 Oscillator and Clock Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.2 Standard I/O Port Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.1.2.1 Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.1.2.2 Port 1 and Port 3 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.1.2.3 Port 2 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.1.3 Detailed Output Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.1.3.1 Type B Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.1.3.2 Type C Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

6.1.3.3 Type D Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

6.1.3.4 Type E Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

6.1.4 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.1.5 Port Loading and Interfacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Semiconductor Group I-1 1997-10-01

General Information

C504

Table of Contents Page

6.1.6 Read-Modify-Write Feature of Ports 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

6.2 Timers/Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

6.2.1 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

6.2.1.1 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

6.2.1.2 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

6.2.1.3 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

6.2.1.4 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23

6.2.1.5 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24

6.2.2 Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25

6.2.2.1 Timer/Counter 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26

6.2.2.2 Auto-Reload (Up or Down Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

6.2.2.3 Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31

6.3 Capture / Compare Unit (CCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32

6.3.1 General Capture/Compare Unit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33

6.3.2 CAPCOM Unit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35

6.3.2.1 CAPCOM Unit Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35

6.3.2.2 CAPCOM Unit Operating Mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36

6.3.2.3 CAPCOM Unit Operating Mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39

6.3.2.4 CAPCOM Unit Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40

6.3.2.5 Burst Mode of CAPCOM / COMP Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42

6.3.2.6 CAPCOM Unit in Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43

6.3.2.7 Trap Function of the CAPCOM Unit in Compare Mode . . . . . . . . . . . . . . . . . . . . . 6-44

6.3.2.8 CAPCOM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46

6.3.3 Compare (COMP) Unit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-61

6.3.3.1 COMP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62

6.3.4 Combined Multi-Channel PWM Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67

6.3.4.1 Control Register BCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68

6.3.4.2 Signal Generation in Multi-Channel PWM Modes . . . . . . . . . . . . . . . . . . . . . . . . . 6-70

6.3.4.3 Block Commutation PWM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73

6.3.4.4 Compare Timer 1 Controlled Multi-Channel PWM Modes . . . . . . . . . . . . . . . . . . . 6-75

6.3.4.5 Software Controlled State Switching in Multi-Channel PWM Modes . . . . . . . . . . . 6-80

6.3.4.6 Trap Function in Multi-Channel Block Commutation Mode . . . . . . . . . . . . . . . . . . 6-81

6.4 Serial Interface (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-82

6.4.1 Multiprocessor Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83

6.4.2 Serial Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83

6.4.3 Baud Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-85

6.4.3.1 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-86

6.4.3.2 Using Timer 2 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87

6.4.4 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-89

6.4.5 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-92

6.4.6 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-95

6.5 10-bit A/D Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98

6.5.1 A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-98

6.5.2 A/D Converter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-100

6.5.3 A/D Converter Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-103

Semiconductor Group I-2 1997-10-01

General Information

C504

Table of Contents Page

6.5.4 A/D Conversion Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-104

6.5.5 A/D Converter Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-108

6.5.6 A/D Converter Analog Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-109

7 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1 Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.2 Interrupt Sources and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.3 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.3.1 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.3.2 Interrupt Prioritiy Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.3.3 Interrupt Request Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

7.4 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

7.5 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

7.6 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

8 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1 Programmable Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1.1 Refreshing the Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.1.2 Watchdog Reset and Watchdog Status Flag (WDTS) . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.2 Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.2.1 Detailed Description of the Oscillator Watchdog Unit. . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.2.2 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

9 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2 Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.2.1 Invoking Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.2.2 Exit from Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

10 OTP Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.3 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.4 Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.1 Basic Programming Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.2 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.5 Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

10.6 Lock Bits Programming / Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

10.7 Access of Version Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

11 Device Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.3 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

11.4 AC Characteristics for C504-L / C504-2R / C504-2E . . . . . . . . . . . . . . . . . . . . . . . 11-8

11.5 AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 . . . . . . . . . . . . . . . . 11-10

11.6 AC Characteristics for C504-L40 / C504-2R40 / C504-2E40 . . . . . . . . . . . . . . . . 11-12

11.7 AC Characteristics of Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16

Semiconductor Group I-3 1997-10-01

General Information

C504

Table of Contents Page

11.8 ROM/OTP Verification Characteristics for C504-2R / C504-2E . . . . . . . . . . . . . . 11-20

11.9 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23

12 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

13 Microelectronics Training Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1

Information on Literature
Semiconductor Group - Addresses

Semiconductor Group I-4 1997-10-01

Introduction

C504

1 Introduction

The C504 is a modified and extended version of the C501 Microcontroller. Its enhanced
functionality, especially the capture compare unit (CCU), allows to use the MCU in motor control
applications. Further, the C504 is compatible with the SAB 80C52/C501 microcontrollers and can
replace it in existing applications.

The C504-2R contains a non-volatile 16K × 8 read-only program memory, a volatile on-chip 512 × 8
read/write data memory, four 8-bit wide ports, three 16-bit timers/counters, a 16-bit capture/
compare unit, a 10-bit compare timer, a twelve source, two priority level interrupt structure, a serial
port, versatile fail save mechanisms, on-chip emulation support logic, and a genuine 10-bit A/D
converter. The C504-L is identical to the C504-2R, except that it lacks the on-chip program memory
The C504-2E is the OTP version in the C504 microcontroller with a 16Kx8 one-time programmable
(OTP) program memory.The term C504 refers to all versions within this documentation unless
otherwise noted.

Oscillator Watchdog

10-Bit ADC

Timer 2

16-Bit

Capture/Compare

Unit

10-Bit Compare Unit

On-Chip Emulation Support Module

Watchdog Timer

Figure 1-1
C504 Functional Units

256 x 8

T0

T1

XRAM

C500

Core

ROM/OTP

16 k x 8

RAM

256 x 8

8-Bit

USART

Port 0

Port 1

Port 2

Port 3

I/O

8-Bit Digital I/O
4-Bit Analog Inputs

I/O

8-Bit Digital I/O
4-Bit Analog Inputs

MCB02589

Semiconductor Group 1-1 1997-10-01

Listed below is a summary of the main features of the C504:

•

Fully compatible to standard 8051 microcontroller

•

Up to 40 MHz external operating frequency

•

16K byte on-chip program memory
– C504-2R: ROM version (with optional ROM protection)
– C504-2E: programmable OTP version
– C504-L : without on-chip program memory)
– alternatively up to 64K byte external program memory

•

256 × 8 RAM

•

256 × 8 XRAM

•

Four 8-bit ports, (2 ports with mixed analog/digital I/O capability)

•

Three 16-bit timers/counters (timer 2 with up/down counter feature)

•

Capture/compare unit for PWM signal generation and signal capturing

- 3-channel, 16-bit capture/compare unit

- 1-channel, 10-bit compare unit

•

USART

•

10-bit A/D Converter with 8 multiplexed inputs

•

Twelve interrupt sources with two priority levels

•

On-chip emulation support logic (Enhanced Hooks Technology

•

Programmable 15-bit Watchdog Timer

•

Oscillator Watchdog

•

Fast Power On Reset

•

Power Saving Modes

•

M-QFP-44 package

•

Temperature ranges: SAB-C504

SAF-C504
SAH-C504
SAK-C504

T

: 0 to 70 ° C

A

T

: – 40 to 85 ° C

A

T

: – 40 to 110 ° C (max. operating frequency.: TBD)

A

: – 40 to 125 ° C (max. operating frequency.: 12 MHz)

T

A

TM

Introduction

C504

)

Semiconductor Group 1-2 1997-10-01

Introduction

C504

Figure 1-2
Logic Symbol

Semiconductor Group 1-3 1997-10-01

1.1 Pin Configuration

This section describes the pin configration of the C504 in the P-MQFP-44 package.

EA

COUT3

P0.7 / AD7

C504-LM
C504-2RM
C504-2EM

ALE

P2.6 / A14

PSEN

P2.7 / A15

P2.5 / A13

22

21
20
19
18
17
16
15
14
13
12

1116

P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8

V

CC

V

SS

XTAL1
XTAL2
P3.7 / RD
P3.6 / WR / INT2

P0.3 / AD3

P0.2 / AD2

P0.1 / AD1

P0.0 / AD0

V

AREF

V

GND

P1.0 / AN0 / T2

P1.1 / AN1 / T2EX

P1.2 / AN2 / CC0

P1.3 / AN3 / COUT0

P1.4 / CC1

P0.6 / AD6

P0.5 / AD5

P0.4 / AD4

33 31 30 29 282726 25242332
34
35
36
37
38
39
40
41
42
43
44

2345 78 109

Introduction

C504

Figure 1-3
Pin Configuration (top view)

RESET

P1.6 / CC2

P1.5 / COUT1

P3.0 / RxD

P1.7 / COUT2

CTRAP

P3.1 / TxD

P3.3 / AN5 / INT1

P3.2 / AN4 / INT0

P3.5 / AN7 / T1

P3.4 / AN6 / T0

MCP02532

Semiconductor Group 1-4 1997-10-01

1.2 Pin Definitions and Functions

This section describes all external signals of the C504 with its function.

Table 1-1
Pin Definitions and Functions

Introduction

C504

Symbol Pin Number

(P-MQFP-44)

P1.0-P1.7 40-44,

1-3

40

41

42

43

44

1

2

3

I/O
*)

I/O

Function

Port 1

is an 8-bit bidirectional port. Port pins can be used for
digital input/output. P1.0 - P1.3 can also be used as analog
inputs of the A/D-converter. As secondary digital functions,
port 1 contains the timer 2 pins and the capture/compare
inputs/outputs. Port 1 pins are assigned to be used as
analog inputs via the register P1ANA.
The functions are assigned to the pins of port 1 as follows:
P1.0 / AN0 / T2 Analog input channel 0 /

input to counter 2

P1.1 / AN1 / T2EX Analog input channel 1 /

capture/reload trigger of timer 2 / up­down count

P1.2 / AN2 / CC0 Analog input channel 2 /

input/output of capture/compare
channel 0

P1.3 / AN3 / COUT0 Analog input channel 3 /

output of capture/compare channel 0

P1.4 / CC1 Input/output of capture/compare

channel 1

P1.5 / COUT1 Output of capture/compare

channel 1

P1.6 / CC2 Input/output of capture/compare

channel 2

P1.7 / COUT2 Output of capture/compare

channel 2

RESET 4 I

RESET

A high level on this pin for the duration of two machine
cycles while the oscillator is running resets the device. An
internal diffused resistor to
using only an external capacitor to

*) I = Input

O = Output

permits power-on reset

V

SS

.

V

CC

Semiconductor Group 1-5 1997-10-01

Table 1-1
Pin Definitions and Functions (cont’d)

Introduction

C504

Symbol Pin Number

(P-MQFP-44)

P3.0-P3.7 5, 7-13

5

7

8

9

10

11

12

13

I/O
*)

I/O

Function

Port 3

is an 8-bit bidirectional port. P3.0 (R × D) and P3.1 (T × D)
operate as defined for the C501. P3.2 to P3.7 contain the
external interrupt inputs, timer inputs, input and as an
additional optinal function four of the analog inputs of the
A/D-converter. Port 3 pins are assigned to be used as
analog inputs by the bits of SFR P3ANA.
P3.6/WR can be assigned as a third interrupt input. The
functions are assigned to the pins of port 3 as follows:
P3.0 / RxD Receiver data input (asynch.) or data

input/output (synch.) of serial
interface

P3.1 / TxD Transmitter data output (asynch.) or

clock output (synch.) of serial
interface

P3.2 / AN4 / INT0 Analog input channel 4 / external

interrupt 0 input / timer 0 gate control
input

P3.3 / AN5 / INT1 Analog input channel 5 / external

interrupt 1 input / timer 1 gate control
input

P3.4 / AN6 / T0 Analog input channel 6 / timer 0

counter input

P3.5 / AN7 / T1 Analog input channel 7 / timer 1

counter input

P3.6 / WR

P3.7 / RD RD control output; enables the

/ INT2 WR control output; latches the data

byte from port 0 into the external data
memory /
external interrupt 2 input

external data memory

CTRAP

*) I = Input

O = Output

Semiconductor Group 1-6 1997-10-01

6I

CCU Trap Input

With CTRAP = low the compare outputs of the CAPCOM
unit are switched to the logic level as defined in the COINI
register (if they are enabled by the bits in SFR TRCON).
CTRAP is an input pin with an internal pullup resistor. For
power saving reasons, the signal source which drives the
CTRAP input should be at high or floating level during
power-down mode.

Table 1-1
Pin Definitions and Functions (cont’d)

Introduction

C504

Symbol Pin Number

(P-MQFP-44)

XTAL2 14 – XTAL2

XTAL1 15 – XTAL1

P2.0-P2.7 18-25 I/O Port 2

I/O
*)

Function

Output of the inverting oscillator amplifier.

Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source, XTAL1
should be driven, while XTAL2 is left unconnected.
are no requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is
divided down by a divide-by-two flip-flop. Minimum and
maximum high and low times as well as rise/fall times
specified in the AC characteristics must be observed.

is a bidirectional I/O port with internal pullup resistors. Port
2 pins that have 1s written to them are pulled high by the
internal pullup resistors, and in that state can be used as
inputs. As inputs, port 2 pins being externally pulled low
will source current (
of the internal pullup resistors. Port 2 emits the high-order
address byte during fetches from external program
memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this
application it uses strong internal pullup resistors when
issuing 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 issues the
contents of the P2 special function register.

There

I

, in the DC characteristics) because

IL

PSEN

ALE 27 O The Address Latch Enable

*) I = Input

O = Output

Semiconductor Group 1-7 1997-10-01

26 O The Program Store Enable

output is a control signal that enables the external program
memory to the bus during external fetch operations. It is
activated every six oscillator periodes except during
external data memory accesses. Remains high during
internal program execution.

output is used for latching the low-byte of the address into
external memory during normal operation. It is activated
every six oscillator periodes except during an external data
memory access. When instructions are executed from
internal ROM (EA
by bit EALE in SFR SYSCON.

=1) the ALE generation can be disabled

Table 1-1
Pin Definitions and Functions (cont’d)

Introduction

C504

Symbol Pin Number

(P-MQFP-44)

I/O
*)

Function

COUT3 28 O 10-Bit compare channel output

This pin is used for the output signal of the 10-bit compare
timer 2 unit. COUT3 can be disabled and set to a high or
low state.

EA

29 I External Access Enable

When held at high level, instructions are fetched from the
internal ROM (C504-2R only) when the PC is less than
4000H.When held at low level, the C504 fetches all
instructions from external program memory.
For the C504-L this pin must be tied low.

P0.0-P0.7 30-37 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1s written to them float, and in that state can be used
as high-impendance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to
external program or data memory. In this application it
uses strong internal pullup resistors when issuing 1 s.
Port 0 also outputs the code bytes during program
verification in the C504-2R. External pullup resistors are
required during program (ROM) verification.

V

AREF

V

AGND

V

SS

V

CC

*) I = Input

O = Output

38 – Reference voltage for the A/D converter.
39 – Reference ground for the A/D converter.
16 – Ground (0V)
17 – Power Supply (+5V)

Semiconductor Group 1-8 1997-10-01

Fundamental Structure

C504

2 Fundamental Structure

The C504 basically is fully compatible to the architecture of the standard 8051 microcontroller
family. Especially it is functionally upward compatible with the SAB 80C52/C501 microcontrollers.
While maintaining all architectural and operational characteristics of the SAB 80C52/C501, the
C504 incorporates a genuine 10-bit A/D Converter, a capture/compare unit, a XRAM data memory
as well as some enhancements in the Timer 2 and Fail Save Mechanism Unit. Figure 2-1 shows a
block diagram of the C504.

V

CC

V

SS

XTAL1
XTAL2

Oscillator Watchdog

OSC & Timing

XRAM

256 x 8

RAM ROM/OTP

256 x 8

16 k x 8

RESET
ALE
PSEN
EA

COUT3
CTRAP

V

AREF

V

AGND

CPU

Timer 0

Timer 1

Timer 2

Interrupt Unit

USART

Capture/Compare Unit

A/D Converter 10-Bit

S & H

MUX

Port 0

Port 1

Port 2

Port 3

Emulation

Support

Logic

Port 0

8-Bit Digital I/O

Port 1

8-Bit Digital I/O
4-Bit Analog Inputs

Port 2

8-Bit Digital I/O

Port 3

8-Bit Digital I/O
4-Bit Analog Inputs

MCB02591

Figure 2-1
Block Diagram of the C504

Semiconductor Group 2-1 1997-10-01

Fundamental Structure

C504

2.1 CPU

The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three­byte instructions. With a 12-MHz crystal, 58% of the instructions execute in 1.0 µs (40 MHz: 300 ns).
The CPU (Central Processing Unit) of the C504 consists of the instruction decoder, the arithmetic
section and the program control section. Each program instruction is decoded by the instruction
decoder. This unit generates the internal signals controlling the functions of the individual units
within the CPU. They have an effect on the source and destination of data transfers and control the
ALU processing.
The arithmetic section of the processor performs extensive data manipulation and is comprised of
the arithmetic/logic unit (ALU), an A register, B register and PSW register.
The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the
control of the instruction decoder. The ALU performs the arithmetic operations add, substract,
multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic
operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)).
Also included is a Boolean processor performing the bit operations as set, clear, completement,
jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its
complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with
the result returned to the carry flag.
The program control section controls the sequence in which the instructions stored in program
memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to
be executed. The conditional branch logic enables internal and external events to the processor to
cause a change in the program execution sequence.

Accumulator

ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific
instructions, however, refer to the accumulator simply as A.

Program Status Word

The Program Status Word (PSW) contains several status bits that reflect the current state of the
CPU.

Semiconductor Group 2-2 1997-10-01

Fundamental Structure

C504

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

H

D7

CY AC

H

D6

H

D5

F0

H

D4

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations.
F0 General Purpose Flag
RS1

RS0

Register Bank select control bits

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07
0 1 Bank 1 selected, data address 08H-0F
1 0 Bank 2 selected, data address 10H-17
1 1 Bank 3 selected, data address 18H-1F

H

D3

H

D2

H

D1

H

D0

H

PSW

H
H
H
H

OV Overflow Flag

Used by arithmetic instruction.
F1 General Purpose Flag
P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

B Register

The B register is used during multiply and divide and serves as both source and destination. For
other instructions it can be treated as another scratch pad register.

Stack Pointer

The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH
and CALL executions and decremented after data is popped during a POP and RET (RETI)
execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in
the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin
a location = 08H above register bank zero. The SP can be read or written under software control.

Semiconductor Group 2-3 1997-10-01

Fundamental Structure

C504

2.2 CPU Timing

A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a phase 1
half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is
active. Thus, a machine cycle consists of 12 oscillator periods, numbered S1P1 (state 1, phase 1)
through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and
logically operations take place during phase 1 and internal register-to-register transfers take place
during phase 2.
The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases.
Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE
(address latch enable) signal are shown for external reference. ALE is normally activated twice
during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1.
Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction
register. If it is a two-byte instruction, the second reading takes place during S4 of the same
machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would
be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In
any case, execution is completed at the end of S6P2.
Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle
instruction.
Most C504 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only
instructions that take more than two cycles to complete; they take four cycles. Normally two code
bytes are fetched from the program memory during every machine cycle. The only exception to this
is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses
external data memory. During a MOVX, the two fetches in the second cycle are skipped while the
external data memory is being addressed and strobed. Figure 2-2 (c) and (d) show the timing for
a normal 1-byte, 2-cycle instruction and for a MOVX instruction.

Semiconductor Group 2-4 1997-10-01

Fundamental Structure

C504

Figure 2-2
Fetch Execute Sequence

Semiconductor Group 2-5 1997-10-01

Memory Organization

3 Memory Organization

The C504 CPU manipulates operands in the following four address spaces:

– up to 64 Kbyte of internal/external program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– 256 bytes of internal XRAM data memory
– a 128 byte special function register area

Figure 3-1 illustrates the memory address spaces of the C504.

C504

Figure 3-1
C504 Memory Map

Semiconductor Group 3-1 1997-10-01

Memory Organization

C504

3.1 Program Memory, "Code Space"

The C504-2R has 16 Kbytes of read-only program memory, while the C504-L has no internal
program memory. The C504-2E provides 16 Kbytes of OTP program memory. The program
memory can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C504 executes
out of internal ROM unless the program counter address exceeds 3FFFH. Locations 4000H through
FFFFH are then fetched from the external program memory. If the EA pin is held low, the C504
fetches all instructions from the external program memory.

3.2 Data Memory, "Data Space"

The data memory address space consists of an internal and an external memory space. The
internal data memory is divided into three physically separate and distinct blocks : the lower 128
bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area.
While the upper 128 bytes of data memory and the SFR area share the same address locations,
they are accessed through different addressing modes. The lower 128 bytes of data memory can
be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be
accessed through register indirect addressing; the special function registers are accessible through
direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers,
occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through
2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the
internal data memory address space, and the stack depth can be expanded up to 256 bytes.

The external data memory can be expanded up to 64 Kbytes and can be accessed by instructions
that use a 16-bit or an 8-bit address.

3.3 General Purpose Registers

The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose
registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program
status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the
PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or
interrupt service routines.

The 8 general purpose registers of the selected register bank may be accessed by register
addressing. With register addressing the instruction op code indicates which register is to be used.
For indirect addressing R0 and R1 are used as pointer or index register to address internal or
external memory (e.g. MOV @R0).

Reset initializes the stack pointer to location 07H and increments it once to start from location 08
which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one
register bank, the SP should be initialized to a different location of the RAM which is not used for
data storage.

H

Semiconductor Group 3-2 1997-10-01

Memory Organization

C504

3.4 XRAM Operation

The XRAM in the C504 is a memory area that is logically located at the upper end of the external
memory space, but is integrated on the chip. Because the XRAM is used in the same way as
external data memory the same instruction types must be used for accessing the XRAM.

The C504 maps 256 bytes of the external data space into the on-chip XRAM. Especially when using
the 8-bit addressing modes this could prevent access to the external memory extension and might
induce problems when porting software. Therefore, it is possible to enable and disable the on-chip
XRAM using the bit XMAP in SFR SYSCON. When the XRAM is disabled (default after reset), all
external data memory accesses will go to the external data memory area.

Special Function Register SYSCON (Address B1H) Reset Value : XX10XXX0

Bit No. MSB LSB

76543210

B1

H

Bit Function

– Not implemented. Reserved for future use.
XMAP Enable XRAM

––

The functions of the shaded bits are not described in this section.

XMAP=0 : XRAM disabled.
XMAP=1 : XRAM enabled.
If XRAM is enabled, 8-bit MOVX instructions using Ri always access the
internal XRAM and do not generate external bus cycles. If XRAM is
enabled, 16-bit MOVX instructions using DPTR, access the XRAM if the
address is in the range of FF00H to FFFFH and do not generate external
bus cycles in this address range.

EALE RMAP –

––

XMAP

SYSCON

B

3.4.1 Reset Operation of the XRAM

The content of the XRAM is not affected by a reset. After power-up the content is undefined, while
it remains unchanged during and after a reset as long as the power supply is not turned off. If a reset
occurs during a write operation to XRAM, the content of a XRAM memory location depends on the
cycle in which the active reset signal is detected (MOVX is a 2-cycle instruction):

Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected.
Reset during 2nd cycle : The old value in XRAM is overwritten by the new value.

After reset the access to the XRAM is disabled (bit XMAP of SYSCON = 0).

Semiconductor Group 3-3 1997-10-01

Memory Organization

C504

3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode)

The XRAM can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect
addressing. These instructions are:

– MOVX A, @DPTR (Read)
– MOVX @DPTR, A (Write)

Using these instructions with the XRAM disabled implies, that port 0 is used as address low/data
bus, port 2 for high address output, and two lines of port 3 (P3.6/WR/INT2, P3.7/RD) for control to
access up to 64 KB of external memory. If the XRAM is enabled and if the effective address stored
in DPTR is in the range of 0000H to FEFFH, these instruction will access external memory.

If XRAM is enabled and if the address is within FF00H to FFFFH, the physically internal XRAM of
the C504 will be accessed. External memory, which is located in this address range, cannot be
accessed in this case because no external bus cycles will generated. Therefore port 0, 2 and 3 can
be used as general purpose I/O if only the XRAM memory space is addressed by the user program.

3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode)

The C504 architecture provides also instructions for accesses to external data memory and XRAM
which use an 8-bit address (indirect addressing with registers R0 or R1). These instructions are:

– MOVX A, @Ri (Read)
– MOVX @Ri, A (Write)

Using these instructions with the XRAM disabled implies, that port 0 is used as address/data bus,
port 2 for high address output, and two lines of port 3 (P3.6/WR/INT2, P3.7/RD) for control. Normally
these instructions are used to access 256 byte pages of external memory.

If the XRAM is enabled these instruction will only access the internal XRAM. External memory
cannot be accessed in this case because no external bus cycle will be generated. Therefore port 0,
2 and 3 can be used as standard I/O, if only the internal XRAM is used.

Semiconductor Group 3-4 1997-10-01

Memory Organization

C504

3.5 Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions: the
standard special function register area and the mapped special function register area. Three special
function registers of the C504 (PCON1, P1ANA, P3ANA) are located in the mapped special function
register area. For accessing the mapped special function register area, bit RMAP in special function
register SYSCON must be set. All other special function registers of the C504 are located in the
standard special function register area.

Special Function Register SYSCON (Address B1H) Reset Value : XX10XXX0

Bit No. MSB LSB

76543210

B1

H

Bit Function

– Not implemented. Reserved for future use.
RMAP Special function register map bit

As long as bit RMAP is set, mapped special function registers can be accessed. This bit is not
cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed,
the bit RMAP must be cleared/set by software, respectively each.

––

The functions of the shaded bits are not described in this section.

RMAP = 0 : The access to the non-mapped (standard) special function

RMAP = 1 : The access to the mapped special function register area is

EALE RMAP –

register area is enabled.

enabled.

––

XMAP

SYSCON

B

There are also 128 directly addressable bits available within each SFR area (standard and mapped
SFR area). All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ...,
F8H, FFH) are bitaddressable.

The 63 special function register (SFR) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. The SFRs of the C504 are listed in table 3-1
and table 3-2. In table 3-1 they are organized in groups which refer to the functional blocks of the
C504. Table 3-2 illustrates the contents of the SFRs in numeric order of their addresses.

Semiconductor Group 3-5 1997-10-01

Memory Organization

C504

Table 3-1
Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B
DPH
DPL
PSW
SP

SYSCON

Interrupt
System

IEN0
IEN1
CCIE
IP0
IP1
ITCON

Ports P0

P1
P1ANA
P2
P3
P3ANA

A/D­Converter

ADCON0
ADCON1

ADDATH
ADDATL
P1ANA
P3ANA

Serial
Channels

PCON
SBUF
SCON

Timer 0/
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) X means that the value is undefined and the location is reserved

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
System Control Register

Interrupt Enable Register 0
Interrupt Enable Register 1

2)

Capture/Compare Interrupt Enable Reg.
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Trigger Condition Register

Port 0
Port 1

2)

Port 1 Analog Input Selection Register
Port 2
Port 3

2)

Port 3 Analog Input Selection Register
A/D Converter Control Register 0

A/D Converter Control Register 1
A/D Converter Data Register High Byte
A/D Converter Data Register Low Byte

2)

Port 1 Analog Input Selection Register

2)

Port 3 Analog Input Selection Register

2)

Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

E0
F0

83
82

D0

81
B1

A8

A9
D6

B8

B9
9A

80
90
90
A0
B0
B0

D8

DC
D9
DA
90
B0

87
99

98
88

8C
8D
8A
8B
89

H

H

H
H

H

H
H

H

H

H

H

H
H

H
H
H

H
H
H

H

H

H

H
H
H

H
H

H
H

H

H
H
H
H

1)

1)

1)

1)

1)

1)

1)

1) 4)

1)

1)

1) 4)

1

4)

4)

1)

1)

00

H

00

H

00

H

00

H

00

H

07

H

XX10XXX0
0X000000

XX000000
00

H

XX000000
XX000000
00101010

FF

H

FF

H

XXXX1111
FF

H

FF

H

XX1111XX
XX000000

01XXX000
00

H

00XXXXXX
XXXX1111
XX1111XX

000X0000

3)

XX

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

3)

B

3)

B

3)

B

3)

B

3)

B

B

3)

B

3)

B

3)

B

3)

B

3)

B

3)

B

3)

B

B

Semiconductor Group 3-6 1997-10-01

Memory Organization

C504

Table 3-1
Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Timer 2 T2CON

T2MOD
RC2H
RC2L
TH2
TL2

Capture /
Compare
Unit

CT1CON
CCPL
CCPH
CT1OFL
CT1OFH
CMSEL0
CMSEL1
COINI
TRCON
CCL0
CCH0
CCL1
CCH1
CCL2
CCH2
CCIR
CCIE
CT2CON
CP2L
CP2H
CMP2L
CMP2H
BCON

Watchdog WDCON

WDTREL

Power
Save Mode

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) X means that the value is undefined and the location is reserved

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

PCON
PCON1

Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload Capture Register, High Byte
Timer 2 Reload Capture Register, Low Byte
Timer 2 High Byte
Timer 2 Low Byte

Compare timer 1 control register
Compare timer 1 period register, low byte
Compare timer 1 period register, high byte
Compare timer 1 offset register, low byte
Compare timer 1 offset register, high byte
Capture/compare mode select register 0
Capture/compare mode select register 1
Compare output initialization register
Trap enable control register
Capture/compare register 0, low byte
Capture/compare register 0, high byte
Capture/compare register 1, low byte
Capture/compare register 1, high byte
Capture/compare register 2, low byte
Capture/compare register 2, high byte
Capture/compare interrupt request flag reg.

2)

Capture/compare interrupt enable register
Compare timer 2 control register
Compare timer 2 period register, low byte
Compare timer 2 period register, high byte
Compare timer 2 compare register, low byte
Compare timer 2 compare register, high byte
Block commutation control register

Watchdog Timer Control Register
Watchdog Timer Reload Register

2)

Power Control Register
Power Control Register 1

C8

C9
CB
CA
CD
CC

E1
DE
DF
E6
E7
E3
E4
E2
CF
C2
C3
C4
C5
C6
C7
E5
D6
C1
D2
D3
D4
D5
D7

C0

86
87

88

H

H

H
H

H
H

H

H

H
H
H
H
H
H

H

H
H
H
H
H
H

H

H
H
H
H
H
H
H

H

H
H

H

1)

1)

4)

00

H

XXXXXXX0
00

H

00

H

00

H

00

H

00010000
00

H

00

H

00

H

00

H

00

H

00

H

FF

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00010000
00

H

B

B

XXXXXX00
00

H

XXXXXX00
00

H

XXXX0000
00

H

000X0000
0XXXXXXX

3)

B

3)

B

3))

B

3)

B

3)

B

3)

B

Semiconductor Group 3-7 1997-10-01

Memory Organization

Table 3-2
Contents of the SFRs, SFRs in numeric order of their addresses

C504

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H
H
H
H

H

1)

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
WDT

.6 .5 .4 .3 .2 .1 .0

80
81
82
83
86

2)

P0 FF

H

SP 07

H

DPL 00

H

DPH 00

H

WDTREL 00

H

Reset

PSEL

87

88
88

89
8A
8B
8C
8D
90
90

98
99
9A

A0
A8

A9

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

PCON 000X-

H

2)

TCON 00

H

2)3)

PCON1 0XXX-

H

TMOD 00

H

TL0 00

H

TL1 00

H

TH0 00

H

TH1 00

H

2)

P1 FF

H

2)3)

P1ANA XXXX-

H

2)

SCON 00

H

SBUF XX

H

ITCON 0010-

H

2)

P2 FF

H

2)

IEN0 0X00-

H

IEN1 XX00-

H

0000

H

XXXX

H
H
H
H
H

H

1111

H

H

1010

H

0000

0000

SMOD PDS IDLS – GF1 GF0 PDE IDLE

B

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
EWPD – – – – – – –

B

GATE C/T

M1 M0 GATE C/T M1 M0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 T2EX T2
– – – – EAN3 EAN2 EAN1 EAN0

B

SM0 SM1 SM2 REN TB8 RB8 TI RI
.7 .6 .5 .4 .3 .2 .1 .0
IT2 IE2 I2ETF I2ETR I1ETF I1ETR I0ETF I0ETR

B

.7 .6 .5 .4 .3 .2 .1 .0
EA – ET2 ES ET1 EX1 ET0 EX0

B

– – ECT1 ECCM ECT2 ECEM EX2 EADC

B

Semiconductor Group 3-8 1997-10-01

Memory Organization

Table 3-2
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C504

Addr Register Content

after

1)

H

B

B

B

B

B

B
H
H
H
H
H
H
H

B0
B0

B1

B8

B9

C0

C1

C2
C3
C4
C5
C6
C7
C8

2)

P3 FF

H

2)3)

P3ANA XX11-

H

SYSCON XX10-

H

2)

IP0 XX00-

H

IP1 XX00-

H

2)

WDCON

H

CT2CON 0001-

H

CCL0 00

H

CCH0 00

H

CCL1 00

H

CCH1 00

H

CCL2 00

H

CCH2 00

H

2)

T2CON 00

H

Reset

11XX

XXX0

0000

0000
XXXX-

0000

0000

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RD WR T1 T0 INT1 INT0 TxD RxD
– – EAN7 EAN6 EAN5 EAN4 – –

– – EALE RMAP – – – XMAP

– – PT2 PS PT1 PX1 PT0 PX0

– – PCT1 PCCM PCT2 PCEM PX2 PADC

– – – – OWDS WDTS WDT SWDT

CT2P ECT2O STE2 CT2

CT2R CLK2 CLK1 CLK0

RES
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/

RL2

C9

CA
CB
CC
CD
CF
D0
D2

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

T2MOD XXXX-

H

RC2L 00

H

RC2H 00

H

TL2 00

H

TH2 00

H

TRCON 00

H

2)

PSW 00

H

CP2L 00

H

XXX0

H
H
H
H
H
H
H

–––––––DCEN

B

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TREN0
CY AC F0 RS1 RS0 OV F1 P
.7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 3-9 1997-10-01

Memory Organization

Table 3-2
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C504

Addr Register Content

after

1)

B

H

B

H

H

B

H

B

B
H
H
H

B

H

D3

D4
D5

D6

D7

D8

D9
DA

DC

DE
DF
E0
E1

E2

CP2H XXXX.

H

CMP2L 00

H

CMP2H XXXX.

H

CCIE 00

H

BCON 00

H

2)

ADCON0 XX00-

H

ADDATH 00

H

ADDATL 00XX-

H

ADCON1 01XX-

H

CCPL 00

H

CCPH 00

H

2)

ACC 00

H

CT1CON 0001-

H

COINI FF

H

Reset

XX00

XX00

0000

XXXX

X000

0000

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

––––––.1.0

.7 .6 .5 .4 .3 .2 .1 .0
––––––.1.0

ECTP ECTC CC2

FEN

BCMP

PWM1 PWM0 EBCE

CC2
REN

CC1
FEN

BCERR

CC1
REN

CC0
FEN

CC0
REN

BCEN BCM1 BCM0

BCEM
– – IADC BSY ADM MX2 MX1 MX0

.9 .8 .7 .6 .5 .4 .3 .2
.1.0––––––

ADCL1 ADCL0 – – – MX2 MX1 MX0

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
CTM ETRP STE1 CT1

CT1R CLK2 CLK1 CLK0

RES

COUT
3I

COUT
XI

COUT
2I

CC2I COUT

1I

CC1I COUT

0I

CC0I

E3

E4

E5
E6
E7
F0

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

CMSEL0 00

H

CMSEL1 00

H

CCIR 00

H

CT1OFL 00

H

CT1OFH 00

H

2)

B 00

H

H

H

H
H
H
H

CMSEL
13

ESMC NMCS 0 0

CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0R
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0

CMSEL
12

CMSEL
11

CMSEL
10

CMSEL
03

CMSEL
23

CMSEL
02

CMSEL
22

CMSEL
01

CMSEL
21

CMSEL
00

CMSEL
20

Semiconductor Group 3-10 1997-10-01