Siemens C501 User Guide

C501

8-Bit Single-Chip Microcontroller

User’s Manual 04.97

http://www.siemens.de/

Semiconductor/

Edition 04.97

This edition was realized using the software system FrameMaker



Published by Siemens AG, Bereich Halbleiter, Marketing-

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Siemens AG 1997.

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Critical components Group of Siemens AG, may only be used in life-support devices or system s

of the Semiconductor

with the express written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used

in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are in-

tended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

C501 User’s Manual Revision History : 04.97

Previous Releases : 02.96, 08.94, 08.93 (Original Version) Page

(previous version)

general C501G-1E OTP version included (new chapter 9, AC/DC characteri stics

Chapter 1

1-2 3-4 to 3-6 4-2

6-10 6-15 follo. 6-23 follo. 6-30 follo. chapter 7

8-2

chapter 9

9-6, 9-9 9-12 9-17

9-18

Page (new version)

Chapter 1

1-2 3-2 to 3-7 4-4 4-5 6-10 6-15, 6-16 6-22, 6-23 6-29 chapter 7

8-4 chapter 9 chapter 10 10-3 10-6,10-8 10-10 10-13 10-15/16 10-18 10-21 chapter 11

Subjects (changes since last revision)

now in chapter 10) Several figures: update with C501-1E signal names and definitions;

P-MQFP-44 package (pin configuration and pin numbers) added Feature list is updated Actualized design of the SFR tables Figure 4-1 moved Description of enhanced hooks emulation concept added Figure 6-6 corrected Improved timer 0/1 register description Improved timer 2 register description Improved serial port register description Improved description of the interrupt related functions: all enable, control, and request register bits now included Table 8-1 moved into chapter 8.4

New chapter 9 “OTP Memory Operation of the C501-1E” included Old chapter 9 (“Device Specifications”) is now chapter 10 “DC Characteristics for C501-1E” included Characteristics for “External Clock Drive” on three pages moved below “Ext. Data Memory Characteristics” Old figure 7 moved to figure 10-4 New chapter 10.8 “OTP Programming and Verification Characteristics” Figure 10-9: M-QFP-44 pin numbers for XTAL1/XTAL2 added M-QFP-44 package outline added Manual index information added

C501

Table of Contents Page

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Program Memory, “Code Space” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 Data Memory, “Data Space” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.3 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.4 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

4 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.1.3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.4 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . 4-4

4.5 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

5 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1.1.1 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.1.2 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.1.3 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.1.3.1 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.1.3.2 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

6.1.3.3 Read-Modify-Write Feature of Ports 1,2 and 3 . . . . . . . . . . . . . . . . . . . . . 6-11

6.2 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

6.2.1 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.2.1.1 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

6.2.1.2 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

6.2.1.3 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19

6.2.1.4 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

6.2.1.5 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

Semiconductor Group I-1

C501

Table of Contents Page

6.2.2 Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

6.2.2.1 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23

6.2.2.2 Auto-Reload (Up or Down Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26

6.2.2.3 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

6.3 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29

6.3.1 Multiprocessor Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30

6.3.2 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30

6.3.3 Baud Rates Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32

6.3.3.1 Using Timer 1 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33

6.3.3.2 Using Timer 2 to Generate Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34

6.3.4 Details about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36

6.3.5 Details about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39

6.3.6 Details about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42

7 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.1.1 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.1.2 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.1.3 Interrupt Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

7.2 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.3 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

7.5 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11

8 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1 Power Saving Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.3 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.4 State of Pins in Software Initiated Power Saving Modes . . . . . . . . . . . . . . . 8-4

9 OTP Memory Operation of the C501-1E . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1 Programming Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 Quick-Pulse Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.3 Encryption Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.4 Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.5 OTP Memory Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

Semiconductor Group I-2

C501

Table of Contents Page

10 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2 DC Characteristics for C501-L / C501-1R . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.3 DC Characteristics for C501-1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.4 AC Characteristics for C501-L / C501-1R / C501-1E . . . . . . . . . . . . . . . . 10-5

10.5 AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 . . . . . . . . . . . 10-7

10.6 AC Characteristics for C501-L40 / C501-1R40 . . . . . . . . . . . . . . . . . . . . . 10-9

10.7 ROM Verification Characteristics for C501-1R . . . . . . . . . . . . . . . . . . . . . 10-14

10.8 OTP Programming and Verification Characteristics for C501-1E . . . . . . 10-15

10.9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19

11 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

Semiconductor Group I-3

Introduction

C501

1 Introduction

The C501-L, C501-1R, and C501-1E described in this document are compatible (also pincompatible) with the 80C52 and can be used in typical 80C52 applications.

The C501-1R contains a non-volatile 8K×8 read-only program memory, a volatile 256×8 read/write data memory, four ports, three 16-bit timers/counters, a seven source, two priority level interrupt structure and a serial port. The C501-L is identical, except that it lacks the program memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip. The term C501 refers to all versions within this specification unless otherwise noted.

Power Saving Modes

Figure 1-1 C501G Functional Units

RAM

256 x 8

CPU

8K x 8 ROM (C501-1R) 8K x 8 OTP (C501-1E)

USART

Port 0

Port 1

Port 2

Port 3

MCA03238

Semiconductor Group 1-1

Listed below is a summary of the main features of the C501:

• Fully compatible to standard 8051 microcontroller

• Versions for 12/24/40 MHz operating frequency

• Program memory : completely external (C501-L)

8K × 8 ROM (C501-1R)

8K × 8 OTP memory (C501-1E)

• 256 × 8 RAM

• Four 8-bit ports

• Three 16-bit timers / counters (timer 2 with up/down counter feature)

• USART

• Six interrupt sources, two priority levels

• Power saving modes

• Quick Pulse programming algorithm (C501-1E only)

• 2-Level program memory lock (C501-1E only)

• P-DIP-40, P-LCC-44, and P-MQFP-44 package

• Temperature ranges : SAB-C501 T

SAF-C501 TA : – 40 ˚C to 85 ˚C

: 0 ˚C to 70˚C

Introduction

C501

Figure 1-2 Logic Symbol

XTAL1 XTAL2

RESET EA

ALE/PROG PSEN

C501

MCL03217

Port 0 8-Bit Digital

Port 1

Port 2

Port 3

Ι/O

/OΙ8-Bit Digital

Semiconductor Group 1-2

Introduction

C501

1.1 Pin Configuration

This section shows the pin configuration of the C501 in the P-LCC-44, P-DIP-40, and P-MQFP-44 packages.

P0.1/AD1

P1.3

P1.4

6 5 4 3 2 1 44 43 42 41 40

P1.5 P1.6 P1.7

RESET P0.7/AD7

RxD/P3.0

N.C.

TxD/P3.1 INT0/P3.2 INT1/P3.3

T0/P3.4 T1/P3.5

8 9

11 12 13 14 15 16 17

WR/P3.6

P1.2

P1.1/T2EX

XTAL1

XTAL2

RD/P3.7

N.C

P1.0/T2

C501

N.C.

P0.0/AD0

P2.1/A9

P2.0/A8

P2.2/A10

P0.3/AD3

P0.2/AD2

397 38 37 36 35 34 33 32

31 30 29

2827262524232221201918

P2.3/A11

P2.4/A12

P0.4/AD4 P0.5/AD5 P0.6/AD6

EA/

N.C. ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13

MCP03214

Figure 1-3 Pin Configuration P-LCC-44 Package (top view)

Semiconductor Group 1-3

Introduction

C501

T2/P1.0

T2EX/P1.1

P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

RxD/P3.0

TxD/P3.1

INT0/P3.2

1 2 3 4 5 6 7 8 9 10 11 12

C501

40 39 38 37 36 35 34 33 32

31 30 29

P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7RESET EA/

ALE/PROG PSEN

INT1/P3.3

13 14

T1/P3.5

15 16

RD/P3.7

XTAL2

XTAL1

17 18 19 20

Figure 1-4 Pin Configuration P-DIP-40 Package (top view)

28 27 26 25 24 23 22

MCP03215

P2.7/A15 P2.6/A14T0/P3.4 P2.5/A13 P2.4/A12WR/P3.6 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8

Semiconductor Group 1-4

P0.6/AD6

P0.5/AD5

P0.4/AD4

EA/

N.C.

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

Introduction

C501

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

N.C.

C501

P1.0/T2

P1.1/T2EX

P1.2 P1.3 P1.4 WR/P3.6

44 12

P1.5

P1.6

P1.7

RESET P0.7/AD7

RxD/P3.0

Figure 1-5 Pin Configuration P-MQFP-44 Package (top view)

N.C.

TxD/P3.1

23242526272829303132

2234 2036

1937 1838 1739 1640 1541 1442 1343

10987654321

T0/P3.4

INT0/P3.2

T1/P3.5 P2.5/A13

INT1/P3.3

P2.4/A12

2135

P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 N.C.

XTAL1 XTAL2 RD/P3.7

MCP03216

Semiconductor Group 1-5

1.2 Pin Definitions and Functions

This section describes all external signals of the C501 with its function.

Table 1-1 Pin Definitions and Functions

Symbol Pin Number I/O*) Function

P-LCC-44 P-DIP-40 P-MQFP-44

Introduction

C501

P1.0 – P1.7 2–9

2 3

*) I = Input

O = Output

1–8

1 2

40–44, 1–3,

40 41

I/O Port 1

is a quasi-bidirectional I/O port with internal pull-up resistors. Port 1 pins that have 1s written to them are pulled hig h by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled l ow will source current ( istics) because of the internal pull-up resistors. Port 1 also contains the timer 2 pins as secondary function. The output latch corresponding to a secondary function must be pro-grammed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 1, as follows: P1.0 T2 Input to counter 2 P1.1 T2EX Capture - Reload trigger of

, in the DC character-

timer 2 / Up-Down count

Semiconductor Group 1-6

Table 1-1 Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-LCC-44 P-DIP-40 P-MQFP-44

Introduction

C501

P3.0 – P3.7 11,

13–19

16 17 18

10–17

14 15 16

5, 7–13

10 11 12

I/O Port 3

is a quasi-bidirectional I/O port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled hig h by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 3 pins being ext ernally pulled low will source current ( characteristics) because of the internal pull-up resistors. Port 3 al so contains the interrupt, timer, serial port 0 and external memory strobe pins which are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 R×D receiver data input (asyn-

P3.1 T×D transmitter data output

P3.2 INT

P3.3 INT1

P3.4 T0 counter 0 input P3.5 T1 counter 1 input P3.6 WR

P3.7 RD

, in the DC

chronous) or data input output (synchronous) of serial interface 0

(asynchronous) or clock output (synchronous) of the serial interface 0

0 interrupt 0 input/timer 0

gate control interrupt 1 input/timer 1 gate control

the write control signal latches the data byte from port 0 into the external data memory the read control signal enables the external data memory to port 0

*) I = Input

O = Output

Semiconductor Group 1-7

Table 1-1 Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-LCC-44 P-DIP-40 P-MQFP-44

XTAL2 20 18 14 – XTAL2

Output of the inverting oscillator amplifier.

XTAL1 21 19 15 – XTAL1

Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cy cle of the external clock signal, since the input to the internal clocking ci rcuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed.

Introduction

C501

P2.0 – P2.7 24–31 21–28 18–25 I/O Port 2

is a quasi-bidirectional I/O port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 2 pins being ext ernally pulled low will source current ( characteristics) because of the internal pull-up resistors. Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-up resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register.

*) I = Input

O = Output

, in the DC

Semiconductor Group 1-8

Introduction

Table 1-1 Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-LCC-44 P-DIP-40 P-MQFP-44

PSEN 32 29 26 O The Program Store Enable

output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. Remains high during internal program execution.

RESET 10 9 4 I RESET

A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused

ALE/PROG

resistor to using only an external capacitor to

33 30 27 I/O The Address Latch Enable

output is used for latching the low-byt e of the address into external memory durin g normal operation. It is activa ted every six oscillator periods except during an external data memory access. For the C501-1E this pin is also the program pulse input (PROG memory programming.

permits power-on reset

C501

) during OTP

*) I = Input

O = Output

35 31 29 I External Access Enable

Semiconductor Group 1-9

When held at high level, instructions are fetched from the internal ROM (C501-1R and C501-1E) when the PC is less than 2000H. When held at low level, the C501 fetches all instructions from external program memory. For the C501-L this pin must be tied low. This pin also receives the programming supply voltage

during OTP memory

programming (C501-1E) only).

Table 1-1 Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-LCC-44 P-DIP-40 P-MQFP-44

P0.0 – P0.7 43–36 39–32 37–30 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-up resistors when issuing 1s. Port 0 also outputs the code by tes during program verification in the C501-1R and C501-1E. External pull-up resistors are required during program verification.

Introduction

C501

22 20 16 – Circuit ground potential 44 40 38 – Supply terminal for all operating modes

N.C. 1, 12,

23, 34

*) I = Input

O = Output

– 6, 17,

28, 39

– No connection

Semiconductor Group 1-10

Fundamental Structure

C501

2 Fundamental Structure

The C501 is fully compatible to the standard 8051 microcontroller family. It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational

characteristics of the 8051 micr ocontroller family, the C501 incorporates some enhancements in the timer 2 and fail save mechanism unit.

Figure 2-6 shows a block diagram of the C501.

XTAL1 XTAL2

RESET ALE/PROG PSEN

EA/

C501

OSC & Timing

Serial Channel

CPU

Timer 0

Timer 1

Timer 2

Interrupt Unit

(USART)

RAM

256 x 8

C501-1R : ROM

C501-1E : OTP

8K x 8

Port 0

Port 1

Port 2

Port 3

Port 0

8-Bit Digit.

Port 1 8-Bit Digit.

Port 2 8-Bit Digit.

Port 3 8-Bit Digit.

Ι/O

/OΙ

Figure 2-6 Block Diagram of the C501

Semiconductor Group 2-1

MCB03219

Fundamental Structure

C501

2.1 CPU

The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 12 MHz crystal, 58% of the in structions execute in 1.0 µs (24 MHz : 500 ns, 40 MHz : 300 ns).

The CPU (Central Processing Unit) of the C501 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. Th is unit generate s the internal si gnals controllin g the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing.

The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register.

The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as se t, clear, complement, jumpif-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag.

The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the a ddress of the next inst ruction to be executed. The conditional branch logic enables internal and external eve nts to the pr ocess or to cause a change in the program execution sequence.

Accumulator

ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A.

Program Status Word

The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU.

Semiconductor Group 2-2

Fundamental Structure

C501

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

CY AC

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations. F0 General Purpose Flag RS1

RS0

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07 0 1 Bank 1 selected, data address 08H-0F 1 0 Bank 2 selected, data address 10H-17 1 1 Bank 3 selected, data address 18H-1F

PSW

H H H H

OV Overflow Flag

Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of “one” bits in the accumulator, i.e. even parity.

B Register

The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register.

Stack Pointer

The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is i nitia lize d to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control.

Semiconductor Group 2-3

Fundamental Structure

C501

2.2 CPU Timing

A machine cycle of the C501 consists of 6 states (12 oscillator periods). Each state is devided into a phase 1 half, during which the phase 1 clock is a ctive, and a phas e 2 half, d uring which the phase 2 clock is active. Thus, a machine cy cle cons ists of 12 osci llator peri ods, numbe rerd S1P1 (state 1, phase 1) through S6P 2 (state 6, phase 2). Each sta te lasts for two oscillator period s. Typically, arithmetic and logically operations take place during phase 1 and internal register-to-register transfers take place during phase 2.

The diagrams in figure 2-7 show the fetch/execute timing related to the intern al states and phases . Since these internal clock signals are not us er-accessible, the XTAL2 oscillato r signals and the ALE (address latch enable) signal are s hown for external re ference. ALE is nor mally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1.

Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2.

Figures 2-7 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction.

Most C501 instructions ar e executed in one cycle. MUL (multipl y) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program me mory during every machine cycle. The only except ion to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-7 c) and d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction.

Semiconductor Group 2-4

Fundamental Structure

C501

Figure 2-7 Fetch Execute Sequence

Semiconductor Group 2-5

Memory Organization

3 Memory Organization

The C501 CPU manipulates operands in the following four address spaces:

– up to 64 Kbyte of internal/external program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – a 128 byte special function register area

Figure 3-1 illustrates the memory address spaces of the C501.

C501

External

Internal

"Code Space"

FFFF

2000

External (EA = 0)(EA = 1)

1FFF

0000

FFFF

External

Indirect

Address

Internal

RAM

0000

"Data Space" "Internal Data Space"

Internal

RAM

Direct

Address

Special Function Register

MCD03224

Figure 3-1 C501 Memory Map

Semiconductor Group 3-1

Memory Organization

C501

3.1 Program Memory, “Code Space”

The C501-1R/-1E h as 8 Kbytes of read-only/OTP program memory, while the C501-L has no internal program memory. The program memory can be externally expande d up to 64 Kbytes. If the EA

pin is held high, the C501 executes out of internal program memory unl ess the address exceeds 1FFFH. Locations 2000H through FFFFH are then fetched from the external program memory. If the EA

3.2 Data Memory, “Data Space”

The data memor y address space consists of an internal and an ext ernal memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirec t addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function regis ters are accessible throug h direct addressing. Four 8-register banks , each bank consisting of eight 8-bi t multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes.

pin is held low, the C501 fetches all instructions from the external program memory.

The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address.

3.3 General Purpose Registers

The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits i n the program status word, RS0 and RS1, select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines.

The 8 general purpose regist ers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0).

Reset initializes the stack pointer to location 07H and increments it once to start from location 08 which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage.

Semiconductor Group 3-2

Memory Organization

C501

3.4 Special Function Registers

All registers, except the p rogram counter an d the fou r general purpose regi ster bank s, resid e in th e special function register area.

The 27 special function register (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area.

All SFRs are listed in table 3-1 and table 3-2. In table 3-2 they are organized in groups which refer to the functional blocks of the C50 1. Table 3-3

illustrates the contents (bits) of the SFRs.

Semiconductor Group 3-3

Memory Organization

C501

Table 3-2 Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B DPH DPL PSW SP

Interrupt System

IE IP

Ports P0

P1 P2 P3

Serial Channel

PCON SBUF SCON

Timer 0 / Timer 1

TCON TH0 TH1 TL0 TL1 TMOD

Timer 2 T2CON

T2MOD RC2H RC2L TH2 TL2

Pow. Sav.

PCON

Modes

Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer

Interrupt Enable Register Interrupt Priority Register

Port 0 Port 1 Port 2 Port 3

Power Control Register Serial Channel Buffer Register Serial Channel Control Register

Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register

Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture Register, High Byte Timer 2 Reload/Capture Register, Low Byt Timer 2 High Byte Timer 2 Low Byte

Power Control Register 87

E0 F0

83 82

A8 B8

80 90 A0 B0

87 99

98 88

8C 8D 8A 8B 89

C9 CB CA CD CC

H H

H H H H

H H

0X000000 XX000000

0XXX0000

XXXXXXX0 00

0XXX0000

1) Bit-addressable special f unc t ion registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X“ means that the value is undef ined and the location is reserved

Semiconductor Group 3-4

Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses

Memory Organization

C501

Addr Register Content

after Reset

80 81 82 83 87

P0 FF

SP 07

DPL 00

DPH 00

PCON 0XXX-

0000

88 89

TCON 00

TMOD 00

8AHTL0 00 8BHTL1 00 8CHTH0 00 8DHTH1 00

90 98 99 A0 A8

P1 FF

SCON 00

SBUF XX

P2 FF

IE 0X00-

0000

B0 B8

P3 FF

IP XX00-

0000

T2CON 00

H H H H

H H H H H H

H H

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 SMOD – – – GF1 GF0 PDE IDLE

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 GATE C/T

M1 M0 GATE C/T M1 M0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 SM0 SM1 SM2 REN TB8 RB8 TI RI .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 EA – ET2 ES ET1 EX1 ET0 EX0

RD WR T1 T0 INT1 INT0 TxD RxD – – PT2 PS PT1 PX1 PT0 PX0

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/

RL2

C9HT2MOD XXXX-

XXX0 CAHRC2L 00 CBHRC2H 00 CCHTL2 00 CDHTH2 00

1) X means that the value is undefine d and the location is reserved

2) Bit-addressable special fun ction registers

H H H H

–––––––DCEN

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 3-5

Memory Organization

Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C501

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H H H

CY AC F0 RS1 RS0 OV F1 P .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0

Reset

D0 E0 F0

1) X means that the value is undefine d and the location is reserved

2) Bit-addressable special fun ction registers

PSW 00

ACC 00

B 00

Semiconductor Group 3-6

External Bus Interface

C501

4 External Bus Interface

The C501 allows for external memory expansion. To accomplish this, the external bus interface common to most 8051-based controllers is employed.

4.1 Accessing External Memory

It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN strobe. Accesses to external data memory use RD functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described.

Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri).

and WR to strobe the memory (alternate

(program store enable) as a read

4.1.1 Role of P0 and P2 as Data/Address Bus

When used for accessing external mem ory, p ort 0 p rovide s the data byte time-m ultip lexed with th e low byte of the address. In this state, port 0 i s disconnected from its own port l atch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this appli cation, the port 0 pins are not open-drain outputs and do not require external pullup resistors.

During any access to external me mory, the CPU wri tes FFH to the port 0 latch (the speci al functio n register), thus obliterating whatever information the port 0 SFR may have been holding.

Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register).

Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified.

If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cy cle and not only for two oscillator periods.

Semiconductor Group 4-1

External Bus Interface

C501

ALE

PSEN

One Machine Cycle One Machine Cycle

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

INST.

PCL

OUT

PCL OUT

valid

PCH OUT

INST. INST. INST. INST.

IN OUT

PCL OUT

PCH PCH OUT

PCL PCL

PCL OUT

valid

PCH

OUTIN IN OUT

valid

One Machine CycleOne Machine Cycle

PCL OUT

(A) without MOVX

OUTOUT

PCL

valid

ALE

PSEN

PCL

OUT

PCH OUT

ININ

DPL or Ri

valid

INST. INST. INST.

PCL OUT

valid

Figure 4-1 External Program Memory Execution

DPH OUT OR

P2 OUT

DATA

PCH OUT

PCL

OUT

PCL OUT

valid

S6S5S4S3S2S1S6S5S4S3S2S1

(B) with MOVX

MCT03220

Semiconductor Group 4-2

External Bus Interface

C501

4.1.2 Timing

The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN

, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b).

Data memory

Program memory

4.1.3 External Program Memory Access

The external program memory is accessed under two conditions:

– whenever signal EA – whenever the program counter (PC) contains a number that is larger than 1FFFH.

This requires the ROM-less version C501-L to have EA bytes to be fetched from external memory.

When the CPU is executing out of exte rnal pro gram memory, all 8 bits of port 2 a re dedi cated to a n output function and may not be used for general-purpose I/O. The contents of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri).

When the C501 executes instructions from external program memory, port 2 is at all times dedicated to output the high-order address byte. This means t hat port 0 and port 2 of the C501 ca n never be used as general-purpose I/O. This means that port 0 and port 2 of the C501-L can never be used as general-purpose I/O. This also applies to the C501-1R/1E when they are operating with external program memory only.

: in a write cycle, the data byte to be written appears on port 0 just before WR is

activated and remains there until after WR incoming byte is accepted at port 0 before the read strobe is deactivated.

: Signal PSEN functions as a read strobe.

is active (low) or

wired low to allow the lower 8 K program

is deactivated. In a read cycle, the

Semiconductor Group 4-3

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