Siemens C500 User Guide

C500

Microcontroller Family Architecture and Instruction Set

User's Manual 09.97

http://www.siemens.de/

Semiconductor/

C500 Architecture and Instruction User’s Manual Revision History : 09.97 Original Version

Previous Releases: 07.96, 01.97

Page Subjects (changes since last revision)

4-88 Table 4-4: Mnemonics for Opcode 83

, 86

and 87

corrected

Page Subjects (changes from 07.96 to 01.97)

Table of

Reference to pages of each instruction added content 4-89

Edition 09.97 Published by Siemens AG,

Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

Siemens AG 1997.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer.

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Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

Table header corrected

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

with the express

C500

Table of Contents Page

1 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2.2.1 Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2.2.2 Internal Data Memory XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.2.2.3 External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.2.3 Special Function Register Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

2 CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.3 Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.4 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.5 Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.5.1 The Importance of Additional Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.5.2 How the eight Datapointers of the C500 are realized . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.5.3 Advantages of Multiple Datapointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5.4 Application Example and Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.6 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.7 Basic Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.8 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

3 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Basic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2.1 Accessing External Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2.2 Accessing External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 Introduction to the Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.1 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.2 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.2.3 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.2.4 Control Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3 Instruction Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

ACALL addr11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

ADD A, <src-byte> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

ADDC A, < src-byte> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

AJMP addr11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

ANL <dest-byte>, <src-byte> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

ANL direct, #data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

ANL C, <src-bit> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

CJNE <dest-byte >, < src-byte >, rel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

CJNE @Ri, #data, rel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21

CLR A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22

CLR bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

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C500

Table of Contents Page

CPL A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

CPL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

DA A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

DEC byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28

DIV AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30

DJNZ <byte>, <rel-addr> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

INC <byte> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33

INC DPTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35

JB bit,rel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36

JBC bit,rel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37

JC rel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38

JMP @A + DPTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39

JNB bit,rel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40

JNC rel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41

JNZ rel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42

JZ rel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43

LCALL addr16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44

LJMP addr16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45

MOV <dest-byte>, <src-byte> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46

MOV <dest-bit>, <src-bit> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51

MOV DPTR, #data16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52

MOVC A, @A + <base-reg> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53

MOVX <dest-byte>, <src-byte> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55

MUL AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57

NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58

ORL <dest-byte>, <src-byte> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59

ORL C, <src-bit> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62

POP direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63

PUSH direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64

RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65

RETI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66

RL A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67

RLC A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68

RR A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-69

RRC A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70

SETB <bit> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-71

SJMP rel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72

SUBB A, <src-byte> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73

SWAP A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75

XCH A, <byte> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76

XCHD A,@Ri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78

XRL <dest-byte>, <src-byte> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79

4.4 Instruction Set Summary Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82

4.4.1 Functional Groups of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82

4.4.2 Hexadecimal Ordered Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87

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Table of Contents Page

5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 P-DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 PLCC Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3 MQFP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

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Fundamental Structure

C500 Family

1 Fundamental Structure

1.1 Introduction

The members of the C500 Siemens microcontroller family are basically fully compatible in architecture and software to the standard 8051 microcontroller family. Especially, they are functionally upward compatible to the SAB 80C52/80C32 microcontroller. While maintaining all architectural and operational characteristics of the SAB 80C52/80C32, the C500 microcontrollers differ in number and complexity of their peripheral units which have been adapted to the specific application areas.

The goal of this “Architecture and Instruction Set Manual“ is to summarize the basic architecture and functional characteristics of all members of the C500 microcontroller family. This includes the description of the architecture and the description of the complete instruction set. Detailed information about the different versions of the C500 microcontrollers are given in the specific User Manuals.

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Fundamental Structure

C500 Family

1.2 Memory Organization

The memory resources of the C500 family microcontrollers are organized in different types of memories (data and program memory), which further can be located internally on the microcontroller chip or outside of the microcontroller. The memory partitioning of the C500 microcontrollers is typical for a Harvard architecture where data and program areas are held in separate memory areas. The on-chip peripheral units are accessed using an internal special function register memory area.

The available memory areas have different sizes and are located in the following five address spaces:

Table 1-1 C500 Address Spaces

Type of Memory Location Size

Program Memory External max. 64 KByte

Internal (ROM, EEPROM) Depending on C500 version

2K up to 64KByte

Data Memory External max. 64 KByte

Internal XRAM Depending on C500 version

256 Byte up to 3 KByte

Internal 128 or 256 Byte

Special Function Register Internal 128/256 Bytes

1.2.1 Program Memory

The program memory of the C500 family microcontrollers can be composed of either completely external program memory, of only internal program memory (on-chip ROM / EEPROM), or of a mixture of internal and external program memory. lf the EA level, the C500 microcontrollers execute the program code always out of the external program memory. Romless C500 derivatives can use this type of program memory only. C500 derivatives with on-chip program memory typically use their internal program memory only. If the internal program memory is used the EA executes instructions internally unless the address exceeds the upper limit of the internal program memory. If the program counter is set to an address (e.g. by a jump instruction) which is higher than the internal program memory, instructions are executed out of an external program memory. When the instruction address again is below the internal program memory size limit, internal program memory is accessed again.

pin must be put to high level. With EA high, the microcontroller

pin (EA= E xternal A ccess) is held at low

Figure 1-1 shows the typical C500 family microcontroller program memory configuration for the two

cases EA=0 and EA=1. The ROM boundary shown in figure 1-1 , applies to the C501 which has 8K byte of internal ROM. Other C500 family microcontrollers with different ROM size have different ROM boundaries.

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Fundamental Structure

C500 Family

Figure 1-1 Program Memory Configuration (Example of the C501)

1.2.2 Data Memory

The data memory area of the C500 family microcontrollers consists of internal and external data memory portions. The internal data memory area is addressed using 8-bit addresses. The external data memory and the internal XRAM data memory are addressed by 8-bit or16-bit addresses.

The content of the internal data memory (also XRAM) is not affected by a reset operation. After power-up the content is undefined, while it remains unchanged during and after a reset as long as the power supply is not turned off. The XRAM content is also maintained when the C500 microcontrollers are in power saving modes.

1.2.2.1 Internal Data Memory

The internal data memory address space is divided into three basic, physically separate and distinct blocks: the lower 128 byte of internal data RAM, the upper 128 byte of internal data RAM, and the 128 byte special function register (SFR) area. The lower internal data RAM and the SFR area further include 128 bit locations each. These bits can be handled by specific bit manipulation instructions.

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Fundamental Structure

C500 Family

Figure 1-2 shows the configuration of the three basic internal RAM areas. The lower data RAM is

located in the address range 00H - 7FH and can be addressed directly (e.g. MOV A,direct) or indirectly (e.g. MOV A,@R0 with address in R0). A bit-addressable area of 128 free programmable, direct addressable bits is located at byte addresses 20H - 2FH of the lower data RAM. Bit 0 of the internal data byte at 20H has the bit address 00H while bit 7 of the internal data byte at 2FH has the bit address 7FH. The lower 32 locations of the internal lower data RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks can be enabled at a time to be used as general purpose registers.

Figure 1-2 Internal Data Memory Organization

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Fundamental Structure

C500 Family

While the SFR area and the upper internal RAM area share the same address locations (80H FFH), they must be accessed through different addressing modes. The upper internal RAM can only be accessed through indirect addressing while the special function registers (SFRs) are accessible only by direct addressing instructions. The SFRs which are located at addresses with

address bit 0-2 equal 0 (addresses 80H, 88H, 90H, ....F0H, FFH) are bitaddressable SFRs.

1.2.2.2 Internal Data Memory XRAM

Some members of the C500 family microcontrollers provide an additional internal data memory area, called the XRAM. This data memory area is logically located at the upper end of the external data memory space (except C502), but it is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM.

Figure 1-3 shows a typical 256 byte XRAM address mapping of the C500 microcontrollers.

Figure 1-3 XRAM Memory Mapping (256 Byte)

Depending on the C500 derivative, the size of the XRAM area differs from 128 upto 3K byte. Further, the XRAM can be enabled or disabled. If an internal XRAM area is disabled, external data memory can be accessed in the address range of the internal XRAM.

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Fundamental Structure

C500 Family

1.2.2.3 External Data Memory

The 64 Kbyte external data memory can be addressed by instructions that use 8-bit or 16-bit indirect addressing. A 16-bit external memory addressing mode is supported by the MOVX instructions using the 16-bit datapointer DPTR for addressing. For 8-bit addressing MOVX instructions with the general purpose registers R0/R1 are used.

1.2.3 Special Function Register Area

The registers of a C500 microcontroller, except the program counter and the four general purpose register banks, reside in the special function register (SFR) area. The special function register area typically provides 128 bytes of direct addressable SFRs. The SFRs which are located at addresses

with address bit 0-2 equal 0 (addresses 80H, 88H, 90H, ....F0H, FFH) are bitaddressable SFRs (see

also figure 1-1). For example, the SFR with byte address 80H provides the bit locations with bit addresses 80H to 87H. The bit addresses of the SFR bits reach from 80H to FFH.

Due to the limited number of 128 standard SFRs, some derivatives of the C500 microcontroller family provide an additional 128 byte SFR area, called the mapped SFR area. The mapped SFR area provides the same addressing capabilities (direct addresses, bit addressing) as the standard SFR area.

Special Function Register SYSCON (Address B1H)

Bit No. MSB LSB

76543210

Bit Function

RMAP Special function register map bit

––

The functions of the shaded bits are not described in this section.

RMAP = 0 : The access to the non-mapped (standard) special function

RMAP = 1 : The access to the mapped special function register area is

– RMAP –

enabled.

––

–

SYSCON

As long as bit RMAP is set, mapped special function registers can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each. Some registers (e.g. ACC) are accessed independently of bit RMAP.

Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank. This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. For indirect addressing modes, the registers R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0).

Semiconductor Group 1-6 1997-09-01

CPU Functions

C500 Family

2 CPU Architecture

The typical architecture of a C500 family microcontroller is shown in figure 2-1 . This block diagram includes all main functional blocks of the C500 microcontrollers. The shaded blocks are basic functional units which are mandatory for each C500 microcontroller. The other functional blocks such as XRAM, peripheral units, and ROM/RAM sizes are specific to each C500 microcontroller derivative.

Figure 2-1 C500 Microcontroller Architecture Block Diagram

The core block represents the CPU (Central Processing Unit) of the C500 family microcontrollers. The CPU consists of the instruction decoder, the arithmetic section, the CPU registers, and the program control section. The housekeeper unit generates internal signals for controlling the functions of the individual internal units within the microcontroller. Port 0 and port 2 are required for accessing external code and data memory and for emulation purposes. The external control signals and the clock generation are handled in the external control block. The access control unit is responsible for the selection of the on-chip memory resources. The IRAM provides the internal RAM which includes the general purpose registers. The interrupt requests from the peripheral units are handled by an interrupt controller unit.

C500 device specific is the configuration of the on-chip peripheral units. Serial interfaces, timers, capture/compare units, A/D converters, watchdog units, or a multiply/divide unit are typical examples for on-chip peripheral units. The external signals of these peripheral units are available at multifunctional parallel I/O ports or at dedicated pins.

Semiconductor Group 2-1 1997-09-01

CPU Functions

C500 Family

The arithmetic section of the core performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. Further, it has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-addadjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag.

The program control section of the core controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence.

2.1 Accumulator

ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A.

2.2 B Register

The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register.

2.3 Program Status Word

The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. The bits of the PSW are used for different functions which are: two register bank selection bits, two carry flags and an overflow flag for arithmetic instructions, a parity bit for the content of the ACC, and two general purpose flags.

The bit definitions of the PSW are shown on the next page.

Semiconductor Group 2-2 1997-09-01

CPU Functions

C500 Family

Special Function Register PSW (Address D0H) Reset Value : 00

Bit No.

Bit Function

CY Carry Flag

Used by arithmetic and conditional branch instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations. F0 General Purpose Flag RS1

RS0

These bits are used to select one of the four register banks.

RS1 RS0 Function

LSBMSB

01234567 PF1OVRS0RS1F0ACCY

PSW

0 0 Registerbank 0 at data address 00H-07H selected 0 1 Registerbank 1 at data address 08H-0FH selected 1 0 Registerbank 2 at data address 10H-17H selected 1 1 Registerbank 3 at data address 18H-1FH selected

OV Overflow Flag

Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag

Always set/cleared by hardware to indicate an odd/even number of "one"

bits in the accumulator, i.e. even parity.

2.4 Stack Pointer

The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control.

Semiconductor Group 2-3 1997-09-01

CPU Functions

C500 Family

2.5 Data Pointer

8-bit accesses to the internal XRAM data memory or the external data memory are executed using the data pointer DPTR as an 16-bit address register. Normally, the C500 family microcontrollers have one data pointer. But some members of the C500 family provide eight data pointers. The availability of eight data pointers especially supports the programming in high level languages which have a demand to store data in large external data memory portions.

Special Function Register DPL (Address 82H) Reset Value : 00 Special Function Register DPH (Address 83H) Reset Value : 00 Special Function Register DPSEL (Address D0H) Reset Value : 00

LSBMSB

Bit No.

Bit Function

– Reserved bits for future use

01234567

LSB.1.2.3.4.5.6.7

.0.1.2.3.4.5.6MSB83

.0.1.2–––––92

DPL

DPH

DPSEL

H H H

DPSEL.2 - 0 Data pointer select bits

DPSEL.2-0 defines the number of the actual active data pointer.DPTR0-7.

DPSEL2 DPSEL1 DPSEL0 Function

0 0 0 Data pointer 0 selected 0 0 1 Data pointer 1 selected 0 1 0 Data pointer 2 selected 0 1 1 Data pointer 3 selected 1 0 0 Data pointer 4 selected 1 0 1 Data pointer 5 selected 1 1 0 Data pointer 6 selected 1 1 1 Data pointer 7 selected

Semiconductor Group 2-4 1997-09-01

CPU Functions

C500 Family

2.5.1 The Importance of Additional Datapointers

The standard 8051 architecture provides just one 16-bit pointer for indirect addressing of external devices (memories, peripherals, latches, etc.). Except for a 16-bit "move immediate" to this datapointer and an increment instruction, any other pointer handling is to be done byte by byte. For complex applications with peripherals located in the external data memory space (e.g. CAN controller) or extended data storage capacity this turned out to be a "bottle neck" for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages.

2.5.2 How the eight Datapointers of the C500 are realized

Simply adding more datapointers is not suitable because of the need to keep up 100% compatibility to the 8051 instruction set. This instruction set, however, allows the handling of only one single 16bit datapointer (DPTR, consisting of the two 8-bit SFRs DPH and DPL).

To meet both of the above requirements (speed up external accesses, 100% compatibility to 8051 architecture) the C500 contains a set of eight 16-bit registers from which the actual datapointer can be selected.

This means that the user’s program may keep up to eight 16-bit addresses resident in these registers, but only one register at a time is selected to be the datapointer. Thus the datapointer in turn is accessed (or selected) via indirect addressing. This indirect addressing is done through a special function register called DPSEL (data pointer select register). All instructions of the C500 which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment.

Figure 5-1 illustrates the addressing mechanism: a 3-bit field in register DPSEL points to the

currently used DPTRx. Any standard 8051 instruction (e.g. MOVX @DPTR, A - transfer a byte from accumulator to an external location addressed by DPTR) now uses this activated DPTRx.

Semiconductor Group 2-5 1997-09-01

CPU Functions

C500 Family

Datapointer

DPTR 0000

.0.1.2

DPTR7

DPTR0

DPH(83 ) DPL(82 )

DPSEL(92 )

DPSEL Selected

.2 .1 .0

0 0 1 DPTR 1 0 1 0 DPTR 2 0 1 1 DPTR 3 1 0 0 DPTR 4 1 0 1 DPTR 5 1 1 0 DPTR 6 1 1 1 DPTR 7

-----

Figure 2-2 Accessing of External Data Memory via Multiple Datapointers

External Data Memory

MCD00779

2.5.3 Advantages of Multiple Datapointers

Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses. Whenever the contents of the datapointer must be altered between two or more 16-bit addresses, one single instruction, which selects a new datapointer, does this job. lf the program uses just one datapointer, then it has to save the old value (with two 8-bit instructions) and load the new address, byte by byte. This not only takes more time, it also requires additional space in the internal RAM.

2.5.4 Application Example and Performance Analysis

The following example shall demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory.

Start address of ROM source table: 1FFF Start address of table in external RAM: 2FA0

H H

Semiconductor Group 2-6 1997-09-01

CPU Functions

C500 Family

Example 1 : Using only One Datapointer (Code for a C501)

Initialization Routine

MOV LOW(SRC_PTR), #0FFH ;Initialize shadow_variables with source_pointer MOV HIGH(SRC_PTR), #1FH MOV LOW(DES_PTR), #0A0H ;Initialize shadow_variables with destination_pointer MOV HIGH(DES_PTR), #2FH

Table Look-up Routine under Real Time Conditions

; Number of cycles PUSH DPL ;Save old datapointer 2 PUSH DPH ; 2 MOV DPL, LOW(SRC_PTR) ;Load Source Pointer 2 MOV DPH, HIGH(SRC_PTR) ; 2 ;INC DPTR Increment and check for end of table (execution time ;CJNE … not relevant for this consideration) – MOVC A,@DPTR ;Fetch source data byte from ROM table 2 MOV LOW(SRC_PTR), DPL ;Save source_pointer and 2 MOV HIGH(SRC_PTR), DPH ;load destination_pointer 2 MOV DPL, LOW(DES_PTR) ; 2 MOV DPH, HIGH(DES_PTR) ; 2 INC DPTR ;Increment destination_pointer

;(ex. time not relevant) – MOVX @DPTR, A ;Transfer byte to destination address 2 MOV LOW(DES_PTR), DPL ;Save destination_pointer 2 MOV HIGH(DES_PTR),DPH ; 2 POP DPH ;Restore old datapointer 2 POP DPL ; 2

; Total execution time (machine cycles) : 28

Semiconductor Group 2-7 1997-09-01

CPU Functions

C500 Family

Example 2 : Using Two Datapointers (Code for a C509)

Initialization Routine

MOV DPSEL, #06H ;Initialize DPTR6 with source pointer MOV DPTR, #1FFFH MOV DPSEL, #07H ;Initialize DPTR7 with destination pointer MOV DPTR, #2FA0H

Table Look-up Routine under Real Time Conditions

; Number of cycles PUSH DPSEL ;Save old source pointer 2 MOV DPSEL, #06H ;Load source pointer 2 ;INC DPTR Increment and check for end of table (execution time ;CJNE … not relevant for this consideration) – MOVC A,@DPTR ;Fetch source data byte from ROM table 2 MOV DPSEL, #07H ;Save source_pointer and

;load destination_pointer 2 MOVX @DPTR, A ;Transfer byte to destination address 2 POP DPSEL ;Save destination pointer and

;restore old datapointer 2

; Total execution time (machine cycles) : 12

The above example shows that utilization of the C500’s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative. Here, four data variables in the internal RAM and two additional stack bytes were spared, too. This means for some applications where all eight datapointers are employed that an C500 program has up to 24 byte (16 variables and 8 stack bytes) of the internal RAM free for other use.

Semiconductor Group 2-8 1997-09-01

CPU Functions

C500 Family

2.6 Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical.

The Enhanced Hooks Technology together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.

, which requires embedded logic in the C500, allows the C500

SYSCON

PCON TCON

Optional

I/O Ports

ICE-System Interface

to Emulation Hardware

RESET

ALE

PSEN

C500

MCU Interface Circuit

Port 3 Port 1

Port 0 Port 2

Target System Interface

RSYSCON

RPCON RTCON

Enhanced Hooks

RPort 0RPort 2

EH-IC

TEA TALE TPSEN

MCS02647

Figure 2-3 Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.

Semiconductor Group 2-9 1997-09-01

CPU Functions

C500 Family

2.7 Basic Interrupt Handling

Each member of the C500 microcontroller family provides several interrupt sources. These interrupts are generated typically by external events or by the internal peripheral units. If an interrupt is accepted by the CPU, the microcontroller interrupts a running program and proceeds the program execution at an interrupt source specific vector address where the interrupt service routine is located. After the execution of a RETI (return from interrupt) instruction the program is continued at the point where it has been interrupted. Figure 2-4 shows an example for the interrupt vector addresses of a C500 microcontroller (C501). Generally, interrupt vector addresses are located in the code memory area starting at address 0003H. The minimum distance between two consecutive vector addresses is always 8 bytes. Therefore, interrupt vectors can be assigned to the following

addresses: 0003H, 000BH, 0013H, 001BH, 0023H, 002BH, 0033H ...... 00FBH.

Figure 2-4 Interrupt Vector Addresses (Example of the C501)

An interrupt source indicates to the interrupt controller an interrupt condition by setting an interrupt request flag. The interrupt request flags are sampled in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition in the preceeding cycle, the polling cycle will find it and the interrupt controller will cause the CPU to branch to the vector address of the appropriate service routine by generating an internal LCALL. This hardwaregenerated LCALL is blocked by any of the following conditions:

1. An interrupt of equal or higher priority is already in progress.

2. The current (polling) cycle is not in the final cycle of the instruction in progress.

3. The instruction in progress is RETI or any write access to interrupt enable or priority registers.

Semiconductor Group 2-10 1997-09-01

CPU Functions

C500 Family

Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to interrupt enable or interrupt priority registers, then at least one more instruction will be executed before any interrupt is vectored too; this delay guarantees that changes of the interrupt status can be observed by the interrupt controller.

The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at the previous machine cycle. Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned, or if the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle interrogates only the pending interrupt requests.

The polling cycle/LCALL sequence is illustrated in figure 2-1.

C2C1 C3 C4 C5

S5P2

Interrupt

is latched

Interrupts are polled

Long Call to Interrupt

Vector Address

Interrupt

Routine

MCT01859

Figure 2-5 Interrupt Detection/Entry Diagram

Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 2-5 then, in accordance with the above rules, it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed.

Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, while in other cases it does not; then this has to be done by the user's software.

The program execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the two top bytes from the stack and reloads the program counter. Execution of the interrupted program continues from the point where it was stopped. Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level. A simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. In this case no interrupt of the same or lower priority level would be acknowledged.

Semiconductor Group 2-11 1997-09-01

CPU Functions

C500 Family

2.8 Interrupt Response Time

If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be next instruction to be executed. The call itself takes two cycles. Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine.

A longer response time would be obtained if the request was blocked by one of the three previously listed conditions. If an interrupt of equal or higher priority is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles since the longest instructions (MUL and DIV) are only 4 cycles long; and, if the instruction in progress is RETI or a write access to interrupt enable or interrupt priority registers the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction, if the instruction is MUL or DIV).

Thus a single interrupt system, the response time is always more than 3 cycles and less than 9 cycles.

Semiconductor Group 2-12 1997-09-01

CPU Timing

C500 Family

3 CPU Timing

3.1 Basic Timing

A machine cycle consists of 6 states. Each state is divided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active. Thus, a machine cycle consists of the states S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Depending on the C500 type of microcontroller, each state lasts either one or two periods of the oscillator clock. Typically, arithmetic and logical operations take place during phase 1 and internal register-to-register transfers take place during phase 2.

The diagrams in figure 3-1 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the ALE (address latch enable) signal is shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1.

The execution of a one-cycle instruction begins at S1P2, when the opcode is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2.

Figures 3-1 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction.

Most C500 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 3-1 (c) and (d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction.

Semiconductor Group 3-1 1997-09-01

CPU Timing

C500 Family

Figure 3-1 Fetch Execute Sequence

Semiconductor Group 3-2 1997-09-01

CPU Timing

C500 Family

3.2 Accessing External Memory

There are two types of external memory accesses: accesses to external program memory and accesses to external data memory. Accesses to external program memory use the signal PSEN (program store enable) as the read strobe. Accesses to external data memory use the RD or WR (alternate functions of P3.7 and P3.6) to access the memory.

Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read, write, or code fetch cycle.

If an 8-bit address is being used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the whole external memory cycle. In this case, port 2 pins can be used to page the external data memory.

In either case, the low byte of the address is time-multiplexed with the data byte on port 0. The ADDRESS/DATA signal drives both FETS in the port 0 output buffers. Thus, in external bus mode the port 0 pins are not open-drain outputs and do not require external pullups. The ALE (address latch enable) signal should be used to latch the address byte into an external latch. The address byte is valid at the negative transition of ALE. Then, in a write cycle, the data byte to be written appears on port 0 just before WR is activated, and remains there until WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 just before the read strobe (RD) is deactivated.

During any access to external memory, the CPU writes FFH to the port 0 latch (the special function register), thus obliterating the information in the port 0 SFR. Also, a MOV P0 instruction must not take place during external memory accesses. If the user writes to port 0 during an external memory fetch, the incoming code byte may be corrupted. Therefore, do not write to port 0 if external memory is used.

3.2.1 Accessing External Program Memory

External program memory is accessed under two conditions:

1. Whenever signal EA is active (low), or

2. Whenever signal EA

than the internal ROM size (e.g. 1FFFFH for an 8K internal ROM or 3FFFH for an 16K internal ROM).

This requires that the ROMless versions have always EA wired to Vss to enable the lower 8K, 16K, or 32K program bytes to be fetched from external memory.

When the CPU is executing out from external program memory (see timing diagram in figure 3-2), all 8 bits of port 2 are dedicated to an output function and may not be used for general purpose I/O. During external program fetches they output the high byte of the PC with the port 2 drivers using the strong pullups to emit bits that are 1´s.

is inactive (high) and the program counter (PC) contains an address greater

Semiconductor Group 3-3 1997-09-01

CPU Timing

C500 Family

Figure 3-2 External Program Memory Fetches

3.2.2 Accessing External Data Memory

The port 2 drivers use the strong pullups during the entire time that they are emitting address bits that are 1´s. This occurs when the MOVX @DPTR instruction is executed and when external program fetches are executed. During this time the port 2 latch (the special function register) does not have to contain 1´s, and the contents of the port 2 SFR are not modified. If the external memory cycle is not immediately followed by another external memory cycle, the undisturbed contents of the port 2 SFR will reappear in the next cycle.

Figure 3-3 and 3-4 show in detail the timings of the external data memory read and write cycles.

Semiconductor Group 3-4 1997-09-01

CPU Timing

C500 Family

Figure 3-3 External Data Memory Read Cycle

Figure 3-4 External Data Memory Write Cycle

Semiconductor Group 3-5 1997-09-01

Instruction Set

C500 Family

4 Instruction Set

The C500 8-bit microcontroller family instruction set includes 111 instructions, 49 of which are single-byte, 45 two-byte and 17 three-byte instructions. The instruction opcode format consists of a function mnemonic followed by a ”destination, source” operand field. This field specifies the data type and addressing method(s) to be used.

Like all other members of the 8051-family, the C500 microcontrollers can be programmed with the same instruction set common to the basic member, the SAB 8051. Thus, the C500 family microcontrollers are 100% software compatible to the SAB 8051 and may be programmed with 8051 assembler or high-level languages.

4.1 Addressing Modes

The C500 uses five addressing modes:

– register – direct – immediate – register indirect – base register plus index-register indirect

Table 4-1 summarizes the memory spaces which may be accessed by each of the addressing modes.

Register addressing accesses the eight working registers (R0 - R7) of the selected register bank. The least significant bit of the instruction opcode indicates which register is to be used. ACC, B, DPTR and CY, the Boolean processor accumulator, can also be addressed as registers.

Direct Addressing

Direct addressing is the only method of accessing the special function registers. The lower 128 bytes of internal RAM are also directly addressable.

Immediate Addressing

Immediate addressing allows constants to be part of the instruction in program memory.

Semiconductor Group 4-1 1997-09-01

Instruction Set

C500 Family

Table 4-1 Addressing Modes and Associated Memory Spaces

Addressing Modes Associated Memory Spaces

B, CY (Bit), DPTR

Direct addressing Lower 128 bytes of internal RAM, special

function registers Immediate addressing Program memory Register indirect addressing Internal RAM (@R1, @R0, SP), external data

memory (@R1, @R0, @DPTR) Base register plus index register addressing Program memory (@A + DPTR, @A + PC)

Register indirect addressing uses the contents of either R0 or R1 (in the selected register bank) as a pointer to locations in a 256-byte block: the 256 bytes of internal RAM or the lower 256 bytes of external data memory. Note that the special function registers are not accessible by this method. The upper half of the internal RAM can be accessed by indirect addressing only. Access to the full 64 Kbytes of external data memory address space is accomplished by using the 16-bit data pointer. Execution of PUSH and POP instructions also uses register indirect addressing. The stack may reside anywhere in the internal RAM.

Base Register plus Index Register Addressing

Base register plus index register addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register (DPTR or PC) and index register, ACC. This mode facilitates look-up table accesses.

Boolean Processor

The Boolean processor is a bit processor integrated into the C500 family microcontrollers. It has its own instruction set, accumulator (the carry flag), bit-addressable RAM and l/O.

The bit manipulation instructions allow:

– set bit – clear bit – complement bit – jump if bit is set – jump if bit is not set – jump if bit is set and clear bit – move bit from / to carry

Addressable bits, or their complements, may be logically AND-ed or OR-ed with the contents of the carry flag. The result is returned to the carry register.

Semiconductor Group 4-2 1997-09-01

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