Siemens C164CI Technical data

Microcomputer Components

16-Bit CMOS Single-Chip Microcontroller

C164CI

Data Sheet 02.98 Preliminary

http://www.siemens.de/

Semiconductor/

C164CI
Revision History: 1998-02 Preliminary

Previous Releases: 04.97 (Advance Information)

Page Subjects

3, 4 Alternate functions for P5 added.

25...30 Register Table updated.
32, 33

I

P6H

and I

removed.

P6L

33, 34 Supply current specification improved.

I

33, 34 Idle supply current specification

improved. (Referring to Revision 11.97)

IDO

39, 40 ADC specification improved.
49, 50 Description for READY

removed.

– “AC Characteristics Demultiplexed Bus” removed.
– “AC Characteristics External Bus Arbitration” removed.

Controller Area Network (CAN): License of Robert Bosch GmbH

Edition 1998-02
Published by Siemens AG,

Bereich Halbleiter, Marketing-

Kommunikation, Balanstraße 73,
81541 München

©

Siemens AG 1998.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are conc erned, liability is only assumed for components, not for app lic ations, processes
and circuits implemented within co mpo nent s or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).
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your nearest Siemens Office, Sem iconductor Group.
Siemens AG is an approved CECC manufacturer.

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Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components
written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safet y or ef fectiv eness of that device or system.

2 Life support devices or systems are intended (a) to be implante d in the human body, or (b) to su pport and/o r maintain a nd sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express

C16x-Family of

C164CI

High-Performance CMOS 16-Bit Microcontrollers

Preliminary
C164CI 16-Bit Microcontroller

● High Performance 16-bit CPU with 4-Stage Pipeline

● 100 ns Instruction Cycle Time at 20 MHz CPU Clock

● 500 ns Multiplication (16 × 16 bit), 1 µs Division (32/16 bit)

● Enhanced Boolean Bit Manipulation Facilities

● Additional Instructions to Support HLL and Operating Systems

● Register-Based Design with Multiple Variable Register Banks

● Single-Cycle Context Switching Support

● Clock Generation via On-Chip PLL or via Direct or Prescaled Clock Input

● Up to 4 MBytes Linear Address Space for Code and Data

● 2 KByte On-Chip Internal RAM (IRAM)

● 64 KByte On-Chip OTP (C164CI-8EM) or ROM (C164CI-8RM)

● Programmable External Bus Characteristics for Different Address Ranges

● 8-Bit or 16-Bit External Data Bus

● Multiplexed External Address/Data Bus

● Four optional Chip Select Signals CS0 - CS3

● 1024 Bytes On-Chip Special Function Register Area

● Idle and Power Down Modes with Flexible Power Management

● 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event

Controller (PEC)

● 16-Priority-Level Interrupt System with 32 Interrupt sources

● 8-Channel 10-bit A/D Converter with 9.7 µs Conversion Time (8.2 µs min.)

● 8-Channel 16-bit General Purpose Capture/Compare Unit (CAPCOM2)

● Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)

(3/6 Capture/Compare Channels and 1 Compare Channel)

● Two Serial Channels (Synchronous/Asynchronous and High-Speed Synchronous)

● Multi-Functional General Purpose Timer Unit with three 16-bit Timers

● On-Chip Full-CAN Interface (V2.0B active) with 15 Message Objects and Basic CAN Feature

● Up to 59 General Purpose I/O Lines

● Programmable Watchdog Timer and Oscillator Watchdog

● On-Chip Real Time Clock

● Ambient temperature range -40 to 125 °C

● Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler

Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer
Disassemblers, Programming Boards

● On-Chip Bootstrap Loader

● 80-Pin MQFP Package, 0.65 mm pitch

This document describes the SAF-C164CI-8EM and the SAK-C164CI-8EM.
For simplicity all versions are referred to by the term C164CI throughout this document.

Semiconductor Group 3 1998-02

C164CI

Introduction

The C164CI is a new low cost derivative of the Siemens C166 Family of 16-bit single-chip CMOS
microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with
high peripheral functionality and enhanced IO-capabilities. It also provides on-chip ROM or OTP
and clock generation via PLL. The C164CI derivative is especially suited for cost sensitive
applications.

XTAL1
XTAL2

RSTIN
RSTOUT

NMI
EA

ALE
RD
WR

V

DD

C164CI

V

AREF

V

SS

V

PORT0
16 bit

PORT1
16 bit

Port 3
9 bit

Port 4
6 bit

Port 8
4 bit

Port 5
8 bit

AGND

Figure 1
Logic Symbol

Ordering Information

The ordering code for Siemens microcontrollers provides an exact reference to the required
product. This ordering code identifies:

● the derivative itself, ie. its function set

● the specified temperature range

● the package

● the type of delivery.

For the available ordering codes for the C164CI please refer to the

„Product Information Microcontrollers“, which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Semiconductor Group 4 1998-02

Pin Configuration

(top view)

C164CI

/EX2IN

/EX1IN

V
P5.4/AN4/T2EUD
P5.5/AN5/T4EUD

P5.6/AN6/T2IN
P5.7/AN7/T4IN

P3.12/BHE

P3.15/CLKOUT

P4.0/A16/CS3
P4.1/A17/CS2
P4.2/A18/CS1

AREF

V

SS

V

P3.4/T3EUD

P3.8/MRST
P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.13/SCLK

DD

P3.6/T3IN

/WRH

V

SS

AGND

V

P5.3/AN3

P5.2/AN2

P5.1/AN1

P5.0/AN0

P8.3/CC19IO

P8.2/CC18IO

P8.1/CC17IO

P8.0/CC16IO

NMI

RSTOUT

RSTIN

P1H.7/CC27IO

P1H.6/CC26IO

P1H.5/CC25IO

80797877767574737271706968676665646362
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21222324252627282930313233343536373839

C164CI

DD

P1H.1/CC6POS1

P1H.4/CC24IO

P1H.3/EX3IN/T7IN

V

P1H.2/CC6POS2

61

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

40

V

SS

P1H.0/CC6POS0/EX0IN
P1L.7/CTRAP
P1L.6/COUT63
V

SS

XTAL1
XTAL2
V

DD

P1L.5/COUT62
P1L.4/CC62
P1L.3/COUT61
P1L.2/CC61
P1L.1/COUT60
P1L.0/CC60
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
V

ss

V

DD

RD

ALE

VPP/EA

WR/WRL

P4.3/A19/CS0

P4.6/A21/CAN_TxD

P4.5/A20/CAN_RxD

P0L.0/AD0

P0L.1/AD1

P0L.2/AD2

P0L.3/AD3

P0L.4/AD4

P0L.5/AD5

P0L.6/AD6

P0L.7/AD7

P0H.0/AD8

DD

V

P0H.1/AD9

P0H.2/AD10

Figure 2

Semiconductor Group 5 1998-02

Pin Definitions and Functions

C164CI

Symbol Pin

Number

P5.0 –
P5.7

P3.4,
P3.6,
P3.8 –
P3.13,
P3.15

76 - 79,
2 - 5

8,
9,
10 –
15,
16

8
9
10
11
12
13
14

15
16

Input (I)
Output (O)

I
I
I

I/O
I/O
I/O
I/O
I/O

I
I
I/O
I/O
O
I/O
O

I/O
O

Function

Port 5 is a 8-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as the (up to 8)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog input channel x).
The following pins of Port 5 also serve as timer inputs:
P5.4 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input
P5.5 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input
P5.6 T2IN GPT1 Timer T2 Input for

Count/Gate/Reload/Capture

P5.7 T4IN GPT1 Timer T4 Input for

Count/Gate/Reload/Capture

Port 3 is a 9-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state.

The following Port 3 pins also serve for alternate functions:
P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input
P3.6 T3IN GPT1 Timer T3 Count/Gate Input
P3.8 MRST SSC Master-Rec./Slave-Transmit I/O
P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I
P3.10 TXD0 ASC0 Clock/Data Output (Asyn./Syn.)
P3.11 RXD0 ASC0 Data Input (Asyn.) or I/O (Syn.)
P3.12 BHE

WRH
P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp.
P3.15 CLKOUT System Clock Output (=CPU Clock)

Ext. Memory High Byte Enable Signal,
Ext. Memory High Byte Write Strobe

P4.0 –
P4.3
P4.5 –
P4.6

Semiconductor Group 6 1998-02

17 - 19,
22,
23 ­24

17

...
22

23

24

I/O
I/O
I/O
I/O

O
O
...
O
O
O
I
O
O

Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0 A16 Least Significant Segment Addr. Line

CS3

... ... ...

P4.3 A19 Segment Address Line

CS0
P4.5 A20 Segment Address Line,

CAN_RxD CAN Receive Data Input
P4.6 A21 Most Significant Segment Addr. Line,

CAN_TxD CAN Transmit Data Output

Chip Select 3 Output

Chip Select 0 Output

Pin Definitions and Functions (cont’d)

C164CI

Symbol Pin

Number

RD 25 O External Memory Read Strobe. RD is activated for every

WR

/

WRL

ALE 27 O Address Latch Enable Output. Can be used for latching the

EA

PORT0:

P0L.0 –
P0L.7,
P0H.0 ­P0H.7

26 O External Memory Write Strobe. In WR-mode this pin is

28 I External Access Enable pin. A low level at this pin during and

29 ­36
37 - 39,
42 - 46

Input (I)
Output (O)

I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L

Function

external instruction or data read access.

activated for every external data write access. In WRL
this pin is activated for low byte data write accesses on a 16­bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.

address into external memory or an address latch in the
multiplexed bus modes.

after Reset forces the C164CI to begin instruction execution
out of external memory. A high level forces execution out of
the internal ROM.
Note: This pin also accepts the programming voltage for OTP

versions of the C164CI.

and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address and data (AD) bus.
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7: A8 - A15 AD8 - AD15

-mode

Semiconductor Group 7 1998-02

Pin Definitions and Functions (cont’d)

C164CI

Symbol Pin

Number

PORT1:

P1L.0 –
P1L.7,
P1H.0 ­P1H.7

47 - 52,
57 - 58
59,
62 - 68
47
48
49
50
51
52
57
58

59

62

63

64

65
...
68

Input (I)
Output (O)

I/O

I/O
O
I/O
O
I/O
O
O
I

I
I
I
I
I
I
I
I
I
...
I

Function

PORT1 consists of the two 8-bit bidirectional I/O ports P1L and
P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as in put, the ou tput driv er is
put into high-impedance state.
The following Port 1 pins also serve for alternate functions:
P1L.0 CC60 CAPCOM6: Input / Output of Ch. 0
P1L.1 COUT60 CAPCOM6: Output of Channel 0
P1L.2 CC61 CAPCOM6: Input / Output of Ch. 1
P1L.3 COUT61 CAPCOM6: Output of Channel 1
P1L.4 CC62 CAPCOM6: Input / Output of Ch. 2
P1L.5 COUT62 CAPCOM6: Output of Channel 2
P1L.6 COUT63 Output of 10-bit Compare Channel
P1L.7 CTRAP
CTRAP

is an input pin with an internal pullup resistor. A low

CAPCOM6: Trap Input

level on this pin switches the compare outputs of the
CAPCOM6 unit to the logic level defined by software.
P1H.0 CC6POS0

CAPCOM6: Position 0 Input

EX0IN Fast External Interrupt 0 Input
P1H.1 CC6POS1

CAPCOM6: Position 1 Input

EX1IN Fast External Interrupt 1 Input
P1H.2 CC6POS2

CAPCOM6: Position 2 Input

EX2IN Fast External Interrupt 2 Input
P1H.3 EX3IN Fast External Interrupt 3 Input

T7IN CAPCOM2: Timer T7 Count Input
P1H.4 CC24IO CAPCOM2: CC24 Capture Input

... ... ...

P1H.7 CC27IO CAPCOM2: CC27 Capture Input

XTAL1

55

I

XTAL1: Input to the oscillator amplifier and input to the

internal clock generator

XTAL2

54

O

XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC Characteristics
must be observed.

RSTIN

69 I Reset Input with Schmitt-Trigger characteristics. A low level at

this pin for a specified duration while the oscillator is running
resets the C164CI. An internal pullup resistor permits power-

V

on reset using only a capacitor connected to

SS

.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN

line is pulled low for the
duration of the internal reset sequence upon a software or
WDT reset.

1)

Semiconductor Group 8 1998-02

Pin Definitions and Functions (cont’d)

C164CI

Symbol Pin

Number

RSTOUT

NMI

P8.0 –
P8.3

70 O Internal Reset Indication Output. This pin is set to a low level

71 I Non-Maskable Interrupt Input. A high to low transition at this

72 ­75

72
...
75

Input (I)
Output (O)

I/O
I/O

I/O
...
I/O

Function

when the part is executing either a hardware-, a software- or a
watchdog timer reset. RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI

pin
must be low in order to force the C164CI to go into power
down mode. If NMI

is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI

should be pulled high externally.

Port 8 is a 4-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high­impedance state.
The following Port 8 pins also serve for alternate functions:
P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out

... ... ...

P8.3 CC19IO CAPCOM2: CC19 Cap.-In/Comp.Out

V

AREF

V

AGND

V

DD

V

SS

1 - Reference voltage for the A/D converter.
80 - Reference ground for the A/D converter.
7, 21,

40, 53,
61

6, 20,

- Digital Supply Voltage:
+ 3 V / + 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode

- Digital Ground.

41, 56,
60

1)

The following behaviour differences must be observed when the bidirectional reset is active:

● Bit BDRSTEN in register SYSCON cannot be changed after EINIT.

● After a reset bit BDRSTEN is cleared.

● Bit WDTR will always be ’0’, even after a watchdog timer reset.

● The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader

may be activated when P0L.4 is low.

● Pin RSTIN may only be connected to external reset devices with an open drain output driver.

Semiconductor Group 9 1998-02

C164CI

Functional Description

The C164CI is a low cost downgrade of the high performance microcontroller C167CR with OTP or
internal ROM, reduced peripheral functionality and a hig h performan ce Capture Compare Unit with
an additional functionality.

The architecture of the C164CI combines advantages of both RISC and CISC processors and of
advanced peripheral subsystems in a very well-balance d way. The following block diagram gives an
overview of the different on-chip components and of the advanced, high bandwidth internal bus
structure of the C164CI.

Note: All time specifications refer to a CPU clock of 20 MHz

(see definition in the AC Characteristics section).

XTAL

P4.5/CAN_RxD
P4.6/CA N_ T xD

16

(C164CI-8RM)
(C164CI-8EM)

PLL-Oscillator

Full-CAN
Interface

V2.0B
active

5

64K

Internal ROM

or OTP

32

Instr./Data

C166-Core

CPU Core

CPU

Data

Data

16

progr. Multiplier:

0.5; 1; 1.5; 2;

2.5; 3; 4; 5

External Instr./Data

16

Interrupt Controller

PEC

up to 12

ext. IR

Interrupt Bus

Peripheral Dat a

External

Bus

(8/16 bit;

(16-bit NON MUX Data / Addresses)

MUX only)

Port 0

XBUS

&

XBUS

Control

Port 4 Port 1

Channel

Port 5

8-

10-Bit

ADC

8

USART

ASC
BRG

Sync.

Channel

(SPI)
SSC
BRG

9

GPT 1

T 2
T 3
T 4

General Purpose
Capture/Compare

Unit

Timer 7

8-Channel 16-bit

Capture/Compare Unit

(CAPCOM2)

Port 8Port 3

4

Capture/Compare Unit for

PWM Generation (CAPCOM6)

1 Compare

Channel

Timer 13

Timer 8

16

16

RTC

3/6 Capture/Compare

Channels

16

Internal

2 KByte

Dual Port

RAM

WDT

16

C164CI V1.2

Figure 3
Block Diagram

Semiconductor Group 10 1998-02

C164CI

Memory Organization

The memory space of the C164CI is configured in a Von Neumann architecture which means that
code memory, data memory, registers and I/O ports are organized within the same linear address
space which includes 4 MBytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bitaddressable.

The C164CI incorporates 64 KByte of on-chip ROM or OTP memory for code or con stant data. The
OTP memory can be programmed by the CPU itself (in system , eg. during booting) or directly via a n
external interface (eg. before assembly). The programming time is approx. 100 µsec per word. An
external programming voltage V

2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the
system stack, general purpose register ba nks and ev en for c ode. A reg ister b ank c an c onsis t of u p

to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called Gene ral Purpos e
Registers (GPRs).

1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
future members of the C16x family.

= 11.5 V must be supplied for this purpose (via pin EA).

PP

In order to meet the needs of designs where more memory is required than is provi ded on c hip, u p
to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller.

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of two different external memory access modes, which are as follows:

– 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-

State Time, Length of ALE and Read Write Delay) have been m ade programmable to allow the user
the adaption of a wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx /
BUSCONx) which allow to access different resources with different bus characteristics. These
address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and
BUSCON2 overrides BUSCON1. All accesses to location s not covered by these 4 address wind ows
are controlled by BUSCON0.

For applications which require less than 4 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 6 address lines, if an address space of 4 MBytes is used.

Note: When the on-chip CAN Module is to be used the segment address output on Port 4 must be

limited to 4 bits (ie. A19...A16) in order to enable the alternate function of the CAN interface
pins.

Semiconductor Group 11 1998-02

C164CI

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pi peline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate mu ltipl y and d ivide
unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C164CI’s instructions can be exec uted in just one
machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycl e instructions have been optimized s o that they can be executed very fast
as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cach e’, allows reducing the exe cution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

ROM

32

CPU

SP
STKOV
STKUN

Exec. Unit

Instr. Ptr.

Instr. Reg.

4-Stage

Pipeline

PSW

SYSCON

BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4 ADDRSEL 4

Data Page Ptr. Code Seg. Ptr.

MDH
MDL

Mul/Div-HW

Bit-Mask Gen

ALU

(16-bit)

Barrel - Shifter

Context Ptr.

ADDRSEL 1
ADDRSEL 2
ADDRSEL 3

R15

General

Purpose

Registers

R0

16

Internal

RAM

R15

R0

16

MCB02147

Figure 4
CPU Block Diagram

Semiconductor Group 12 1998-02

C164CI

The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.

A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack
is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implem entation of the CPU can efficiently be utilized
by a programmer via the highly efficient C164CI instruction set which includes the following
instruction classes:

– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible op erand types are bits, by tes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.

Semiconductor Group 13 1998-02

C164CI

Interrupt System

With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal
program execution), the C164CI is capable of reacting very fast to the occurrence of non­deterministic events.

The architecture of the C164CI supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and

a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word dat a transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmi ssion or reception of b locks of data. The C164CI
has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request fla g, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related regis ter, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritize d service reques t. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.

Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature program mable ed ge detecti on (rising edge, fa lling
edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.

The following table shows all of the possible C164CI interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:

Source of Interrupt or PEC
Service Request

Fast External Interrupt 0 CC8IR CC8IE CC8INT 00’0060
Fast External Interrupt 1 CC9IR CC9IE CC9INT 00’0064
Fast External Interrupt 2 CC10IE CC10IE CC10INT 00’0068
Fast External Interrupt 3 CC11IE CC11IE CC11INT 00’006C
GPT1 Timer 2 T2IR T2IE T2INT 00’0088
GPT1 Timer 3 T3IR T3IE T3INT 00’008C

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

H
H
H

H

H

H

Trap
Number

18

H

19

H

1A

H

1B

H

22

H

23

H

Semiconductor Group 14 1998-02

C164CI

Source of Interrupt or PEC
Service Request

GPT1 Timer 4 T4IR T4IE T4INT 00’0090

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

H

Trap
Number

24
A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0 28
A/D Overrun Error ADEIR A DEIE ADEINT 00’00A4 29
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8
ASC0 Receive S0RIR S0RIE S0RINT 00’00AC
ASC0 Error S0EIR S0EIE S0EINT 00’00B0
SSC Transmit SCTIR SCTIE SCTINT 00’00B4
SSC Receive SCRIR SCRIE SCRINT 00’00B8
SSC Error SCEIR S CEIE SCEINT 00’00BC
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4
CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CC
CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0
CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4
CAPCOM Register 26 CC26IR CC26IE CC426NT 00’00E8
CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00EC
CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8
CAPCOM 6 Interrupt CC6IR CC6IE CC6INT 00’00FC
XPER Node 0 Int / CAN XP0IR XP0IE XP0INT 00’0100
XPER Node 3 Int / PLL / T14 XP3IR XP3IE XP3INT 00’010C
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C
CAPCOM 6 Timer 12 T12IR T12IE T12INT 00’0134
CAPCOM 6 Timer 13 T13IR T13IE T13INT 00’0138
CAPCOM 6 Emergency CC6EIR CC6EIE CC6EINT 00’013C

2A

H

2B

H

2C

H

2D

H

2E

H

2F

H

30

H

31

H

32

H

33

H

38

H

39

H

3A

H

3B

H

3D

H

3E

H

3F

H

40

H

43

H

47

H

4D

H

4E

H

4F

H

H
H
H

H
H
H
H

H
H
H
H
H
H
H
H

H

H

H

H
H
H
H
H

H

H
H

Semiconductor Group 15 1998-02

C164CI

The C164CI also provides an excellent mechanism to identify and to process exceptions or error

conditions that arise during run-time, so-cal led ‘Hardware Trap s’. Ha rdware traps c ause im mediate
non-maskable system reaction which is similar to a standard interrupt service (branching to a
dedicated vector table location). The occurence of a hardware trap is additionally signified by an
individual bit in the trap flag register (TFR). Except when another higher prioritize d trap service is in
progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error condit ions that can arise during run­time:

Exception Condition Trap

Flag

Trap
Vector

Vector
Location

Reset Functions:

Hardware Reset
Software Reset
Watchdog Timer Overflow

RESET
RESET
RESET

00’0000
00’0000
00’0000

Class A Hardware Traps:

Non-Maskable Interrupt
Stack Overflow
Stack Underflow

NMI
STKOF
STKUF

NMITRAP
STOTRAP
STUTRAP

00’0008
00’0010
00’0018

Class B Hardware Traps:

Undefined Opcode
Protected Instruction

UNDOPC
PRTFLT

BTRAP
BTRAP

00’0028

00’0028
Fault
Illegal Word Operand

ILLOPA

BTRAP

00’0028
Access
Illegal Instruction Access
Illegal External Bus

ILLINA
ILLBUS

BTRAP
BTRAP

00’0028

00’0028
Access

Reserved [2C
Software Traps

TRAP Instruction

Any

[00’0000

00’01FC

in steps

of 4

Trap
Number

00

H
H
H

H
H
H

H
H

H

H
H

– 3CH][0BH – 0FH]

H

00
00

02
04
06

0A
0A

0A

0A
0A

H
H
H

H
H
H

H
H

H

H
H

Any

–

H

]

H

H

[00

– 7FH]

H

Trap
Priority

III
III
III

II
II
II

I
I

I

I
I

Current
CPU
Priority

Semiconductor Group 16 1998-02