Sharp LZ24BP Datasheet

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1

DESCRIPTION

The LZ24BP is a 1/4-type (4.5 mm) solid-state
image sensor that consists of PN photo-diodes and
CCDs (charge-coupled devices). With approxi­mately 350 000 pixels (692 horizontal x 504
vertical), the sensor provides a stable high­resolution color image. All pixel signals can be read
independently via the vertical shift register and
horizontal shift register.

FEATURES

• Progressive scan

• Square pixel

• Compatible with VGA format

• Number of effective pixels : 659 (H) x 494 (V)

• Number of optical black pixels
– Horizontal : 2 front and 31 rear
– Vertical : 8 front and 2 rear

• Number of dummy bits
– Horizontal : 16
– Vertical : 5

• Pixel pitch : 5.6 µm (H) x 5.6 µm (V)

• R, G, and B primary color mosaic filters

• Low fixed-pattern noise and lag

• No burn-in and no image distortion

• Blooming suppression structure

• Built-in output amplifier

• Built-in overflow drain voltage circuit and reset
gate voltage circuit

• Horizontal shift register clock and reset gate clock
voltage : 3.3 V (TYP.)

• Variable electronic shutter (1/30 to 1/10 000 s)

• Package :
14-pin half-pitch WDIP [Plastic]
(WDIP014-P-0400A)
Row space : 10.16 mm

PIN CONNECTIONS

PRECAUTIONS

• The exit pupil position of lens should be more
than 25 mm from the top surface of the CCD.

• Refer to "PRECAUTIONS FOR CCD AREA

SENSORS" for details.

LZ24BP

1/4-type Progressive-scan Color CCD

Area Sensor with 350 k Pixels

LZ24BP

ØV2

ØV1

ØV3A

ØV3B

PW

GND

OS

Ø

H2

ØH1

ØRS

NC

OFD

GND

OD

1

2

3

4

5

6

7

14

13

12

11

10

9

8

14-PIN HALF-PITCH WDIP

TOP VIEW

(WDIP014-P-0400A)

LZ24BP

2

PIN DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

(TA = +25 ˚C)

PARAMETER SYMBOL RATING UNIT

Output transistor drain voltage V

OD 0 to +18 V

Reset gate clock voltage V

ØRS Internal output V

Vertical shift register clock voltage V

ØV –11.5 to +17.5 V

Horizontal shift register clock voltage VØH –0.3 to +12 V
Voltage difference between P-well and vertical clock V

PW-VØV –29 to 0 V

Storage temperature T

STG –40 to +85 ˚C

Ambient operating temperature T

OPR –20 to +70 ˚C

2

NOTE

NOTES :

1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is
applied below 27 Vp-p.

2. Do not connect to DC voltage directly. When Ø

RS is connected to GND, connect VOD to GND. Reset gate clock is

applied below 8 Vp-p.

3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 28 V.

1VInternal outputVOFDOverflow drain voltage

3V0 to +15V

ØV-VØVVoltage difference between vertical clocks

SYMBOL PIN NAME

OD Output transistor drain
OS Output signals
ØRS Reset transistor clock
Ø

V1, ØV2, ØV3A, ØV3B Vertical shift register clock

ØH1, ØH2 Horizontal shift register clock

PW P-well
GND Ground
NC No connection

Overflow drainOFD

3

LZ24BP

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE

Ambient operating temperature T

OPR 25.0 ˚C

Output transistor drain voltage V

OD 14.55 15.0 15.45 V

NOTES :

1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.

2. V

PW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected

to V

L of V driver IC.

* To apply power, first connect GND and then turn on V

OD. After turning on VOD, turn on PW first and then turn on other powers

and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.

1V22.5VØOFD

Overflow drain clock

P-well voltage VPW –10.0 VØVL V2

Ground GND 0.0 V

V–8.5–9.0–9.5

V

ØV1L, VØV2L

VØV3AL, VØV3BL

Vertical shift
register clock

LOW level

INTERMEDIATE level

HIGH level

V

ØV1I, VØV2I

VØV3AI, VØV3BI

VØV3AH, VØV3BH 14.55

0.0

15.0 15.45VV

LOW levelHorizontal shift

register clock

V

ØH1L, VØH2L –0.05 0.0 0.05 V

HIGH level VØH1H, VØH2H 3.0 3.3 5.5 V

1V5.53.33.0V

ØRSReset gate clock p-p level

Reset gate clock frequency f

ØRS 12.27 MHz

Horizontal shift register clock frequency fØH1, fØH2 12.27 MHz

Vertical shift register clock frequency

f

ØV1, fØV2

fØV3A, fØV3B

15.73 kHz

p-p level