Sharp LZ23H3V1 Datasheet

LZ23H3V1

DESCRIPTION

The LZ23H3V1 is a 1/3-type (6.0 mm) solid-state image sensor that consists of PN photo-diodes and CCDs (charge-coupled devices). With approximately 1 090 000 pixels (1 217 horizontal x 893 vertical), the sensor provides a stable highresolution color image.

FEATURES

• Optical size : Number of effective pixels – Approx. 1 000 k; 6.6 mm – Approx. 790 k; 5.9 mm (compatible with XGA

format)

• Interline scan format

• Square pixel

• Number of effective pixels : 1 174 (H) x 884 (V)

• Number of optical black pixels – Horizontal : 3 front and 40 rear – Vertical : 7 front and 2 rear

• Number of dummy bits – Horizontal : 22 – Vertical : 2

• Pixel pitch : 4.6 µm (H) x 4.6 µm (V)

• R, G, and B primary color mosaic filters

• Supports monitoring mode

• Low fixed-pattern noise and lag

• No burn-in and no image distortion

• Blooming suppression structure

• Built-in output amplifier

• Built-in overflow drain voltage circuit and reset gate voltage circuit

• Variable electronic shutter

• Package : 16-pin shrink-pitch WDIP [Ceramic] (WDIP016-N-0500C) Row space : 12.70 mm

PIN CONNECTIONS

PRECAUTIONS

• The exit pupil position of lens should be 15 to 50 mm from the top surface of the CCD.

• Refer to "PRECAUTIONS FOR CCD AREA SENSORS" for details.

(1 024)

1 000 k pixels

1 156

790 k pixels

866

(768)

(5.9 mm) 6.6 mm

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

LZ23H3V1

1/3-type Interline Color CCD Area

Sensor with 1 090 k Pixels

1OD

2GND

3OFD

4PW

5Ø

6NC

7Ø

9Ø

GND

V1A

ØV1B

ØV2

ØV3A

ØV3B

ØV4

16-PIN SHRINK-PITCH WDIP

TOP VIEW

(WDIP016-N-0500C)

LZ23H3V1

PIN DESCRIPTION

SYMBOL PIN NAME

OD Output transistor drain OS Output signals ØRS Reset transistor clock Ø

V1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4 Vertical shift register clock

ØH1, ØH2 Horizontal shift register clock

PW P-well GND Ground NC No connection

Overflow drainOFD

ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C)

PARAMETER SYMBOL RATING UNIT

Output transistor drain voltage V

OD 0 to +18 V

Reset gate clock voltage V

ØRS Internal output V

Vertical shift register clock voltage V

ØV VPW to +18 V

Horizontal shift register clock voltage VØH –0.3 to +12 V Voltage difference between P-well and vertical clock V

PW-VØV –29 to 0 V

Storage temperature T

STG –40 to +85 ˚C

Ambient operating temperature T

OPR –20 to +70 ˚C

NOTE

NOTES :

1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is applied below 27 Vp-p.

2. Do not connect to DC voltage directly. When Ø

RS is connected to GND, connect VOD to GND. Reset gate clock is

applied below 8 Vp-p.

3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 28 V.

1VInternal outputVOFDOverflow drain voltage

3V0 to +15V

ØV-VØVVoltage difference between vertical clocks

LZ23H3V1

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE

Ambient operating temperature T

OPR 25.0 ˚C

Output transistor drain voltage V

OD 14.55 15.0 15.45 V

NOTES :

1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.

2. V

PW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected

to V

L of V driver IC.

3. Operation frequency is 14.32 MHz.

4. Operation frequency is 18.00 MHz.

* To apply power, first connect GND and then turn on V

OD. After turning on VOD, turn on PW first and then turn on other powers

and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.

1V26.524.5VØOFD

Overflow drain clock

P-well voltage VPW –10.0 VØVL V2

Ground GND 0.0 V

V–8.5–9.0–9.5

ØV1AL, VØV1BL, VØV2L

VØV3AL, VØV3BL, VØV4L Vertical shift register clock

LOW level

INTERMEDIATE level

HIGH level

ØV1AI, VØV1BI, VØV2I

VØV3AI, VØV3BI, VØV4I

VØV1AH, VØV1BH VØV3AH, VØV3BH

14.55

0.0

15.0 15.45VV

LOW levelHorizontal shift

ØH1L, VØH2L –0.05 0.0 0.05 V

HIGH level V

ØH1H, VØH2H 4.5 5.0 5.5 V

1V5.55.04.5V

ØRSReset gate clock p-p level

Reset gate clock frequency f

ØRS

14.32 MHz 3

Horizontal shift register clock frequency f

ØH1, fØH2

14.32 MHz 3

Vertical shift register clock frequency

ØV1A, fØV1B, fØV2

fØV3A, fØV3B, fØV4

10.88 kHz 3 4kHz13.47

4MHz18.00

p-p level

LZ23H3V1

CHARACTERISTICS (Drive method : 1/30 s frame accumulation)

A = +25 ˚C, Operating conditions : The typical values specified in "

RECOMMENDED OPERATING CONDITIONS

Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE

Standard output voltage V

O 150 mV 2

Photo response non-uniformity PRNU 10 % 3

Saturation output voltage V

SAT

450 530 mV 4

Dark output voltage V

DARK 0.5 3.0 mV 1, 6

Dark signal non-uniformity DSNU 0.5 2.0 mV 1, 7 Sensitivity (green channel) R 105 150 mV 8 Smear ratio SMR –75 –65 dB 9

NOTES :

• Within the recommended operating conditions of VOD, V

OFD of the internal output satisfies with ABL larger than

500 times exposure of the standard exposure conditions, and V

SAT larger than 330 mV.

1. T

A = +60 ˚C

2. The average output voltage of G signal under uniform illumination. The standard exposure conditions are defined as when Vo is 150 mV.

3. The image area is divided into 10 x 10 segments under the standard exposure conditions. Each segment's voltage is the average output voltage of all pixels within the segment. PRNU is defined by (Vmax – Vmin)/Vo, where Vmax and Vmin are the maximum and minimum values of each segment's voltage respectively.

4. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. V

SAT is the minimum

segment's voltage under 10 times exposure of the standard exposure conditions. The operation of OFDC is high. (for still image capturing)

5. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. V

SAT is the minimum

segment's voltage under 10 times exposure of the standard exposure conditions. The operation of OFDC is low.

6. The average output voltage under non-exposure conditions.

7. The image area is divided into 10 x 10 segments under non-exposure conditions. DSNU is defined by (Vdmax – Vdmin), where Vdmax and Vdmin are the maximum and minimum values of each segment's voltage respectively.

8. The average output voltage of G signal when a 1 000 lux light source with a 90% reflector is imaged by a lens of F4, f50 mm.

9. The sensor is exposed only in the central area of V/10 square with a lens at F4, where V is the vertical image size. SMR is defined by the ratio of the output voltage detected during the vertical blanking period to the maximum output voltage in the V/10 square.

10. The sensor is exposed at the exposure level corresponding to the standard conditions. AI is defined by the ratio of the output voltage measured at the 1st field during the non-exposure period to the standard output voltage.

11. The sensor is exposed only in the central area of V/10 square, where V is the vertical image size. ABL is defined by the ratio of the exposure at the standard conditions to the exposure at a point where blooming is observed.

12. The sensor is exposed at the exposure level corresponding to the standard conditions. LCR is defined by (∆V

G/VO) x 100, where ∆VG is the difference

between the average output voltage of G signal at the 1st field, and that of G signal at the 2nd field.

5mV410330

11500ABLBlooming suppression ratio

10%1.0AIImage lag

Output transistor drain current I

OD 4.0 8.0 mA

12%3.0LCRLine crawling

LZ23H3V1

PIXEL STRUCTURE

1 pin

1 174 (H) x 884 (V)

OPTICAL BLACK

(2 PIXELS)

OPTICAL BLACK

(7 PIXELS)

OPTICAL BLACK

(3 PIXELS)

OPTICAL BLACK

(40 PIXELS)

COLOR FILTER ARRAY

GBGBG

RGRGR

GBGBG

RGRGR

GBGBG

RGRGR

BGBGB

GRGRG

BGBGB

GRGRG

BGBGB

GRGRG

BGBGB

GRGRG

BGBGB

GRGRG

BGBGB

GRGRG

GBGBG

RGRGR

GBGBG

RGRGR

GBGBG

RGRGR

(1, 884) (1 174, 884)

(1, 1) (1 174, 1)

V3B

ØV1A

ØV1B

ØV3A

ØV1A

ØV3A

ØV1B

ØV3B

ØV1B

ØV3A

ØV3B

Pin arrangement of the vertical readout clock

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LZ23H3V1

TIMING CHART

NOTES :

1. Do not use these signals immediately after field accumulation mode is transferred to frame accumulation mode for still image capturing.

2. Do not use these signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring mode image.

* Apply at least an OFD shutter pulse to OFD in each field accumulation mode.

* Do not use the field signals immediately after frame accumulation mode is transferred to field

accumulation mode.

ØV3A

ØV2

ØV1B

ØV1A

TIMING CHART EXAMPLE

OFDC

OFD

ØV4

ØV3B

(at OFD shutter operation)

Field accumulation mode Field accumulation

Not for use 

(NOTE 1)

Not for use 

(NOTE 1)

Not for use 

(NOTE 2)

Frame accumulation mode

(2.3..882.883) (2.3..882.883) (2.4..882.884) (1.3..881.883) mode (2.3..882.883)

(Number of  vertical line)

Pulse diagram in more detail is shown in the figure q to t after next page.

Field accumulation mode Frame accumulation

mode at first

Frame accumulation mode Field accumulation

mode at first

Field accumulation  mode

qqwer e'tq

ØOFD

ØV3A

OFDC

ØV3B

ØV2

ØV1B

ØV1A

Shutter speed

1/1 000 s

VERTICAL TRANSFER TIMING FOR 14.3 MHz OPERATION ¿FIELD ACCUMULATION MODE¡

453 1 6 10

874 875 878 879 882 883 OB2 OB1 OB2 OB5 OB6 2 3 6 7 10 11 14 15 18 19

GB RG GB RG GB RG GB RG GB RGGB RG GB RG GB RG



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