Samsung S3C7044, S3C7048, S3P7048 Datasheet

S3C7044/C7048/P7048 PRODUCT OVERVIEW

1PRODUCT OVERVIEW

The S3C7044/C7048 single-chip CMOS microcontroller has been designed for very high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

The S3P7048 is the microcontroller which has 8K-bytes one-time-programmable ROM and the functions are
same to S3C7044/C7048.

With two 8-bit timer/counters, an 8-bit serial I/O interface, and eight software n-channel open-drain I/O pins, the
S3C7044/C7048 offers an excellent design solution for a wide variety of general-purpose applications.

Up to 36 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts
provide fast response to internal and external events.

In addition, the S3C7044/C7048's advanced CMOS technology provides for low power consumption and a wide
operating voltage range.

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PRODUCT OVERVIEW S3C7044/C7048/P7048

FEATURES SUMMARY

Memory

• 512 × 4-bit RAM

• 4096 × 8-bit ROM: S3C7044

• 8192 × 8-bit ROM: S3C7048

36 I/O Pins

• Input only: 4 pins

• I/O: 24 pins

• N-channel open-drain I/O: 8 pins

Memory-Mapped I/O Structure

• Data memory bank 15

8-Bit Basic Timer

• 4 interval timer functions

Two 8-Bit Timer/Counters

• Programmable interval timer

• External event counter function

• Timer/counters clock outputs to TCLO0 and

TCLO1 pins

Bit Sequential Carrier

• Supports 16-bit serial data transfer in arbitrary
format

Interrupts

• 3 external interrupt vectors

• 4 internal interrupt vectors

• 2 quasi-interrupts

Power-Down Modes

• Idle: Only CPU clock stops

• Stop: System clock stops

Oscillation Sources

• Crystal or Ceramic for system clock

• Oscillation frequency : 0.4 – 6.0MHz

• CPU clock divider circuit (by 4. 8, or 64)

Instruction Execution Times

• 0.95, 1.91, 15.3 µs at 4.19 MHz

• 0.67, 1.33, 10.7 µs at 6.0 MHz

Watch Timer

• Time interval generation: 0.5 s, 3.9 ms at

4.19 MHz

• 4 frequency outputs to the BUZ pin

8-Bit Serial I/O Interface

• 8-bit transmit/receive mode

• 8-bit receive mode

• LSB-first or MSB-first transmission selectable

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Operating Temperature

• - 40 °C to 85 °C

Operating Voltage Range

• 1.8 V to 5.5 V (Main)

• 2.0 V to 5.5 V (OTP)

Package Types

• 42-pin SDIP, 44-pin QFP

S3C7044/C7048/P7048 PRODUCT OVERVIEW

FUNCTION OVERVIEW

SAM47 CPU

All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up
to 32K-byte of program memory. The arithmetic logic unit(ALU) performs 4-bit addition, subtraction, logical, and
shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operation in two cycles.

CPU REGISTERS
program counter

A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Usually, the PC
is incremented by the number of bytes of the fetched instruction. The one instruction fetch that does not
increment the PC is the 1-byte REF instruction which references instruction stored in a look-up table in the ROM.
Whenever a reset operation or an interrupt occurs, bits PC12 though PC0 are set to the vector address.

Stack pointer

An 8-bit stack pointer (SP) stores addresses for stack operation. The stack area is located in general-purpose
data memory bank 0. The SP is 8-bit read/writeable and SP bit 0 must always be logic zero.

During an interrupt or a subroutine call, the PC value and the PSW are written to the stack area. When the
service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction
is executed.

The stack pointer can access the stack despite data memory access enable flag status. Since the reset value of
the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00H. This sets
the first register of the stack area to data memory location 0FFH.

PROGRAM MEMORY

In its standard configuration, the 4096 x 8-bit (S3C7404), 8192 x 8-bit (S3C7408) ROM is divided into four areas:

 16-byte area for vector addresses
 96-byte instruction reference area
 16-byte general-purpose area (0010 – 001FH)
 3968-byte area for general-purpose program memory (S3C7404)
 8064-byte area for general-purpose program memory (S3C7408)

The vector address area is used mostly during reset operation and interrupts. These 16 bytes can alternately be
used as general-purpose ROM.

The REF instruction references 2x1-byte or 2-byte instruction stored in reference area location 0020H – 007FH.
REF can also reference three-byte instruction such as JP or CALL. So that a REF instruction can reference these
instruction, however, the JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written to
the reference area with the format TJP or TCALL instead of the normal instruction name. Unused location in the
REF instruction look-up area can be allocated to general-purpose use.

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PRODUCT OVERVIEW S3C7044/C7048/P7048

DATA MEMORY
Overview

The 512 x 4bit data memory has five areas:

 32 x 4-bit working register area
 224 x 4-bit general-purpose area in bank 0 which is also used as the stack area
 256 x 4-bit general-purpose area in bank 1
 128 x 4-bit area in bank 15 for memory-mapped I/O addresses

The data memory area is also organized as three memory banks  bank0, bank1, and bank15. You use the
select memory bank instruction (SMB) to select one of the banks as working data memory.

Data stored in RAM location are 1-, 4-, and 8-bit addressable. After a hardware reset, data memory initialization
values must be defined by program code.

Data Memory addressing modes

The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, or 15. When the
EMB flag is logic zero, only location 00H–7FH of bank 0 and bank 15 can be accessed. When the EMB flag is
set to logic one, all three data memory banks can be accessed based on the current SMB value.

Working registers

The RAM's working register area in data memory bank 0 is also divided into four register banks. Each register
bank has eight 4-bit registers. Paired 4-bit registers are 8-bit addressable.

Register A can be used as a 4-bit accumulator and double register EA as an 8-bit extended accumulator; double
registers WX, WL, and HL are used as address pointers for indirect addressing.

To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for
main programs and banks 1, 2, and 3 for interrupt service routines.

Bit sequential carrier

The bit sequential carrier (BSC) mapped in data memory bank 15 is a 16-bit general register that you can
manipulate using 1-, 4-, and 8-bit RAM control instructions.

Using the BSC register, addresses and bit location can be specified sequentially using 1-bit indirect addressing
instructions. In this way, a program can generate 16-bit data output by moving the bit location sequentially,
incrementing or decrementing the value of the L register. You can also use direct addressing to manipulate data
in the BSC.

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S3C7044/C7048/P7048 PRODUCT OVERVIEW

CONTROL REGISTERS
Program Status Word

The 8-bit program status word (PSW) controls ALU operation and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.

Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.

IS1 IS0 EMB ERB

C SC2 SC1 SC0

Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag ( C ) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.

Select Bank (SB) Register

Two 4-bit location called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.

'SMB n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SMB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.

The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.

CLOCK CIRCUITS

System oscillation circuit generates the internal clock signals for the CPU and peripheral hardwares. The system
clock can use a crystal, ceramic, or RC oscillation source, or an externally-generated clock signal. To drive
S3C7044/C7048 using an external clock source, the external clock signal should be input to Xin, and its inverted

signal to X

out

.

A 4-bit power control register is used to enable or disable oscillation, and to select the CPU clock. The internal
system clock signal (fx) can be divided internally to produce three CPU clock frequencies  fx/4, fx/8, or fx/64.

INTERRUPTS

Interrupt requests can be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, and INT4). There are two quasi-interrupts: INT2 and INTW.

INT2/KS0–KS7 detects rising/falling edges of incoming signals and INTW detects time intervals of 0.5 seconds
of 3.91 milliseconds at 4.19MHz. The following components support interrupt processing:

 Interrupt enable flags
 Interrupt request flags
 Interrupt priority registers
 Power-down termination circuit

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PRODUCT OVERVIEW S3C7044/C7048/P7048

POWER-DOWN

To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle
mode and the STOP instruction initiates stop mode.

In idle mode, only the CPU clock stops while peripherals and the oscillation source continue to operate normally.
Stop mode effects only the system clock. In stop mode system clock oscillation stops completely, halting all

operations except for a few basic peripheral functions. RESET or an interrupt (with the exception of INT0) can be
used to terminate either idle or stop mode.

RESETRESET

When a RESET signal occurs during normal operation or during power-down mode, the CPU enters idle mode
when the reset operation is initiated. When the standard oscillation stabilization interval (31.3 ms at 4.19 MHz)
has elapsed, normal CPU operation resumes.

I/O PORTS

The S3C7044/C7048 has 9 I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–FFCH in
bank 15 of the RAM.

There are 4 input pins, 24 configurable I/O pins, and 8 software n-channel open-drain I/O pins, for a total of 36
I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using
bit manipulation instructions.

TIMERS AND TIMER/COUNTERS

The timer function has four main components: an 8-bit basic interval timer, two 8-bit timer/counters, and a watch
timer. The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected CPU clock
frequency.

The programmable 8-bit timer/counters are used for external event counting, generation of arbitrary clock
frequencies for output, and dividing external clock signals. The 8-bit timer/counter 0 generates a clock signal

(SCK) for the serial I/O interface.
The watch timer has an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. Its

functions include real-time and watch-time measurement, and frequency outputs for buzzer sound.

SERIAL I/O INTERFACE

The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The
serial interface has the following functional components:

 8-bit mode register
 Clock selector circuit
 8-bit buffer register
 3-bit serial clock counter

The serial I/O circuit can be set either to transmit-and-receive or to receive-only mode. MSB-first or LSB-first
transmission is also selectable. The serial interface operates with an internal or an external clock source, or using
the clock signal generated by the 8-bit timer/counter 0. To modify transmission frequency, the appropriate bits in
the serial I/O mode register (SMOD) must be manipulated.

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S3C7044/C7048/P7048 PRODUCT OVERVIEW

BLOCK DIAGRAM

P4.0–P4.3

P5.0–P5.3

P6.0–P6.3 /

KS0–KS3

P7.0–P7.3 /

KS4–KS7

P8.0–P8.3

INT0, INT1,

INT2,INT4

8-BIT

TIMER/

COUNTER 0

8-BIT

TIMER/

COUNTER 1

I/O PORT 4

I/O PORT 5

I/O PORT 6

I/O PORT 7

I/O PORT 8

RESET

INTERRUPT

CONTROL

BLOCK

INTERNAL

INTERRUPTS

INSTRUCTION DECODER

ARITHMETIC

LOGIC UNIT

512 x 4-BIT

DATA

MEMORY

Xin Xout

AND

CLOCK

BASIC

TIMER

INSTRUCTION

REGISTER

PROGRAM
COUNTER

PROGRAM

STATUS WORD

STACK

POINTER

PROGRAM MEMORY

4 KBYTE: S3C7404
8 KBYTE: S3C7408

WATCH

TIMER

I/O PORT 0

SERIAL

I/O

INPUT

PORT 1

I/O PORT 2

I/O PORT 3

P0.0 /

SCK

P0.1 / SO
P0.2 / SI
P0.3 / BTCO

P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4

P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ

P3.0 / TCL0
P3.1 / TCL1
P3.2
P3.3

Figure 1-1. S3C7044/C7048/P0408 Block Diagram

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PRODUCT OVERVIEW S3C7044/C7048/P7048

PIN ASSIGNMENTS

P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

P2.3/BUZ

P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0

P0.3/BTCO

P0.2/SI

P0.1/SO

P0.0/SCK

P8.3
P8.2
P8.1
P8.0
P3.3

P3.2
P3.1/TCL1
P3.0/TCL0

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38

S3C7044/C7048

(42-SDIP-600)

37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

VSS
P7.0/KS4
P7.1/KS5
P7.2/KS6
P7.3/KS7
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
XIN
XOUT

RESET

P5.0
P5.1
P5.2
P5.3
P4.0
P4.1
P4.2
P4.3
TEST

Figure 1-2. S3C7044/C7048 Pin Assignment Diagrams (42-SDIP Pakage)

1-8

S3C7044/C7048/P7048 PRODUCT OVERVIEW

P3.1/TCL1

P3.0/TCL0

P5.3
P5.2
P5.1
P5.0

RESET

XOUT

XIN
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0

P4.0

4443424140393837363534

1
2
3
4
5

S3C7044/C7048

6

(44-QFP-1010B)

7
8
9
10
11

1213141516171819202122

P7.3/KS7

P7.2/KS6

VDD

VSS

P7.1/KS5

P7.0/KS4

P1.3/INT4

P1.2/INT2

TEST

P4.3

P4.2

P4.1

P3.3

P3.2

NC

P2.3/BUZ

P1.1/INT1

P2.2/CLO

P1.0/INT0

33
32
31
30
29
28
27
26
25
24
23

NC
P8.0
P8.1
P8.2
P8.3
P0.0/SCK
P0.1/SO
P0.2/SI
P0.3/BTCO
P2.0/TCLO0
P2.1/TCLO1

Figure 1-3. S3C7044/C7048 Pin Assignment Diagrams (44-QFP Pakage)

1-9

PRODUCT OVERVIEW S3C7044/C7048/P7048

PIN DESCRIPTIONS

Table 1-1. S3C7044/C7048/P0408 Pin Description

Pin Name Pin Type Description Number Share Pin

P0.0
P0.1
P0.2
P0.3

P1.0
P1.1
P1.2
P1.3

P2.0
P2.1
P2.2
P2.3

P3.0
P3.1
P3.2
P3.3

P4.0–P4.3
P5.0–P5.3

P6.0–P6.3
P7.0–P7.3

P8.0–P8.3 I/O 4-bit I/O ports.

I/O 4-bit I/O port.

1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.

12 (28)
11 (27)
10 (26)

9 (25)
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

I 4-bit input port.

1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are assignable by software to
pins P1.0, P1.1, and P1.2.

4 (20)

3 (19)

2 (18)

1 (17)

I/O Same as port 0. 8 (24)

7 (23)

6 (22)

5 (21)

I/O Same as port 0. 20 (38)

19 (37)
18 (36)
17 (35)

I/O 4-bit I/O ports.

N-channel open-drain output up to 9 volts.
1-bit and 4-bit read/write and test is possible.
Ports 4 and 5 can be paired to support 8-bit data

26–23

(44–41)

30–27

(4–1)
transfer.
8-bit unit pull-up resistors are assignable by mask
option.

I/O 4-bit I/O ports.

1-bit or 4-bit read/write and test is possible.
Port 6 pins are individually software configurable as
input or output.

37–34

(11–8)

41–38

(15–12)
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins
(port 6 only).
Ports 6 and 7 can be paired to enable 8-bit data
transfer.

16–13

1-bit and 4-bit read/write and test is possible.

(32–29)
Pins are individually software configurable as input or
output.
4-bit pull-down resistors are software assignable;
pull-down resistors are automatically disabled for
output pins.

SCK

SO

SI

BTCO

INT0
INT1
INT2
INT4

TCLO0
TCLO1

CLO
BUZ

TCL0
TCL1

–

KS0–KS3
KS4–KS7

–

NOTE: Parentheses indicate pin number for 44 QFP package.

1-10

S3C7044/C7048/P7048 PRODUCT OVERVIEW

Table 1-1. S3C7044/C7048 Pin Descriptions (Continued)

Pin Name Pin Type Description Number Share

Pin

SCK

I/O Serial I/O interface clock signal 12 (28) P0.0

SO I/O Serial data output 11 (27) P0.1
SI I/O Serial data input 10 (26) P0.2
BTCO I/O Basic timer clock output (2 Hz, 16 Hz, 64 Hz, or 256

9 (25) P0.3

Hz at 4.19 MHz)

INT0, INT1 I External interrupts. The triggering edge for INT0 and

INT1 is selectable. INT0 is synchronized to system

4, 3

(20, 19)

P1.0, P1.1

clock.
INT2 I Quasi-interrupt with detection of rising edges 2 (18) P1.2
INT4 I External interrupt with detection of rising and falling

1 (17) P1.3

edges.
TCLO0 I/O Timer/counter 0 clock output 8 (24) P2.0
TCLO1 I/O Timer/counter 1 clock output 7 (23) P2.1
CLO I/O Clock output 6 (22) P2.2
BUZ I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at

5 (21) P2.3

4.19 MHz for buzzer sound
TCL0 I/O External clock input for timer/counter 0 20 (38) P3.0
TCL1 I/O External clock input for timer/counter 1 19 (37) P3.1
KS0–KS3

I/O Quasi-interrupt inputs with falling edge detection 37–34

P6.0–P6.3

(11–8)

KS4–KS7

41–38

P7.0–P7.3

(15–12)

V

DD

– Power supply 21 (39)

–

V

SS

RESET

Xin, X

out

– Ground 42 (16)

I Reset signal 31 (5)

– Crystal, ceramic, or RC oscillator signal for system

clock (For external clock input, use Xin and input
Xin's reverse phase to X

out

)

33, 32

(7, 6)

TEST – Test signal input (must be connected to VSS) 22 (40)
NC – No connection (must be connected to VSS) (33, 34) –

NOTE: Parentheses indicate pin number for 44 QFP package.

–
–
–

–

1-11

PRODUCT OVERVIEW S3C7044/C7048/P7048

Table 1-2. Overview of S3C7044/C7048 Pin Data

Pin Names Share Pins I/O Type Reset Value Circuit Type

P0.0–P0.3

SCK, SO, SI, BTCO

I/O Input D-1

P1.0–P1.2 INT0, INT1, INT2 I Input A-3
P1.3 INT4 I Input B-4
P2.0–P2.3 TCLO0, TCLO1, CLO,

I/O Input D

BUZ
P3.0–P3.1 TCL0, TCL1 I/O Input D-1
P3.2–P3.3 – I/O Input D
P4.0–P4.3

– I/O

(NOTE)

E-2

P5.0–P5.3
P6.0–P6.3

P7.0–P7.3

KS0–KS3

KS4–KS7

I/O Input D-1

P8.0–P8.3 – I/O Input D-2
Xin, X

RESET

out

– – – –
– I – B

TEST – I – –
NC – – – –
VDD, V

SS

– – – –

NOTE: When pull-up resistors are provided, port 4 and port 5 pins are reset to high level; with no pull-ups, they are reset to

high impedance.

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