Samsung M471B5673FH0-CF8 User Manual

Rev. 1.31, Dec. 2010

M471B2873FHS
M471B5673FH0

204pin Unbuffered SODIMM

based on 1Gb F-die

78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other­wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.

- 1 -

Rev. 1.31

Unbuffered SODIMM datasheet DDR3 SDRAM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First Release Dec. 2009 - S.H.Kim

1.1 - Changed DIMM IDD Definition Jan. 2010 - S.H.Kim

- Added DIMM IDD Specification

1.2 - Added "CL5" to Supported CL setting Feb. 2010 - S.H.Kim

1.21 - Corrected Typo. Mar. 2010 - S.H.Kim

1.3 - Updated the datasheet following JEDEC(JESD79-3E). Jul. 2010 - S.H.Kim

1.31 - Corrected Typo. Dec. 2010 - S.H.Kim

- 2 -

Rev. 1.31

Unbuffered SODIMM datasheet DDR3 SDRAM

Table Of Contents

204pin Unbuffered SODIMM based on 1Gb F-die

1. DDR3 Unbuffered SODIMM Ordering Information........................................................................................................4

2. Key Features................................................................................................................................................................. 4

3. Address Configuration ..................................................................................................................................................4

4. x64 DIMM Pin Configurations (Front side/Back Side)................................................................................................... 5

5. Pin Description ............................................................................................................................................................. 6

6. Input/Output Functional Description..............................................................................................................................7

7. Function Block Diagram:...............................................................................................................................................8

7.1 1GB, 128Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................................... 8

7.2 2GB, 256Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................... 9

8. Absolute Maximum Ratings ..........................................................................................................................................10

8.1 Absolute Maximum DC Ratings............................................................................................................................... 10

8.2 DRAM Component Operating Temperature Range ................................................................................................ 10

9. AC & DC Operating Conditions.....................................................................................................................................10

9.1 Recommended DC Operating Conditions (SSTL-15).............................................................................................. 10

10. AC & DC Input Measurement Levels ..........................................................................................................................11

10.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 11

10.2 V

10.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 13

10.3.1. Differential Signals Definition ......................................................................................................................... 13

10.3.2. Differential Swing Requirement for Clock (CK - CK

10.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 14

10.3.4. Differential Input Cross Point Voltage ............................................................................................................ 15

10.4 Slew Rate Definition for Single Ended Input Signals .............................................................................................15

10.5 Slew rate definition for Differential Input Signals ................................................................................................... 15

11. AC & DC Output Measurement Levels .......................................................................................................................16

11.1 Single Ended AC and DC Output Levels............................................................................................................... 16

11.2 Differential AC and DC Output Levels ................................................................................................................... 16

11.3 Single-ended Output Slew Rate ............................................................................................................................ 16

11.4 Differential Output Slew Rate ................................................................................................................................ 17

12. DIMM IDD specification definition ............................................................................................................................... 18

13. IDD SPEC Table .........................................................................................................................................................20

14. Input/Output Capacitance ...........................................................................................................................................21

15. Electrical Characteristics and AC timing .....................................................................................................................22

15.1 Refresh Parameters by Device Density................................................................................................................. 22

15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 22

15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 22

15.3.1. Speed Bin Table Notes .................................................................................................................................. 26

16. Timing Parameters by Speed Grade ..........................................................................................................................27

16.1 Jitter Notes ............................................................................................................................................................ 30

16.2 Timing Parameter Notes........................................................................................................................................ 31

17. Physical Dimensions :.................................................................................................................................................32

17.1 128Mbx8 based 128Mx64 Module (1 Rank) - M471B2873FHS ............................................................................ 32

17.2 128Mbx8 based 256Mx64 Module (2 Ranks) - M471B5673FH0 .......................................................................... 33

Tolerances.................................................................................................................................................... 12

REF

) and Strobe (DQS - DQS) ............................................. 13

- 3 -

Rev. 1.31

Unbuffered SODIMM datasheet DDR3 SDRAM

1. DDR3 Unbuffered SODIMM Ordering Information

Part Number

M471B2873FHS-CF8/H9/K0 1GB 128Mx64 128Mx8(K4B1G0846F-HC##)*8 1 30mm

M471B5673FH0-CF8/H9/K0 2GB 256Mx64 128Mx8(K4B1G0846F-HC##)*16 2 30mm

NOTE :

1. "##" - F8/H9/K0
2 F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9 & K0 - 1600Mbps 11-11-11

- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)

2

Density Organization Component Composition

Number of

Rank

Height

2. Key Features

Speed

tCK(min) 2.5 1.875 1.5 1.25 ns

CAS Latency 6 7911tCK

tRCD(min) 15 13.125 13.5 13.75 ns

tRP(min) 15 13.125 13.5 13.75 ns

tRAS(min) 37.5 37.5 36 35 ns

tRC(min) 52.5 50.625 49.5 48.75 ns

• JEDEC standard 1.5V ± 0.075V Power Supply

•V

= 1.5V ± 0.075V

DDQ

• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin

• 8 independent internal bank

• Programmable CAS Latency: 5,6,7,8,9,10,11

• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)

• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

• Asynchronous Reset

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

6-6-6 7-7-7 9-9-9 11-11-11

85°C, 3.9us at 85°C < T

CASE

CASE

≤ 95°C

Unit

3. Address Configuration

Organization Row Address Column Address Bank Address Auto Precharge

128x8(1Gb) based Module A0-A13 A0-A9 BA0-BA2 A10/AP

- 4 -

Rev. 1.31

Unbuffered SODIMM datasheet DDR3 SDRAM

4. x64 DIMM Pin Configurations (Front side/Back Side)

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1

3

V

REFDQ

V

2

SS

4 DQ4 KEY 141 DQ34 142 DQ39

5DQ06DQ573CKE074CKE1

7DQ18

9

V

SS

10 DQS077 NC 78

11 DM 0 12 D QS0 7 9 BA2 80

13

V

SS

14

15 DQ2 16 DQ6 83 A12/BC

V

SS

71

V

SS

72

V

SS

139

143 DQ35 144

V

SS

V

SS

75

81

V

DD

V

DD

76

82

V

A15

A14

V

DD

DD

145

3

3

147

149

151

84 A11 153 DM5 154 DQS5

17 DQ3 18 DQ7 85 A9 86 A7 155

19

V

SS

20

V

SS

87

V

DD

88

V

DD

157 DQ42 158 DQ46

21 DQ8 22 DQ12 89 A8 90 A6 159 DQ43 160 DQ47

23DQ924DQ1391A592A4161

25

27 DQS

V

SS

26

1 28 DM1 95 A3 96 A2 165 DQ49 166 DQ53

29 DQS1 30 RESET

31

V

SS

32

V

SS

93

V

DD

94

V

DD

163 DQ48 164 DQ52

97 A1 98 A0 167

V

SS

99

V

DD

100

V

DD

169

33 DQ10 34 DQ14 101 CK0 102 CK1 171

35 DQ11 36 DQ15 103 CK0 104 CK1 173

37

V

SS

38

39 DQ16 40 DQ20

41 DQ17 42 DQ21

43

45 DQS

V

SS

44

246 DM2

47 DQS2 48

49

V

SS

50 DQ22 11 7

51 DQ18 52 DQ23

53 DQ19 54

55

V

SS

56 DQ28

57 DQ24 58 DQ29

59 DQ25 60

61

V

SS

62 DQS3 129 DQ32 130 DQ36 199

63 DM3 64 DQS3

65

V

SS

66

67 DQ26 68 DQ30

69 DQ27 70 DQ31

NOTE :

1. NC = No Connect, NU = Not Usable, RFU = Reserved Future Use

2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.

3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.

V

SS

105

107

109

V

SS

111

113

V

SS

115

119

V

SS

121

123

125 TEST 126

V

SS

127

131

V

SS

133

135

137

V

DD

106

V

DD

175 DQ50 176 DQ55

A10/AP 108 BA1 177 DQ51 178

BA0 110 RAS 179

V

DD

112

V

DD

181 DQ56 182 DQ61

WE 11 4 S0 183 DQ57 184

CAS 116 ODT0 185

V

A13

DD

118

3

120 ODT1 189

V

DD

187 DM7 188 DQS7

S1 122 NC 191 DQ58 192 DQ62

V

DD

V

SS

124

128

V

V

REFCA

V

DD

SS

193 DQ59 194 DQ63

195

197 SA0 198 NC

DQ33 132 DQ37 201 SA1 202 SCL

V

SS

134

V

SS

203

DQS4 136 DM4

DQS4 138

V

SS

V

SS

140 DQ38

V

V

SS

146 DQ44

DQ40 148 DQ45

DQ41 150

V

SS

V

SS

V

SS

V

SS

DQS

DQS6

V

SS

6

152 DQS5

156

162

168

170

172

174 DQ54

V

V

V

V

DM6

V

V

V

SS

180 DQ60

V

V

V

V

V

DDSPD

V

SS

SS

SS

TT

186 DQS7

190

196

V

V

200 SDA

204

V

SS

SS

SS

SS

SS

SS

SS

SS

SS

SS

TT

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

- 5 -

Rev. 1.31

Unbuffered SODIMM datasheet DDR3 SDRAM

5. Pin Description

Pin Name Description Number Pin Name Description Number

CK0, CK1 Clock Inputs, positive line 2 DQ0-DQ63 Data Input/Output 64

CK

0, CK1 Clock Inputs, negative line 2 DM0-DM7

Data Masks/ Data strobes,
Termination data strobes

CKE0, CKE1 Clock Enables 2 DQS0-DQS7 Data strobes 8

RAS

CAS

WE

S

0, S1 Chip Selects 2

A0-A9, A11,

A13-A15

A10/AP Address Input/Autoprecharge 1

A12/BC

BA0-BA2 SDRAM Bank Addresses 3

Row Address Strobe 1 DQS0-DQS7 Data strobes complement 8

Column Address Strobe 1 RESET Reset Pin 1

Write Enable 1 TEST

V

DD

Address Inputs 14

Address Input/Burst chop 1

V

V

REFDQ

V

REFCA

V

DDSPD

V

SS

TT

Logic Analyzer specific test pin (No connect
on SODIMM)

Core and I/O Power 18

Ground 52

Input/Output Reference 2

SPD and Temp sensor Power 1

Termination Voltage 2

ODT0, ODT1 On-die termination control 2 NC Reserved for future use 3

SCL Serial Presence Detect (SPD) Clock Input 1 Total 204

SDA SPD Data Input/Output 1

SA0-SA1 SPD Address 2

NOTE:

*The V

DD

and V

pins are tied common to a single power-plane on these designs.

DDQ

8

1

- 6 -

Rev. 1.31

Unbuffered SODIMM datasheet DDR3 SDRAM

6. Input/Output Functional Description

Symbol Typ e Function

CK0-CK1

-CK1

CK0

CKE0-CKE1 Input

S

0-S1 Input

AS, CAS, WE Input

R

BA0-BA2 Input Selects which DDR3 SDRAM internal bank of eight is activated.

ODT0-ODT1 Input Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.

A0-A9,

A10/AP,

A11

A12/BC

A13-A15

DQ0-DQ63 I/O Data Input/Output pins.

DM0-DM7 Input

DQS0-DQS7
DQS

0-DQS7

V

DD,VDDSPD,

V

SS

V

REFDQ,

V

REFCA

SDA I/O

SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.

SA0-SA1 Input Address pins used to select the Serial Presence Detect and Temp sensor base address.

TEST I/O The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules

RESET

Input

Input

I/O

Supply Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.

Supply Reference voltage for SSTL15 inputs.

Input RESET In Active Low This signal resets the DDR3 SDRAM

The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and
falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera­tions is synchronized to the input clock.

Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,
CKE low initiates the Power Down mode or the Self Refresh mode.

Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is
selected by S

When sampled at the cross point of the rising edge of CK and falling edge of CK
the operation to be executed by the SDRAM.

During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of
CK and falling edge of CK
cross point of the rising edge of CK and falling edge of CK
autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0­BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre­charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre­charge.A12(BC
performed (HIGH, no burst chop; LOW, burst chopped)

The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input
data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.

The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3
SDRAMs and is sent at the leading edge of the data window. DQS
the crosspoint of respective DQS and DQS

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be
connected from the SDA bus line to V

0; Rank 1 is selected by S1.

, signals CAS, RAS, and WE define

. During a Read or Write command cycle, defines the column address when sampled at the

. In addition to the column address, AP is used to invoke

) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be

.

on the system planar to act as a pull up.

DDSPD

signals are complements, and timing is relative to

- 7 -

Rev. 1.31

Unbuffered SODIMM datasheet DDR3 SDRAM

7. Function Block Diagram:

7.1 1GB, 128Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

S0

RAS

CASWECK0

CK0

CKE0

ODT0

A[0:N]

DQS0
DQS0

DM0

DQ[0:7]

DQS2
DQS

DM2

DQ[16:23]

/BA[0:N]

240Ω

DQS
DQS
DM
DQ[0:7]

DQS

2

DQS
DM
DQ[0:7]

CS

CS

RAS

RAS

± 1%

ZQ

D0

CASWECKCKCKE

240

Ω

± 1%

ZQ

D1

CASWECKCKCKE

ODT

ODT

A[0:N]/BA[0:N]

A[0:N]/BA[0:N]

DQS1
DQS1

DM1

DQ[8:15]

DQS3
DQS

DM3

DQ[24:31]

3

DQS
DQS
DM
DQ[0:7]

CS

RAS

DQS
DQS
DM
DQ[0:7]

CS

RAS

240Ω

± 1%

ZQ

D4

CASWECKCKCKE

240

Ω

± 1%

ZQ

D5

CASWECKCKCKE

ODT

ODT

A[0:N]/BA[0:N]

V

DDSPD

V

REFCA

V

REFDQ

A[0:N]/BA[0:N]

ODT1

CKE1

RESET

SCL
SA0
SA1

V

V

CK0

CK0

CK1

CK1

SCL
A0

(SPD)

A1
A2

WP

V

tt

DD

SS

S1

SDA

V

tt

SPD

D0 - D7

D0 - D7

D0 - D7

D0 - D7, SPD

D0 - D7

D0 - D7

Terminated near
card edge

NC

NC

NC

D0 - D7

DQS4
DQS4

DM4

DQ[32:39]

DQS6
DQS6

DM6

DQ[48:55]

DQS
DQS
DM
DQ[0:7]

CS

RAS

DQS
DQS
DM
DQ[0:7]

CS

RAS

240Ω

± 1%

ZQ

D2

CASWECKCKCKE

Ω

240

± 1%

ZQ

D3

CASWECKCKCKE

ODT

ODT

DQS5
DQS5

DM5

DQ[40:47]

A[0:N]/BA[0:N]

DQS7
DQS7

DM7

DQ[56:63]

A[0:N]/BA[0:N]

DQS
DQS
DM
DQ[0:7]

CS

RAS

DQS
DQS
DM
DQ[0:7]

CS

RAS

240Ω

± 1%

ZQ

D6

CASWECKCKCKE

Ω

240

± 1%

ZQ

D7

CASWECKCKCKE

ODT

ODT

V

tt

D7D6D5D4

A[0:N]/BA[0:N]

A[0:N]/BA[0:N]

NOTE :

1. DQ wiring may differ from that shown how­ever ,DQ, DM, DQS and DQS

V4V3V2V1

V4V3V2V1

D3D2D1D0

tt

V

Address and Controllines

relationships

are maintained as shown

Vtt

V

DD

Vtt

Rank0

- 8 -

Rev. 1.31

Unbuffered SODIMM datasheet DDR3 SDRAM

7.2 2GB, 256Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

DQS3
DQS3

DM3

DQ[24:31]

DQS1
DQS

DM1

DQ[8:15]

DQS0
DQS0

DM0

DQ[0:7]

D12

CS

RAS

CASWECKCKCKE

D6

CS

RAS

CASWECKCKCKE

D7

V

DD

240Ω

± 1%

ZQ

240Ω

± 1%

ZQ

240Ω

± 1%

ZQ

ODT

ODT

Vtt

DQS4
DQS4
DM4
DQ[32:39]

A[N:0]/BA[N:0]

DQS6

6

DQS
DM6
DQ[48:55]

A[N:0]/BA[N:0]

DQS7
DQS7
DM7
DQ[56:63]

V

DD

Vtt

Rank0

Rank1

Vtt

240Ω

DQS
DQS
DM
DQ[0:7]

CS

RAS

DQS
DQS
DM
DQ[0:7]

CS

RAS

DQS
DQS
DM
DQ[0:7]

± 1%

ZQ

D4

CASWECKCKCKE

240Ω

± 1%

ZQ

D14

CASWECKCKCKE

240Ω

± 1%

ZQ

D15

ODT

ODT

DQS
DQS
DM
DQ[0:7]

A[N:0]/BA[N:0]

DQS
DQS
DM
DQ[0:7]

A[N:0]/BA[N:0]

DQS
DQS
DM
DQ[0:7]

S1

RAS

CASWECK1

CK1

CKE1

ODT1

A[0:N]

/BA[0:N]

S0

CK0

CK0

CKE0

ODT0

240Ω

DQS
DQS
DM
DQ[0:7]

DQS

1

DQS
DM
DQ[0:7]

DQS
DQS
DM
DQ[0:7]

CS

RAS

CASWECKCKCKE

CS

RAS

CASWECKCKCKE

D11

D1

D0

± 1%

ZQ

240Ω

± 1%

ZQ

240Ω

± 1%

ZQ

ODT

ODT

A[N:0]/BA[N:0]

A[N:0]/BA[N:0]

DQS
DQS
DM
DQ[0:7]

CS

RAS

DQS
DQS
DM
DQ[0:7]

CS

RAS

DQS
DQS
DM
DQ[0:7]

240Ω

± 1%

ZQ

D3

CASWECKCKCKE

240Ω

± 1%

ZQ

D9

CASWECKCKCKE

240Ω

± 1%

ZQ

D8

ODT

ODT

A[N:0]/BA[N:0]

A[N:0]/BA[N:0]

CS

RAS

CASWECKCKCKE

DQS2
DQS2

DM2

DQ[16:23]

SCL
SA0
SA1

NOTE :

1. DQ wiring may differ from that shown how­ever ,DQ, DM, DQS and DQS

SCL
A0
A1
A2

DQS
DQS
DM
DQ[0:7]

CS

RAS

CASWECKCKCKE

(SPD)

WP

D2

240Ω

± 1%

ZQ

ODT

A[N:0]/BA[N:0]

ODT

A[N:0]/BA[N:0]

SDA

relationships

are maintained as shown

CS

RAS

DQS
DQS
DM
DQ[0:7]

CS

RAS

CASWECKCKCKE

240Ω

± 1%

ZQ

D10

CASWECKCKCKE

V

tt

V

DDSPD

V

REFCA

V

REFDQ

V

DD

V

SS

CK0

CK1

CK0

CK1

RESET

ODT

ODT

A[N:0]/BA[N:0]

A[N:0]/BA[N:0]

CS

RAS

DQS
DQS
DM
DQ[0:7]

CS

RAS

V

tt

SPD

D0 - D15

D0 - D15

D0 - D15

D0 - D15, SPD

D0 - D7

D8 - D15

D0 - D7

D8 - D15

D0 - D7

CASWECKCKCKE

240Ω

± 1%

ZQ

D13

CASWECKCKCKE

ODT

ODT

A[N:0]/BA[N:0]

CS

RAS

CASWECKCKCKE

DQS
DQS
DM
DQ[0:7]

A[N:0]/BA[N:0]

CS

RAS

CASWECKCKCKE

V2

V3

V4

V4

V3

V2

ODT

A[N:0]/BA[N:0]

240Ω

± 1%

ZQ

D5

ODT

A[N:0]/BA[N:0]

V1

V9

V5

V1

V5

V

tt

V1

V9

Address and Controllines

V8

V6

V6

V8

DQS5
DQS5
DM5
DQ[40:47]

D6D12D3D9

V7

D7D5D10D8

D15D13D2D0

V7

D14D4D11D1

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Rev. 1.31

Unbuffered SODIMM datasheet DDR3 SDRAM

8. Absolute Maximum Ratings

8.1 Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

V

DD

V

Voltage on V

DDQ

V

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and V

equal to or less than 300mV.

Voltage on any pin relative to V

IN, VOUT

T

Storage Temperature -55 to +100 °C 1, 2

STG

DDQ

Voltage on VDD pin relative to V

pin relative to V

DDQ

must be within 300mV of each other at all times; and V

SS

SS

SS

must be not greater than 0.6 x V

REF

8.2 DRAM Component Operating Temperature Range

Symbol Parameter rating Unit NOTE

T

OPER

NOTE :

1. Operating Temperature T
JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main­tained between 0-85°C under all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

OPER

Operating Temperature Range 0 to 95 °C 1, 2, 3

-0.4 V ~ 1.975 V V 1,3

-0.4 V ~ 1.975 V V 1,3

-0.4 V ~ 1.975 V V 1

, When VDD and V

DDQ

are less than 500mV; V

DDQ

REF

may be

9. AC & DC Operating Conditions

9.1 Recommended DC Operating Conditions (SSTL-15)

Symbol Parameter

V

DD

V

DDQ

NOTE:

1. Under all conditions V

2. V

tracks with VDD. AC parameters are measured with VDD and V

DDQ

Supply Voltage 1.425 1.5 1.575 V 1,2

Supply Voltage for Output 1.425 1.5 1.575 V 1,2

must be less than or equal to VDD.

DDQ

tied together.

DDQ

Min. Typ . Max.

Rating

Units NOTE

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