Samsung M471B5273DH0-CH9 User Manual

Rev. 1.4. Aug. 2011

M471B5773DH0
M471B5273DH0

204pin Unbuffered SODIMM

based on 2Gb D-die

78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other­wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

ⓒ 2011 Samsung Electronics Co., Ltd. All rights reserved.

- 1 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First Release Aug. 2010 - S.H.Kim

1.01 - Changed note comment on page. 27, 35 Aug. 2010 - S.H.Kim

1.1 - Corrected IDD current spec.(IDD7) Sep. 2010 - S.H.Kim

1.2 - Changed Input/Output capacitance on page 21. Sep. 2010 - S.H.Kim

1.3 - Changed 1866 speed bin table on page 26. Nov. 2010 - S.H.Kim

1.31 - Corrected typo. Dec. 2010 - S.H.Kim

1.32 - Corrected typo. May. 2011 - J.Y.Lee

1.33 - Corrected typo. Jul. 2011 - J.Y.Lee

1.4 - Changed timing parameters (Setup/Hold time) Aug. 2011 - J.Y.Lee

- 2 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

Table Of Contents

204pin Unbuffered SODIMM based on 2Gb D-die

1. DDR3 Unbuffered SODIMM Ordering Information........................................................................................................4

2. Key Features................................................................................................................................................................. 4

3. Address Configuration ..................................................................................................................................................4

4. x64 DIMM Pin Configurations (Front side/Back Side)...................................................................................................5

5. Pin Description ............................................................................................................................................................. 6

6. Input/Output Functional Description..............................................................................................................................7

7. Function Block Diagram:...............................................................................................................................................8

7.1 2GB, 256Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................................... 8

7.2 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................... 9

8. Absolute Maximum Ratings .......................................................................................................................................... 10

8.1 Absolute Maximum DC Ratings............................................................................................................................... 10

8.2 DRAM Component Operating Temperature Range ................................................................................................10

9. AC & DC Operating Conditions.....................................................................................................................................10

9.1 Recommended DC Operating Conditions (SSTL-15).............................................................................................. 10

10. AC & DC Input Measurement Levels ..........................................................................................................................11

10.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 11

10.2 V

10.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 13

10.3.1. Differential Signals Definition .........................................................................................................................13

10.3.2. Differential Swing Requirement for Clock (CK-CK

10.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 14

10.3.4. Differential Input Cross Point Voltage ............................................................................................................ 15

10.4 Slew Rate Definition for Single Ended Input Signals .............................................................................................15

10.5 Slew rate definition for Differential Input Signals ...................................................................................................15

11. AC & DC Output Measurement Levels .......................................................................................................................16

11.1 Single Ended AC and DC Output Levels............................................................................................................... 16

11.2 Differential AC and DC Output Levels ................................................................................................................... 16

11.3 Single-ended Output Slew Rate ............................................................................................................................ 16

11.4 Differential Output Slew Rate ................................................................................................................................ 17

12. DIMM IDD specification definition ...............................................................................................................................18

13. IDD SPEC Table .........................................................................................................................................................20

14. Input/Output Capacitance ...........................................................................................................................................21

15. Electrical Characteristics and AC timing .....................................................................................................................22

15.1 Refresh Parameters by Device Density................................................................................................................. 22

15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 22

15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 22

15.3.1. Speed Bin Table Notes .................................................................................................................................. 27

16. Timing Parameters by Speed Grade ..........................................................................................................................28

16.1 Jitter Notes ............................................................................................................................................................ 34

16.2 Timing Parameter Notes........................................................................................................................................ 35

17. Physical Dimensions :.................................................................................................................................................36

17.1 256Mbx8 based 256Mx64 Module (1 Rank) - M471B5773DH0 ............................................................................ 36

17.2 256Mbx8 based 512Mx64 Module (2 Ranks) - M471B5273DH0 .......................................................................... 37

Tolerances.................................................................................................................................................... 12

REF

) and Strobe (DQS-DQS) ................................................ 13

- 3 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

1. DDR3 Unbuffered SODIMM Ordering Information

Part Number

M471B5773DH0-CF8/H9/K0/MA 2GB 256Mx64 256Mx8(K4B2G0846D-HC##)*8 1 30mm

M471B5273DH0-CF8/H9/K0/MA 4GB 512Mx64 256Mx8(K4B2G0846D-HC##)*16 2 30mm

NOTE :

1. "##" - F8/H9/K0/MA

2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11 / MA - 1866Mbps 13-13-13

- DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)

2

Density Organization Component Composition

Number of

Rank

Height

2. Key Features

Speed

tCK(min) 2.5 1.875 1.5 1.25 1.07 ns

CAS Latency 6 791113 tCK

tRCD(min) 15 13.125 13.5 13.75 13.91 ns

tRP(min) 15 13.125 13.5 13.75 13.91 ns

tRAS(min) 37.5 37.5 36 35 34 ns

tRC(min) 52.5 50.625 49.5 48.75 47.91 ns

• JEDEC standard 1.5V ± 0.075V Power Supply

•V

= 1.5V ± 0.075V

DDQ

• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin,
933MHz fCK for 1866Mb/sec/pin

• 8 independent internal bank

• Programmable CAS Latency: 5,6,7,8,9,10,11,13

• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9 (DDR3-1866)

• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

• Asynchronous Reset

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

6-6-6 7-7-7 9-9-9 11-11 -11 13-13-13

85°C, 3.9us at 85°C < T

CASE

CASE

≤ 95°C

Unit

3. Address Configuration

Organization Row Address Column Address Bank Address Auto Precharge

256Mx8(2Gb) based Module A0-A14 A0-A9 BA0-BA2 A10/AP

- 4 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

4. x64 DIMM Pin Configurations (Front side/Back Side)

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1

3

V

REFDQ

V

2

SS

4 DQ4 KEY 141 DQ34 142 DQ39

5 DQ0 6 DQ5 73 CKE0 74 CKE1

7DQ18

9

V

SS

10 DQS077 NC 78

11 DM0 12DQS079 BA2 80

13

V

SS

14

15 DQ2 16 DQ6 83 A12/BC

V

SS

71

V

SS

72

V

SS

139

143 DQ35 144

V

SS

V

SS

75

81

V

DD

V

DD

76

82

V

A15

A14

V

DD

DD

145

3

3

147

149

151

84 A11 153 DM5 154 DQS5

17 DQ3 18 DQ7 85 A9 86 A7 155

19

V

SS

20

V

SS

87

V

DD

88

V

DD

157 DQ42 158 DQ46

21 DQ8 22 DQ12 89 A8 90 A6 159 DQ43 160 DQ47

23 DQ9 24 DQ13 91 A5 92 A4 161

25

27 DQS

V

SS

26

1 28 DM1 95 A3 96 A2 165 DQ49 166 DQ53

29 DQS1 30 RESET

31

V

SS

32

V

SS

93

V

DD

94

V

DD

163 DQ48 164 DQ52

97 A1 98 A0 167

V

SS

99

V

DD

100

V

DD

169

33 DQ10 34 DQ14 101 CK0 102 CK1 171

35 DQ11 36 DQ15 103 CK0104CK1 173

37

V

SS

38

39 DQ16 40 DQ20

41 DQ17 42 DQ21

43

45 DQS

V

SS

44

246 DM2

47 DQS2 48

49

V

SS

50 DQ22 117

50 DQ18 52 DQ23

53 DQ19 54

55

V

SS

56 DQ28

57 DQ24 58 DQ29

59 DQ25 60

61

V

SS

62 DQS3 129 DQ32 130 DQ36 199

63 DM3 64 DQS3

65

V

SS

66

67 DQ26 68 DQ30

69 DQ27 70 DQ31

NOTE :

1. NC = No Connect, NU = Not Usable, RFU = Reserved Future Use

2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.

3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.

V

SS

105

107

109

V

SS

111

113

V

SS

115

119

V

SS

121

123

125 TEST 126

V

SS

127

131

V

SS

133

135

137

V

DD

106

V

DD

175 DQ50 176 DQ55

A10/AP 108 BA1 177 DQ51 178

BA0 110 RAS 179

V

DD

112

V

DD

181 DQ56 182 DQ61

WE 114 S0 183 DQ57 184

CAS 116 ODT0 185

V

A13

DD

118

3

120ODT1189

V

DD

187 DM7 188 DQS7

S1 122 NC 191 DQ58 192 DQ62

V

DD

V

SS

124

128

V

V

REFCA

V

DD

SS

193 DQ59 194 DQ63

195

197 SA0 198 NC

DQ33 132 DQ37 201 SA1 202 SCL

V

SS

134

V

SS

203

DQS4136 DM4

DQS4 138

V

SS

V

SS

140 DQ38

V

V

SS

146 DQ44

DQ40 148 DQ45

DQ41 150

V

SS

V

SS

V

SS

V

SS

DQS

DQS6

V

SS

6

152 DQS5

156

162

168

170

172

174 DQ54

V

V

V

V

DM6

V

V

V

SS

180 DQ60

V

V

V

V

V

DDSPD

V

SS

SS

SS

TT

186 DQS7

190

196

V

V

200 SDA

204

V

SS

SS

SS

SS

SS

SS

SS

SS

SS

SS

TT

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

- 5 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

5. Pin Description

Pin Name Description Number Pin Name Description Number

CK0, CK1 Clock Inputs, positive line 2 DQ0-DQ63 Data Input/Output 64

CK

0, CK1 Clock Inputs, negative line 2 DM0-DM7

Data Masks/ Data strobes,
Termination data strobes

CKE0, CKE1 Clock Enables 2 DQS0-DQS7 Data strobes 8

RAS

CAS

WE

S

0, S1 Chip Selects 2

A0-A9, A11,

A13-A15

A10/AP Address Input/Autoprecharge 1

A12/BC

BA0-BA2 SDRAM Bank Addresses 3

Row Address Strobe 1 DQS0-DQS7 Data strobes complement 8

Column Address Strobe 1 RESET Reset Pin 1

Write Enable 1 TEST

V

DD

Address Inputs 14

Address Input/Burst chop 1

V

V

REFDQ

V

REFCA

V

DDSPD

V

SS

TT

Logic Analyzer specific test pin (No connect
on SODIMM)

Core and I/O Power 18

Ground 52

Input/Output Reference 2

SPD and Temp sensor Power 1

Termination Voltage 2

ODT0, ODT1 On-die termination control 2 NC Reserved for future use 3

SCL Serial Presence Detect (SPD) Clock Input 1 Total 204

SDA SPD Data Input/Output 1

SA0-SA1 SPD Address 2

NOTE:

*The V

DD

and V

pins are tied common to a single power-plane on these designs.

DDQ

8

1

- 6 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

6. Input/Output Functional Description

Symbol Ty pe Function

CK0-CK1

-CK1

CK0

CKE0-CKE1 Input

S

0-S1 Input

AS, CAS, WE Input

R

BA0-BA2 Input Selects which DDR3 SDRAM internal bank of eight is activated.

ODT0-ODT1 Input Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.

A0-A9,

A10/AP,

A11

A12/BC

A13-A15

DQ0-DQ63 I/O Data Input/Output pins.

DM0-DM7 Input

DQS0-DQS7
DQS

0-DQS7

V

DD,VDDSPD,

V

SS

V

REFDQ,

V

REFCA

SDA I/O

SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.

SA0-SA1 Input Address pins used to select the Serial Presence Detect and Temp sensor base address.

TEST I/O The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules

RESET

Input

Input

I/O

Supply Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.

Supply Reference voltage for SSTL15 inputs.

Input RESET In Active Low This signal resets the DDR3 SDRAM

The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and
falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera­tions is synchronized to the input clock.

Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,
CKE low initiates the Power Down mode or the Self Refresh mode.

Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is
selected by S

When sampled at the cross point of the rising edge of CK and falling edge of CK
the operation to be executed by the SDRAM.

During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of
CK and falling edge of CK
cross point of the rising edge of CK and falling edge of CK
autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0­BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre­charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre­charge.A12(BC
performed (HIGH, no burst chop; LOW, burst chopped)

The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input
data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.

The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3
SDRAMs and is sent at the leading edge of the data window. DQS
the crosspoint of respective DQS and DQS

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be
connected from the SDA bus line to V

0; Rank 1 is selected by S1.

, signals CAS, RAS, and WE define

. During a Read or Write command cycle, defines the column address when sampled at the

. In addition to the column address, AP is used to invoke

) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be

.

on the system planar to act as a pull up.

DDSPD

signals are complements, and timing is relative to

- 7 -

Rev. 1.4

NOTE :

1. DQ wiring may differ from that shown how­ever ,DQ, DM, DQS and DQS

relationships

are maintained as shown

V

SS

V

DD

D0 - D7

V

REFCA

V

DDSPD

SPD

CK0

V

REFDQ

D0 - D7

D0 - D7

D0 - D7, SPD

V

tt

CK0

CK1

CK1

S1

V

tt

D0 - D7

D0 - D7

NC

V

tt

V4V3V2V1

D7D6D5D4

V

tt

V4V3V2V1

D3D2D1D0

Address and Controllines

A0
A1
A2

SA0
SA1

SCL

SDA

WP

SCL

(SPD)

S0

RAS

CASWECK0

CK0

CKE0

ODT0

A[0:N]

/BA[0:N]

DQS0
DQS0

DM0

DQS
DQS

D0

CS

RAS

CASWECKCKCKE

ODT

A[0:N]/BA[0:N]

ZQ

DQ[0:7]

DM

240Ω

± 1%

DQ[0:7]

CS

RAS

CASWECKCKCKE

ODT

A[0:N]/BA[0:N]

DQS1
DQS1

DM1

DQS
DQS

D4

ZQ

DQ[0:7]

DM

240Ω

± 1%

DQ[8:15]

DQS2
DQS

2

DM2

DQS
DQS

D1

CS

RAS

CASWECKCKCKE

ODT

A[0:N]/BA[0:N]

ZQ

DQ[0:7]

DM

240

Ω

± 1%

DQ[16:23]

CS

RAS

CASWECKCKCKE

ODT

A[0:N]/BA[0:N]

DQS3
DQS

3

DM3

DQS
DQS

D5

ZQ

DQ[0:7]

DM

240

Ω

± 1%

DQ[24:31]

DQS4
DQS4

DM4

DQS
DQS

D2

CS

RAS

CASWECKCKCKE

ODT

A[0:N]/BA[0:N]

ZQ

DQ[0:7]

DM

240Ω

± 1%

DQ[32:39]

CS

RAS

CASWECKCKCKE

ODT

A[0:N]/BA[0:N]

DQS5
DQS5

DM5

DQS
DQS

D6

ZQ

DQ[0:7]

DM

240Ω

± 1%

DQ[40:47]

DQS6
DQS6

DM6

DQS
DQS

D3

CS

RAS

CASWECKCKCKE

ODT

A[0:N]/BA[0:N]

ZQ

DQ[0:7]

DM

240

Ω

± 1%

DQ[48:55]

CS

RAS

CASWECKCKCKE

ODT

A[0:N]/BA[0:N]

DQS7
DQS7

DM7

DQS
DQS

D7

ZQ

DQ[0:7]

DM

240

Ω

± 1%

DQ[56:63]

Vtt

V

DD

Vtt

ODT1

NC

CKE1

NC

RESET

D0 - D7

Terminated near
card edge

Rank0

Unbuffered SODIMM datasheet DDR3 SDRAM

7. Function Block Diagram:

7.1 2GB, 256Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

- 8 -

Rev. 1.4

S1

RAS

CASWECK1

CK1

CKE1

ODT1

A[0:N]

/BA[0:N]

S0

CK0

CK0

CKE0

ODT0

DQS3
DQS3

DM3

DQS
DQS

D11

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

DQ[0:7]

DM

240Ω

± 1%

DQ[24:31]

D3

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

240Ω

± 1%

Vtt

V

DD

Vtt

Rank0

Rank1

V

SS

V

DD

D0 - D15

V

REFCA

V

DDSPD

SPD

CK0

V

REFDQ

D0 - D15

D0 - D15

D0 - D15, SPD

V

tt

CK1

CK0

CK1

RESET

V

tt

D8 - D15

D0 - D7

D0 - D7

D8 - D15

D0 - D7

DQS
DQS

DQ[0:7]

DM

DQS1
DQS1

DM1

DQS
DQS

D1

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

DQ[0:7]

DM

240

Ω

± 1%

DQ[8:15]

D9

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

240Ω

± 1%

DQS
DQS

DQ[0:7]

DM

DQS0
DQS0

DM0

DQS
DQS

D0

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

DQ[0:7]

DM

240Ω

± 1%

DQ[0:7]

D8

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

240Ω

± 1%

DQS
DQS

DQ[0:7]

DM

DQS2
DQS2

DM2

DQS
DQS

D2

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

DQ[0:7]

DM

240Ω

± 1%

DQ[16:23]

D10

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

240Ω

± 1%

DQS
DQS

DQ[0:7]

DM

DQS
DQS

D4

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

DQ[0:7]

DM

240Ω

± 1%

D12

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

240Ω

± 1%

DQS
DQS

DQ[0:7]

DM

DQS
DQS

D14

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

DQ[0:7]

DM

240

Ω

± 1%

D6

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

240Ω

± 1%

DQS
DQS

DQ[0:7]

DM

DQS
DQS

D15

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

DQ[0:7]

DM

240Ω

± 1%

D7

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

240Ω

± 1%

DQS
DQS

DQ[0:7]

DM

DQS
DQS

D13

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

DQ[0:7]

DM

240Ω

± 1%

D5

CS

RAS

CASWECKCKCKE

ODT

A[N:0]/BA[N:0]

ZQ

240Ω

± 1%

DQS
DQS

DQ[0:7]

DM

DQS4
DQS4
DM4
DQ[32:39]

DQS6
DQS6
DM6
DQ[48:55]

DQS7
DQS7
DM7
DQ[56:63]

DQS5
DQS5
DM5
DQ[40:47]

V

DD

Vtt

A0
A1
A2

SA0
SA1

SCL

SDA

WP

SCL

(SPD)

V7

V8

V5

V6

V2

V3

D6D12D3D9

V

tt

Address and Controllines

D7D5D10D8

V1

V4

V9

V7

V6

V9

V8

V4

V3

D15D13D2D0

D14D4D11D1

V1

V2

V5

V1

NOTE :

1. DQ wiring may differ from that shown however ,DQ, DM, DQS and DQS

relationships are maintained as shown

Unbuffered SODIMM datasheet DDR3 SDRAM

7.2 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

- 9 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

8. Absolute Maximum Ratings

8.1 Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

V

DD

V

Voltage on V

DDQ

V

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and V

equal to or less than 300mV.

Voltage on any pin relative to V

IN, VOUT

T

Storage Temperature -55 to +100 °C 1, 2

STG

DDQ

Voltage on VDD pin relative to V

pin relative to V

DDQ

must be within 300mV of each other at all times;and V

SS

SS

SS

must be not greater than 0.6 x V

REF

8.2 DRAM Component Operating Temperature Range

Symbol Parameter rating Unit NOTE

T

OPER

NOTE :

1. Operating Temperature T
JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main­tained between 0-85°C under all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

OPER

Operating Temperature Range 0 to 95 °C 1, 2, 3

-0.4 V ~ 1.975 V V 1,3

-0.4 V ~ 1.975 V V 1,3

-0.4 V ~ 1.975 V V 1

, When VDD and V

DDQ

are less than 500mV; V

DDQ

REF

may be

9. AC & DC Operating Conditions

9.1 Recommended DC Operating Conditions (SSTL-15)

Symbol Parameter

V

DD

V

DDQ

NOTE:

1. Under all conditions V

2. V

tracks with VDD. AC parameters are measured with VDD and V

DDQ

Supply Voltage 1.425 1.5 1.575 V 1,2

Supply Voltage for Output 1.425 1.5 1.575 V 1,2

must be less than or equal to VDD.

DDQ

tied together.

DDQ

Min. Typ . Max.

Rating

Units NOTE

- 10 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

10. AC & DC Input Measurement Levels

10.1 AC & DC Logic Input Levels for Single-ended Signals

[ Table 1 ] Single-ended AC & DC input levels for Command and Address

Symbol Parameter

V

(DC100)

IH.CA

(DC100)

V

IL.CA

V

(AC175)

IH.CA

(AC175)

V

IL.CA

(AC150)

V

IH.CA

V

(AC150)

IL.CA

V

(AC135)

IH.CA

(AC135)

V

IL.CA

(AC125)

V

IH.CA

(AC125)

V

IL.CA

V

REFCA

NOTE :

1. For input only pins except RESET

2. See ’Overshoot/Undershoot Specification’ on page 18.

3. The AC peak noise on V

4. For reference : approx. V

5. V

(dc) is used as a simplified symbol for V

IH

6. V

(dc) is used as a simplified symbol for V

IL

7. V

(ac) is used as a simplified symbol for V

IH

(AC150) value is used when VREF + 150mV is referenced, V

, V

IH.CA

VREF + 125mV is referenced.

(ac) is used as a simplified symbol for V

8. V

IL

enced, V
when V

REF

DC input logic high

DC input logic low

AC input logic high

AC input logic low Note 2

AC input logic high

AC input logic low Note 2

AC input logic high - -

AC input logic low - - Note 2

AC input logic high - -

AC input logic low - - Note 2

Reference Voltage for ADD,

(DC)

CMD inputs

, V

may not allow V

REF

/2 ± 15mV

DD

(AC150) value is used when V

IL.CA

- 125mV is referenced.

REF

= V

(DC)

REFCA

to deviate from V

REF

(DC100)

IH.CA

(DC100)

IL.CA

(AC175), V

IH.CA

(AC175) and V

IL.CA

- 150mV is referenced, V

REF

DDR3-800/1066/1333/1600 DDR3-1866

Min. Max. Min. Max.

V

+ 100 V

REF

V

SS

V

+ 175

REF

V

+150

REF

0.49*V

DD

(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

REF

(AC150), V

IH.CA

IL.CA

IH.CA

(AC135) value is used when VREF + 135mV is referenced and V

IH.CA

(AC150), V

DD

V

- 100 V

REF

Note 2 - - mV 1,2,7

V

- 175

REF

Note 2 - -

V

-150

REF

0.51*V

DD

(AC135) and V

(AC135) and V

IL.CA

(AC135) value is used when V

IL.CA

IH.CA

(AC125); V

(AC125); V

IL.CA

V

+ 100 V

REF

SS

--mV1,2,8

--

V

+ 135

REF

V

+125

REF

0.49*V

DD

(AC175) value is used when V

IH.CA

(AC175) value is used when V

IL.CA

- 135mV is referenced and V

REF

Unit NOTE

DD

V

- 100

REF

mV 1,5

mV 1,6

mV 1,2,7

mV 1,2,8

Note 2 mV 1,2,7

V

- 135

REF

Note 2

V

-125

REF

0.51*V

DD

REF

(AC125) value is used when

IH.CA

IL.CA

mV 1,2,8

mV 1,2,7

mV 1,2,8

V 3,4

+ 175mV is referenced

- 175mV is refer-

REF

(AC125) value is used

[ Table 2 ]

Single-ended AC & DC input levels for DQ and DM

Symbol Parameter

V

(DC100)

IH.DQ

V

(DC100)

IL.DQ

(AC175)

V

IH.DQ

(AC175)

V

IL.DQ

(AC150)

V

IH.DQ

(AC150)

V

IL.DQ

V

(AC135)

IH.DQ

(AC135)

V

IL.DQ

V

REF

DQ

NOTE :

1. For input only pins except RESET

2. See ’Overshoot/Undershoot Specification’ on page 18.

3. The AC peak noise on V

4. For reference : approx. V

(dc) is used as a simplified symbol for V

5. V

IH

6. V

(dc) is used as a simplified symbol for V

IL

(ac) is used as a simplified symbol for V

7. V

IH

V

(AC150) value is used when V

IH.DQ

(ac) is used as a simplified symbol for V

8. V

IL

V

- 150mV is referenced.

REF

DC input logic high

DC input logic low

AC input logic high

AC input logic low NOTE 2

AC input logic high

AC input logic low NOTE 2

AC input logic high - - - -

AC input logic low - - - - NOTE 2

Reference Voltage for DQ,

(DC)

DM inputs

, V

may not allow V

REF

/2 ± 15mV

DD

REF

= V

REF

(DC)

REFDQ

to deviate from V

REF

(DC100)

IH.DQ

(DC100)

IL.DQ

IH.DQ

+ 150mV is referenced.

(AC175), V

IL.DQ

DDR3-800/1066 DDR3-1333/1600 DDR3-1866

Min. Max. Min. Max. Min. Max.

V

+ 100 V

REF

V

SS

V

+ 175

REF

V

+ 150

REF

0.49*V

(AC175), V

IL.DQ

DD

V

- 100 V

REF

NOTE 2----mV1,2,7

V

- 175

REF

NOTE 2

V

- 150

REF

0.51*V

DD

(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

REF

(AC150) and V

IH.DQ

(AC150) ; V

IL.DQ

V

+ 100 V

REF

SS

V

----mV1,2,8

V

+ 150

REF

DD

V

0.51*V

IH.DQ

NOTE 2

0.49*V

DD

(AC135) ; V

IH.DQ

(AC175) value is used when V

V

DD

- 100 V

REF

+ 100 V

REF

SS

NOTE 2 - - mV 1,2,7

- 150

REF

DD

(AC175) value is used when V

- 175mV is referenced, V

REF

- - mV 1,2,8

V

+ 135

REF

0.49*V

DD

Unit NOTE

mV 1,5

mV 1,6

V

REF

DD

- 100

NOTE 2 mV 1,2,7

V

- 135

REF

0.51*V

+ 175mV is referenced,

REF

(AC150) value is used when

IL.DQ

DD

mV 1,2,8

V 3,4

- 11 -

Rev. 1.4

voltage

V

DD

V

SS

time

Unbuffered SODIMM datasheet DDR3 SDRAM

10.2 V

Tolerances.

REF

The dc-tolerance limits and ac-noise limits for the reference voltages V

V

(t) as a function of time. (V

REF

V

(DC) is the linear average of V

REF

thermore V

(t) may temporarily deviate from V

REF

stands for V

REF

REF

REFCA

and V

REFDQ

likewise).

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V

(DC) by no more than ± 1% VDD.

REF

REFCA

and V

are illustrate in Figure 1. It shows a valid reference voltage

REFDQ

REF

. Fur-

Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V

" shall be understood as V

"V

REF

This clarifies, that dc-variations of V

which setup and hold is measured. System timing and voltage budgets need to account for V

(DC), as defined in Figure 1.

REF

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

REF

(DC) deviations from the optimum position within the

REF

REF

.

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

Timing and voltage effects due to ac-noise on V

up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

REF

ac-noise.

REF

- 12 -

Rev. 1.4

0.0

tDVAC

V

IH

.DIFF.MIN

half cycle

Differential Input Voltage (i.e. DQS-DQS, CK-CK)

time

tDVAC

VIH.DIFF.AC.MIN

V

IL

.DIFF.MAX

V

IL

.DIFF.AC.MAX

Unbuffered SODIMM datasheet DDR3 SDRAM

10.3 AC and DC Logic Input Levels for Differential Signals

10.3.1 Differential Signals Definition

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

10.3.2 Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS)

Symbol Parameter

V

IHdiff

V

ILdiff

V

(AC)

IHdiff

V

(AC)

ILdiff

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK - CK

then the reduced level applies also here.

3. These values are not defined, however they single-ended signals CK, CK

nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"

use VIH/VIL(AC) of ADD/CMD and V

differential input high +0.2 NOTE 3 V 1

differential input low NOTE 3 -0.2 V 1

differential input high ac

2 x (VIH(AC) - V

differential input low ac NOTE 3

; for DQS - DQS use VIH/VIL(AC) of DQs and V

REFCA

[ Table 3 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS.

tDVAC [ps] @ |V

Slew Rate [V/ns]

> 4.0 75 - 175 - TBD - TBD -

4.0 57 - 170 - TBD - TBD -

= 350mV

min max min max min max min max

IH/Ldiff

(AC)|

tDVAC [ps] @ |V

3.0 50 - 167 - TBD - TBD -

2.0 38 - 163 - TBD - TBD -

1.8 34 - 162 - TBD - TBD -

1.6 29 - 161 - TBD - TBD -

1.4 22 - 159 - TBD - TBD -

1.2 13 - 155 - TBD - TBD -

1.0 0 - 150 - TBD - TBD -

< 1.0 0 - 150 - TBD - TBD -

DDR3-800/1066/1333/1600/1866

min max

)

REF

, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-

IH/Ldiff

(AC)|

tDVAC [ps] @ |V

= 300mV

NOTE 3 V 2

2 x (VIL(AC) - V

; if a reduced ac-high or ac-low level is used for a signal group,

REFDQ

REF

IH/Ldiff

)

(AC)|

= 270mV

unit NOTE

tDVAC [ps] @ |V

V2

(AC)|

IH/Ldiff

= 250mV

- 13 -

Rev. 1.4

VDD or V

DDQ

V

SEH

min

V

DD

/2 or V

DDQ

/2

V

SEL

max

V

SEH

VSS or V

SSQ

V

SEL

CK or DQS

time

Unbuffered SODIMM datasheet DDR3 SDRAM

10.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.

CK and CK

have to approximately reach V

half-cycle.

DQS, DQS

have to reach V

SEH

min / V

ing a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V

signals, then these ac-levels apply also for the single-ended signals CK and CK

min / V

SEH

max (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle proceeding and follow-

SEL

max (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every

SEL

150(AC)/VIL150(AC) is used for ADD/CMD

IH

.

Figure 3. Single-ended requirement for differential signals

Note that while ADD/CMD and DQ signal requirements are with respect to V

with respect to V

ended components of differential signals the requirement to reach V

/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

DD

SEL

, the single-ended components of differential signals have a requirement

REF

max, V

min has no bearing on timing, but adds a restriction on the common

SEH

mode characteristics of these signals.

[ Table 4 ] Single-ended levels for CK, DQS, CK, DQS

Symbol Parameter

V

SEH

V

SEL

NOTE :

1. For CK, CK

2. V

IH

reduced level applies also here

3. These values are not defined, however the single-ended signals CK, CK

nals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"

use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.

(AC)/VIL(AC) for DQs is based on V

Single-ended high-level for strobes

Single-ended high-level for CK, CK

Single-ended low-level for strobes NOTE3

Single-ended low-level for CK, CK

; VIH(AC)/VIL(AC) for ADD/CMD is based on V

REFDQ

(V

(VDD/2)+0.175

, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-

DDR3-800/1066/1333/1600/1866

Min Max

/2)+0.175

DD

NOTE3

; if a reduced ac-high or ac-low level is used for a signal group, then the

REFCA

Unit NOTE

NOTE3 V 1, 2

NOTE3 V 1, 2

/2)-0.175

(V

(V

DD

/2)-0.175

DD

V1, 2

V1, 2

- 14 -

Rev. 1.4

V

DD

CK, DQS

VDD/2

CK, DQS

V

SS

V

IX

V

IX

V

IX

V

IHdiffmin

0

V

ILdiffmax

delta TRdiff

delta TFdiff

Unbuffered SODIMM datasheet DDR3 SDRAM

10.3.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK

cross point of true and complement signal to the mid level between of V

[ Table 5 ] Cross point voltage for differential input signals (CK, DQS)

Symbol Parameter

V

IX

V

IX

NOTE :

1. Extended range for V

±250 mV, and the differential slew rate of CK-CK

2. The relation between V

(V

/2) + VIX(Min) - V

DD

- ((VDD/2) + VIX(Max)) ≥ 25mV

V

SEH

and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual

and VSS.

DD

Figure 4. VIX Definition

Differential Input Cross Point Voltage relative to VDD/2 for CK,CK

Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS

is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V

IX

Min/Max and V

IX

≥ 25mV

SEL

is larger than 3 V/ ns.

should satisfy following.

SEL/VSEH

DDR3-800/1066/1333/1600/1866

Min Max

-150 150 mV 2

-175 175 mV 1

-150 150 mV 2

SEL

/ V

Unit NOTE

of at least VDD/2

SEH

10.4 Slew Rate Definition for Single Ended Input Signals

See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.

10.5 Slew rate definition for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.

[ Table 6 ] Differential input slew rate definition

Description

Differential input slew rate for rising edge (CK-CK

Differential input slew rate for falling edge (CK-CK

NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds

and DQS-DQS)

and DQS-DQS)

Figure 5. Differential input slew rate definition for DQS, DQS and CK, CK

Measured

From To

V

ILdiffmax

V

IHdiffmin

V

V

- 15 -

IHdiffmin

ILdiffmax

V

IHdiffmin

V

IHdiffmin

Defined by

- V

ILdiffmax

Delta TRdiff

- V

ILdiffmax

Delta TFdiff

Rev. 1.4

V

OH(AC)

V

OL(AC)

delta TRsedelta TFse

VTT

Unbuffered SODIMM datasheet DDR3 SDRAM

11. AC & DC Output Measurement Levels

11.1 Single Ended AC and DC Output Levels

[ Table 7 ] Single Ended AC and DC output levels

Symbol Parameter DDR3-800/1066/1333/1600/1866 Units NOTE

(DC) DC output high measurement level (for IV curve linearity) 0.8 x V

V

OH

V

(DC) DC output mid measurement level (for IV curve linearity) 0.5 x V

OM

V

(DC) DC output low measurement level (for IV curve linearity) 0.2 x V

OL

V

(AC) AC output high measurement level (for output SR) VTT + 0.1 x V

OH

V

(AC) AC output low measurement level (for output SR) VTT - 0.1 x V

OL

NOTE : 1. The swing of +/-0.1 x V

load of 25Ω to V

TT=VDDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test

DDQ

/2.

DDQ

DDQ

DDQ

DDQ

DDQ

11.2 Differential AC and DC Output Levels

[ Table 8 ] Differential AC and DC output levels

Symbol Parameter DDR3-800/1066/1333/1600/1866 Units NOTE

(AC) AC differential output high measurement level (for output SR) +0.2 x V

V

OHdiff

V

(AC) AC differential output low measurement level (for output SR) -0.2 x V

OLdiff

NOTE : 1. The swing of +/-0.2xV

load of 25Ω to V

TT=VDDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test

DDQ

/2 at each of the differential outputs.

DDQ

DDQ

V

V

V

V1

V1

V1

V1

11.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.

[ Table 9 ] Single ended Output slew rate definition

Description

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 10 ] Single ended output slew rate

Parameter Symbol

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Min Max Min Max Min Max Min Max Min Max

Single ended output slew rate SRQse 2.5 5 2.5 5 2.5 5 2.5 5 2.5

Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals

For Ron = RZQ/7 setting

NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ

- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the

signals in the same byte lane are static (i.e they stay at either high or low).

remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

Measured

From To

(AC) VOH(AC)

V

OL

V

(AC) VOL(AC)

OH

Defined by

(AC)-VOL(AC)

V

OH

Delta TRse

(AC)-VOL(AC)

V

OH

Delta TFse

Units

1)

5

V/ns

Figure 6. Single-ended Output Slew Rate Definition

- 16 -

Rev. 1.4

V

OHdiff

(AC)

V

OLdiff

(AC)

delta TRdiffdelta TFdiff

VTT

Unbuffered SODIMM datasheet DDR3 SDRAM

11.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

(AC) for differential signals as shown in below.

diff

OLdiff

(AC) and V

[ Table 11 ] Differential Output slew rate definition

Description

Differential output slew rate for rising edge

Differential output slew rate for falling edge

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

V

V

Measured

From To

(AC) V

OLdiff

(AC) V

OHdiff

OHdiff

OLdiff

(AC)

(AC)

V

V

OHdiff

OHdiff

Defined by

(AC)-V

OLdiff

Delta TRdiff

(AC)-V

OLdiff

Delta TFdiff

(AC)

(AC)

[ Table 12 ] Differential Output slew rate

Parameter Symbol

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Min Max Min Max Min Max Min Max Min Max

Units

Differential output slew rate SRQdiff 5 10 5 10 5 10 5 10 5 12 V/ns

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

diff : Differential Signals
For Ron = RZQ/7 setting

OH-

Figure 7. Differential output slew rate definition

- 17 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

12. DIMM IDD specification definition

Symbol Description

IDD0

IDD1

IDD2N

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDD4W

IDD5B

IDD6

IDD6ET

IDD7

IDD8

Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:

0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

2)

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

tern

Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8

and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

2)

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

tern

Precharge Standby Current

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode

2)

Registers

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit

3)

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit

3)

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0

Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode

2)

Registers

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

1)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers
Signal: stable at 0

Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

1)

; AL: 0; CS: High between RD; Command, Address,

Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Operating Burst Write Current

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

1)

; AL: 0; CS: High between WR; Command, Address,

Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

; Pattern Details: Refer to Component Datasheet for detail pattern

at HIGH

Burst Refresh Current

CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and

RTT: Enabled in Mode Registers

Self Refresh Current: Normal Temperature Range

TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8

Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

Self-Refresh Current: Extended Temperature Range (optional)

TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and CK:

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8

2)

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

4)

; Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and CK:

1)

; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

6)

1)

; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

2)

; ODT Signal: FLOATING

Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8

between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:

Enabled in Mode Registers

2)

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

RESET Low Current
RESET : Low; External clock : off; CK and CK

: LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :

FLOATING

1)

; AL: 0; CS: High between ACT and PRE;

1)

; AL: 0; CS: High between ACT, RD

2)

; ODT Signal: stable

2)

; ODT Signal: stable

1)

; AL: 0; CS: High between REF; Command,

2)

; ODT Signal: FLOATING

1)

; AL: CL-1; CS: High

2)

; ODT

2)

;

2)

;

2)

;

- 18 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

NOTE :

1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device

7) IDD current measure method and detail patterns are described on DDR3 component datasheet

8) VDD and VDDQ are merged on module PCB.

9) DIMM IDD SPEC is measured with Qoff condition

(IDDQ values are not considered)

- 19 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

13. IDD SPEC Table

M471B5773DH0 : 2GB (256Mx64) Module

Symbol

IDD0 280 320 360 400 mA

IDD1 360 400 440 480 mA

IDD2P0(slow exit) 96 96 96 96 mA

IDD2P1(fast exit) 120 120 120 136 mA

IDD2N 136 160 160 160 mA

IDD2Q 136 160 160 160 mA

IDD3P 136 136 160 160 mA

IDD3N 240 280 280 296 mA

IDD4R 520 600 720 800 mA

IDD4W 560 640 760 880 mA

IDD5B 880 920 960 960 mA

IDD6 96 96 96 96 mA

IDD7 840 1080 1120 1160 mA

IDD8 96 96 96 96 mA

(DDR3-1066@CL=7)

CF8

CH9

(DDR3-1333@CL=9)

CK0

(DDR3-1600@CL=11)

CMA

(DDR3-1866@CL=13)

Unit NOTE

M471B5273DH0 : 4GB (512Mx64) Module

Symbol

IDD0 416 480 520 560 mA 1

IDD1 496 560 600 640 mA 1

IDD2P0(slow exit) 192 192 192 192 mA

IDD2P1(fast exit) 240 240 240 272 mA

IDD2N 272 320 320 320 mA

IDD2Q 272 320 320 320 mA

IDD3P 272 272 320 320 mA

IDD3N 376 440 440 456 mA

IDD4R 656 760 880 960 mA 1

IDD4W 696 800 920 1040 mA 1

IDD5B 1016 1080 1120 1120 mA 1

IDD6 192 192 192 192 mA

IDD7 976 1240 1280 1320 mA 1

IDD8 192 192 192 192 mA

NOTE :

1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.

(DDR3-1066@CL=7)

CF8

CH9

(DDR3-1333@CL=9)

CK0

(DDR3-1600@CL=11)

CMA

(DDR3-1866@CL=13)

Unit NOTE

- 20 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

14. Input/Output Capacitance

[ Table 13 ] Input/Output Capacitance

Parameter Symbol

Input/output capacitance
(DQ, DM, DQS, DQS

, TDQS, TDQS)

Input capacitance
(CK and CK)

Input capacitance delta
(CK and CK)

Input capacitance
(All other input-only pins)

Input capacitance delta
(DQS and DQS)

Input capacitance delta
(All control input-only pins)

Input capacitance delta
(all ADD and CMD input-only pins)

Input/output capacitance delta
(DQ, DM, DQS, DQS

, TDQS, TDQS)

CIO 1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 1.4 2.2 pF 1,2,3

CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 pF 2,3

CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4

CI 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 0.75 1.2 pF 2,3,6

CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 pF 2,3,5

CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8

CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10

CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11

Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 - 3 pF 2, 3, 12

NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance.

1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS

2. This parameter is not subject to production test. It is verified by design and characterization.

The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with

V

, V

, VSS, V

DD

DDQ

termination off.

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value of CCK-CCK

5. Absolute value of CIO(DQS)-CIO(DQS)

6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.

7. CDI_CTRL applies to ODT, CS and CKE

8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))

9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE

10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))

11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))

12. Maximum external load capacitance on ZQ pin: 5pF

applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=V

SSQ

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Min Max Min Max Min Max Min Max Min Max

=1.5V, V

DDQ

BIAS=VDD

Units NOTE

/2 and on-die

- 21 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

15. Electrical Characteristics and AC timing

(0 °C<T

15.1 Refresh Parameters by Device Density

All Bank Refresh to active/refresh cmd time tRFC 110 160 260 350 ns

Average periodic refresh interval tREFI

NOTE :

1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in
this material.

15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Parameter min min min min min

CL 6 7 91113tCK

tRCD 15 13.13 13.5 13.75 13.91 ns

tRP 15 13.13 13.5 13.75 13.91 ns

tRAS 37.5 37.5 36 35 34 ns

tRC 52.5 50.63 49.5 48.75 47.91 ns

tRRD 10 7.5 6.0 6.0 5.0 ns

tFAW 40 37.5 30 30 27 ns

≤95 °C, V

CASE

Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units NOTE

= 1.5V ± 0.075V; VDD = 1.5V ± 0.075V)

DDQ

0 °C ≤ T

CASE

85 °C < T

CASE

≤ 85°C

≤ 95°C

7.8 7.8 7.8 7.8 μs

3.9 3.9 3.9 3.9 μs 1

Units NOTEBin (CL - tRCD - tRP) 6-6-6 7-7-7 9-9-9 11- 11-11 13-13-13

15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

[ Table 14 ] DDR3-800 Speed Bins

Speed DDR3-800

Units NOTECL-nRCD-nRP 6 - 6 - 6

Parameter Symbol min max

Internal read command to first data tAA 15 20 ns

ACT to internal read or write delay time tRCD 15 - ns

PRE command period tRP 15 - ns

ACT to ACT or REF command period tRC 52.5 - ns

ACT to PRE command period tRAS 37.5 9*tREFI ns

CL = 5 CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,10,11

CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3

Supported CL Settings 5, 6 nCK

Supported CWL Settings 5 nCK

- 22 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

[ Table 15 ] DDR3-1066 Speed Bins

Speed DDR3-1066

Units NOTECL-nRCD-nRP 7 - 7 - 7

Parameter Symbol min max

Internal read command to first data tAA 13.125 20 ns

ACT to internal read or write delay time tRCD 13.125 - ns

PRE command period tRP 13.125 - ns

ACT to ACT or REF command period tRC 50.625 - ns

ACT to PRE command period tRAS 37.5 9*tREFI ns

CL = 5

CL = 6

CL = 7

CL = 8

Supported CL Settings 5, 6,7,8 nCK

Supported CWL Settings 5,6 nCK

CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,5,10,11

CWL = 6 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,5

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,9

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3

- 23 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

[ Table 16 ] DDR3-1333 Speed Bins

Speed DDR3-1333

Units NOTECL-nRCD-nRP 9 -9 - 9

Parameter Symbol min max

Internal read command to first data tAA

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to ACT or REF command period tRC

ACT to PRE command period tRAS 36 9*tREFI ns

CL = 5

CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,6,10,11

CWL = 6,7 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6

CL = 6

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,6

CWL = 7 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CL = 7

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,6

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5 tCK(AVG) Reserved ns 4

CL = 8

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,6

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4

CL = 9

CL = 10

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,9

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) Reserved ns 1,2,3

Supported CL Settings 5,6,7,8,9 nCK

Supported CWL Settings 5,6,7 nCK

13.5

(13.125)

13.5

(13.125)

13.5

(13.125)

49.5

(49.125)

9

9

9

9

20 ns

- ns

- ns

- ns

- 24 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

[ Table 17 ] DDR3-1600 Speed Bins

Speed DDR3-1600

Units NOTECL-nRCD-nRP 11-11-11

Parameter Symbol min max

Internal read command to first data tAA

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to ACT or REF command period tRC

ACT to PRE command period tRAS 35 9*tREFI ns

CL = 5

CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,7,10,11

CWL = 6,7,8 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7

CL = 6

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7

CWL = 7, 8 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CL = 7

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,7

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7

CWL = 8 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CL = 8

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,7

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CL = 9

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,7

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CL = 10

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,7

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CL = 11

CWL = 5,6,7 tCK(AVG) Reserved ns 4

CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,9

Supported CL Settings 5,6,7,8,9,10,11 nCK

Supported CWL Settings 5,6,7,8 nCK

13.75

(13.125)

13.75

(13.125)

13.75

(13.125)

48.75

(48.125)

9

9

9

9

20 ns

- ns

- ns

- ns

- 25 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

[ Table 18 ] DDR3-1866 Speed Bins

Speed DDR3-1866

Units NOTECL-nRCD-nRP 13-13-13

Parameter Symbol min max

Internal read command to first data tAA

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to ACT or REF command period tRC

ACT to PRE command period tRAS 34 9*tREFI ns

CL = 5

CWL = 5 tCK(AVG) 3.0 3.3 ns

CWL = 6,7,8,9 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,8

CL = 6

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 7,8,9 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CL = 7

CWL = 6 tCK(AVG) 1.875 2.5 ns 1,2,3,4,8

CWL = 7,8,9 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CL = 8

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,8

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 8,9 tCK(AVG) Reserved ns 4

CWL = 5,6 tCK(AVG) Reserved ns 4

CL = 9

CWL = 7 tCK(AVG) 1.5 1.875 ns 1,2,3,4,8

CWL = 8 tCK(AVG) Reserved ns 4

CWL = 9 tCK(AVG) Reserved ns 4

CWL = 5,6 tCK(AVG) Reserved ns 4

CL = 10

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,8

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 5,6,7 tCK(AVG) Reserved ns 4

CL = 11

CWL = 8 tCK(AVG) 1.25 1.5 ns 1,2,3,4,8

CWL = 9 tCK(AVG) Reserved ns 1,2,3,4

CL = 12

CL = 13

CWL = 5,6,7,8 tCK(AVG) Reserved ns 4

CWL = 9 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6,7,8 tCK(AVG) Reserved ns 4

CWL = 9 tCK(AVG) 1.07 <1.25 ns 1,2,3,9

Supported CL Settings 5,6,7,8,9,10,11,13 nCK

Supported CWL Settings 5,6,7,8,9 nCK

13.91

(13.125)

13.91

(13.125)

13.91

(13.125)

47.91

(47.125)

12

12

12

12

20 ns

- ns

- ns

- ns

1,2,3,4,8,10,

11

- 26 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

15.3.1 Speed Bin Table Notes

Absolute Specification (T

NOTE :

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements

from CL setting as well as requirements from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-

anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next "SupportedCL".

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or

1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.

4. "Reserved" settings are not allowed. User must program a different value.

5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,

DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte

20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte

18), and tRPmin (Byte 20). DDR3-1866(CL13) devices supporting downshift to DDR3-1600(CL11) or DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in
SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 devices supporting down binning to DDR3-1333 or DDR3-1066 should program

13.125ns in SPD byte for tAAmin (Byte 16), tRCDmin (Byte 18) and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be
programmed accodingly. For example, 49.125ns, (tRASmin + tRPmin = 36ns + 13.125ns) for DDR3-1333 and 48.125ns (tRASmin + tRPmin = 35ns + 13.125ns) for DDR3-

1600.

10. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.

11. For CL5 support DIMM SPD include CL5 on supportable CAS Latency(Byte 14-bit1 set HIGH).

12. For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting must be programed to match. For example,

DDR3-1866 devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for tAAmin(byte16), tRCDmin(Byte18) and
tRPmin (byte20). Once tRP (Byte20) is programmed to 13.125ns, tRCmin (Byte21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRP­min = 34ns + 13.125ns)

OPER

; V

= VDD = 1.5V +/- 0.075 V);

DDQ

- 27 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

16. Timing Parameters by Speed Grade

[ Table 19 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.)

Speed DDR3-800 DDR3-1066 DDR3-1333

Parameter Symbol MIN MAX MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - 8 - ns 6

Average Clock Period tCK(avg)

Clock Period tCK(abs)

Average high pulse width tCH(avg) 0. 47 0.53 0.47 0.53 0.47 0.53 tCK(avg)

Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)

Clock Period Jitter tJIT(per) -100 100 -90 90 -80 80 ps

Clock Period Jitter during DLL locking period tJIT(per, lck) -90 90 -80 80 -70 70 ps

Cycle to Cycle Period Jitter tJIT(cc) 200 180 160 ps

Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 180 160 140 ps

Cumulative error across 2 cycles tERR(2per) - 147 147 - 132 132 - 118 118 ps

Cumulative error across 3 cycles tERR(3per) - 175 175 - 157 157 - 140 140 ps

Cumulative error across 4 cycles tERR(4per) - 194 194 - 175 175 - 155 155 ps

Cumulative error across 5 cycles tERR(5per) - 209 209 - 188 188 - 168 168 ps

Cumulative error across 6 cycles tERR(6per) - 222 222 - 200 200 - 177 177 ps

Cumulative error across 7 cycles tERR(7per) - 232 232 - 209 209 - 186 186 ps

Cumulative error across 8 cycles tERR(8per) - 241 241 - 217 217 - 193 193 ps

Cumulative error across 9 cycles tERR(9per) - 249 249 - 224 224 - 200 200 ps

Cumulative error across 10 cycles tERR(10per) - 257 257 - 231 231 - 205 205 ps

Cumulative error across 11 cycles tERR(11per) - 263 263 - 237 237 - 210 210 ps

Cumulative error across 12 cycles tERR(12per) - 269 269 - 242 242 - 215 215 ps

Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper)

Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - 0.43 - tCK(avg) 25

Absolute clock Low pulse width tCL(abs) 0.43 - 0.43 - 0.43 - tCK(avg) 26

Data Timing

DQS,DQS to DQ skew, per group, per access tDQSQ - 200 - 150 - 125 ps 13

DQ output hold time from DQS, DQS tQH 0.38 - 0.38 - 0.38 - tCK(avg) 13, g

DQ low-impedance time from CK, CK tLZ(DQ) -800 400 -600 300 -500 250 ps 13,14, f

DQ high-impedance time from CK, CK tHZ(DQ) - 400 - 300 - 250 ps 13,14, f

tDS(base)

Data setup time to DQS, DQS referenced
to V

(AC)VIL(AC) levels

IH

Data hold time to DQS, DQS referenced
to VIH(DC)VIL(DC) levels

DQ and DM Input pulse width for each input tDIPW 600

Data Strobe Timing

DQS, DQS differential READ Preamble tRPRE 0.9 NOTE 19 0.9 NOTE 19 0.9 NOTE 19 tCK 13, 19, g

DQS, DQS differential READ Postamble tRPST 0.3 NOTE 11 0.3 NOTE 11 0.3 NOTE 11 tCK 11, 13, b

DQS, DQS differential output high time tQSH 0.38 - 0.38 - 0.4 - tCK(avg) 13, g

DQS, DQS differential output low time tQSL 0.38 - 0.38 - 0.4 - tCK(avg) 13, g

DQS, DQS differential WRITE Preamble tWPRE 0.9 - 0.9 - 0.9 - tCK

DQS, DQS differential WRITE Postamble tWPST 0.3 - 0.3 - 0.3 - tCK

DQS, DQS rising edge output access time from rising CK, CK tDQSCK -400 400 -300 300 -255 255 ps 13,f

DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS) -800 400 -600 300 -500 250 ps 13,14,f

DQS, DQS high-impedance time (Referenced from RL+BL/2) tHZ(DQS) - 400 - 300 - 250 ps 12,13,14

DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 29, 31

DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 30, 31

DQS, DQS rising edge to CK, CK rising edge tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 tCK(avg) c

DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.2 - 0.2 - 0.2 - tCK(avg) c, 32

DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.2 - 0.2 - 0.2 - tCK(avg) c, 32

AC175

tDS(base)

AC150

tDH(base)

DC100

tCK(avg)min +

tJIT(per)min

125

150

tCK(avg)max +

tJIT(per)max

tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max

75

-

-

-

-

See Speed Bins Table

tCK(avg)min +

tJIT(per)min

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per) min

100

490

tCK(avg)max +

tJIT(per)max

25

75

tCK(avg)min +

tJIT(per)min

-

-

-

-

tCK(avg)max +

tJIT(per)max

- - ps d, 17

30 - ps d, 17

65 - ps d, 17

400

-

Units NOTE

ps

ps

ps 24

ps 28

- 28 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

[ Table 19 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.)

Speed DDR3-800 DDR3-1066 DDR3-1333

Parameter Symbol MIN MAX MIN MAX MIN MAX

Command and Address Timing

DLL locking time tDLLK 512 - 512 - 512 - nCK

internal READ Command to PRECHARGE Command delay tRTP

Delay from start of internal write transaction to internal read com­mand

WRITE recovery time tWR 15 - 15 - 15 - ns e

Mode Register Set command cycle time tMRD 4 - 4 - 4 - nCK

Mode Register Set command updat e delay tMOD

CAS to CAS command delay tCCD 4 - 4 - 4 - nCK

Auto precharge write recovery + precharge time tDAL(min) WR + roundup (tRP / tCK(AVG)) nCK

Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - nCK 22

ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42 ns e

ACTIVE to ACTIVE command period for 1KB page size tRRD

ACTIVE to ACTIVE command period for 2KB page size tRRD

Four activate window for 1KB page size tFAW 40 - 37.5 - 30 - ns e

Four activate window for 2KB page size tFAW 50 - 50 - 45 - ns e

Command and Address setup time to CK, CK referenced to
VIH(AC) / VIL(AC) levels

Command and Address hold time from CK, CK referenced to
VIH(DC) / VIL(DC) levels

Control & Address Input pulse width for each input tIPW 900

Calibration Timing

Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - nCK

Normal operation Full calibration time tZQoper 256 - 256 - 256 - nCK

Normal operation short calibration time tZQCS 64 - 64 - 64 - nCK 23

Reset Timing

Exit Reset from CKE HIGH to a valid command tXPR

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL tXS

Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - tDLLK(min) - tDLLK(min) - nCK

Minimum CKE low width for Self refresh entry to exit timing tCKESR

Valid Clock Requirement after Self Refresh Entry (SRE) or Power ­Down Entry (PDE)

Valid Clock Requirement before Self Refresh Exit (SRX) or Power­Down Exit (PDX) or Reset Exit

tWTR

tIS(base)

AC175

tIS(base)

AC150

tIH(base)

DC100

tCKSRE

tCKSRX

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns)

max

(4nCK,10ns)

max

(4nCK,10ns)

200

200+150

275

max(5nCK,

tRFC + 10ns)

max(5nCK,tRF

C + 10ns)

tCKE(min) +

1tCK

max(5nCK,

10ns)

max(5nCK,

10ns)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns)

max

(4nCK,7.5ns)

max

(4nCK,10ns)

125

125+150

200

780

max(5nCK,

tRFC + 10ns)

max(5nCK,tRF

C + 10ns)

tCKE(min) +

1tCK

max(5nCK,

10ns)

max(5nCK,

10ns)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns)

max

(4nCK,6ns)

max

(4nCK,7.5ns)

65 - ps b,16

65+125 - ps b,16,27

140 - ps b,16

620 - ps 28

max(5nCK,

tRFC + 10ns)

max(5nCK,tRF

C + 10ns)

tCKE(min) +

1tCK

max(5nCK,

10ns)

max(5nCK,

10ns)

Units NOTE

- e

- e,18

-

- e

- e

-

-

-

-

-

- 29 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

[ Table 19 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333

Speed DDR3-800 DDR3-1066 DDR3-1333

Parameter Symbol MIN MAX MIN MAX MIN MAX

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Pre­charge Power Down with DLL
frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands re­quiring a locked DLL

CKE minimum pulse width tCKE

Command pass disable delay tCPDED 1 - 1 - 1 - nCK

Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK 15

Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - 1 - nCK 20

Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - 1 - nCK 20

Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 - RL + 4 +1 - RL + 4 +1 -

Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)

Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)

Timing of WR command to Power Down entry
(BC4MRS)

Timing of WRA command to Power Down entry
(BC4MRS)

Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 1 - 20,21

Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) - tMOD(min) - tMOD(min) -

ODT Timing

ODT high time without write command or with write command
and BC4

ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - nCK

Asynchronous RTT turn-on delay (Power-Down with DLL fro­zen)

Asynchronous RTT turn-off delay (Power-Down with DLL fro­zen)

RTT turn-on tAON -400 400 -300 300 -250 250 ps 7,f

RTT_NOM and RTT_WR turn-off time from ODTLoff reference tAOF 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) 8,f

RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) f

Write Leveling Timing

First DQS/DQS rising edge after write leveling mode is pro­grammed

DQS/DQS delay after write leveling mode is programmed tWLDQSEN 25 - 25 - 25 - tCK 3

Write leveling setup time from rising CK, CK crossing to rising
DQS, DQS

Write leveling hold time from rising DQS, DQS crossing to rising
CK, CK

Write leveling output delay tWLO 0 9 0 9 0 9 ns

Write leveling output error tWLOE 0 2 0 2 0 2 ns

crossing

crossing

tXP

tXPDLL

tWRPDEN

tWRAPDEN WL+4+WR +1 - WL+4+WR+1 - WL+4+WR+1 - nCK 10

tWRPDEN

tWRAPDEN

ODTH4 4 - 4 - 4 - nCK

tAONPD 2 8.5 2 8.5 2 8.5 ns

tAOFPD 2 8.5 2 8.5 2 8.5 ns

tWLMRD 40 - 40 - 40 - tCK 3

tWLS 325 - 245 - 195 - ps

tWLH 325 - 245 - 195 - ps

max

(3nCK,

7.5ns)

max

(10nCK,

24ns)

max

(3nCK,

7.5ns)

WL + 4
+(tWR/

tCK(avg))

WL + 2
+(tWR/

tCK(avg))

WL +2 +WR

+1

-

-

-

-

-

-

max

(3nCK,

7.5ns)

max

(10nCK,

24ns)

max

(3nCK,

5.625ns)

WL + 4

+(tWR/

tCK(avg))

WL + 2

+(tWR/

tCK(avg))

WL +2 +WR

+1

-

-

-

-

-

-

max

(3nCK,6ns)

max

(10nCK,

24ns)

max

(3nCK,

5.625ns)

WL + 4
+(tWR/

tCK(avg))

WL + 2
+(tWR/

tCK(avg))

WL +2 +WR

+1

Units NOTE

-

- 2

-

- nCK 9

- nCK 9

- nCK 10

- 30 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

[ Table 20 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.)

Speed DDR3-1600 DDR3-1866

Parameter Symbol MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - ns 6

Average Clock Period tCK(avg) See Speed Bins Table ps

Clock Period tCK(abs)

Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 tCK(avg)

Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 tCK(avg)

Clock Period Jitter tJIT(per) -70 70 -60 60 ps

Clock Period Jitter during DLL locking period tJIT(per, lck) -60 60 -50 50 ps

Cycle to Cycle Period Jitter tJIT(cc) 140 120 ps

Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 120 100 ps

Cumulative error across 2 cycles tERR(2p er) -103 103 -88 88 ps

Cumulative error across 3 cycles tERR(3p er) -122 122 -105 105 ps

Cumulative error across 4 cycles tERR(4p er) -136 136 -117 117 ps

Cumulative error across 5 cycles tERR(5p er) -147 147 -126 126 ps

Cumulative error across 6 cycles tERR(6p er) -155 155 -133 133 ps

Cumulative error across 7 cycles tERR(7p er) -163 163 -139 139 ps

Cumulative error across 8 cycles tERR(8p er) -169 169 -145 145 ps

Cumulative error across 9 cycles tERR(9p er) -175 175 -150 150 ps

Cumulative error across 10 cycles tERR(10per) -180 180 -154 154 ps

Cumulative error across 11 cycles tERR(11per) -184 184 -158 158 ps

Cumulative error across 12 cycles tERR(12per) -188 188 -161 161 ps

Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper)

Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - tCK(avg) 25

Absolute clock Low pulse width tCL(abs) 0.43 - 0.43 - tCK(avg) 26

Data Timing

DQS,DQS to DQ skew, per group, per access tDQSQ - 100 - 85 ps 13

DQ output hold time from DQS, DQS tQH 0. 38 - 0.38 - tCK(avg) 13, g

DQ low-impedance time from CK, CK tLZ(DQ) -450 225 -390 195 ps 13,14, f

DQ high-impedance time from CK, CK tHZ(DQ) - 225 - 195 ps 13,14, f

tDS(base)

Data setup time to DQS, DQS referenced to VIH(AC)VIL(AC) lev­els

Data hold time to DQS, DQS referenced to VIH(AC)VIL(AC) levels

DQ and DM Input pulse width for each input tDIPW 360

Data Strobe Timing

DQS, DQS differential READ Preamble tRP RE 0.9 NOTE 19 0.9 NOTE 19 tCK 13, 19, g

DQS, DQS differential READ Postamble tRPST 0.3 NOTE 11 0.3 NOTE 11 tCK 11, 13, b

DQS, DQS differential output high time tQSH 0.4 - 0.4 - tCK(avg) 13, g

DQS, DQS differential output low time tQSL 0.4 - 0.4 - tCK(avg) 13, g

DQS, DQS differential WRITE Preamble tWPRE 0.9 - 0.9 - tCK

DQS, DQS differential WRITE Postamble tWPST 0.3 - 0.3 - tCK

DQS, DQS rising edge output access time from rising CK, CK tDQSCK -225 225 -195 195 ps 13,f

DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS) -450 225 -390 195 ps 13,14,f

DQS, DQS high-impedance time (Referenced from RL+BL/2) tHZ(DQS) - 225 - 195 ps 12,13,14

DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 tCK 29, 31

DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 tCK 30, 31

DQS, DQS rising edge to CK, CK rising edge tDQSS -0.27 0.27 -0.27 0.27 tCK(avg) c

DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.9 NOTE 19 0.18 - tCK(avg) c, 32

DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.3 NOTE 11 0.18 - tCK(avg) c, 32

AC150

tDS(base)

AC135

tDH(base)

DC100

tCK(avg)min + tJIT(per)min

10 - -

- - 0

45 - 20

tCK(avg)max +

tJIT(per)max

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max

-

tCK(avg)min +

tJIT(per)min

320

tCK(avg)max +

tJIT(per)max

-

-

-

-

Units NOTE

ps

ps 24

ps d, 17

ps d, 17

ps d, 17

ps 28

- 31 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

[ Table 20 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.)

Speed DDR3-1600 DDR3-1866

Parameter Symbol MIN MAX MIN MAX

Command and Address Timing

DLL locking time tDLLK 512 - 512 - nCK

internal READ Command to PRECHARGE Command delay tRTP

Delay from start of internal write transaction to internal read com­mand

WRITE recovery time tWR 15 - 15 - ns e

Mode Register Set command cycle time tMRD 4 - 4 - nCK

Mode Register Set command updat e delay tMOD

CAS# to CAS# command delay tCCD 4 - 4 - nCK

Auto precharge write recovery + precharge time tDAL(min)

Multi-Purpose Register Recovery Time tMPRR 1 - 1 - nCK 22

ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42 ns e

ACTIVE to ACTIVE command period for 1KB page size tRRD

ACTIVE to ACTIVE command period for 2KB page size tRRD

Four activate window for 1KB page size tFA W 30 - 27 - ns e

Four activate window for 2KB page size tFA W 40 - 35 - ns e

Command and Address setup time to CK, CK referenced to
VIH(AC) / VIL(AC) levels

Command and Address hold time from CK, CK referenced to
VIH(AC) / VIL(AC) levels

Control & Address Input pulse width for each input tIPW 560 - 535

Calibration Timing

Power-up and RESET calibration time tZQinitI 512 - max(512nCK,640ns) - nCK

Normal operation Full calibration time tZQoper 256 - max(256nCK,320ns) - nCK

Normal operation short calibration time tZQCS 64 - max(64nCK,80ns) - nCK 23

Reset Timing

Exit Reset from CKE HIGH to a valid command tXPR

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL tXS

Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - tDLLK(min) - nCK

Minimum CKE low width for Self refresh entry to exit timing tCKESR tCKE(min) + 1tCK - tCKE(min) + 1nCK -

Valid Clock Requirement after Self Refresh Entry (SRE) or Power­Down Entry (PDE)

Valid Clock Requirement before Self Refresh Exit (SRX) or Power­Down Exit (PDX) or Reset Exit

tWTR

tIS(base)

AC175

tIS(base)

AC150

tIS(base)

AC135

tIS(base)

AC125

tIH(base)

DC100

tCKSRE

tCKSRX

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns)

max

(4nCK,6ns)

max

(4nCK,7.5ns)

45 - - - ps b,16

170 - -

- - 65

- - 150

120 - 100

max(5nCK, tRFC +

10ns)

max(5nCK,tRFC +

10ns)

max(5nCK,

10ns)

max(5nCK,

10ns)

-

-

-

-

-

-

-

-

-

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(12nCK,15ns)

WR + roundup (tRP /

tCK(AVG))

max

(4nCK, 5ns)

max

(4nCK, 6ns)

max(5nCK, tRFC +

10ns)

max(5nCK,tRFC +

10ns)

max(5nCK,

10ns)

max(5nCK,

10ns)

- e

- e,18

-

- e

- e

-

-

-

-

-

-

-

-

-

Units NOTE

nCK

ps b,16

ps b,16

ps b,16,27

ps b,16

ps 28

- 32 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

[ Table 20 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866

Speed DDR3-1600 DDR3-1866

Parameter Symbol MIN MAX MIN MAX

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Pre­charge Power Down with DLL
frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands re­quiring a locked DLL

CKE minimum pulse width tCKE

Command pass disable delay tC PDED 1 - 2 - nCK

Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK 15

Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - nCK 20

Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - nCK 20

Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 - RL + 4 +1 -

Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)

Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)

Timing of WR command to Power Down entry
(BC4MRS)

Timing of WRA command to Power Down entry
(BC4MRS)

Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 20,21

Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) - tMOD(min) -

ODT Timing

ODT high time without write command or with write command
and BC4

ODT high time with Write command and BL8 ODTH8 6 - 6 - nCK

Asynchronous RTT turn-on delay (Power-Down with DLL fro­zen)

Asynchronous RTT turn-off delay (Power-Down with DLL fro­zen)

RTT turn-on tAON -225 225 -195 195 ps 7,f

RTT_NOM and RTT_WR turn-off time from ODTLoff reference tAOF 0.3 0.7 0.3 0.7 tCK(avg) 8,f

RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 tCK(avg) f

Write Leveling Timing

First DQS pulse rising edge after tDQSS margining mode is pro­grammed

DQS/DQS delay after tDQS margining mode is programmed tWLDQSEN 25 - 25 - tCK 3

Write leveling setup time from rising CK, CK crossing to rising
DQS, DQS

Write leveling hold time from rising DQS, DQS crossing to rising
CK, CK

Write leveling output delay tWLO 0 7.5 0 7.5 ns

Write leveling output error tWLOE 0 2 0 2 ns

crossing

crossing

tXP

tXPDLL

tWRPDEN

tWRAPDEN WL + 4 +WR +1 - WL + 4 +WR +1 - nCK 10

tWRPDEN

tWRAPDEN WL +2 +WR +1 - WL +2 +WR +1 - nCK 10

ODTH4 4 - 4 - nCK

tAONPD 2 8.5 2 8.5 ns

tAOFPD 2 8.5 2 8.5 ns

tWLMRD 40 - 40 - tCK 3

tWLS 165 - 140 - ps

tWLH 165 - 140 - ps

max

(3nCK,6ns)

max

(10nCK,

24ns)

max

(3nCK,5ns)

WL + 4 +(tWR/

tCK(avg))

WL + 2 +(tWR/

tCK(avg))

- max(3nCK,6ns) -

- max(10nCK,24ns) - 2

- max(3nCK,5ns) -

-

-

WL + 4 +(tWR/

tCK(avg))

WL + 2 +(tWR/

tCK(avg))

- nCK 9

- nCK 9

Units NOTE

- 33 -

Rev. 1.4

Unbuffered SODIMM datasheet DDR3 SDRAM

16.1 Jitter Notes

Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the

input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,
another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.

Specific Note b These parameters are measured from a command/address signal (CKE, CS

edge to its respective clock signal (CK/CK
tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,
these parameters should be met whether clock jitter is present or not.

Specific Note c These parameters are measured from a data strobe signal (DQS, DQS

The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.

Specific Note d These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal

(DQS, DQS

Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com­mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.

Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input

clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +
193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(der­ated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to
tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the
min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.

) crossing.

) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.

, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition

) crossing to its respective clock signal (CK, CK) crossing.

Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input

clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has
tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +
tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =
tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/
max usage!)

- 34 -

Rev. 1.4

ZQCorrection

(TSens x Tdriftrate) + (VSens x Vdriftrate)

0.5

(1.5 x 1) + (0.15 x 15)

= 0.133

~

~

128ms

Unbuffered SODIMM datasheet DDR3 SDRAM

16.2 Timing Parameter Notes

1. Actual value dependant upon measurement level definitions which are TBD.

2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register

5. Value must be rounded-up to next higher integer value

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"

8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10. WR in clock cycles as programmed in MR0

11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing

Diagram Datasheet.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated

by TBD

13. Value is only valid for RON34

14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.

15. tREFI depends on T

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,

V

(DC) = V

REF

See "Address/Command Setup, Hold and Derating" on component datasheet.

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,

V

(DC)= V

REF

See "Data Setup, Hold and Slew Rate Derating" on component datasheet.

18. Start of internal write transaction is defined as follows ;

For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL

19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram

Datasheet"

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down

IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time

such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming

the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-

ject to in the application, is illustrated. The interval could be defined by the following formula:

OPER

DQ(DC). For input only pins except RESET, V

REF

DQ(DC). For input only pins except RESET, V

REF

REF

REF

(DC)=V

(DC)=V

REF

REF

CA(DC).

CA(DC).

where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu­lated as:

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or 100ps for DDR3-

1333/1600 of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mv - 150
mV) / 1 V/ns].

28. Pulse width of a input signal is defined as the width between the first crossing of V

(DC) and the consecutive crossing of V

REF

REF

(DC)

29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.

30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.

31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

33. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75ps for DDR3-1866 and 65ps for DDR3-2133

to accommodate for the lower alternate threshold of 125mV and another 10ps to account for the earlier reference point [(135mv - 125mV) / 1 V/ns].

- 35 -

Rev. 1.4

The used device is 256M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0846D - HC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

0.25 MAX

2.55

Detail BDetail A

1.00 ± 0.10

0.45 ± 0.03

4.00 ± 0.10

0.10 ABM C

2X 4.00 ± 0.10

0.10 ABM C

2X 1.80

(OPTIONAL HOLES)

0.60

Units : Millimeters

21.00

24.80

63.60

39.00

AB

Max 3.8

1.00 ± 0.10

SPD

1.65

6

30.00 ± 0.15

20.00

67.60

0.10 ABM C

Unbuffered SODIMM datasheet DDR3 SDRAM

17. Physical Dimensions :

17.1 256Mbx8 based 256Mx64 Module (1 Rank) - M471B5773DH0

- 36 -

Rev. 1.4

The used device is 256M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0846D - HC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

0.25 MAX

2.55

Detail BDetail A

1.00 ± 0.10

0.45 ± 0.03

4.00 ± 0.10

0.10 ABM C

2X 4.00 ± 0.10

0.10 ABM C

2X 1.80

(OPTIONAL HOLES)

0.60

Units : Millimeters

21.00

24.80

63.60

39.00

A

B

Max 3.8

1.00 ± 0.10

SPD

1.65

6

30.00 ± 0.15

20.00

67.60

0.10 ABM C

Unbuffered SODIMM datasheet DDR3 SDRAM

17.2 256Mbx8 based 512Mx64 Module (2 Ranks) - M471B5273DH0

- 37 -