Samsung M378B5173EB0-CK0 User Manual

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Page 1

Rev. 1.1, Apr. 2014

M378B5173EB0 M378B1G73EB0

240pin Unbuffered DIMM

based on 4Gb E-die

78FBGA with Lead-Free & Halogen-Free (RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.

1.35V

Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.

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For updates or additional information about Samsung products, contact your nearest Samsung office.

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- 1 -

Page 2

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

Revision History

Revision No. History Draft Date Remark Editor

1.0 - First SPEC Release Oct. 2014 - J.Y.Lee

1.1 - Added to 1866(13-13-13) speed from Product line-up Apr. 2015 - J.Y.Lee

- 2 -

Page 3

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

Table Of Contents

240pin Unbuffered DIMM based on 4Gb E-die

1. DDR3L Unbuffered DIMM Ordering Information...........................................................................................................4

2. Key Features.................................................................................................................................................................4

3. Address Configuration ..................................................................................................................................................4

4. x64 DIMM Pin Configurations (Front side/Back side) ...................................................................................................5

5. Pin Description .............................................................................................................................................................6

6. SPD and Thermal Sensor for ECC UDIMMs ................................................................................................................6

7. Input/Output Functional Description..............................................................................................................................7

7.1 Address Mirroring Feature.......................................................................................................................................8

7.1.1. DRAM Pin Wiring Mirroring .............................................................................................................................. 8

8. Function Block Diagram:...............................................................................................................................................9

8.1 4GB, 512Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)..................................................... 9

8.2 8GB, 1Gx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) .......................................................10

9. Absolute Maximum Ratings ..........................................................................................................................................14

9.1 Absolute Maximum DC Ratings............................................................................................................................... 14

9.2 DRAM Component Operating Temperature Range ................................................................................................14

10. AC & DC Operating Conditions...................................................................................................................................14

10.1 Recommended DC Operating Conditions .............................................................................................................14

11. AC & DC Input Measurement Levels ..........................................................................................................................15

11.1 AC & DC Logic Input Levels for Single-ended Signals..........................................................................................15

11.2 VREF Tolerances .................................................................................................................................................. 17

11.3 AC and DC Logic Input Levels for Differential Signals ..........................................................................................18

11.3.1. Differential Signals Definition ......................................................................................................................... 18

11.3.2. Differential Swing Requirement for Clock (CK -

11.3.3. Single-ended Requirements for Differential Signals ......................................................................................20

11.3.4. Differential Input Cross Point Voltage ............................................................................................................ 21

11.4 Slew Rate Definition for Single Ended Input Signals.............................................................................................22

11.5 Slew rate definition for Differential Input Signals ................................................................................................... 22

12. AC & DC Output Measurement Levels .......................................................................................................................22

12.1 Single Ended AC and DC Output Levels...............................................................................................................22

12.2 Differential AC and DC Output Levels ................................................................................................................... 22

12.3 Single-ended Output Slew Rate ............................................................................................................................ 23

12.4 Differential Output Slew Rate ................................................................................................................................ 24

13. IDD specification definition..........................................................................................................................................25

14. IDD SPEC Table .........................................................................................................................................................27

15. Input/Output Capacitance ...........................................................................................................................................29

16. Electrical Characteristics and AC timing .....................................................................................................................30

16.1 Refresh Parameters by Device Density................................................................................................................. 30

16.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................30

16.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................30

16.3.1. Speed Bin Table Notes .................................................................................................................................. 34

17. Timing Parameters by Speed Grade ..........................................................................................................................35

17.1 Jitter Notes ............................................................................................................................................................39

17.2 Timing Parameter Notes........................................................................................................................................ 40

18. Physical Dimensions...................................................................................................................................................41

18.1 512Mbx8 based 512Mx64 Module (1 Rank) - M378B5173EB0 ............................................................................41

18.2 512Mbx8 based 1Gx64 Module (2 Ranks) - M378B1G73EB0..............................................................................42

CK) and Strobe (DQS - DQS) ............................................. 18

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Page 4

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

1. DDR3L Unbuffered DIMM Ordering Information

Part Number

M378B5173EB0-YK0/MA 4GB 512Mx64 512Mx8(K4B4G0846E-BY##)*8 1 30mm

M378B1G73EB0-YK0/MA 8GB 1Gx64 512Mx8(K4B4G0846E-BY##)*16 2 30mm

NOTE :

1. "##" - K0/MA

2. K0(1600Mbps 11-11-11) / CMA(1866Mbps 13-13-13)

- DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11)

Density Organization

Component Composition

Number of

Rank

2. Key Features

Speed

tCK(min) 2.5 1.875 1.5 1.25 1.071 ns

CAS Latency 6 7 9 11 13 nCK

tRCD(min) 15 13.125 13.5 13.75 13.91 ns

tRP(min) 15 13.125 13.5 13.75 13.91 ns

tRAS(min) 37.5 37.5 36 35 34 ns

tRC(min) 52.5 50.625 49.5 48.75 47.91 ns

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

6-6-6 7-7-7 9-9-9 11-11-11 13-13-13

Height

Unit

• JEDEC standard 1.35V(1.28V~1.14V) & 1.5V(1.425V~1.575V) Power Supply

•V

• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin, 933MHz fCK for

• 8 independent internal bank

• Programmable CAS Latency: 6,7,8,9,10,11,13

• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) ,8 (DDR3-1600) and 9(DDR3-1866)

• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

• Asynchronous Reset

= 1.35V(1.28V~1.14V) & 1.5V(1.425V~1.575V)

DDQ

1866Mb/sec/pin

write [either On the fly using A12 or MRS]

85C, 3.9us at 85C < T

CASE

95C

3. Address Configuration

Organization Row Address Column Address Bank Address Auto Precharge

512Mx8(4Gb) based Module A0-A15 A0-A9 BA0-BA2 A10/AP

- 4 -

Page 5

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

4. x64 DIMM Pin Configurations (Front side/Back side)

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

REFDQ

121

122 DQ4 43 NC 163

3 DQ0 123 DQ5 44

4 DQ1 124

125 DM0 46 NC 166

DQS0 126 NC 47

7 DQS0 127

128 DQ6 KEY 89

9 DQ2 129 DQ7 49 NC 169

10 DQ3 130

131 DQ12 51

12 DQ8 132 DQ13 52 BA2 172 A14 93

13 DQ9 133

134 DM1 54

DQS1 135 NC 55 A11 175 A9 96 DQ42 216 DQ47

16 DQS1 136

137 DQ14 57

18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53

19 DQ11 139

140 DQ20 60

21 DQ16 141 DQ21 61 A2 181 A1 102

22 DQ17 142

143 DM2 63

DQS2 144 NC 64

25 DQS2 145

146 DQ22 66

27 DQ18 147 DQ23 67

28 DQ19 148

149 DQ28 69

30 DQ24 150 DQ29 70 A10/AP 190 BA1 111

31 DQ25 151

152 DM3 72

DQS3 153 NC 73 WE 193 S0 114 DQ58 234 DQ63

34 DQS3 154

155 DQ30 75

36 DQ26 156 DQ31 76

37 DQ27 157

158 NC 78

39 NC 159 NC 79 NC 199

40 NC 160

161 NC 81 DQ32 201 DQ37

NOTE : NC = No Connect; NU = Not Used; RFU = Reserved Future Use

S1, ODT1, CKE1: Used for dual-rank UDIMMs; NC on single-rank UDIMMs

2. CK1,NC and

CK1,NC : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated

3. TEST (pin 167) used by memory bus analysis tools (unused on memory DIMMs)

42 NC 162 NC 82 DQ33 202

164 NC 84 DQS4 204 NC

203 DM4

45 NC 165 NC 85 DQS4 205

167

NC (TEST)

87 DQ34 207 DQ39

206 DQ38

48 NC 168 Reset 88 DQ35 208

50 CKE0 170

171 A15 92

CKE1,NC

90 DQ40 210 DQ45

91 DQ41 211

209 DQ44

212 DM5

DQS5 213 NC

53 NC 173

174 A12/BC 95

56 A7 176

177 A8 98

59 A4 179

180 A3 101

94 DQS5 214

215 DQ46

97 DQ43 217

218 DQ52

100 DQ49 220

221 DM6

DQS6 222 NC

68 NC 188 A0 109 DQ57 229

CK1,NC

REF

182

183

184 CK0 105 DQ50 225 DQ55

185 CK0 106 DQ51 226

186

187 NC 108 DQ56 228 DQ61

189

103 DQS6 223

104

107

110

224 DQ54

227 DQ60

230 DM7

DQS7 231 NC

71 BA0 191

192 RAS 113

74 CAS 194

S1, NC

ODT1, NC

195 ODT0 116

196 A13 117 SA0 237 SA1

197

198 NC 119 SA2 239

200 DQ36

112 DQS7 232

233 DQ62

115 DQ59 235

236

118 SCL 238 SDA

120

240

DDSPD

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

- 5 -

Page 6

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

5. Pin Description

Pin Name Description Pin Name Description

A0-A15 SDRAM address bus SCL

BA0-BA2 SDRAM bank select SDA

RAS SDRAM row address strobe SA0-SA2

CAS SDRAM column address strobe

WE SDRAM write enable

S0, S1 DIMM Rank Select Lines

CKE0,CKE1 SDRAM clock enable lines

ODT0, ODT1 On-die termination control lines

DQ0 - DQ63 DIMM memory data bus

CB0 - CB7 DIMM ECC check bits NC Spare Pins(no connect)

DQS0 - DQS8

DQS0-DQS8

DM0-DM8

CK0, CK1

SDRAM data strobes (positive line of differential pair)

SDRAM differential data strobes (negative line of differential pair)

SDRAM data masks/high data strobes (x8-based x72 DIMMs)

SDRAM clocks (positive line of differential pair)

SDRAM clocks (negative line of differential pair)

VDD*

DDQ

REFDQ

REFCA

DDSPD

TEST

RESET Set DRAMs Known State

EVENT Reserved for optional temperature-sensing hardware

RFU Reserved for future use

I2C serial bus clock for EEPROM

C serial bus data line for EEPROM

I2C serial address select for EEPROM

SDRAM core power supply

SDRAM I/O Driver power supply

SDRAM I/O reference supply

SDRAM command/address reference supply

Power supply return (ground)

Serial EEPROM positive power supply

Used by memory bus analysis tools (unused on memory DIMMs)

SDRAM I/O termination supply

NOTE : *The V

** DQS8,

and V

DQS8, DM8 arefor ECC UDIMM only

pins are tied common to a single power-plane on these designs.

DDQ

6. SPD and Thermal Sensor for ECC UDIMMs

On DIMM thermal sensor will provide DRAM temperature readout through a integrated thermal sensor.

SCL

EVENT

NOTE :

1. Raw Cards D (1Rx8 ECC) and E (2Rx8 ECC) support a thermal sensor.

2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not. When only the SPD is placed on the module, R2 is placed but R1 is not.

[ Table 1 ] Temperature Sensor Characteristics

Grade Range

75 < Ta < 95 - +/- 0.5 +/- 1.0

40 < Ta < 125 - +/- 1.0 +/- 2.0 -

-20 < Ta < 125 - +/- 2.0 +/- 3.0 -

Resolution 0.25 C /LSB -

R1 0 

R2 0 

EVENT

WP/

SA0 SA1 SA2

Temperature Sensor Accuracy

Min. Typ. Max.

SDA

Units NOTE

C

- 6 -

Page 7

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

7. Input/Output Functional Description

Symbol Type Function

CK0-CK1 CK0-CK1

CKE0-CKE1 SSTL

S0-S1 SSTL

RAS, CAS, WE SSTL RAS, CAS, and WE (ALONG WITH S) define the command being entered.

ODT0-ODT1 SSTL

REFDQ

REFCA

DDQ

BA0-BA2 SSTL Selects which SDRAM bank of eight is activated.

A0-A15 SSTL

DQ0-DQ63 CB0-CB7

DM0-DM8

VDD,V

DQS0-DQS8

SA0-SA2 -

SDA -

SCL -

DDSPD

RESET - The RESET pin is connected to the RESET pin on each DRAM. When low, all DRAMs are set to a know state.

EVENT Output

NOTE :

1. DM8, DQS8 and

SSTL

Supply Reference voltage for SSTL 15 I/O inputs.

Supply Reference voltage for SSTL 15 command/address inputs.

Supply

SSTL Data and Check Bit Input/Output pins.

SSTL

Supply

SSTL Data strobe for input and output data.

Supply

DQS8 are for ECC UDIMM only

CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing)

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh mode

Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new command are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks.

When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming the function is enabled in the Extended Mode Register Set (EMRS).

Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered DIMM designs, V

During a Bank Activate command cycle, Address input defines the row address (RA0-RA13) During a Read or Write command cycle, Address input defines the column address, In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop; Low, burst chopped).

DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading.

Power and ground for DDR3 SDRAM input buffers, and core logic. VDD and V

these modules.

These signals and tied at the system planar to either VSS or V

range.

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to V

This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to V

Power supply for SPD EEPROM. This supply is separate from the V

from 3.0V to 3.6V.

This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part

shares the same power plane as VDD pins.

DDQ

to act as a pull-up on the system board.

DDSPD

to act as a pull-up on the system board.

DDSPD

pins are tied to VDD/V

DDQ

to configure the serial SPD EERPOM address

DDSPD

DD/VDDQ

power plane. EEPROM supply is operable

DDQ

planes on

- 7 -

Page 8

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

7.1 Address Mirroring Feature

There is a via grid located under the DRAMs for wiring the CA signals (address, bank address, command, and control lines) to the DRAM pins. The length of the traces from the vias to the DRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces. The pins on the DRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5, A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 DRAM pins are wired straight, with no mismatch between the connector pin assignment and the DRAM pin assignment. Some of the Rank 1 DRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight.

7.1.1 DRAM Pin Wiring Mirroring

Connector Pin

A3 A3 A4

A4 A4 A3

A5 A5 A6

A6 A6 A5

A7 A7 A8

A8 A8 A7

BA0 BA0 BA1

BA1 BA1 BA0

Rank 0 Rank 1

DRAM Pin

Figure 1illustrates the wiring in both the mirrored and non-mirrored case. The lengths of the traces to the DRAM pins, is obviously shorter. The via grid is smaller as well.

Figure 1. Wiring Differences for Mirrored and Non-Mirrored Addresses

Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a "load mode" operation, the specific address is required. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank. SAMSUNG DDR3 dual rank UDIMM R/C B(2Rx8) and R/C E(2Rx8) Modules are using Mirrored Addresses mode.

- 8 -

Page 9

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

8. Function Block Diagram:

8.1 4GB, 512Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)

S0 DQS0 DQS0 DM0

DM CS DQS DQS

DQS1 DQS1 DM1

DQS2 DQS2 DM2

DQS3 DQS3 DM3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM NU/ CS DQS DQS

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

BA0 - BA2 BA0-BA2 : SDRAMs D0 - D7

A0 - A13 A0-A13 : SDRAMs D0 - D7

RAS RAS : SDRAMs D0 - D7

CAS CAS : SDRAMs D0 - D7

CKE0 CKE : SDRAMs D0 - D7

WE WE : SDRAMs D0 - D7

ODT0 ODT : SDRAMs D0 - D7

CK0 CK : SDRAMs D0 - D7

Serial PD

SCL

SA0 SA1

DDSPD SPD

VDD/V

DDQ

REFDQ

REFCA

SA2

DQS4 DQS4 DM4

DQS5 DQS5 DM5

DQS6 DQS6 DM6

DQS7 DQS7 DM7

SDA

D0 - D7

DM CS DQS DQS

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

NOTE :

1. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ resistor is 240 Ohm +/- 1%

2. One SPD exists per module.

- 9 -

Page 10

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

8.2 8GB, 1Gx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

S1 S0 DQS0 DQS0 DM0

DQS1 DQS1 DM1

DQS2 DQS2 DM2

DQS3 DQS3 DM3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DM CS DQS DQS

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

D10

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

D11

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DQS4 DQS4 DM4

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38

DQS5 DQS5 DM5

DQS6 DQS6 DM6

DQS7 DQS7 DM7

DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

ZQZQ ZQZQ

DM CS DQS DQS

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

D12

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

D13

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

D14

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

DM CS DQS DQS

I/O 0 I/O 1

D15

I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

BA0 - BA2 BA0-BA2 : SDRAMs D0 - D15

A0 - A15 A0-A15 : SDRAMs D0 - D15

CKE1 CKE : SDRAMs D8 - D15

CKE0 CKE : SDRAMs D0 - D7

RAS RAS : SDRAMs D0 - D15

CAS CAS : SDRAMs D0 - D15

WE WE : SDRAMs D0 - D15

ODT0 ODT : SDRAMs D0 - D7

ODT1 ODT : SDRAMs D8 - D15

CK0 CK : SDRAMs D0 - D7

CK1 CK : SDRAMs D8 - D15

Serial PD

SCL

SA0 SA1

DDSPD SPD

DD/VDDQ

REFDQ

REFCA

SA2

- 10 -

SDA

D0 - D15

NOTE :

1. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ resistor is 240 Ohm +/- 1%

2. One SPD exists per module.

Page 11

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

11. Absolute Maximum Ratings

11.1 Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

Voltage on V

DDQ

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and V

equal to or less than 300mV.

Voltage on any pin relative to V

IN, VOUT

Storage Temperature -55 to +100 C 1, 2

STG

DDQ

11.2 DRAM Component Operating Temperature Range

Symbol Parameter rating Unit NOTE

OPER

NOTE :

1. Operating Temperature T JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85C under all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

Voltage on VDD pin relative to V

pin relative to V

DDQ

must be within 300mV of each other at all times;and V

Operating Temperature Range 0 to 95 C 1, 2, 3

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

OPER

-0.4 V ~ 1.8 V V 1,3

-0.4 V ~ 1.8 V V 1

must be not greater than 0.6 x V

REF

, When VDD and V

DDQ

are less than 500mV; V

DDQ

REF

may be

12. AC & DC Operating Conditions

12.1 Recommended DC Operating Conditions

Symbol Parameter Operation Voltage

DDQ

NOTE:

1. Under all conditions V

2. V

tracks with VDD. AC parameters are measured with VDD and V

DDQ

& V

3. V

DDQ

Supply Voltage

Supply Voltage for Output

must be less than or equal to VDD.

DDQ

rating are determinied by operation voltage.

1.35V 1.283 1.35 1.45 V 1, 2, 3

1.5V 1.425 1.5 1.575 V 1, 2, 3

1.35V 1.283 1.35 1.45 V 1, 2, 3

1.5V 1.425 1.5 1.575 V 1, 2, 3

DDQ

tied together.

Rating

Min. Typ. Max.

Units NOTE

- 14 -

Page 12

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

13. AC & DC Input Measurement Levels

13.1 AC & DC Logic Input Levels for Single-ended Signals

[ Table 2 ] Single Ended AC and DC input levels for Command and Address(1.35V)

Symbol Parameter

(DC90)

IH.CA

(DC90)

IL.CA

(AC160)

IH.CA

(AC160)

IL.CA

(AC135)

IH.CA

(AC135)

IL.CA

(AC125)

IH.CA

(AC125)

IL.CA

REFCA

NOTE :

1. For input only pins except

2. See "Overshoot and Undershoot specifications" section.

3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).

4. For reference: approx. VDD/2 +/- 13.5 mV

5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V , the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIHL.CA(AC150),

VIH/L.CA(AC135), VIH/L.CA(AC125)etc.) apply. The 1.5 V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIHL.CA(AC125)etc.) do not apply when the device is operated in the 1.35 voltage range.

DC input logic high

DC input logic low

AC input logic high

AC input logic low Note 2

AC input logic high

AC input logic lowM Note 2

AC input logic high - -

AC input logic low - - Note 2

Reference Voltage for ADD,

(DC)

CMD inputs

RESET, V

REF

= V

REFCA

(DC)

DDR3L-800/1066/1333/1600 DDR3L-1866

Min. Max. Min. Max.

1.35V

+ 90 V

REF

+ 160

REF

+135

REF

0.49*V

- 90 V

REF

Note 2 - - mV 1,2,5

- 160

REF

Note 2

-135

REF

0.51*V

+ 90 V

REF

- - mV 1,2,5

+135

REF

Note 2

+ 125

REF

0.49*V

Unit NOTE

- 90

REF

mV 1

Note 2 mV 1,2,5

REF

-135

mV 1,2,5

Note 2 mV 1,2,5

+ 125

REF

0.51*V

mV 1,2,5

V 3,4

[ Table 3 ] Single-ended AC & DC input levels for Command and Address(1.5V)

Symbol Parameter

(DC100)

IH.CA

(DC100)

IL.CA

(AC175)

IH.CA

(AC175)

IL.CA

(AC150)

IH.CA

(AC150)

IL.CA

(AC135)

IH.CA

(AC135)

IL.CA

(AC125)

IH.CA

(AC125)

IL.CA

REFCA

NOTE :

1. For input only pins except

2. See "Overshoot and Undershoot specifications" section.

3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).

4. For reference: approx. VDD/2 +/- 15 mV.

5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)

6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)

7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is

referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is used when Vref + 0.125V is referenced.

8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is

referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value is used when Vref - 0.125V is referenced.

9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device

DC input logic high

DC input logic low

AC input logic high

AC input logic low Note 2

AC input logic high

AC input logic low Note 2

AC input logic high - -

AC input logic low - - Note 2

AC input logic high - -

AC input logic low - - Note 2

Reference Voltage for ADD,

(DC)

CMD inputs

RESET, V

REF

= V

REFCA

(DC)

DDR3-800/1066/1333/1600 DDR3-1866

Min. Max. Min. Max.

+ 100 V

REF

+ 175

REF

+150

REF

0.49*V

- 100 V

REF

Note 2 - - mV 1,2,7

- 175

REF

Note 2 - - mV 1,2,7

-150

REF

0.51*V

+ 100 V

REF

- - mV 1,2,8

+ 135

REF

+125

REF

0.49*V

Unit NOTE

- 100

REF

mV 1,5

mV 1,6

Note 2 mV 1,2,7

REF

- 135

mV 1,2,8

Note 2 mV 1,2,7

REF

0.51*V

-125

mV 1,2,8

V 3,4,9

- 15 -

Page 13

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

[ Table 4 ] Single Ended AC and DC input levels for DQ and DM(1.35V)

Symbol Parameter

DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866

Min. Max. Min. Max. Min. Max.

Unit NOTE

1.35V

(DC90)

IH.DQ

(DC90)

IL.DQ

(AC160)

IH.DQ

(AC160)

IL.DQ

(AC135)

IH.DQ

(AC135)

IL.DQ

(AC130)

IH.DQ

(AC130)

IL.DQ

REF

NOTE :

1. For input only pins except

2. See "Overshoot and Undershoot specifications" section.

3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference:approx. +/- 13.5 mV).

4. For reference: approx. VDD/2 +/- 13.5 mV.

5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V, the respective levels in JESD79-3 ( VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/

L.DQ(AC150), VIH/L.DQ(AC135), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) do not apply when the device is operated in the 1.35 voltage range.

DC input logic high

DC input logic low

AC input logic high

AC input logic low Note 2

AC input logic high

AC input logic low Note 2

AC input logic high - - - -

AC input logic low - - - - Note 2

Reference Voltage for DQ,

(DC)

DM inputs

RESET, V

REF

= V

REFDQ

(DC)

REF

0.49*V

+ 90 V

+ 160

+ 135

- 90 V

REF

+ 90 V

REF

- 90 V

REF

+ 90 V

REF

- 90

REF

mV 1

Note 2 - - - - mV 1,2,5

REF

Note 2

REF

0.51*V

- 160

- 135

- - - - mV 1,2,5

+ 135

REF

Note 2

0.49*V

Note 2 - - mV 1,2,5

- 135

REF

0.51*V

- - mV 1,2,5

+ 130

REF

0.49*V

Note 2 mV 1,2,5

- 130

REF

0.51*V

mV 1,2,5

V 3,4

[ Table 5 ] Single-ended AC & DC input levels for DQ and DM (1.5V)

Symbol Parameter

DDR3-800/1066 DDR3-1333/1600 DDR3-1866

Min. Max. Min. Max. Min. Max.

Unit NOTE

1.5V

(DC100)

IH.DQ

(DC100)

IL.DQ

(AC175)

IH.DQ

(AC175)

IL.DQ

(AC150)

IH.DQ

(AC150)

IL.DQ

(AC135)

IH.DQ

(AC135)

IL.DQ

REF

NOTE :

1. For input only pins except

2. See "Overshoot and Undershoot specifications" section.

3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).

4. For reference: approx. VDD/2 +/- 15 mV.

5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)

6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)

7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC175) value is used when Vref + 0.175V is referenced,

VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.

8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC175) value is used when Vref - 0.175V is referenced,

VIL.DQ(AC150) value is used when Vref - 0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.

9. VrefDQ(DC) is measured relative to VDD at the same point in time on the same device

10. Optional in DDR3 SDRAM for DDR3-800/1066/1333/1600: Users should refer to the DRAM supplier data sheetand/or the DIMM SPD to determine if DDR3 SDRAM devices

support this option.

DC input logic high

DC input logic low

AC input logic high

AC input logic low NOTE 2

AC input logic high

AC input logic low NOTE 2

AC input logic high

AC input logic low NOTE 2

Reference Voltage for DQ,

(DC)

DM inputs

RESET, V

REF

= V

REFDQ

(DC)

REF

0.49*V

+ 100 V

REF

NOTE 2 - - - - mV 1,2,7

REF

NOTE 2

REF

NOTE 2

REF

0.51*V

+ 175

+ 150

+ 135

REF

- 100 V

- 175

REF

- 150

- 135

NOTE 2

REF

NOTE 2

0.49*V

+ 100 V

REF

- 100 V

+ 100 V

REF

- 100

REF

mV 1,5

mV 1,6

- - - - mV 1,2,8

+ 150

+ 135

NOTE 2 - - mV 1,2,7

REF

NOTE 2

REF

0.51*V

- 150

- 135

- - mV 1,2,8

+ 135

REF

NOTE 2

0.49*V

NOTE 2 mV 1,2,7,10

- 135

REF

0.51*V

mV 1,2,8,10

V 3,4,9

- 16 -

Page 14

Rev. 1.1

Unbuffered DIMM

13.2 V

The dc-tolerance limits and ac-noise limits for the reference voltages V

(t) as a function of time. (V

REF

(DC) is the linear average of V

REF

thermore V

Tolerances

REF

(t) may temporarily deviate from V

REF

voltage

stands for V

REF

REFCA

(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V

REF

datasheet DDR3L SDRAM

and V

(DC) by no more than ± 1% VDD.

REFDQ

likewise).

REFCA

and V

are illustrate in Figure 2. It shows a valid reference voltage

REFDQ

REF

. Fur-

time

Figure 2. Illustration of VREF(DC) tolerance and VREF ac-noise limits

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V

" shall be understood as V

REF

This clarifies, that dc-variations of V

which setup and hold is measured. System timing and voltage budgets need to account for V

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

Timing and voltage effects due to ac-noise on V

(DC), as defined in Figure 2.

REF

affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

REF

(DC) deviations from the optimum position within the

REF

up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

REF

ac-noise.

REF

- 17 -

Page 15

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

13.3 AC and DC Logic Input Levels for Differential Signals

13.3.1 Differential Signals Definition

tDVAC

VIH.DIFF.AC.MIN

.DIFF.MIN

0.0 half cycle

.DIFF.MAX

.DIFF.AC.MAX

Differential Input Voltage (i.e. DQS-DQS, CK-CK)

tDVAC

time

Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC

13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

DDR3-800/1066/1333/1600/1866

Symbol Parameter

min max min max

IHdiff

ILdiff

(AC)

IHdiff

(AC)

ILdiff

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK -

3. These values are not defined, however they single-ended signals CK,

CK use VIH/VIL(AC) of ADD/CMD and V

then the reduced level applies also here.

nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"

differential input high +0.18 NOTE 3 +0.20 NOTE 3 V 1

differential input low NOTE 3 -0.18 NOTE 3 -0.20 V 1

differential input high ac

2 x (VIH(AC) - V

differential input low ac NOTE 3

; for DQS - DQS use VIH/VIL(AC) of DQs and V

REFCA

REF

)

NOTE 3

2 x (VIL(AC) - V

CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-

2 x (VIH(AC) - V

)

REF

REFDQ

unit NOTE1.35V 1.5V

)

REF

NOTE 3

; if a reduced ac-high or ac-low level is used for a signal group,

NOTE 3 V 2

2 x (VIL(AC) - V

REF

)

- 18 -

Page 16

Rev. 1.1

Unbuffered DIMM

[ Table 6 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V)

DDR3L-800/1066/1333/1600 DDR3L-1866

Slew Rate [V/ns]

> 4.0 189 - 201 - 163 - 168 - 176 -

4.0 189 - 201 - 163 - 168 - 176 -

3.0 162 - 179 - 140 - 147 - 154 -

2.0 109 - 134 - 95 - 105 - 111 -

1.8 91 - 119 - 80 - 91 - 97 -

1.6 69 - 100 - 62 - 74 - 78 -

1.4 40 - 76 - 37 - 52 - 56 -

1.2 note - 44 - 5 - 22 - 24 -

1.0 note - note - note - note - note -

< 1.0 note - note - note - note - note -

NOTE: Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.

[ Table 7 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V)

Slew Rate [V/ns]

> 4.0 75 - 175 - 214 - 134 - 139 -

4.0 57 - 170 - 214 - 134 - 139 -

3.0 50 - 167 - 191 - 112 - 118 -

2.0 38 - 119 - 146 - 67 - 77 -

1.8 34 - 102 - 131 - 52 - 63 -

1.6 29 - 81 - 113 - 33 - 45 -

1.4 22 - 54 - 88 - 9 - 23 -

1.2 note - 19 - 56 - note - note -

1.0 note - note - 11 - note - note -

< 1.0 note - note - note - note - note -

NOTE: Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VILdiff(ac) level

tDVAC [ps] @ |V

(AC)| = 320mV

Ldiff

min max min max min max min max min max

tDVAC [ps]

@ V

(AC)= 350mV

IH/Ldiff

min max min max min max min max min max

IH/

DDR3-800/1066/1333/1600 DDR3-1866

@ V

datasheet DDR3L SDRAM

tDVAC [ps] @ |V

(AC)| = 270mV

Ldiff

tDVAC [ps]

(AC)= 300mV

IH/Ldiff

IH/

(DQS - DQS#) only

tDVAC [ps]

@ |VIH/Ldiff(ac)|

=270mV

tDVAC [ ps ]

@ VIH/L diff(ac)

=270mv

(Optional)

tDVAC [ps]

@ |VIH/Ldiff(ac)|

=250mV

tDVAC [ps]

@ V

IH/Ldiff

= 270mV

(AC)

tDVAC [ps]

@ |VIH/Ldiff(ac)|

tDVAC [ps]

@ V

=250mV(CK - CK#) only

=260mV

IH/Ldiff

(AC)

- 19 -

Page 17

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

13.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.

CK and CK have to approximately reach V

half-cycle.

DQS, DQS have to reach V

SEH

min / V

ing a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V

signals, then these ac-levels apply also for the single-ended signals CK and

VDD or V

SEH

VDD/2 or V

DDQ

min / V

SEH

max (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle proceeding and follow-

SEL

max (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every

SEL

150(AC)/VIL150(AC) is used for ADD/CMD

CK .

DDQ

min

SEH

CK or DQS

max

SEL

VSS or V

SSQ

Figure 4. Single-ended requirement for differential signals

Note that while ADD/CMD and DQ signal requirements are with respect to V

with respect to V

ended components of differential signals the requirement to reach V

/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

SEL

, the single-ended components of differential signals have a requirement

REF

max, V

min has no bearing on timing, but adds a restriction on the common

SEH

mode characteristics of these signals.

[ Table 8 ] Single ended levels for CK, DQS,

Symbol Parameter

SEH

SEL

NOTE :

1. For CK,

2. V

3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-

CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.

(AC)/VIL(AC) for DQs is based on V

reduced level applies also here

nals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"

Single-ended high-level for strobes

Single-ended high-level for CK, CK

Single-ended low-level for strobes NOTE 3

Single-ended low-level for CK, CK NOTE 3

REFDQ

CK, DQS

Min Max

(VDD/2)+0.175

/2)+0.175

; VIH(AC)/VIL(AC) for ADD/CMD is based on V

DDR3-800/1066/1333/1600/1866

; if a reduced ac-high or ac-low level is used for a signal group, then the

REFCA

SEL

time

NOTE 3 V 1, 2

/2)-0.175

(VDD/2)-0.175

Unit NOTE

V 1, 2

- 20 -

Page 18

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

13.3.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual

cross point of true and complement signal to the mid level between of VDD and VSS.

CK, DQS

VDD/2

VSEH VSEL

Figure 5. VIX Definition

CK, DQS

[ Table 9 ] Cross point voltage for differential input signals (CK, DQS) : 1.35V

Symbol Parameter

NOTE :

1. The relationbetween Vix Min/Max and VSEL/VSEH should satisfy following. (VDD/2) + Vix(Min) - VSEL 25mV VSEH - ((VDD/2) + Vix(Max)) 25mV

Differential Input Cross Point Voltage relative to VDD/2 for CK,CK

Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS

[ Table 10 ] Cross point voltage for differential input signals (CK, DQS) : 1.5V

Symbol Parameter

NOTE :

1. Extended range for V

±250 mV, and the differential slew rate of CK-

Differential Input Cross Point Voltage relative to VDD/2 for CK,CK

Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS

is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V

CK is larger than 3 V/ ns.

DDR3L-800/1066/1333/1600/1866

Min Max

Unit NOTE

-150 150 mV 1

-150 150 mV

DDR3-800/1066/1333/1600/1866

Min Max

Unit NOTE

-150 150 mV

-175 175 mV 1

-150 150 mV

/ V

SEL

of at least VDD/2

SEH

- 21 -

Page 19

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

13.4 Slew Rate Definition for Single Ended Input Signals

See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals. See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.

13.5 Slew rate definition for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.

[ Table 11 ] Differential input slew rate definition

Description

Differential input slew rate for rising edge (CK-CK and DQS-DQS)

Differential input slew rate for falling edge (CK-CK and DQS-DQS)

NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds

Measured

From To

ILdiffmax

IHdiffmin

ILdiffmax

IHdiffmin

Defined by

- V

ILdiffmax] /

Delta TRdiff

Delta TFdiff

ILdiffmax

delta TFdiff

delta TRdiff

Figure 6. Differential input slew rate definition for DQS, DQS and CK, CK

14. AC & DC Output Measurement Levels

14.1 Single Ended AC and DC Output Levels

[ Table 12 ] Single Ended AC and DC output levels

Symbol Parameter DDR3-800/1066/1333/1600/1866 Units NOTE

VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x V

(DC) DC output mid measurement level (for IV curve linearity) 0.5 x V

(DC) DC output low measurement level (for IV curve linearity) 0.2 x V

VOH(AC) AC output high measurement level (for output SR) VTT + 0.1 x V

(AC) AC output low measurement level (for output SR) VTT - 0.1 x V

NOTE : 1. The swing of +/-0.1 x V

load of 25 to V

TT=VDDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test

DDQ

/2.

DDQ

14.2 Differential AC and DC Output Levels

[ Table 13 ] Differential AC and DC output levels

Symbol Parameter DDR3-800/1066/1333/1600/1866 Units NOTE

(AC) AC differential output high measurement level (for output SR) +0.2 x V

OHdiff

(AC) AC differential output low measurement level (for output SR) -0.2 x V

OLdiff

NOTE : 1. The swing of +/-0.2xV

load of 25 to VTT=V

DDQ

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test

DDQ

/2 at each of the differential outputs.

DDQ

- 22 -

Page 20

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

14.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)

for single ended signals as shown in below.

[ Table 14 ] Single ended Output slew rate definition

Description

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 15 ] Single ended output slew rate

Parameter Symbol

Single ended output slew rate SRQse

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

se : Single-ended Signals

For Ron = RZQ/7 setting

NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).

- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

Operation

Voltage

1.35V 1.75

1.5V 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 V/ns

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Min Max Min Max Min Max Min Max Min Max

Measured

From To

(AC) VOH(AC) [VOH(AC)-VOL(AC)] / Delta TRse

(AC) VOL(AC) [VOH(AC)-VOL(AC)] / Delta TFse

1.75

Defined by

1.75

Units

V/ns

(AC)

OHdiff

VTT

(AC)

OLdiff

delta TRdiffdelta TFdiff

Figure 7. Single-ended output slew rate definition

- 23 -

Page 21

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

14.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

(AC) for differential signals as shown in below.

OHdiff

[ Table 16 ] Differential Output slew rate definition

Description

Differential output slew rate for rising edge

Differential output slew rate for falling edge

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 17 ] Differential Output slew rate

Parameter Symbol

Differential output slew rate SRQdiff

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

diff : Differential Signals

For Ron = RZQ/7 setting

Operation

Voltage

1.35V 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 V/ns

Measured

From To

(AC) V

OLdiff

(AC) V

OHdiff

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Min Max Min Max Min Max Min Max Min Max

1.5V 5 10 5 10 5 10 5 10 5 12 V/ns

(AC) [V

OHdiff

(AC) [V

OLdiff

OHdiff

(AC)-V

Defined by

(AC)] / Delta TRdiff

OLdiff

(AC)]/ Delta TFdiff

OLdiff

(AC) and

Units

OHdiff

VTT

OLdiff

delta TRdiffdelta TFdiff

Figure 8. Differential output slew rate definition

(AC)

- 24 -

Page 22

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

15. IDD specification definition

Symbol Description

Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8

IDD0

IDD1

IDD2N

IDD2P0

IDD2P1

IDD2Q

IDD3N

IDD3P

IDD4R

IDD4W

IDD5B

IDD6

IDD6ET

IDD7

IDD8

Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

tern

Operating One Bank Active-Read-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8

and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

tern

Precharge Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Regis-

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

ters

Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit

Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit

Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

ODT Signal: stable at 0

Active Standby Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers

ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Active Power-Down Current CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers

Signal: stable at 0

Operating Burst Read Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Operating Burst Write Current CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8

Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers

HIGH; Pattern Details: Refer to Component Datasheet for detail pattern

Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8

Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and RTT: Enabled in Mode Registers

Self Refresh Current: Normal Temperature Range TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

; Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and CK:

; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

Self-Refresh Current: Extended Temperature Range (optional) TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and CK:

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8

; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: CL-1; CS: High

between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:

Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

RESET Low Current RESET : Low; External clock : off; CK and

CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :

FLOATING

; AL: 0; CS: High between ACT and PRE;

; AL: 0; CS: High between ACT, RD

; AL: 0; CS: stable at 1; Command, Address, Bank

; AL: 0; CS: High between RD; Command, Address,

; AL: 0; CS: High between WR; Command, Address,

; AL: 0; CS: High between REF; Command,

; ODT Signal: FLOATING

;

; ODT

; ODT Signal: stable

;

- 25 -

Page 23

Rev. 1.1

Unbuffered DIMM

NOTE :

1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device

7) IDD current measure method and detail patterns are described on DDR3 component datasheet

8) VDD and VDDQ are merged on module PCB.

9) DIMM IDD SPEC is measured with Qoff condition

(IDDQ values are not considered)

datasheet DDR3L SDRAM

- 26 -

Page 24

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

16. IDD SPEC Table

M378B5173EB0 : 4GB(512Mx64) Module

DDR3-1600 DDR3-1866

Symbol

11-11-11 11-11-11 13-13-13 13-13-13

IDD0 200 230 350 240 mA

IDD1 280 320 470 360 mA

IDD2P0(slow exit) 60 90 180 90 mA

IDD2P1(fast exit) 60 90 180 90 mA

IDD2N 90 100 220 110 mA

IDD2Q 80 100 210 100 mA

IDD3P 80 90 180 90 mA

IDD3N 170 180 370 180 mA

IDD4R 510 570 730 640 mA

IDD4W 510 570 720 640 mA

IDD5B 1520 1600 1670 1600 mA

IDD6 100 120 240 120 mA

IDD7 970 1040 1190 1130 mA

IDD8 120 120 240 120 mA

NOTE :

1. DIMM IDD SPEC is based on the condition that de-actived rank(IDLE) is IDD2N. Please refer to Table 18.

2. IDD current measure method and detail patterns are described on DDR3 component datasheet.

3. VDD and VDDQ are merged on module PCB.

4. DIMM IDD SPEC is measured with Qoff condition. (IDDQ values are not considered)

Unit NOTE1.35V 1.5V 1.35V 1.5V

M378B1G73EB0 : 8GB(1Gx64) Module

DDR3-1600 DDR3-1866

Symbol

11-11-11 11-11-11 13-13-13 13-13-13

IDD0 290 330 240 360 mA

IDD1 370 420 360 470 mA

IDD2P0(slow exit) 130 180 90 180 mA

IDD2P1(fast exit) 130 180 90 180 mA

IDD2N 180 210 110 220 mA

IDD2Q 160 190 100 210 mA

IDD3P 160 180 90 180 mA

IDD3N 340 370 180 370 mA

IDD4R 600 670 620 750 mA

IDD4W 590 670 610 750 mA

IDD5B 1610 1700 1560 1710 mA

IDD6 190 240 120 240 mA

IDD7 1060 1140 1080 1240 mA

IDD8 240 240 120 240 mA

NOTE :

1. DIMM IDD SPEC is based on the condition that de-actived rank(IDLE) is IDD2N. Please refer to Table 18.

2. IDD current measure method and detail patterns are described on DDR3 component datasheet.

3. VDD and VDDQ are merged on module PCB.

4. DIMM IDD SPEC is measured with Qoff condition. (IDDQ values are not considered)

Unit NOTE1.35V 1.5V 1.35V 1.5V

- 27 -

Page 25

Rev. 1.1

Unbuffered DIMM

[ Table 18 ] DIMM Rank Status

SEC DIMM Operating Rank The other Rank

IDD0 IDD0

IDD1 IDD1

IDD2P0 IDD2P

IDD2N IDD2N

IDD2Q IDD2Q IDD2Q

IDD3P IDD3P IDD3P

IDD3N IDD3N IDD3N

IDD4R IDD4R

IDD4W IDD4W

IDD5B IDD5B

IDD6 IDD6

IDD7 IDD7

IDD8 IDD8

datasheet DDR3L SDRAM

IDD2N

IDD2P

IDD2N

IDD6

IDD2N

IDD8

- 28 -

Page 26

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

17. Input/Output Capacitance

Parameter Symbol

Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS)

Input capacitance (CK and CK)

Input capacitance delta (CK and CK)

Input capacitance (All other input-only pins)

Input/Output capacitance delta (DQS and DQS)

Input capacitance delta (All control input-only pins)

Input capacitance delta (all ADD and CMD input-only pins)

Input/output capacitance delta (DQ, DM, DQS, DQS, TDQS, TDQS)

Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 - 3 pF 2, 3, 12

Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS)

Input capacitance (CK and CK)

Input capacitance delta (CK and CK)

Input capacitance (All other input-only pins)

Input capacitance delta (DQS and DQS)

Input capacitance delta (All control input-only pins)

Input capacitance delta (all ADD and CMD input-only pins)

Input/output capacitance delta (DQ, DM, DQS, DQS, TDQS, TDQS)

Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 - 3 pF 2, 3, 12

[ Table 19 ] Input/Output Capacitance

NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance.

1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS

2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with

, V

, VSS, V

DDQ

die termination off.

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value of CCK-CCK

5. Absolute value of CIO(DQS)-CIO(DQS)

6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.

7. CDI_CTRL applies to ODT, CS and CKE

8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))

9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE

10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))

11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))

12. Maximum external load capacitance on ZQ pin: 5pF

applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=V

SSQ

CIO 1.4 2.5 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.0 pF 1,2,3

CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.4 pF 2,3

CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4

CI 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF 2,3,6

CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 pF 2,3,5

CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8

CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10

CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11

CIO 1.4 3.0 1.4 2.7 1.4 2.5 1.4 2.3 1.4 2.2 pF 1,2,3

CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 pF 2,3

CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4

CI 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 pF 2,3,6

CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 pF 2,3,5

CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8

CDI_ADD_CMD -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10

CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Min Max Min Max Min Max Min Max Min Max

1.35V

1.5V

=1.5V or 1.35V, V

DDQ

Units NOTE

/2 and on-

BIAS=VDD

- 29 -

Page 27

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

18. Electrical Characteristics and AC timing

[0 C<T

18.1 Refresh Parameters by Device Density

All Bank Refresh to active/refresh cmd time tRFC 110 160 260 350 ns

Average periodic refresh interval tREFI

NOTE :

1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material.

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Parameter min min min min min

95 C, V

CASE

Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units NOTE

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

CL 6 791113tCK

tRCD 15 13.13 13.5 13.75 13.91 ns

tRP 15 13.13 13.5 13.75 13.91 ns

tRAS 37.5 37.5 36 35 34 ns

tRC 52.5 50.63 49.5 48.75 47.91 ns

tRRD 10 7.5 6.0 6.0 5.0 ns

tFAW 40 37.5 30 30 27 ns

= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V); VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)]

DDQ

0CT

85CT

CASE

 85C

 95C

7.8 7.8 7.8 7.8 s

3.9 3.9 3.9 3.9 s 1

Units NOTEBin (CL - tRCD - tRP) 6-6-6 7-7-7 9-9-9 11-11-11 13-13-13

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

[ Table 20 ] DDR3-800 Speed Bins

Speed DDR3-800

Units NOTECL-nRCD-nRP 6 - 6 - 6

Parameter Symbol min max

Internal read command to first data tAA 15 20 ns

ACT to internal read or write delay time tRCD 15 - ns

PRE command period tRP 15 - ns

ACT to ACT or REF command period tRC 52.5 - ns

ACT to PRE command period tRAS 37.5 9*tREFI ns

CL = 6 / CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3

Supported CL Settings 6 nCK

Supported CWL Settings 5 nCK

- 30 -

Page 28

Rev. 1.1

Unbuffered DIMM

[ Table 21 ] DDR3-1066 Speed Bins

Speed DDR3-1066

Parameter Symbol min max

Internal read command to first data tAA 13.125 20 ns

ACT to internal read or write delay time tRCD 13.125 - ns

PRE command period tRP 13.125 - ns

ACT to ACT or REF command period tRC 50.625 - ns

ACT to PRE command period tRAS 37.5 9*tREFI ns

CL = 6

CL = 7

CL = 8

Supported CL Settings 6,7,8 nCK

Supported CWL Settings 5,6 nCK

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,5

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,8

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3

datasheet DDR3L SDRAM

Units NOTECL-nRCD-nRP 7 - 7 - 7

[ Table 22 ] DDR3-1333 Speed Bins

Speed DDR3-1333

Units NOTECL-nRCD-nRP 9 -9 - 9

Parameter Symbol min max

Internal read command to first data tAA 13.5 (13.125)

ACT to internal read or write delay time tRCD 13.5 (13.125)

PRE command period tRP 13.5 (13.125)

ACT to ACT or REF command period tRC 49.5 (49.125)

ACT to PRE command period tRAS 36 9*tREFI ns

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6

CL = 6

CL = 7

CL = 8

CL = 9

CL = 10

Supported CL Settings 6,7,8,9,10 nCK

Supported CWL Settings 5,6,7 nCK

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,6

CWL = 7 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,6

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,6

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,8

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3

20 ns

- ns

- 31 -

Page 29

Rev. 1.1

Unbuffered DIMM

[ Table 23 ] DDR3-1600 Speed Bins

Speed DDR3-1600

Parameter Symbol min max

Intermal read command to first data tAA

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to ACT or REF command period tRC

ACT to PRE command period tRAS 35 9*tREFI ns

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7

CL = 6

CL = 7

CL = 8

CL = 9

CL = 10

CL = 11

Supported CL Settings 6,7,8,9,10,11 nCK

Supported CWL Settings 5,6,7,8 nCK

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7

CWL = 7, 8 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,7

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7

CWL = 8 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,7

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,7

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,7

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,7

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6,7 tCK(AVG) Reserved ns 4

CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,8

datasheet DDR3L SDRAM

Units NOTECL-nRCD-nRP 11-11-11

13.75

(13.125)

13.75

(13.125)

13.75

(13.125)

48.75

(48.125)

20 ns

- ns

- 32 -

Page 30

Rev. 1.1

Unbuffered DIMM

[ Table 24 ] DDR3-1866 Speed Bins

Speed DDR3-1866

Parameter Symbol min max

Internal read command to first data tAA

ACT to internal read or write delay time tRCD

PRE command period tRP

ACT to ACT or REF command period tRC

ACT to PRE command period tRAS 34 9*tREFI ns

CL = 5

CL = 6

CL = 7

CL = 8

CL = 9

CL = 10

CL = 11

CL = 12

CL = 13

Supported CL Settings 5,6,7,8,9,10,11,13 nCK

Supported CWL Settings 5,6,7,8,9 nCK

CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,8

CWL = 6,7,8,9 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,8

CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 7,8,9 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 2.5 ns 1,2,3,4,8

CWL = 7,8,9 tCK(AVG) Reserved ns 4

CWL = 5 tCK(AVG) Reserved ns 4

CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,8

CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 8,9 tCK(AVG) Reserved ns 4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 1.875 ns 1,2,3,4,8

CWL = 8 tCK(AVG) Reserved ns 4

CWL = 9 tCK(AVG) Reserved ns 4

CWL = 5,6 tCK(AVG) Reserved ns 4

CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,8

CWL = 8 tCK(AVG) Reserved ns 1,2,3,4,8

CWL = 5,6,7 tCK(AVG) Reserved ns 4

CWL = 8 tCK(AVG) 1.25 1.5 ns 1,2,3,4,8

CWL = 9 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6,7,8 tCK(AVG) Reserved ns 4

CWL = 9 tCK(AVG) Reserved ns 1,2,3,4

CWL = 5,6,7,8 tCK(AVG) Reserved ns 4

CWL = 9 tCK(AVG) 1.071 <1.25 ns 1,2,3,10

datasheet DDR3L SDRAM

Units NOTECL-nRCD-nRP 13-13-13

13.91

(13.125)

13.91

(13.125)

13.91

(13.125)

47.91

(47.125)

20 ns

- ns

- 33 -

Page 31

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

18.3.1 Speed Bin Table Notes

Absolute Specification [T

NOTE :

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements

from CL setting as well as requirements from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-

anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "Supported CL".

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or

1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.

4. "Reserved" settings are not allowed. User must program a different value.

5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

9. Any DDR3-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

10. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,

DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte

20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte

18), and tRPmin (Byte 20). DDR3-1866(CL13) devices supporting downshift to DDR3-1600(CL11) or DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-2133(CL14) devices supporting downshift to DDR3-1866(CL13) or DDR3-1600(CL11) or DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and

48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).

11. DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.

12. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.

13. For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting must be programed to match. For example,

DDR3-1866 devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for tAAmin(byte16), tRCDmin(Byte18) and tRPmin (byte20). Once tRP (Byte20) is programmed to 13.125ns, tRCmin (Byte21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin = 34ns + 13.125ns)

OPER

; V

= VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)];

DDQ

- 34 -

Page 32

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

19. Timing Parameters by Speed Grade

[ Table 25 ] Timing Parameters by Speed Bin(Cont.)

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

Average Clock Period tCK(avg) See Speed Bins Table ps

Clock Period tCK(abs)

Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)

Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)

Clock Period Jitter tJIT(per) -100 100 -90 90 -80 80 -70 70 -60 60 ps

Clock Period Jitter during DLL locking period tJIT(per, lck) -90 90 -80 80 -70 70 -60 60 -50 50 ps

Cycle to Cycle Period Jitter tJIT(cc) 200 180 160 140 120 ps

Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 180 160 140 120 100 ps

Cumulative error across 2 cycles tERR(2per) - 147 147 - 132 132 - 118 118 -103 103 -88 88 ps

Cumulative error across 3 cycles tERR(3per) - 175 175 - 157 157 - 140 140 -122 122 -105 105 ps

Cumulative error across 4 cycles tERR(4per) - 194 194 - 175 175 - 155 155 -136 136 -117 117 ps

Cumulative error across 5 cycles tERR(5per) - 209 209 - 188 188 - 168 168 -147 147 -126 126 ps

Cumulative error across 6 cycles tERR(6per) - 222 222 - 200 200 - 177 177 -155 155 -133 133 ps

Cumulative error across 7 cycles tERR(7per) - 232 232 - 209 209 - 186 186 -163 163 -139 139 ps

Cumulative error across 8 cycles tERR(8per) - 241 241 - 217 217 - 193 193 -169 169 -145 145 ps

Cumulative error across 9 cycles tERR(9per) - 249 249 - 224 224 - 200 200 -175 175 -150 150 ps

Cumulative error across 10 cycles tERR(10per) - 257 257 - 231 231 - 205 205 -180 180 -154 154 ps

Cumulative error across 11 cycles tERR(11per) - 263 263 - 237 237 - 210 210 -184 184 -158 158 ps

Cumulative error across 12 cycles tERR(12per) - 269 269 - 242 242 - 215 215 -188 188 -161 161 ps

Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper)

Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - 0.43 - 0.43 - 0.43 - tCK(avg) 25

Absolute clock Low pulse width tCL(abs) 0.43 - 0.43 - 0.43 - 0.43 - 0.43 - tCK(avg) 26

Data Timing

DQS,DQS to DQ skew, per group, per access tDQSQ - 200 - 150 - 125 - 100 - 85 ps 13

DQ output hold time from DQS, DQS tQH 0.38 - 0.38 - 0.38 - 0.38 - 0.38 - tCK(avg) 13, g

DQ low-impedance time from CK, CK tLZ(DQ) -800 400 -600 300 -500 250 -450 225 -390 195 ps 13,14, f

DQ high-impedance time from CK, CK tHZ(DQ) - 400 - 300 - 250 - 225 - 195 ps 13,14, f

Data setup time to DQS, DQS referenced to

(AC)VIL(AC) levels

Data hold time from DQS, DQS referenced to

(DC)VIL(DC) levels

DQ and DM Input pulse width for each input tDIPW 600

tCK(DLL_OF

tDS(base)

AC160

tDS(base)

AC135

tDS(base)

AC125

tDS(base)

AC175

tDS(base)

AC150

tDS(base)

AC135

tDH(base)

DC90

tDH(base)

DC100

8 - 8 - 8 - 8 - 8 - ns 6

tCK(avg)mi

n +

tJIT(per)min

140

125

160

150

tCK(avg)ma

x +

tJIT(per)ma

tCK(avg)ma

tCK(avg)mi

tJIT(per)min

110

100

490

x +

n +

tJIT(per)ma

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max

tCK(avg)ma

tCK(avg)mi

n +

tJIT(per)ma

tJIT(per)min

1.35V

------psd, 17

45 - 25 - - - ps d, 17

- - - - 10 - ps d, 17

1.5V

- - - - - - ps d, 17

30 - 10 - - - ps d, 17

- - - - 68 - ps d, 17

1.35V

75 - 55 - 30 - ps d, 17

1.5V

65 - 45 - 20 - ps d, 17

400

x +

tCK(avg)mi

n +

tJIT(per)min

360

tCK(avg)ma

x +

tJIT(per)ma

tCK(avg)mi

n +

tJIT(per)min

320

tCK(avg)ma

tJIT(per)ma

x +

Units NOTE

ps 24

ps 28

- 35 -

Page 33

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

[ Table 25 ] Timing Parameters by Speed Bin (Cont.)

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Data Strobe Timing

DQS, DQS differential READ Preamble tRPRE 0.9 Note 19 0.9 Note 19 0.9 Note 19 0.9 Note 19 0.9 NOTE 19 tCK(avg) 13, 19, g

DQS, DQS differential READ Postamble tRPST 0.3 Note 11 0.3 Note 11 0.3 Note 11 0.3 Note 11 0.3 NOTE 11 tCK(avg) 11, 13, b

DQS, DQS differential output high time tQSH 0.38 - 0.38 - 0.4 - 0.4 - 0.4 - tCK(avg) 13, g

DQS, DQS differential output low time tQSL 0.38 - 0.38 - 0.4 - 0.4 - 0.4 - tCK(avg) 13, g

DQS, DQS differential WRITE Preamble tWPRE 0.9 - 0.9 - 0.9 - 0.9 - 0.9 - tCK(avg)

DQS, DQS differential WRITE Postamble tWPST 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - tCK(avg)

DQS, DQS rising edge output access time from rising

CK,

DQS, DQS low-impedance time (Referenced from RL-

DQS, DQS high-impedance time (Referenced from RL+BL/2)

DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) 29, 31

DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) 30, 31

DQS, DQS rising edge to CK, CK rising edge tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 -0.27 0.27 -0.27 0.27 tCK(avg) c

DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.2 - 0.2 - 0.2 - 0.18 - 0.18 - tCK(avg) c, 32

DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.2 - 0.2 - 0.2 - 0.18 - 0.18 - tCK(avg) c, 32

Command and Address Timing

DLL locking time tDLLK 512 - 512 - 512 - 512 - 512 - nCK

internal READ Command to PRECHARGE Command delay

Delay from start of internal write transaction to internal read command

WRITE recovery time tWR 15 - 15 - 15 - 15 - 15 - ns e

Mode Register Set command cycle time tMRD 4 - 4 - 4 - 4 - 4 - nCK

Mode Register Set command update delay tMOD

CAS to CAS command delay tCCD 4 - 4 - 4 - 4 - 4 - nCK

Auto precharge write recovery + precharge time tDAL(min) WR + roundup (tRP / tCK(AVG)) nCK

Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - 1 - 1 - nCK 22

ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” ns e

ACTIVE to ACTIVE command period for 1KB page size tRRD

ACTIVE to ACTIVE command period for 2KB page size tRRD

Four activate window for 1KB page size tFAW 40 - 37.5 - 30 - 30 - 27 - ns e

Four activate window for 2KB page size tFAW 50 - 50 - 45 - 40 - 35 - ns e

Command and Address setup time to CK, CK referenced to V

(AC) / VIL(AC) levels

tDQSCK -400 400 -300 300 -255 255 -225 225 -195 195 ps 13,f

tLZ(DQS) -800 400 -600 300 -500 250 -450 225 -390 195 ps 13,14,f

tHZ(DQS) - 400 - 300 - 250 - 225 - 195 ps 12,13,14

tRTP

tWTR

tIS(base)

AC160

tIS(base)

AC135

tIS(base)

AC125

tIS(base)

AC175

tIS(base)

AC150

tIS(base)

AC135

tIS(base)

AC125

max

(4nCK,7.5

ns)

max

(4nCK,7.5

ns)

max

(12nCK,15

ns)

max

(4nCK,10n

max

(4nCK,10n

215

365

- - - - - - - -

200

350

max

(4nCK,7.5

ns)

max

(4nCK,7.5

ns)

max

(12nCK,15

ns)

max

(4nCK,7.5

ns)

max

(4nCK,10n

140

290

125

275

max

(4nCK,7.5n

max

(4nCK,7.5n

max

(12nCK,15

ns)

max

(4nCK,6ns)

max

(4nCK,7.5n

1.35V

80 - 60 - - - ps b,16

205 - 185 - - - ps b,16,27

1.5V

65 - 45 - - - ps b,16

190 - 170 - - - ps b,16,27

- - - - 65 - ps b,16

- - - - 150

max

(4nCK,7.5

ns)

max

(4nCK,7.5

ns)

max

(12nCK,15

ns)

max

(4nCK,6ns

)

max

(4nCK,7.5

ns)

max

(4nCK,7.5

ns)

max

(4nCK,7.5

ns)

max

(12nCK,15

ns)

max

(4nCK,

5ns)

max

(4nCK,

6ns)

75 - ps b,16,27

Units NOTE

- e

- e,18

- e

ps b,16,27

- 36 -

Page 34

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

[ Table 25 ] Timing Parameters by Speed Bin(Cont.)

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Command and Address Timing

1.35V

tIH(base)

Command and Address hold time from CK, CK referenced to V

Control & Address Input pulse width for each input tIPW 900

Calibration Timing

Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - 512 -

Normal operation Full calibration time tZQoper 256 - 256 - 256 - 256 -

Normal operation short calibration time tZQCS 64 - 64 - 64 - 64 -

Reset Timing

Exit Reset from CKE HIGH to a valid command tXPR

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE)

Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL

CKE minimum pulse width tCKE

Command pass disable delay tCPDED 1 - 1 - 1 - 1 - 2 - nCK

Power Down Entry to Exit Timing tPD

Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - 1 - 1 - 1 - nCK 20

Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - 1 - 1 - 1 - nCK 20

Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 - RL + 4 +1 - RL + 4 +1 - RL + 4 +1 - RL + 4 +1 -

Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF)

Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF)

Timing of WR command to Power Down entry (BC4MRS)

Timing of WRA command to Power Down entry (BC4MRS)

Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 1 - 1 - 1 - 20,21

Timing of MRS command to Power Down entry tMRSPDEN

ODT Timing

ODT high time without write command or with write command and BC4

ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - 6 - 6 - nCK

(DC) / VIL(DC) levels

DC90

tIH(base)

DC100

tXS

tXSDLL

tCKESR

tCKSRE

tCKSRX

tXP

tXPDLL

tWRPDEN

tWRAPDEN

tWRPDEN

tWRAPDEN

ODTH4 4 - 4 - 4 - 4 - 4 - nCK

285

275 200 140 120 - 100 - ps b,16

max(5nC

K, tRFC +

10ns)

max(5nC K,tRFC +

10ns)

tDLLK(mi

tCKE(min

) + 1tCK

max(5nC

10ns)

max(5nC

10ns)

max

(3nCK,

7.5ns)

max

(10nCK,

24ns)

max

(3nCK,

7.5ns)

tCKE(min

tCK(avg))

+WR +1

tCK(avg))

+WR +1

tMOD(mi

)

WL + 4 +(tWR/

WL + 4

WL + 2 +(tWR/

WL +2

9*tREFI

210

780

max(5nC

K, tRFC +

10ns)

max(5nC K,tRFC +

10ns)

tDLLK(mi

tCKE(min

) + 1tCK

max(5nC

10ns)

max(5nC

10ns)

max

(3nCK,

7.5ns)

max

(10nCK,

24ns)

max

(3nCK,

5.625ns)

tCKE(min

)

WL + 4

+(tWR/

tCK(avg))

WL + 4

+WR +1

WL + 2

+(tWR/

tCK(avg))

WL +2

+WR +1

tMOD(mi

9*tREFI

150 - 130 - 110 - ps b,16

1.5V

620

max(5nC

K, tRFC +

10ns)

max(5nC K,tRFC +

10ns)

tDLLK(mi

tCKE(min

) + 1tCK

max(5nC

10ns)

max(5nC

10ns)

max

(3nCK,6n

max

(10nCK,

24ns)

max

(3nCK,

5.625ns)

tCKE(min

)

WL + 4 +(tWR/

tCK(avg))

WL + 4

+WR +1

WL + 2 +(tWR/

tCK(avg))

WL +2

+WR +1

tMOD(mi

9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK(avg) 15

560

max(5nC

K, tRFC +

10ns)

max(5nC

K,tRFC +

10ns)

tDLLK(mi

tCKE(min)

+ 1tCK

max(5nC

10ns)

max(5nC

10ns)

max

(3nCK,6n

max

(10nCK,

24ns)

max

(3nCK,5n

WL + 4 +(tWR/

tCK(avg))

WL + 4

+WR +1

WL + 2 +(tWR/

tCK(avg))

WL +2

+WR +1

tMOD(min

)

535

max(512n CK,640ns

)

max(256n CK,320ns

)

max(64nC

K,80ns)

max(5nC

tRFC(min)

+ 10ns)

max(5nC

K,tRFC(m

in) + 10ns)

tDLLK(mi

tCKE(min)

+ 1nCK

max(5nC

10ns)

max(5nC

10ns)

max(3nC

K,6ns)

max(10nC

K,24ns)

max(3nC

K,5ns)

WL + 4 +(tWR/

tCK(avg))

WL + 4

+WR +1

WL + 2 +(tWR/

tCK(avg))

WL +2

+WR +1

tMOD(min

)

Units NOTE

ps 28

- nCK

- nCK 23

- nCK

- 2

- nCK 9

- nCK 10

- nCK 9

- nCK 10

- 37 -

Page 35

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

[ Table 25 ] Timing Parameters by Speed Bin

Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

ODT Timing

Asynchronous RTT turn-on delay (Power-Down with DLL frozen)

Asynchronous RTT turn-off delay (Power-Down with DLL frozen)

RTT turn-on tAON -400 400 -300 300 -250 250 -225 225 -195 195 ps 7,f

RTT_NOM and RTT_WR turn-off time from ODTLoff reference

RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) f

Write Leveling Timing

First DQS/DQS rising edge after write leveling mode is programmed

DQS/DQS delay after write leveling mode is programmed

Write leveling setup time from rising CK, CK crossing to rising DQS,

Write leveling hold time from rising DQS, DQS crossing to rising CK,

Write leveling output delay tWLO 0 9 0 9 0 9 0 7.5 0 7.5 ns

Write leveling output error tWLOE 0 2 0 2 0 2 0 2 0 2 ns

DQS crossing

CK crossing

tAONPD 2 8.5 2 8.5 2 8.5 2 8.5 2 8.5 ns

tAOFPD 2 8.5 2 8.5 2 8.5 2 8.5 2 8.5 ns

tAOF 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) 8,f

tWLMRD 40 - 40 - 40 - 40 - 40 - tCK(avg) 3

tWLDQSEN 25 - 25 - 25 - 25 - 25 - tCK(avg) 3

tWLS 325 - 245 - 195 - 165 - 140 - ps

tWLH 325 - 245 - 195 - 165 - 140 - ps

Units NOTE

- 38 -

Page 36

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

19.1 Jitter Notes

Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the

input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.

Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition

edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not.

Specific Note c These parameters are measured from a data strobe signal (DQS, DQS) crossing to its respective clock signal (CK, CK) crossing.

The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the

clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.

Specific Note d These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal

(DQS, DQS) crossing.

Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.

Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input

clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!) Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.

Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input

clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/ max usage!)

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Page 37

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

19.2 Timing Parameter Notes

1. Actual value dependant upon measurement level definitions which are TBD.

2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register

5. Value must be rounded-up to next higher integer value

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"

8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10. WR in clock cycles as programmed in MR0

11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing Diagram Datasheet.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated

by TBD

13. Value is only valid for RON34

14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.

15. tREFI depends on T

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,

(DC) = V

REF

See "Address/Command Setup, Hold and Derating" on component datasheet.

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS,

(DC)= V

REF

See "Data Setup, Hold and Slew Rate Derating" on component datasheet.

18. Start of internal write transaction is defined as follows ;

For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL

19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram Data-

sheet"

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down

IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time

such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming

the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-

ject to in the application, is illustrated. The interval could be defined by the following formula:

OPER

DQ(DC). For input only pins except RESET, V

REF

DQ(DC). For input only pins except RESET, V

REF

(DC)=V

REF

CA(DC).

DQS differential slew rate. Note for DQ and DM signals,

CA(DC).

ZQCorrection

(TSens x Tdriftrate) + (VSens x Vdriftrate)

where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if TSens = 1.5% /C, VSens = 0.15% / mV, Tdriftrate = 1C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as:

0.5

(1.5 x 1) + (0.15 x 15)

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-

nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].

28. Pulse width of a input signal is defined as the width between the first crossing of V

29. tDQSL describes the instantaneous differential input low pulse width on DQS-

30. tDQSH describes the instantaneous differential input high pulse width on DQS-

31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

= 0.133

DQS, as measured from one falling edge to the next consecutive rising edge.

DQS, as measured from one rising edge to the next consecutive falling edge.

128ms

(DC) and the consecutive crossing of V

REF

(DC)

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Page 38

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

20. Physical Dimensions

20.1 512Mbx8 based 512Mx64 Module (1 Rank) - M378B5173EB0

133.35

128.95

SPD

54.675

Units : Millimeters

Max 2.70

30.00

1.270 ± 0.10

47.00

71.00

2.50

5.00

1.50±0.10

Detail A

2.50 ± 0.20

3.80

Detail B

0.80 ± 0.05

0.2

1.00

The used device is 512M x8 DDR3L SDRAM, Flip-Chip. DDR3 SDRAM Part NO : K4B4G0846E-BY

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

- 41 -

Page 39

Rev. 1.1

Unbuffered DIMM

datasheet DDR3L SDRAM

20.2 512Mbx8 based 1Gx64 Module (2 Ranks) - M378B1G73EB0

133.35

128.95

SPD

54.675

Units : Millimeters

Max 4.0

30.00

1.270 ± 0.10

47.00

71.00

2.50

5.00

1.50±0.10

Detail A

2.50 ± 0.20

3.80

Detail B

0.80 ± 0.05

0.2

1.00

The used device is 512M x8 DDR3L SDRAM, Flip-Chip. DDR3 SDRAM Part NO : K4B4G0846E-BY

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

- 42 -

Samsung M378B5173EB0-CK0 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. DDR3L Unbuffered DIMM Ordering Information

2. Key Features

3. Address Configuration

4. x64 DIMM Pin Configurations (Front side/Back side)

5. Pin Description

6. SPD and Thermal Sensor for ECC UDIMMs

7. Input/Output Functional Description

7.1 Address Mirroring Feature

7.1.1 DRAM Pin Wiring Mirroring

8. Function Block Diagram:

8.1 4GB, 512Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)

8.2 8GB, 1Gx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

11. Absolute Maximum Ratings

11.1 Absolute Maximum DC Ratings

11.2 DRAM Component Operating Temperature Range

12. AC & DC Operating Conditions

12.1 Recommended DC Operating Conditions

13. AC & DC Input Measurement Levels

13.1 AC & DC Logic Input Levels for Single-ended Signals

13.3 AC and DC Logic Input Levels for Differential Signals

13.3.1 Differential Signals Definition

13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

13.3.3 Single-ended Requirements for Differential Signals

13.3.4 Differential Input Cross Point Voltage

13.4 Slew Rate Definition for Single Ended Input Signals

13.5 Slew rate definition for Differential Input Signals

14. AC & DC Output Measurement Levels

14.1 Single Ended AC and DC Output Levels

14.2 Differential AC and DC Output Levels

14.3 Single-ended Output Slew Rate

14.4 Differential Output Slew Rate

15. IDD specification definition

16. IDD SPEC Table

17. Input/Output Capacitance

18. Electrical Characteristics and AC timing

18.1 Refresh Parameters by Device Density

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

18.3.1 Speed Bin Table Notes

19. Timing Parameters by Speed Grade

19.1 Jitter Notes

19.2 Timing Parameter Notes

20. Physical Dimensions

20.1 512Mbx8 based 512Mx64 Module (1 Rank) - M378B5173EB0

20.2 512Mbx8 based 1Gx64 Module (2 Ranks) - M378B1G73EB0