Samsung KT8555J Datasheet

KT8555 TIME SLOT ASSIGNMENT CIRCUIT

ORDERING INFORMATION

INTRODUCTION

The KT8555 is a per channel Time Slot Assignment Circuit
(TSAC) that produces 8-bit receive and transmit time slots for
four 1 CHIP CODEC.
Each frame synchronization pulse may be independently
assigned to a time slot in a frame of up to 84 time slots.

FEATURES

l Single, 5V operation
l Low power consumption: 5mW
l Controls four 1 CHIP CODEC
l Independent transmit and receive frame syncs

enables

l channel unidirectional mode
l Up to 64 time slots per frame
l Compatible with KT8554/7 CODECs
l TTL and CMOS compatible

PIN CONFIGURATION

FSX1

1

20-CERDIP

Device Package Operating Temperature

KT8555J 20-CERDIP

V

20

CC

- 20°C ~ + 125°C

FSR1

2

FSX0

3

FSR0

4

TS

D

CLK

CS

MODE

GND

KT8555

5

X

6

C

7

C

8

9

Fig. 1

19

18

17

16

15

14

13

12

1110

FSR2

FSX2

FSR3

FSX3

CH0

CH1

RSYC/CH2

XSY

C

BCLK

KT8555 TIME SLOT ASSIGNMENT CIRCUIT

PIN DESCRIPTION

Pin No Symbol Description

3

1
18
16

4

2
19
17

5 TS

6 D

7 CLK

8 CS The active-low chip select for the control interface.

9 MODE
10 GND Ground

11 BCLK The bit clock input (2.048 MHz)
12 XSY

13 RSYC /CH2

14 CH1 The input for the NSB (next significant bit) of the channel select word.

15 CH0
20 V

FSX0
FSX1
FSX2
FSX3
FSR0
FSR1
FSR2
FSR3

CC

A frame sync output which is normally low, and goes active-high for 8 cycles of
BCLK when a valid transmit time slot assignment is made.

A frame sync output which is normally low, and goes active-high for 8 cycles of
BCLK when a valid receive time slot assignment is made.

X

C

C

C

This pin pulls low during any active transmit time slot. (N-channel open drain)
The input for an 8 bit serial control word. X is the first bit clocked in.
The clock input for the control interface.

Mode 1 = Open or V
Mode 2 = Gnd

CC

The transmit TSO sync pulse input. Must be synchronous with BCLK.
The transmit time slot 0 sync pulse input. Must be synchronous with BCLK.
In mode 1 this input is the receive time slot 0 sync pulse, RSYC, which must be
synchronous with BCLK. In mode 2 this is the CH2 input for the MSB of the
channel select word.

The input for the LSB (last significant bit) of the channel select word,
which defines the frame sync output affected by the following control word.

Power supply pin. 5V ±5%

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)

Characteristic Symbol Value Unit

Positive Supply Voltage
Input Voltage
Output Voltage
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 secs)

V

CC

V

I

V

O

T

OPR

T

STG

T

LEAD

V

+ 0.3 ~ - 0.3

CC

V

+ 0.3 ~ - 0.3

CC

- 25 ~ 125

- 65 ~ 150

7.0

300

V
V
V

°C
°C
°C