Richtek RT8209A, RT8209B, RT8209C Datasheet

Single Synchronous Buck Controller

RT8209A/B/C

General Description

The RT8209A/B/C PWM controller provides high efficiency,

excellent transient response, and high DC output accuracy

needed for stepping down high voltage batteries to

generate low voltage CPU core, I/O, and chipset RAM

supplies in notebook computers.

The constant-on-time PWM control scheme handles wide

input/output voltage ratios with ease and provides 100ns

“instant-on” response to load transients while maintaining

a relatively constant switching frequency.

The RT8209A/B/C achieves high efficiency at a reduced

cost by eliminating the current-sense resistor found in

traditional current mode PWMs. Efficiency is further

enhanced by its ability to drive very large synchronous

rectifier MOSFETs. The buck conversion allows this device

to directly step down high voltage batteries for the highest

possible efficiency. The RT8209A/B/C is intended for CPU

core, chipset, DRAM, or other low voltage supplies as

low as 0.75V. The RT8209A is in a WQFN-16L 3x3

package, the RT8209B is in a WQFN-14L 3.5x3.5 package

and the RT8209C is available in a TSSOP-14 package.

Ordering Information

RT8209

Package Type
QW : WQFN-16L 3x3 (W-Type)
QW : WQFN-14L 3.5x3.5 (W-Type)
C : TSSOP-14

Operating Temperature Range
G : Green (Halogen Free with Commer­ cial Standard)

A : WQFN-16L 3x3
B : WQFN-14L 3.5x3.5
C : TSSOP-14

Features

zz

Ultra-High Efficiency

z

zz

zz

z Resistor Programmable Current Limit by Low Side

zz

R

zz

z Quick Load Step Response within 100ns

zz

zz

z 1% V

zz

zz

z 4.5V to 26V Battery Input Range

zz

zz

z Resistor Programmable Frequency

zz

zz

z Integrated Bootstrap Switch

zz

zz

z Integrated Negative Current Limiter

zz

zz

z Over/Under Voltage Protection

zz

zz

z 4 Steps Current Limit During Soft-Start

zz

zz

z Power Good Indicator

zz

zz

z RoHS Compliant and Halogen Free

zz

Sense (Lossless Limit)

DS(ON)

Accuracy over Line and Load

FB

Applications

z Notebook Computers

z System Power Supplies

z I/O Supplies

Marking Information

For marking information, contact our sales representative

directly or through a Richtek distributor located in your

area, otherwise visit our website for detail.

Note :

Richtek Green products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

DS8209A/B/C-03 April 2010 www.richtek.com

1

RT8209A/B/C

Pin Configurations

TON

EN/DEM

BOOT

NC

13141516

NC

GND

12

UGATE

11

PHASE

10

CS

17

9

VDDP

8765

PGND

LGATE

R

2

R

T

8

2

O

N

T

D

V

D

P

1

R

0

1

2

R

0

1

0

k

2

C

1

µ

F

R

1

8

D

D

V

O

O

D

G

P

C

S

6

k

1

VOUT

2

VDD

3

FB

PGOOD

4

NC

RT8209A (WQFN-16L 3x3)

Typical Application Circuit

P

D

D

V

D

P

O

O

G

(TOP VIEW)

EN/DEM

BOOT

141

NC

R

R

13

UGATE

12

PHASE

11

CS

15

10

VDDP

96

87

PGND

4

0

C

5

0

3

µ

F

1

0

.

C

1

B

S

1

0

9

3

N

2

TON

3

VOUT

4

VDD

5

FB

PGOOD LGATE

GND

RT8209B (WQFN-14L 3.5x3.5)

T

O

N

5

k

0

0

9

A

C

/

B

/

O

B

O

T

U

T

E

G

A

P

S

E

H

A

A

L

G

T

E

N

D

P

G

F

B

14

EN/DEM

TON

VOUT

VDD

FB

PGOOD

GND

2

3

4

5

6

7

BOOT

13

UGATE

12

PHASE

11

CS

10

VDDP

9

LGATE

8

PGND

RT8209C (TSSOP-14)

V

I

N

5

.

4

o

t

2

V

6

V

C

4

1

µ

F

0

1

Q

B

S

C

1

1

L

9

1

1

µ

N

0

3

S

S

Q

2

H

7

*

R

C

7

*

*

R

8

1

2

k

R

9

3

0

k

V

1

.

=

0

V

O

p

t

O

:

o

a

i

n

l

*

C

5

C

6

*

5

U

T

C

1

2

2

0

µ

F

/

E

D

C

M

M

C

EN/DEM

G

Functional Pin Description

Pin No.

RT8209A RT8209B/C

1 3 VOUT

2 4 VDD

3 5 FB

4 6 PGOOD

5, 14

17 (Exposed pad)

RT 8209B :

15 (Exposed pa d)

O

U

V

T

D

N

Pin Name Pin Function

Outpu t Vo lta ge Pin. Conne ct to the o utpu t of PWM converter.
VOUT is an inpu t of the PW M cont roller.

Analog sup ply voltage input for the interna l anal og inte grated
circuit. Bypass to GND with a 1 μF ceramic c apacitor.

Feed back In put Pin. C onnect FB to a resistor voltage divider
from VOUT to GND to adjust VOUT from 0.7 5V to 3. 3V
Power goo d s ignal open-drain output of PWM converte r. This
pin will be pulled h igh when the output voltage is within the
targe t range.
No interna l connecti on. The e xposed pad must b e soldered to

NC

a large PCB and conne cted to GND for maximum power
dissipation.

To be continued

DS8209A/B/C-03 April 2010www.richtek.com

2

RT8209A/B/C

Pin No.

Pin Na me Pin Function

RT8209A RT8209B/C

6 7 GND Analog Ground.

7 8 PGND Power Ground.

8 9 LGATE

9 10 VDDP

Low side N-MOSFET gate driver output for PWM. This pin
swings between GND and VDDP.

VDDP is the gate driver supply for external MOSFETs. Bypass
to GND wi th a 1μF ceramic capacitor.

Over Current Trip Point Set Input. Connect resistor from this

10 1 1 CS

pin to signal ground to set threshold for both over current and
negative over current limit.

11 12 PHASE

12 1 3 UGAT E

13 1 4 BOOT

The UGATE High Side Gate Driver Ret urn. Also serves as
anode of over current comparator.

High side N-MOSFET floating gate driver output for the PWM
converter. This pin swings between PHASE and BOOT.

Bootstrap Capacitor Connection for PWM Converter. Connect
to an external ceramic capacitor to PHASE.
Enable/Diode Emulation Mode Control Input. Connect to VDD

15 1 EN/D EM

for diode-emulation mode, connect to GND for shutdown and
floating the pin for CCM mode.

16 2 TON

On Time/Frequency Adjustment Pin. Connect to PHASE
through a resistor. TON is an input for the PWM controller.

Function Block Diagram

TRIG

-

GM

+

On-time

Compute

1-SHOT

+

-

+

-

+

-

SS Timer

VOUT

TON

FB

VDD

EN/DEM

SS

(internal)

V

REF

125% V

70% V

REF

REF

OV

UV

90% V

­+

Latch

S1 Q

Latch

S1 Q

REF

Thermal

Shutdown

BOOT

R

QS

Min. T

OFF

QTRIG

1-SHOT

­+

Diode

Emulation

+

-

-

+

GM

DRV

DRV

10µA

UGATE

PHASE

VDDP

LGATE

PGND

PGOOD

CS

GND

DS8209A/B/C-03 April 2010 www.richtek.com

3

RT8209A/B/C

Absolute Maximum Ratings (Note 1)

z VDD, VDDP, VOUT, EN/DEM, FB, PGOOD, TON to GND------------------------------------------------------- −0.3V to 6V
z BOOT to GND -------------------------------------------------------------------------------------------------------------- −0.3V to 38V

z BOOT to PHASE ---------------------------------------------------------------------------------------------------------- −0.3V to 6V

z PHASE to GND

DC----------------------------------------------------------------------------------------------------------------------------- –0.3V to 32V

< 20ns ----------------------------------------------------------------------------------------------------------------------- −8V to 38V

z UGATE to PHASE

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 20ns ----------------------------------------------------------------------------------------------------------------------- −5V to 7.5V

z CS to GND ------------------------------------------------------------------------------------------------------------------ −0.3V to 6V

z LGATE to GND ------------------------------------------------------------------------------------------------------------- −0.3V to 6V

z LGATE to GND

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 20ns ----------------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

z PGND to GND -------------------------------------------------------------------------------------------------------------- –0.3V to 0.3V

z Power Dissipation, P

D

WQFN−16L 3x3 ------------------------------------------------------------------------------------------------------------ 1.471W

WQFN−14L 3.5x3.5 ------------------------------------------------------------------------------------------------------- 1.667W

TSSOP-14 ------------------------------------------------------------------------------------------------------------------- 0.741W

z Package Thermal Resistance (Note 2)

WQFN−16L 3x3, θJA------------------------------------------------------------------------------------------------------ 68°C/W

WQFN−16L 3x3, θJC------------------------------------------------------------------------------------------------------ 7.5°C/W

WQFN−14L 3.5x3.5, θJA------------------------------------------------------------------------------------------------- 60°C/W

WQFN−14L 3.5x3.5, θJC------------------------------------------------------------------------------------------------- 7.5°C/W

TSSOP-14, θJA------------------------------------------------------------------------------------------------------------- 135°C/W

z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C

z Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
z Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Mode) ---------------------------------------------------------------------------------------------- 2kV

MM (Machine Mode) ------------------------------------------------------------------------------------------------------ 200V

@ T

= 25°C

A

Recommended Operating Conditions (Note 4)

z Input Voltage, V

z Supply Voltage, V

z Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C

z Ambient Temperature Range --------------------------------------------------------------------------------------------

4

---------------------------------------------------------------------------------------------------------- 4.5V to 26V

IN

, V

DD

---------------------------------------------------------------------------------------------- 4.5V to 5.5V

DDP

−40°C to 85°C

DS8209A/B/C-03 April 2010www.richtek.com

RT8209A/B/C

Electrical Characteristics

(V

= 15V, V

IN

PWM Controller

Quiescent Supply Current

Shutdown Current

FB Reference Voltage V
FB Input Bias Current VFB = 0.75V −1 0.1 1 μA
Output Voltage Range V

On Time

Minimum Off-Time 250 400 550 ns
VOUT Shutdown Discharge

Resistance

Current Sensing

Current Limiter Source Current CS to GND 9 10 11 μA
Curr en t C omparat or O ffset −10 -- 10 mV
Zer o Cr ossing Thr eshold PH AS E to GND , EN /D EM = 5V −10 -- 5 mV

Fa ul t Protection

Current Limit Threshold

Current Limit Setting Range CS to GND 50 -- 200 mV
Output UV Threshold UVP detect 60 70 80 %
OVP Threshold V
OV Fault Delay FB forced above OV threshold -- 20 -- μs

Threshold

Current Limit Step Duration at
Soft Start
UVP Blanking Time From EN signal going high -- 512 -- clks

Thermal Shutdown T

Driver On-Resista nce

= V

DD

= 5V, TA = 25°C, unless otherwise specified)

DDP

Parameter Symbol Test Conditions Min Typ Max Unit

I

V

VDD

I

V

VDDP

I

SHDN_VDD

I

SHDN_VDDP

REF

OUT

EN/DEM = 0V -- 1 10 μA

V

0.75 -- 3.3 V

= 0.8V, EN/DEM = 5V -- 500 800 μA

FB

= 0.8V, EN/DEM = 5V -- 1 10 μA

FB

EN/DEM = 0V -- -- 1 μA

= 4.5V to 5.5V 0.742 0.750 0.758 V

DD

V

PHASE

R

TON

= 12V, V

= 250kΩ

OUT

= 2.5V,

336 420 504 ns

EN/DEM = GND -- 20 -- Ω

GND − PHASE, VCS = 50mV 40 50 60 mV
GND − PHASE, V

FB_OVP

OVP detect 120 125 130 %

Rising edge, PWM disabled below
this level

= 200mV 190 200 210 mV

CS

4.1 4.3 4.5 V VDD Under Voltage Lockout

Hysteresis -- 80 -- mV

Each step -- 128 -- clks

Hysteresis = 10°C -- 155 -- °C

SHDN

UGATE Driver Pull-up V

UGATE Driver Sink V

BOOT

BOOT

− V

− V

= 5V -- 2 5 Ω

PHASE

= 5V -- 1 5 Ω

PHASE

LGATE Driver Pull-up LGATE, High State (Source) -- 1 5 Ω
LGATE Driver Pull-down LGATE, Low State (Sink) -- 0.5 2.5 Ω

UGATE Driver Source/Sink
Curr ent

LGATE Driver Source Current V

LGATE Driver Sink Current V

LGATE Rising (V

Dead Time

V

UGATE

V

BOOT

LGATE

LGATE

− V

− V

PHASE

PHASE

= 2.5V,

= 5V

-- 1 -- A

= 2.5V -- 1 -- A

= 2.5V -- 3 -- A

= 1.5V) -- 30 - - ns

PHASE

UGATE Rising -- 30 - - ns

To be continued

DS8209A/B/C-03 April 2010 www.richtek.com

5

RT8209A/B/C

Parameter Symbol Test Conditions Min Typ Max Unit

Internal BOOT Charging S witch
On Resistance

Logic I/O

EN/DEM Logic Input Voltage

Logic Input Current

PGOOD

PGOOD Th reshold

Fa ult Propag ation Delay

Out put Low Voltage I
Leakage Current High state, forced to 5V -- -- 1 μA

VDD P to BOOT, 10mA -- -- 80 Ω

EN/DEM Low -- -- 0.8 V

EN/DEM High 2.9 -- -- V

EN/DEM float -- 2 -- V

EN /DEM = VDD -- 1 5

μA

EN/DEM = 0 −5 1 --

with respect to referen ce,

V

FB

PGOOD from Low t o High
V

with respect to reference,

FB

PGOOD from High to Low

87 90 93 %

-- 125 -- %

Hysteresis -- 3 -- %

Fallin g ed ge, FB forced below
PGOOD trip threshold

= 1mA -- -- 0.4 V

SINK

-- 20 -- μs

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of

JA

JEDEC 51-7 thermal measurement standard. The case point of θ

is on the expose pad for the WQFN package.

JC

DS8209A/B/C-03 April 2010www.richtek.com

6

Typical Operating Characteristics

RT8209A/B/C

2.5V Efficiency vs. Load Current

100

DEM Mode

90

80

70

60

50

40

Efficiency (%)

30

CCM Mode

20

10

0

0.001 0.01 0.1 1 10

VIN = 8V, V
EN = VDD & Floating.

OUT

Load Current (A)

2.5V Efficiency vs. Load Current

100

90

DEM Mode

80

70

60

50

40

Efficiency (%)

30

20

CCM Mode

10

0

0.001 0.01 0.1 1 10

Load Current (A)

VIN = 12V, V
EN = VDD & Floating.

OUT

= 2.5V,

= 2.5V,

1.05V Efficiency vs. Load Current

100

90

DEM Mode

80

70

60

50

40

Efficiency (%)

30

20

CCM Mode

10

0

0.001 0.01 0.1 1 10

VIN = 8V, V
EN = VDD & Floating.

OUT

Load Current (A)

1.05V Efficiency vs. Load Current

100

90

DEM Mode

80

70

60

50

40

Efficiency (%)

30

20

CCM Mode

10

0

0.001 0.01 0.1 1 10

Load Current (A)

VIN = 12V, V
EN = VDD & Floating.

OUT

= 1.05V,

= 1.05V,

2.5V Efficiency vs. Load Current

100

90

DEM Mode

80

70

60

50

40

Efficiency (%)

30

20

CCM Mode

10

0

0.001 0.01 0.1 1 10

Load Current (A)

VIN = 20V, V
EN = VDD & Floating.

OUT

100

Efficiency (%)

= 2.5V,

1.05V Efficiency vs. Load Current

90

DEM Mode

80

70

60

50

40

30

20

CCM Mode

10

0

0.001 0.01 0.1 1 10

Load Current (A)

VIN = 20V, V
EN = VDD & Floating.

= 1.05V,

OUT

DS8209A/B/C-03 April 2010 www.richtek.com

7

RT8209A/B/C

Switching Frequency vs. R

900

800

700

600

500

400

300

200

Switching Frequency (kHz) 1

100

0

100 200 300 400 500 600 700

V

OUT

V

= 2.5V

OUT

= 1.05V

R

Resistance (kΩ)

TON

VIN = 15V, EN = Floating

Resistance

TON

CCM Mode

1.05V Switching Frequency vs. Load Current

400

VIN = 12V, V
EN = VDD & Floating.

350

300

250

= 1.05V,

OUT

CCM Mode

Switching Frequency vs. Input Voltage

500

450

V

= 2.5V

OUT

400

350

300

V

= 1.05V

OUT

250

200

150

100

Switching Frequency (kHz) 1

50

0

6 1014182226

I

= 2A, EN = Floating

OUT

Input Voltage (V)

CCM Mode

1.05V Switching Frequency vs. Load Current

400

VIN = 20V, V
EN = VDD & Floating.

350

300

250

= 1.05V,

OUT

CCM Mode

200

150

100

Switching Frequency (kHz) 1

50

0

0.001 0.01 0.1 1 10

DEM Mode

Load Current (A)

2.5V Switching Frequency vs. Load Current

450

400

350

300

250

200

150

100

Switching Frequency (kHz) 1

50

0

0.001 0.01 0.1 1 10

Load Current (A)

CCM Mode

EN = VDD & Floating

DEM Mode

VIN = 12V

= 2.5V

V

OUT

200

150

100

Switching Frequency (kHz) 1

50

0

0.001 0.01 0.1 1 10

DEM Mode

Load Current (A)

2.5V Switching Frequency vs. Load Current

450

400

350

300

250

200

150

100

Switching Frequency (kHz) 1

50

0

0.001 0.01 0.1 1 10

CCM Mode

EN = VDD & Floating

Load Current (A)

DEM Mode

VIN = 20V

V

OUT

= 2.5V

DS8209A/B/C-03 April 2010www.richtek.com

8

RT8209A/B/C

0.8

0.6

0.4

0.2

Shutdown Input Current (uA) 1

V

OUT

(1V/Div)

UGATE

(20V/Div)

Shutdown Input Current vs. Input Voltage

1

EN = GND, No Load

0

7 9 11 13 15 17 19 21 23 25

Input Voltage (V)

Power On from EN (DEM Mode)

V

OUT

(1V/Div)

UGATE

(20V/Div)

EN

(2V/Div)

PGOOD1

(5V/Div)

VOUT

(200mV/Div)

I

L

(10A/Div)

Power On from EN (CCM Mode)

No Load, VIN = 12V, V

Time (400μs/Div)

= 2.5V, EN = Floating

OUT

Power On in Short Circuit

EN

(2V/Div)

PGOOD1

(5V/Div)

VOUT

(1V/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

No Load, VIN = 12V, V

Time (400μs/Div)

OVP (DEM Mode)

Time (100μs/Div)

= 2.5V, EN = VDD

OUT

VIN = 12V, V
EN = VDD, No Load

OUT

= 2.5V

UGATE

(20V/Div)

LGATE

(5V/Div)

VOUT

(500mV/Div)

I

L

(10A/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

VIN = 12V, EN = Floating (CCM Mode)

Time (2ms/Div)

UVP (DEM Mode)

VIN = 12V, V
EN = VDD, No Load

Time (20μs/Div)

OUT

= 1.05V

DS8209A/B/C-03 April 2010 www.richtek.com

9

RT8209A/B/C

V

OUT_ac-

coupled

(100mV/Div)

I

L

(10A/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

V

OUT_ac-

coupled

(100mV/Div)

2.5V Load Transient Response

VIN = 12V, V

= 2.5V, EN = VDD (CCM Mode)

OUT

Time (20μs/Div)

Mode Transition DEM to CCM

V

OUT_ac-

coupled

(100mV/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

EN

(5V/Div)

Mode Transition CCM to DEM

VIN = 12V, No Load

Time (40μs/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

EN

(5V/Div)

VIN = 12V, No Load

Time (40μs/Div)

10

DS8209A/B/C-03 April 2010www.richtek.com

RT8209A/B/C

Application Information

The RT8209A/B/C PWM controller provides high efficiency,

excellent transient response, and high DC output accuracy

needed for stepping down high voltage batteries to

generate low voltage CPU core, I/O, and chipset RAM

supplies in notebook computers. Richtek Mach

ResponseTM technology is specifically designed for

providing 100ns “instant-on” response to load steps while

maintaining a relatively constant operating frequency and

inductor operating point over a wide range of input voltages.

The topology circumvents the poor load transient timing

problems of fixed-frequency current-mode PWMs while

avoiding the problems caused by widely varying switching

frequencies in conventional constant-on-time and constant

off-time PWM schemes. The DRVTM mode PWM

modulator is specifically designed to have better noise

immunity for such a single output application.

PWM Operation

TM

The Mach ResponseTM DRV

the output filter capacitor's effective series resistance

(ESR) to act as a current sense resistor, so the output

ripple voltage provides the PWM ramp signal. Refer to the

function block diagram, the synchronous UGATE driver

will be turned on at the beginning of each cycle. After the

internal one-shot timer expires, the UGATE driver will be

turned off. The pulse width of this one shot is determined

by the converter's input voltage and the output voltage to

keep the frequency fairly constant over the input voltage

range. Another one-shot sets a minimum off-time (400ns

typ.).

On-Time Control

The on-time one-shot comparator has two inputs. One

input monitors the output voltage, while the other input

samples the input voltage and converts it to a current.

This input voltage proportional current is used to charge

an internal on-time capacitor. The on-time is the time

required for the voltage on this capacitor to charge from

zero volts to V

, thereby making the on-time of the high

OUT

side switch directly proportional to output voltage and

inversely proportional to input voltage. The implementation

results in a nearly constant switching frequency without

the need a clock generator.

mode controller relies on

T_ON = 9.6p x R

TON

x (V

+ 0.1) / (VIN − 0.3) + 50ns

OUT

Although this equation provides a good approximation to

start with, the accuracy depends on each design and

selection of the high side MOSFET.

And then the switching frequency is:

OUT

f =

R

V

V x T_ON

IN

is the external resistor connected from the PHASE

TON

to TON pin.

Mode Selection (EN/DEM) Operation

The EN/DEM pin enables the supply. When EN/DEM is

tied to VDD, the controller is enabled and operates in

diode-emulation mode. When the EN/DEM pin is floating,

the RT8209A/B/C will operate in forced-CCM mode.

Diode-Emulation Mode (EN/DEM = High)

In diode-emulation mode, the RT8209A/B/C automatically

reduces switching frequency at light-load conditions to

maintain high efficiency. This reduction of frequency is

achieved smoothly and without increasing VOUT ripple or

load regulation. As the output current decreases from

heavy-load condition, the inductor current is also reduced,

and eventually comes to the point that its valley touches

zero current, which is the boundary between continuous

conduction and discontinuous conduction modes. By

emulating the behavior of diodes, the low side MOSFET

allows only partial of negative current when the inductor

freewheeling current reach negative. As the load current

is further decreased, it takes longer and longer to discharge

the output capacitor to the level than requires the next

“ON” cycle. The on-time is kept the same as that in the

heavy-load condition. In reverse, when the output current

increases from light load to heavy load, the switching

frequency increases to the preset value as the inductor

current reaches the continuous condition. The transition

load point to the light-load operation can be calculated as

follows (Figure 1) :

V-V

()

≈

IN OUT

2L

I x T_ON

LOAD

where T_ON is On-time.

DS8209A/B/C-03 April 2010 www.richtek.com

11

RT8209A/B/C

I

L

Slope = (VIN -V

0

t

ON

OUT

) / L

i

L, peak

i

Load

= i

t

L, peak

/ 2

Figure 1. Boundary Condition of CCM/DEM

The switching waveforms may appear noisy and

asynchronous when light loading causes diode-emulation

operation, but this is a normal operating condition that

results in high light-load efficiency. Trade-offs in DEM noise

vs. light-load efficiency is made by varying the inductor

value. Generally, low inductor values produce a broader

efficiency vs. load curve, while higher values result in higher

full-load efficiency (assuming that the coil resistance

remains fixed) and less output voltage ripple. The

disadvantages for using higher inductor values include

larger physical size and degrade load transient response

(especially at low input-voltage levels).

the trip voltage setting resistor, RCS. The CS terminal

source 10μA ICS current, and the trip level is set to the CS

trip voltage, V

cand be calculated as following equation.

CS

VCS (mV) = RCS (kΩ) x 10 (μA)

Inductor current is monitored by the voltage between the

PGND pin and the PHASE pin, so the PHASE pin should

be connected to the drain terminal of the low side

MOSFET. ICS has positive temperature coefficient to

compensate the temperature dependency of the R

DS(ON)

PGND is used as the positive current sensing node so

PGND should be connected to the source terminal of the

bottom MOSFET.

As the comparison is done during the OFF state, V

CS

sets the valley level of the inductor current. Thus, the

load current at over current threshold, I

LOAD_OC

, can be

calculated as follows.

CS Ripple

I = +

LOAD_OC

V

CS

= + x

R2 x L x f V

DS(ON) IN

VI

R2

DS(ON)

V-V x V

1

I

L

()

IN OUT OUT

.

Forced-CCM Mode (EN/DEM = Floating)

The low oise, forced-CCM mode (EN/DEM = floating)

disables the zero-crossing comparator, which controls the

low-side switch on-time. This causes the low side gate

drive waveform to become the complement of the high

side gate-drive waveform. This in turn causes the inductor

current to reverse at light loads as the PWM loop to

maintain a duty ratio VOUT/VIN. The benefit of forced-

CCM mode is to keep the switching frequency fairly

constant, but it comes at a cost. The no-load battery

current can be up to 10mA to 40mA, depending on the

external MOSFETs.

Current Limit Setting (OCP)

RT8209A/B/C has cycle-by-cycle current limiting control.

The current limit circuit employs a unique “valley” current

sensing algorithm. If PHASE voltage plus the current limit

threshold is below zero, the PWM is not allowed to initiate

a new cycle (Figure 2). In order to provide both good

accuracy and a cost effective solution, the RT8209A/B/C

supports temperature compensated MOSFET R

DS(ON)

sensing. The CS pin should be connected to GND through

I

L, peak

I

Load

I

LIM

0

t

Figure 2. Valley Current-Limit

MOSFET Gate Driver (UGATE, LGA TE)

The high side driver is designed to drive high current, low

R

N-MOSFET(s). When configured as a floating

DS(ON)

driver, 5V bias voltage is delivered from VDDP supply. The

average drive current is proportional to the gate charge at

VGS = 5V times switching frequency. The instantaneous

drive current is supplied by the flying capacitor between

BOOT and PHASE pins. A dead time to prevent shoot

through is internally generated between high side

MOSFET off to low side MOSFET on, and low side

MOSFET off to high side MOSFET on. The low side driver

is designed to drive high current, low R

N-MOSFET(s).

DS(ON)

12

DS8209A/B/C-03 April 2010www.richtek.com

RT8209A/B/C

The internal pull-down transistor that drives LGATE low is

robust, with a 0.5Ω typical on resistance. A 5V bias

voltage is delivered from VDDP supply. The instantaneous

drive current is supplied by the flying capacitor between

VDDP and PGND.

For high current applications, some combinations of high

and low side MOSFETs might be encountered that will

cause excessive gate-drain coupling, which can lead to

efficiency-killing, EMI-producing shoot-through currents.

This is often remedied by adding a resistor in series with

BOOT, which increases the turn-on time of the high side

MOSFET without degrading the turn-off time (Figure 3).

V

IN

BOOT

UGATE

PHASE

10

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over

voltage protection. When the output voltage exceeds 25%

of the set voltage threshold, over voltage protection is

triggered and the low side MOSFET is latched on. This

activates the low side MOSFET to discharge the output

capacitor. The RT8209A/B/C is latched once OVP is

triggered and can only be released by VDD or EN/DEM

power on reset. There is a 20μs delay built into the over

voltage protection circuit to prevent false transitions.

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage protection. When the output voltage is less than

70% of the set voltage threshold, under voltage protection

is triggered and then both UGATE and LGATE gate drivers

are forced low. There is a 2.5μs delay built into the under

voltage protection circuit to prevent false transitions. During

soft-start, the UVP blanking time is 512 UGATE clks.

Figure 3. Reducing the UGATE Rise Time

Power-Good Output (PGOOD)

The power good output is an open-drain output and requires

a pull-up resistor. When the output voltage is 25% above

or 10% below its set voltage, PGOOD gets pulled low. It

is held low until the output voltage returns to within these

tolerances once more. In soft start, PGOOD is actively

held low and is allowed to transition high until soft start is

over and the output reaches 93% of its set voltage. There

is a 2.5us delay built into PGOOD circuitry to prevent

false transitions.

POR, UVLO and Soft-Start

Power On Reset (POR) occurs when VDD rises above to

approximately 4.3V, the RT8209A/B/C will reset the fault

latch and preparing the PWM for operation. Below 4.1

V

, the VDD under voltage-lockout (UVLO) circuitry

(MIN)

inhibits switching by keeping UGATE and LGATE low. A

built-in soft-start is used to prevent surge current from

power supply input after EN/DEM is enabled. The

maximum allowed current limit is segmented in 4 steps:

25%, 50%, 75% and 100% during this period, each step

is 128 UGATE clks. The current limit steps can eliminate

the V

folded-back in the soft-start duration.

OUT

Output V oltage Setting (FB)

The output voltage can be adjusted from 0.75V to 3.3V by

setting the feedback resistor R1 and R2 (Figure 4). Choose

R2 to be approximately 10kΩ, and solve for R1 using the

equation:

R1

V = V x 1+

OUT REF

where V

REF

⎛⎞
⎜⎟

R2

⎝⎠

is 0.75V.(typ.)

UGATE

PHASE

LGATE

VOUT

FB

GND

V

IN

V

OUT

R1

R2

Figure 4. Setting VOUT with a Resistor Divider

Output Inductor Selection

The switching frequency (on-time) and operating point (%

ripple or LIR) determine the inductor value as follows :

T x V-V

L =

()

ON IN OUT

L x I

IR LOAD(MAX)

DS8209A/B/C-03 April 2010 www.richtek.com

13

RT8209A/B/C

Where LIR is the ratio of peak-of-peak ripple current to the

maximum average inductor current. Find a low pass

inductor having the lowest possible DC resistance that

fits in the allowed dimensions. Ferrite cores are often the

best choice, although powdered iron is inexpensive and

can work well at 200kHz. The core must be large enough

and not to saturate at the peak inductor current (I

⎡⎤

L

⎛⎞

I = I + x I

PEAK LOAD(MAX) LOAD(MAX)

IR

⎢⎥

⎜⎟

2

⎝⎠

⎣⎦

PEAK

) :

Output Capacitor Selection

The output filter capacitor must have ESR low enough to

meet output ripple and load-transient requirement, yet have

high enough ESR to satisfy stability requirements. Also,

the capacitance value must be high enough to absorb the

inductor energy going from a full-load to no-load condition

without tripping the OVP circuit. For CPU core voltage

converters and other applications where the output is

subject to violent load transient, the output capacitor’s

size depends on how much ESR is needed to prevent the

output from dipping too low under a load transient. Ignoring

the sag due to finite capacitance :

V

ESR

≤

P-P

I

LOAD(MAX)

However, it is easy to add sufficient series resistance by

placing the capacitors a couple of inches downstream from

the inductor and connecting VOUT or FB divider close to

the inductor. There are two related but distinct ways

including double-pulsing and feedback loop instability to

identify the unstable operation. Double-pulsing occurs due

to noise on the output or because the ESR is too low that

there is not enough voltage ramp in the output voltage

signal. This “fools” the error comparator into triggering a

new cycle immediately after a 400ns minimum off-time

period has expired. Double-pulsing is more annoying than

harmful, resulting in nothing worse than increased output

ripple. However, it may indicate the possible presence of

loop instability, which is caused by insufficient ESR. Loop

instability can result in oscillation at the output after line

or load perturbations that can trip the over voltage

protection latch or cause the output voltage to fall below

the tolerance limit. The easiest method for stability

checking is to apply a very zero-to-max load transient

and carefully observe the output-voltage-ripple envelope

for overshoot and ringing. It helps to simultaneously monitor

the inductor current with AC probe. Do not allow more

than one ringing cycle after the initial step-response under-

or over-shoot.

In non-CPU applications, the output capacitor’s size

depends on how much ESR is needed to maintain at an

acceptable level of output voltage ripple :

V

ESR

≤

L x I

P-P

IR LOAD(MAX)

Organic semiconductor capacitor(s) or specially polymer

capacitor(s) are recommended.

Output Capacitor Stability

Stability is determined by the value of the ESR zero relative

to the switching frequency. The point of instability is given

by the following equation :

f =

ESR

2 x π x ESR x C 4

1

OUT

f

SW

≤

Do not put high value ceramic capacitors directly across

the outputs without taking precautions to ensure stability.

Large ceramic capacitors can have a high ESR zero

frequency and cause erratic and unstable operation.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

P

Where T

temperature 125°C, T

θ

= ( T

D(MAX)

J(MAX)

is the junction to ambient thermal resistance.

JA

− TA ) / θ

J(MAX)

JA

is the maximum operation junction

is the ambient temperature and the

A

For recommended operating conditions specification of

RT8209A/B/C, where T

is the maximum junction

J(MAX)

temperature of the die (125°C) and TA is the maximum

ambient temperature. The junction to ambient thermal

resistance θJA is layout dependent. For WQFN-16L 3x3

packages, the thermal resistance θJA is 68°C/W on the

14

DS8209A/B/C-03 April 2010www.richtek.com

RT8209A/B/C

standard JEDEC 51-7 four layers thermal test board. For

WQFN-14L 3.5x3.5 packages, the thermal resistance θ

JA

is 60°C/W on the standard JEDEC 51-7 four layers thermal

test board. For TSSOP-14 packages, the thermal

resistance θJA is 135°C/W on the standard JEDEC 51-7

four layers thermal test board. The maximum power

dissipation at TA = 25°C can be calculated by following

formula :

P

= (125°C − 25°C)/(68°C/W) = 1.471 W for

D(MAX)

WQFN-16L 3x3 packages

P

= (125°C − 25°C)/(60°C/W) = 1.667 W for

D(MAX)

WQFN-14L 3.5x3.5 packages

P

= (125°C − 25°C)/(135°C/W) = 0.741 W for

D(MAX)

TSSOP-14 packages

The maximum power dissipation depends on operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance θJA. For RT8209A/B/C packages, the Figure

5 of derating curves allows the designer to see the effect

of rising ambient temperature on the maximum power

allowed.

1.8

1.6

1.4

1.2

WQFN -16L 3x3

1.0

TSSOP-14

0.8

0.6

0.4

0.2

Maximum Power Dissipation (W) 1

0.0
0 25 50 75 100 125

WQFN -14L 3.5x3.5

Ambient Temperature (°C)

Four Layers PCB

Layout Considerations

Layout is very important in high frequency switching

converter design. If the layout is designed improperly, the

PCB could radiate excessive noise and contribute to the

converter instability. The following points must be followed

for a proper layout of RT8209A/B/C.

` Connect an RC low-pass filter from VDDP to VDD, 1μF

and 10Ω are recommended. Place the filter capacitor

close to the IC.

` Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high voltage switching node.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as

short as possible to reduce stray inductance.

` All sensitive analog traces and components such as

VOUT, FB, GND, EN/DEM, PGOOD, CS, VDD, and TON

should be placed away from high voltage switching

nodes such as PHASE, LGATE, UGATE, or BOOT

nodes to avoid coupling. Use internal layer(s) as ground

plane(s) and shield the feedback trace from power traces

and components.

` Current sense connections must always be made using

Kelvin connections to ensure an accurate signal, with

the current limit resistor located at the device.

` Power sections should connect directly to ground

plane(s) using multiple vias as required for current

handling (including the chip power ground connections).

Power components should be placed to minimize loops

and reduce losses.

Figure 5. Derating Curves for RT8209A/B/C Packages

DS8209A/B/C-03 April 2010 www.richtek.com

15

RT8209A/B/C

Outline Dimension

D

E

A

A3

A1

D2

e

SEE DETAIL A

1

E2

b

L

1
2

1
2

DETAIL A

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120

D2 1.300 1.750 0.051 0.069

E 2.950 3.050 0.116 0.120

E2 1.300 1.750 0.051 0.069

e 0.500 0.020

L 0.350 0.450

0.014 0.018

W-Type 16L QFN 3x3 Package

16

DS8209A/B/C-03 April 2010www.richtek.com

RT8209A/B/C

2

DETAIL A

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.8 00 0 .028 0.031

A1 0.000 0.050 0.000 0.00 2

A3 0.175 0.250 0.007 0.01 0

b 0.180 0.300 0 .007 0.01 2

D 3.40 0 3.6 00 0 .134 0.142

D2 1.950 2.150 0 .077 0.08 5

E 3.400 3.6 00 0 .134 0.142

E2 1.950 2.150 0.077 0.08 5

1

1

2

e 0.500 0.0 20

e1 1.500 0.0 60

L 0.300 0.500

0.012 0.02 0

W-Type 14L QFN 3.5x3.5 Package

DS8209A/B/C-03 April 2010 www.richtek.com

17

RT8209A/B/C

D

L

E

A

b

E1

e

A2

A1

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 1.000 1.20 0 0.0 39 0.0 47

A1 0.050 0.150 0.002 0.0 06

A2 0.800 1.050 0.031 0.0 41

b 0.190 0.300 0.0 07 0.0 12

D 4.90 0 5.10 0 0.1 93 0.201

e 0.650 0.026

E 6.300 6.50 0 0.2 48 0.2 56

E1 4.300 4.500 0.169 0.1 77

L 0.450 0.750 0.0 18 0.0 30

14-Lead TSSOP Plastic Package

Richtek Technology Corporation

Headquarter

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit

design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be

guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

18

Richtek Technology Corporation

Taipei Office (Marketing)

8F, No. 137, Lane 235, Paochiao Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: [phone] Fax: [phone]

Email: [e-mail]

DS8209A/B/C-03 April 2010www.richtek.com