SC600Y&SC600T
Hardware Design
Smart LTE Module Series
Rev: SC600Y&SC600T_Hardware_Design_V1.0
Date: 2019-07-01
Status: Preliminary
www.quectel.com
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GENERAL NOTES
QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION
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Copyright © Quectel Wireless Solutions Co., Ltd. 2019. All rights reserved.
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About the Document
History
Revision
Date
Author
Description
1.0
2019-07-01
Light WANG/
Rock CHEN
Initial
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Contents
About the Document ................................................................................................................................... 2
Contents ....................................................................................................................................................... 3
Table Index ................................................................................................................................................... 6
Figure Index ................................................................................................................................................. 8
1 Introduction ........................................................................................................................................ 14
1.1. Safety Information ..................................................................................................................... 15
2 Product Concept ................................................................................................................................ 16
2.1. General Description .................................................................................................................. 16
2.2. Key Features ............................................................................................................................. 19
2.3. Functional Diagram ................................................................................................................... 23
2.4. Evaluation Board ....................................................................................................................... 24
3 Application Interfaces ....................................................................................................................... 25
3.1. General Description .................................................................................................................. 25
3.2. Pin Assignment ......................................................................................................................... 26
3.3. Pin Description .......................................................................................................................... 27
3.4. Power Supply ............................................................................................................................ 43
3.4.1. Power Supply Pins ......................................................................................................... 43
3.4.2. Decrease Voltage Drop .................................................................................................. 43
3.4.3. Reference Design for Power Supply .............................................................................. 44
3.5. Turn on and off Scenarios ......................................................................................................... 45
3.5.1. Turn on Module Using the PWRKEY ............................................................................. 45
3.5.2. Turn off Module .............................................................................................................. 47
3.6. VRTC Interface ......................................................................................................................... 48
3.7. Power Output ............................................................................................................................ 49
3.8. Battery Charge and Management ............................................................................................. 49
3.9. USB Interface ............................................................................................................................ 51
3.10. UART Interfaces ........................................................................................................................ 54
3.11. (U)SIM Interfaces ...................................................................................................................... 56
3.12. SD Card Interface ..................................................................................................................... 58
3.13. GPIO Interfaces ........................................................................................................................ 60
3.14. I2C Interfaces ............................................................................................................................ 63
3.15. I2S Interface .............................................................................................................................. 64
3.16. SPI Interfaces ............................................................................................................................ 64
3.17. ADC Interfaces .......................................................................................................................... 65
3.18. Vibrator Drive Interface ............................................................................................................. 65
3.19. LCM Interfaces .......................................................................................................................... 66
3.20. Touch Panel Interfaces ............................................................................................................. 70
3.21. Camera Interfaces..................................................................................................................... 71
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3.21.1. Design Considerations ................................................................................................... 77
3.21.2. Flashlight Interfaces ....................................................................................................... 79
3.22. Sensor Interfaces ...................................................................................................................... 80
3.23. Audio Interfaces ........................................................................................................................ 80
3.23.1. Reference Circuit Design for Microphone Interfaces ..................................................... 82
3.23.2. Reference Circuit Design for Earpiece Interface ........................................................... 83
3.23.3. Reference Circuit Design for Headphone Interface ....................................................... 83
3.23.4. Reference Circuit Design for Loudspeaker Interface..................................................... 84
3.23.5. Audio Interfaces Design Considerations........................................................................ 84
3.24. Emergency Download Interface ................................................................................................ 85
4 Wi-Fi and BT ....................................................................................................................................... 86
4.1. Wi-Fi Overview .......................................................................................................................... 86
4.1.1. Wi-Fi Performance ......................................................................................................... 86
4.2. BT Overview .............................................................................................................................. 88
4.2.1. BT Performance ............................................................................................................. 89
5 GNSS ................................................................................................................................................... 90
5.1. GNSS Performance .................................................................................................................. 90
5.2. GNSS RF Design Guidelines .................................................................................................... 91
6 Antenna Interfaces ............................................................................................................................. 92
6.1. Main/Rx-diversity Antenna Interfaces ....................................................................................... 92
6.1.1. Main and Rx-diversity Antenna Interfaces Reference Design ....................................... 95
6.1.2. Reference Design of RF Layout..................................................................................... 96
6.2. Wi-Fi/BT Antenna Interface ....................................................................................................... 98
6.3. GNSS Antenna Interface ........................................................................................................... 99
6.3.1. Recommended Circuit for Passive Antenna .................................................................. 99
6.3.2. Recommended Circuit for Active Antenna ................................................................... 100
6.4. Antenna Installation ................................................................................................................. 100
6.4.1. Antenna Requirements ................................................................................................ 100
6.4.2. Recommended RF Connector for Antenna Installation ............................................... 101
7 Electrical, Reliability and Radio Characteristics .......................................................................... 103
7.1. Absolute Maximum Ratings .................................................................................................... 103
7.2. Power Supply Ratings ............................................................................................................. 103
7.3. Operation and Storage Temperatures ..................................................................................... 104
7.4. Current Consumption .............................................................................................................. 105
7.5. RF Output Power .....................................................................................................................111
7.6. RF Receiving Sensitivity ......................................................................................................... 114
7.7. Electrostatic Discharge ........................................................................................................... 116
8 Mechanical Dimensions .................................................................................................................. 118
8.1. Mechanical Dimensions of the Module ................................................................................... 118
8.2. Recommended Footprint ........................................................................................................ 120
8.3. Top and Bottom View of the Module ....................................................................................... 121
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9 Storage, Manufacturing and Packaging ........................................................................................ 122
9.1. Storage .................................................................................................................................... 122
9.2. Manufacturing and Soldering .................................................................................................. 123
9.3. Packaging ............................................................................................................................... 124
10 Appendix A References ................................................................................................................... 126
11 Appendix B GPRS Coding Schemes ............................................................................................. 129
12 Appendix C GPRS Multi-slot Classes ............................................................................................ 130
13 Appendix D EDGE Modulation and Coding Schemes ................................................................. 132
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Table Index
TABLE 1: SC600Y-EM*/SC600T-EM* FREQUENCY BANDS .......................................................................... 16
TABLE 2: SC600Y-NA*/SC600T-NA* FREQUENCY BANDS ........................................................................... 17
TABLE 3: SC600Y-JP*/SC600T-JP* FREQUENCY BANDS ............................................................................. 17
TABLE 4: SC600Y-WF*/SC600T-WF* FREQUENCY BANDS .......................................................................... 18
TABLE 5: SC600Y&SC600T KEY FEATURES ................................................................................................. 19
TABLE 6: I/O PARAMETERS DEFINITION ....................................................................................................... 27
TABLE 7: PIN DESCRIPTION ........................................................................................................................... 27
TABLE 8: POWER DESCRIPTION ................................................................................................................... 49
TABLE 9: PIN DEFINITION OF CHARGING INTERFACE ............................................................................... 50
TABLE 10: PIN DEFINITION OF USB INTERFACE ......................................................................................... 52
TABLE 11: USB TRACE LENGTH INSIDE THE MODULE ............................................................................... 54
TABLE 12: PIN DEFINITION OF UART INTERFACES ..................................................................................... 54
TABLE 13: PIN DEFINITION OF (U)SIM INTERFACES ................................................................................... 56
TABLE 14: PIN DEFINITION OF SD CARD INTERFACE ................................................................................ 59
TABLE 15: SD CARD SIGNAL TRACE LENGTH INSIDE THE MODULE ....................................................... 60
TABLE 16: PIN DEFINITION OF GPIO INTERFACES ..................................................................................... 60
TABLE 17: PIN DEFINITION OF I2C INTERFACES ......................................................................................... 63
TABLE 18: PIN DEFINITION OF I2S INTERFACE ........................................................................................... 64
TABLE 19: PIN DEFINITION OF SPI INTERFACES ........................................................................................ 65
TABLE 20: PIN DEFINITION OF ADC INTERFACES ....................................................................................... 65
TABLE 21: PIN DEFINITION OF VIBRATOR DRIVE INTERFACE .................................................................. 66
TABLE 22: PIN DEFINITION OF LCM INTERFACES ....................................................................................... 66
TABLE 23: PIN DEFINITION OF TOUCH PANEL INTERFACES ..................................................................... 70
TABLE 24: PIN DEFINITION OF CAMERA INTERFACES ............................................................................... 72
TABLE 25: MIPI TRACE LENGTH INSIDE THE MODULE............................................................................... 77
TABLE 26: PIN DEFINITION OF FLASHLIGHT INTERFACES ........................................................................ 79
TABLE 27: PIN DEFINITION OF SENSOR INTERFACES ............................................................................... 80
TABLE 28: PIN DEFINITION OF AUDIO INTERFACES ................................................................................... 81
TABLE 29: WI-FI TRANSMITTING PERFORMANCE ....................................................................................... 86
TABLE 30: WI-FI RECEIVING PERFORMANCE .............................................................................................. 87
TABLE 31: BT DATA RATE AND VERSIONS .................................................................................................... 89
TABLE 32: BT TRANSMITTING AND RECEIVING PERFORMANCE ............................................................. 89
TABLE 33: GNSS PERFORMANCE ................................................................................................................. 90
TABLE 34: PIN DEFINITION OF MAIN/RX-DIVERSITY ANTENNA INTERFACES ......................................... 92
TABLE 35: SC600Y-JP*/SC600T-JP* MODULE OPERATING FREQUENCIES .............................................. 92
TABLE 36: SC600Y-EM*/SC600T-EM* MODULE OPERATING FREQUENCIES............................................ 93
TABLE 37: SC600Y-NA*/SC600T-NA* MODULE OPERATING FREQUENCIES ............................................ 94
TABLE 38: PIN DEFINITION OF WI-FI/BT ANTENNA INTERFACE ................................................................ 98
TABLE 39: WI-FI/BT FREQUENCY................................................................................................................... 98
TABLE 40: PIN DEFINITION OF GNSS ANTENNA .......................................................................................... 99
TABLE 41: GNSS FREQUENCY ....................................................................................................................... 99
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TABLE 42: ANTENNA REQUIREMENTS ........................................................................................................ 100
TABLE 43: ABSOLUTE MAXIMUM RATINGS ................................................................................................ 103
TABLE 44: SC600Y&SC600T MODULES POWER SUPPLY RATINGS ........................................................ 103
TABLE 45: OPERATION AND STORAGE TEMPERATURES ........................................................................ 104
TABLE 46: SC600Y-JP*/SC600T-JP* CURRENT CONSUMPTION ............................................................... 105
TABLE 47: SC600Y-EM*/SC600T-EM* CURRENT CONSUMPTION ............................................................ 106
TABLE 48: SC600Y-NA*/SC600T-NA* CURRENT CONSUMPTION .............................................................. 110
TABLE 49: SC600Y-JP*/SC600T-JP* RF OUTPUT POWER .......................................................................... 111
TABLE 50: SC600Y-EM*/SC600T-EM* RF OUTPUT POWER ........................................................................ 112
TABLE 51: SC600Y-NA*/SC600T-NA* RF OUTPUT POWER ......................................................................... 113
TABLE 52: SC600Y-JP*/SC600T-JP* RF RECEIVING SENSITIVITY ............................................................. 114
TABLE 53: SC600Y-EM*/SC600T-EM* RF RECEIVING SENSITIVITY .......................................................... 115
TABLE 54: SC600Y-NA*/SC600T-NA* RF RECEIVING SENSITIVITY ........................................................... 116
TABLE 55: ESD CHARACTERISTICS (TEMPERATURE: 25°C , HUMIDITY: 45%) ........................................ 117
TABLE 56: RECOMMENDED THERMAL PROFILE PARAMETERS ............................................................. 123
TABLE 57: REEL PACKAGING ....................................................................................................................... 125
TABLE 58: RELATED DOCUMENTS .............................................................................................................. 126
TABLE 59: TERMS AND ABBREVIATIONS .................................................................................................... 126
TABLE 60: DESCRIPTION OF DIFFERENT CODING SCHEMES ................................................................ 129
TABLE 61: GPRS MULTI-SLOT CLASSES .................................................................................................... 130
TABLE 62: EDGE MODULATION AND CODING SCHEMES ......................................................................... 132
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Figure Index
FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 23
FIGURE 2: PIN ASSIGNMENT (TOP VIEW)..................................................................................................... 26
FIGURE 3: VOLTAGE DROP SAMPLE ............................................................................................................. 43
FIGURE 4: STAR STRUCTURE OF POWER SUPPLY .................................................................................... 44
FIGURE 5: REFERENCE CIRCUIT OF POWER SUPPLY .............................................................................. 45
FIGURE 6: TURN ON THE MODULE USING DRIVING CIRCUIT ................................................................... 46
FIGURE 7: TURN ON THE MODULE USING KEYSTROKE ........................................................................... 46
FIGURE 8: TIMING OF TURNING ON MODULE ............................................................................................. 47
FIGURE 9: TIMING OF TURNING OFF MODULE ........................................................................................... 48
FIGURE 10: RTC POWERED BY COIN CELL ................................................................................................. 48
FIGURE 11: REFERENCE DESIGN FOR BATTERY CHARGING CIRCUIT ................................................... 51
FIGURE 12: USB 2.0 INTERFACE REFERENCE DESIGN ............................................................................. 53
FIGURE 13: USB TYPE-C INTERFACE REFERENCE DESIGN ..................................................................... 53
FIGURE 14: REFERENCE CIRCUIT WITH LEVEL TRANSLATOR CHIP (FOR UART5) .............................. 55
FIGURE 15: RS232 LEVEL MATCH CIRCUIT (FOR UART5) .......................................................................... 56
FIGURE 16: REFERENCE CIRCUIT FOR (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR
................................................................................................................................................................... 57
FIGURE 17: REFERENCE CIRCUIT FOR (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR
................................................................................................................................................................... 58
FIGURE 18: REFERENCE CIRCUIT FOR SD CARD INTERFACE ................................................................. 59
FIGURE 19: REFERENCE CIRCUIT FOR VIBRATOR CONNECTION ........................................................... 66
FIGURE 20: REFERENCE CIRCUIT DESIGN FOR LCM0 INTERFACE ......................................................... 68
FIGURE 21: REFERENCE CIRCUIT DESIGN FOR LCM1 INTERFACE ......................................................... 69
FIGURE 22: REFERENCE DESIGN OF LCM1 EXTERNAL BACKLIGHT DRIVING CIRCUIT ....................... 70
FIGURE 23: REFERENCE CIRCUIT DESIGN FOR TOUCH PANEL INTERFACES ....................................... 71
FIGURE 24: REFERENCE CIRCUIT DESIGN FOR TWO-CAMERA APPLICATIONS .................................... 75
FIGURE 25: REFERENCE CIRCUIT DESIGN FOR THREE-CAMERA APPLICATIONS ................................ 76
FIGURE 26: REFERENCE CIRCUIT DESIGN FOR FLASHLIGHT INTERFACES .......................................... 80
FIGURE 27: REFERENCE CIRCUIT DESIGN FOR ANALOG ECM-TYPE MICROPHONE ........................... 82
FIGURE 28: REFERENCE CIRCUIT DESIGN FOR MEMS-TYPE MICROPHONE ........................................ 82
FIGURE 29: REFERENCE CIRCUIT DESIGN FOR EARPIECE INTERFACE ................................................ 83
FIGURE 30: REFERENCE CIRCUIT DESIGN FOR HEADPHONE INTERFACE ........................................... 83
FIGURE 31: REFERENCE CIRCUIT DESIGN FOR LOUDSPEAKER INTERFACE ....................................... 84
FIGURE 32: REFERENCE CIRCUIT DESIGN FOR EMERGENCY DOWNLOAD INTERFACE ..................... 85
FIGURE 33: REFERENCE CIRCUIT DESIGN FOR MAIN AND RX-DIVERSITY ANTENNA INTERFACES .. 95
FIGURE 34: MICROSTRIP DESIGN ON A 2-LAYER PCB ............................................................................... 96
FIGURE 35: COPLANAR WAVEGUIDE DESIGN ON A 2-LAYER PCB ........................................................... 96
FIGURE 36: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND)
................................................................................................................................................................... 97
FIGURE 37: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND)
................................................................................................................................................................... 97
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FIGURE 38: REFERENCE CIRCUIT DESIGN FOR WI-FI/BT ANTENNA INTERFACE .................................. 98
FIGURE 39: REFERENCE CIRCUIT DESIGN FOR GNSS PASSIVE ANTENNA ........................................... 99
FIGURE 40: REFERENCE CIRCUIT DESIGN FOR GNSS ACTIVE ANTENNA ........................................... 100
FIGURE 41: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) .............................................. 101
FIGURE 42: MECHANICALS OF U.FL-LP CONNECTORS ........................................................................... 102
FIGURE 43: SPACE FACTOR OF MATED CONNECTOR (UNIT: MM) ......................................................... 102
FIGURE 44: MODULE TOP AND SIDE DIMENSIONS .................................................................................... 118
FIGURE 45: MODULE BOTTOM DIMENSIONS (TOP VIEW) ........................................................................ 119
FIGURE 46: RECOMMENDED FOOTPRINT (TOP VIEW) ............................................................................ 120
FIGURE 47: TOP VIEW OF SC600Y/SC600T MODULES ............................................................................. 121
FIGURE 48: BOTTOM VIEW OF SC600Y/SC600T MODULES ..................................................................... 121
FIGURE 49: RECOMMENDED REFLOW SOLDERING THERMAL PROFILE .............................................. 123
FIGURE 50: TAPE DIMENSIONS ................................................................................................................... 124
FIGURE 51: REEL DIMENSIONS ................................................................................................................... 125
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OEM/Integrators Installation Manual
Important Notice to OEM integrators
1. This module is limited to OEM installation ONLY.
2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b).
3. The separate approval is required for all other operating configurations, including portable
configurations with respect to Part 2.1093 and different antenna configurations
4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify
compliance as a composite system. When testing the host device for compliance with Part
15 Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the
transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation
should confirm that the module's intentional emissions are compliant (i.e. fundamental and out of band
emissions). The host manufacturer must verify that there are no additional unintentional emissions other
than what is permitted in Part 15 Subpart B or emissions are complaint with the transmitter(s) rule(s).
The Grantee will provide guidance to the host manufacturer for Part 15 B requirements if needed.
End Product Labeling
When the module is installed in the host device, the FCC/IC ID label must be visible through a window on
the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a
second label must be placed on the outside of the final device that contains the following text: “Contains
FCC ID: XMR2019SC600NA ”
“Contains IC: 10224A-2019SC600NA “
The FCC ID/IC ID can be used only when all FCC/IC compliance requirements are met.
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In the event that these conditions cannot be met (for example certain laptop configurations or co-location
with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC
ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for
re-evaluating the end product (including the transmitter) and obtaining a separate FCC/IC authorization.
Manual Information to the End User
The OEM integrator has to be aware not to provide information to the end user regarding how to install or
remove this RF module in the user’s manual of the end product which integrates this module. The end
user manual shall include all required regulatory information/warning as show in this manual.
Federal Communication Commission Interference Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference
received, including interference that may cause undesired operation.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant
to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference in a residential installation. This equipment generates, uses and can radiate radio frequency
energy and, if not installed and used in accordance with the instructions, may cause harmful interference
to radio communications. However, there is no guarantee that interference will not occur in a particular
installation. If this equipment does cause harmful interference to radio or television reception, which can
be determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one of the following measures:
- Reorient or relocate the receiving antenna.
- Increase the separation between the equipment and receiver.
- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
- Consult the dealer or an experienced radio/TV technician for help.
Any changes or modifications not expressly approved by the party responsible for compliance could void
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the user's authority to operate this equipment. This transmitter must not be co-located or operating in
conjunction with any other antenna or transmitter.
Industry Canada Statement
This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the
following two conditions:
(1) This device may not cause interference; and
(2) This device must accept any interference, including interference that may cause undesired
operation of the device.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts
de licence. L'exploitation est autorisée aux deux conditions suivantes:
(1) l'appareil ne doit pas produire de brouillage, et
(2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est
susceptible d'en compromettre le fonctionnement."
The device could automatically discontinue transmission in case of absence of information to transmit, or
operational failure. Note that this is not intended to prohibit transmission of control or signaling information
or the use of repetitive codes where required by the technology.
The device for operation in the band 5150–5250 MHz is only for indoor use to reduce the potential for
harmful interference to co-channel mobile satellite systems;
The maximum antenna gain permitted for devices in the bands 5250–5350 MHz and 5470–5725 MHz
shall comply with the e.i.r.p. limit; and
The maximum antenna gain permitted for devices in the band 5725–5825 MHz shall comply with the
e.i.r.p. limits specified for point-to-point and non point-to-point operation as appropriate.
L'appareil peut interrompre automatiquement la transmission en cas d'absence d'informations à
transmettre ou de panne opérationnelle. Notez que ceci n'est pas destiné à interdire la transmission
d'informations de contrôle ou de signalisation ou l'utilisation de codes répétitifs lorsque cela est requis par
la technologie.
Le dispositif utilisé dans la bande 5150-5250 MHz est réservé à une utilisation en intérieur afin de réduire
le risque de brouillage préjudiciable aux systèmes mobiles par satellite dans le même canal;
Le gain d'antenne maximal autorisé pour les dispositifs dans les bandes 5250-5350 MHz et 5470-5725
MHz doit être conforme à la norme e.r.p. limite; et
Le gain d'antenne maximal autorisé pour les appareils de la bande 5725-5825 MHz doit être conforme à
la norme e.i.r.p. les limites spécifiées pour un fonctionnement point à point et non point à point, selon le
cas.
CAN ICES-3(B)/ NMB-3(B)
Radiation Exposure Statement
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This equipment complies with FCC/IC radiation exposure limits set forth for an uncontrolled environment.
This equipment should be installed and operated with minimum distance 20 cm between the radiator &
your body.
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1 Introduction
This document defines the SC600Y&SC600T modules and describes their air interfaces and hardware
interfaces which are connected with customers’ applications.
This document can help customers quickly understand module interface specifications, electrical and
mechanical details as well as other related information of SC600Y&SC600T modules. Associated with
application note and user guide, customers can use SC600Y&SC600T modules to design and set up
mobile applications easily.
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1.1. Safety Information
The following safety precautions must be observed during all phases of operation, such as usage, service
or repair of any cellular terminal or mobile incorporating SC600Y&SC600T modules. Manufacturers of the
cellular terminal should send the following safety information to users and operating personnel, and
incorporate these guidelines into all manuals supplied with the product. If not so, Quectel assumes no
liability for customers’ failure to comply with these precautions.
Full attention must be given to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.
Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If the device offers an Airplane Mode, then it should be
enabled prior to boarding an aircraft. Please consult the airline staff for more
restrictions on the use of wireless devices on boarding the aircraft.
Wireless devices may cause interference on sensitive medical equipment, so
please be aware of the restrictions on the use of wireless devices when in
hospitals, clinics or other healthcare facilities.
Cellular terminals or mobiles operating over radio signals and cellular network
cannot be guaranteed to connect in all possible conditions (for example, with
unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such
conditions, please remember using emergency call. In order to make or receive a
call, the cellular terminal or mobile must be switched on in a service area with
adequate cellular signal strength.
The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it
receives and transmits radio frequency signals. RF interference can occur if it is
used close to TV set, radio, computer or other electric equipment.
In locations with potentially explosive atmospheres, obey all posted signs to turn
off wireless devices such as your phone or other cellular terminals. Areas with
potentially explosive atmospheres include fuelling areas, below decks on boats,
fuel or chemical transfer or storage facilities, areas where the air contains
chemicals or particles such as grain, dust or metal powders, etc.
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2 Product Concept
2.1. General Description
SC600Y&SC600T are a series of Smart LTE modules based on Qualcomm platform and Android
operating system, and provide industrial grade performance. Their general features are listed below:
⚫ Support worldwide LTE-FDD, LTE-TDD, DC-HSDPA, DC-HSUPA, HSPA+, HSDPA, HSUPA,
WCDMA, EDGE and GPRS coverage
⚫ Support short-range wireless communication via Wi-Fi 802.11a/b/g/n/ac and BT4.2 LE standards
⚫ Integrate GPS/GLONASS/BeiDou satellite positioning systems
⚫ Support multiple audio and video codecs
⚫ Built-in high performance AdrenoTM 506 graphics processing unit
⚫ Provide multiple audio and video input/output interfaces as well as abundant GPIO interfaces
SC600Y&SC600T modules are composed of standard version (SC600Y-XX) and high-performance
version (SC600T-XX). They are available in SC600Y-EM*/ SC600T-EM*, SC600Y-NA*/ SC600T-NA*,
SC600Y-JP*/ SC600T-JP*, SC600Y-WF*/ SC600T-WF*.
The following table shows the supported frequency bands of SC600Y&SC600T.
Table 1: SC600Y-EM*/SC600T-EM* Frequency Bands
Type
Frequency Bands
LTE-FDD
B1/B2/B3/B4/B5/B7/B8/B20/B28A/B28B
LTE-TDD
B38/B39/B40/B41
WCDMA
B1/B2/B4/B5/B8
TD-SCDMA
/
EVDO/CDMA
/
GSM
850/900/1800/1900MHz
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Wi-Fi 802.11a/b/g/n/ac
2402MHz~2482MHz; 5180MHz~5825MHz
BT4.2 LE
2402MHz~2480MHz
GNSS
GPS: 1575.42MHz±1.023MHz
GLONASS: 1597.5MHz~1605.8MHz
BeiDou: 1561.098MHz±2.046MHz
Table 2: SC600Y-NA*/SC600T-NA* Frequency Bands
Type
Frequency Bands
LTE-FDD
B2/B4/B5/B7/B12/B13/B14/B17/B25/B26/B66/B71
LTE-TDD
B41
WCDMA
B2/B4/B5
TD-SCDMA
/
EVDO/CDMA
/
GSM
/
Wi-Fi 802.11a/b/g/n/ac
2402MHz~2482MHz; 5180MHz~5825MHz
BT4.2 LE
2402MHz~2480MHz
GNSS
GPS: 1575.42MHz±1.023MHz
GLONASS: 1597.5MHz~1605.8MHz
BeiDou: 1561.098MHz±2.046MHz
Table 3: SC600Y-JP*/SC600T-JP* Frequency Bands
Type
Frequency Bands
LTE-FDD
B1/B3/B5/B8/B11/B18/B19/B21/B26/B28A/B28B
LTE-TDD
B41
WCDMA
B1/B6/B8/B19
TD-SCDMA
/
EVDO/CDMA
/
GSM
/
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Wi-Fi 802.11a/b/g/n/ac
2402MHz~2482MHz; 5180MHz~5825MHz
BT4.2 LE
2402MHz~2480MHz
GNSS
GPS: 1575.42MHz±1.023MHz
GLONASS: 1597.5MHz~1605.8MHz
BeiDou: 1561.098MHz±2.046MHz
Table 4: SC600Y-WF*/SC600T-WF* Frequency Bands
Type
Frequency Bands
LTE-FDD
/
LTE-TDD
/
WCDMA
/
TD-SCDMA
/
EVDO/CDMA
/
GSM
/
Wi-Fi 802.11a/b/g/n/ac
2402MHz~2482MHz; 5180MHz~5825MHz
BT4.2 LE
2402MHz~2480MHz
GNSS
/
“*” means under development.
SC600Y&SC600T are SMD-type modules which can be embedded into applications through its 323 pins
(including 152 LCC pads and 171 LGA pads). With a compact profile of 43.0mm × 44.0mm × 2.85mm,
SC600Y&SC600T can meet almost all requirements for M2M applications such as smart metering, smart
home, security, routers, wireless POS, mobile computing devices, PDA phone, tablet PC, etc.
NOTE
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2.2. Key Features
The following table describes the detailed features of SC600Y&SC600T modules.
Table 5: SC600Y&SC600T Key Features
Features
Details
Application Processor
SC600Y-XX
Octa-core ARM Cortex-A53 64-bit CPU @1.8GHz
⚫ Two quad-core processors with 512KB L2 cache
SC600T-XX
Octa-core ARM Cortex-A53 64-bit CPU @2.0GHz (high performance)
⚫ One quad-core with 1MB L2 cache
⚫ One quad-core with 512KB L2 cache
Modem system
Hexagon DSP v56 core up to 850MHz
768KB L2 cache
GPU
SC600Y-XX
AdrenoTM 506 with 64-bit addressing, designed for 600MHz
SC600T-XX
AdrenoTM 506 with 64-bit addressing, designed for 650MHz
Memory
16GB eMMC + 2GB LPDDR3 (default)
32GB eMMC + 4GB LPDDR3 (optional)
Operating System
Android OS 9.0
Power Supply
VBAT Supply Voltage: 3.55V~4.4V
Typical: 3.8V
Transmitting Power
Class 4 (33dBm±2dB) for GSM850
Class 4 (33dBm±2dB) for EGSM900
Class 1 (30dBm±2dB) for DCS1800
Class 1 (30dBm±2dB) for PCS1900
Class E2 (27dBm±3dB) for GSM850 8-PSK
Class E2 (27dBm±3dB) for EGSM900 8-PSK
Class E2 (26dBm±3dB) for DCS1800 8-PSK
Class E2 (26dBm±3dB) for PCS1900 8-PSK
Class 3 (24dBm+1/-3dB) for WCDMA bands
Class 3 (24dBm+3/-1dB) for EVDO/CDMA BC0
Class 2 (24dBm+1/-3dB) for TD-SCDMA bands
Class 3 (23dBm±2dB) for LTE-FDD bands
Class 3 (23dBm±2dB) for LTE-TDD bands
LTE Features
Support 3GPP R8 Cat 6* and Cat 4
Support 1.4 to 20MHz RF bandwidth
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Support Multiuser MIMO in DL direction
⚫ Cat 6* FDD: Max 300Mbps (DL)/Max 50Mbps (UL)
⚫ Cat 6* TDD: Max 265Mbps (DL)/Max 30Mbps (UL)
⚫ Cat 4 FDD: Max 150Mbps (DL)/Max 50Mbps (UL)
⚫ Cat 4 TDD: Max 130Mbps (DL)/Max 30Mbps (UL)
UMTS Features
Support 3GPP R9 DC-HSDPA/DC-HSUPA/HSPA+/HSDPA/HSUPA/WCDMA
Support QPSK, 16-QAM and 64-QAM modulation
⚫ DC-HSDPA: Max 42Mbps (DL)
⚫ DC-HSUPA: Max 11.2Mbps (UL)
⚫ WCDMA: Max 384Kbps (DL)/Max 384Kbps (UL)
GSM Features
R99
CSD: 9.6kbps, 14.4kbps
GPRS
Support GPRS multi-slot class 33 (33 by default)
Coding scheme: CS-1, CS-2, CS-3 and CS-4
Max 107Kbps (DL), 85.6Kbps (UL)
EDGE
Support EDGE multi-slot class 33 (33 by default)
Support GMSK and 8-PSK for different MCS (Modulation and Coding Scheme)
Downlink coding schemes: CS 1-4 and MCS 1-9
Uplink coding schemes: CS 1-4 and MCS 1-9
Max 296Kbps (DL), 236.8Kbps (UL)
WLAN Features
2.4GHz/5GHz, support 802.11a/b/g/n/ac, maximally up to 433Mbps
Support AP and STA mode
Bluetooth Features
BT4.2 LE
GNSS Features
GPS/GLONASS/BeiDou
SMS
Text and PDU mode
Point-to-point MO and MT
SMS cell broadcast
LCM Interfaces
Support two groups of 4-lane MIPI_DSI
Support dual LCDs
Support WUXGA up to (1920×1200) at 60fps
Provide one high voltage output for powering a string of WLEDs
Provide four drivers for sinking the current from WLED strings, and each sink
current can reach up to 25mA
Camera Interfaces
Support three groups of 4-lane MIPI_CSI, up to 2.1Gbps per lane
Support 3 cameras (4-lane + 4-lane + 4-lane) or 4 cameras (4-lane + 4-lane +
2-lane + 1-lane)
SC600Y-XX
up to 21MP with dual ISP
SC600T-XX
up to 24MP with dual ISP
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Video Codec
SC600Y-XX
Video encoding and decoding: up to 1080P @60fps
Wi-Fi Video: encoding up to 1080P @30fps; decoding up to 1080P @60fps
SC600T-XX
Video encoding and decoding: up to 4K @30fps, up to 1080P @60fps
Wi-Fi Video: encoding up to 1080P @30fps; decoding up to 1080P @60fps
Audio Interfaces
Audio Input
Three analog microphone inputs, integrating internal bias voltage
Audio Output
Class AB stereo headphone output
Class AB earpiece differential output
Class D speaker differential amplifier output
Audio Codec
G711, QCELP, EVRC, EVRC-B, EVRC-WB, AMR-NB, AMR-WB, GSM-EFR,
GSM-FR, GSM-HR
USB Interface
Support with USB 3.0 or 2.0 specifications, with transmission rates up to
5Gbps on USB 3.0 and 480Mbps on USB 2.0.
Support USB OTG
Used for AT command communication, data transmission, software debugging
and firmware upgrade
UART Interfaces
4 UART Interfaces: UART5, UART6, UART4 and UART2
⚫ UART5 & UART6: 4-wire UART interface with RTS/CTS hardware flow
control, baud rate up to 4Mbps
⚫ UART4: 2-wire UART interface
⚫ UART2: 2-wire UART interface used for debugging
Vibrator drive interface
Drive ERM vibrator
SD Card Interface
Support SD 3.0
Support SD card hot-plug
(U)SIM Interfaces
2 (U)SIM interfaces
Support USIM/SIM card: 1.8V/2.95V
Support Dual SIM Dual Standby (supported by default)
I2C Interfaces
Five I2C interfaces, used for peripherals such as TP, camera, sensor, etc.
I2S Interface
Support for I2S peripherals
Flashlight Interface
2 high current Flash and torch LED driver
⚫ 1A each for Flash mode and 300mA each for torch mode by default
⚫ 1.5A each for Flash mode and 300mA each for torch mode maximally
ADC Interfaces
2 general purpose ADC interfaces
Support up to 15-bit sampling accuracy
SPI Interfaces
Two SPI interfaces, only support master mode
⚫ One SPI interface used for peripheral device
⚫ One SPI interface used for sensor application, such as fingerprint sensors
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Charging Interface
Used for battery voltage detection, fuel gauge, battery temperature detection
Real Time Clock
Supported
Antenna Interfaces
Main antenna, Rx-diversity antenna, GNSS antenna and Wi-Fi/BT antenna
interfaces
Physical Characteristics
Size: (43.0±0.15)mm × (44.0±0.15)mm × (2.85±0.2)mm
Package: LCC + LGA
Weight: approx. 13.0g
Temperature Range
Operating temperature range: -35°C ~ +65°C
1)
Extended temperature range: -40°C ~ +75°C
2)
Storage temperature range: -40°C ~ +90°C
Firmware Upgrade
Over USB interface
RoHS
All hardware components are fully compliant with EU RoHS directive
1. 1) Within operation temperature range, the module is 3GPP compliant.
2. 2) Within extended temperature range, the module remains the ability to establish and maintain a
voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There
are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like
P
out
might reduce in their value and exceed the specified tolerances. When the temperature returns to
the normal operating temperature levels, the module will meet 3GPP specifications again.
3. “*” means under development.
NOTES
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2.3. Functional Diagram
The following figure shows a block diagram of SC600Y&SC600T and illustrates the major functional
parts.
⚫ Power management
⚫ Radio frequency
⚫ Baseband
⚫ LPDDR3+eMMC flash
⚫ Peripheral interfaces
-- USB interface
-- (U)SIM interfaces
-- UART interfaces
-- SD card interface
-- I2C interfaces
-- ADC interfaces
-- LCM (MIPI) interfaces
-- TP (touch panel) interfaces
-- Camera (MIPI) interfaces
-- Audio interfaces
Baseband
Tranceiver
WCN
LPDDR
eMMC
USB_VBUS
Battery
Flash
WLED
Motor
Charge
OTG
Boost
DIP
XO
ANT_ GNSS
ANT_WiFi/BT
GPIOs
I2C
SD 3.0
UART
2×(U)SIM
USB
2.0/3.0
3×CAM
2×TP2×LCM2×SPI
EAR
SPK
MICs ADCs
HK ADC
Flash
Haptics
RFCLK
BBCLK
MEM
Multimedia
Connectivity
Air Interface
Porcessors
Codec
Power
Signal
Power
Function
SAW
48MHz
5G FEM
Duplexs
PA
PAM
SAW
LNA
SAW
SAW
Switch
SAW
ANT_DRX
ANT_ MAIN
19. 2M
XO
PMU
HK ADC
& MPPs
PWM
Headset
VRTC
VBAT
APT
VDD_RF
LED
PWRKEY
PMI
C1
SD_LDO11
USIM1_VDD
USIM2_VDD
LDO6_1P8
LDO5_1P8
SD_LDO12
LDO22_2P8
LDO10_2P8
LDO17_2P85
LDO23_1P2
LDO2_1P1
I2S
WLED IC
VPH_PWR
Figure 1: Functional Diagram
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2.4. Evaluation Board
In order to help customers develop applications with SC600Y&SC600T conveniently, Quectel supplies
the evaluation board, USB to RS232 converter cable, USB Type-C data cable, power adapter, earphone,
antenna and other peripherals to control or test the module. For more details, please refer to document
[1].
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3 Application Interfaces
3.1. General Description
SC600Y&SC600T are equipped with 323-pin 1.0mm pitch SMT pads that can be embedded into cellular
application platform. The following chapters provide the detailed description of pins/interfaces listed
below.
⚫ Power supply
⚫ VRTC interface
⚫ Charging interface
⚫ USB interface
⚫ UART interfaces
⚫ (U)SIM interfaces
⚫ SD card interface
⚫ GPIO interfaces
⚫ I2C interfaces
⚫ I2S interfaces
⚫ SPI interfaces
⚫ ADC interfaces
⚫ Vibrator drive interface
⚫ LCM interfaces
⚫ TP (touch panel) interfaces
⚫ Camera interfaces
⚫ Flashlight interfaces
⚫ Sensor interfaces
⚫ Audio interfaces
⚫ Emergency download interface
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3.2. Pin Assignment
The following figure shows the pin assignment of SC600Y&SC600T modules.
313
314
315
316
317
318
319
306
307
308
309
310
311
312
299
300
301
302
303
304
305
292
293
294
295
296
297
298
285
286
287
288
289
290
291
278
279
280
281
282
283
284
271
272
273
274
275
276
277
264
265
266
268
269
270
267
257
258
259
261
262
263
260
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
39
41
42
43
44
45
46
47
48
49
51
52
53
54
40
50
555657585960616263
64
323
321
322
2
4
25
26
27
29
28
30
31
32
33
34
35
36
37
38
656667
68
697071
72
737475
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
109
111
112
113
114
115
116
117
118
120
121
122
123
124
125
126
128
129
130
131
132
133
134
135
136
137
138
139
141
142
143
144
145
146
147
148
149
150
151
152
127
140
153
154
155
156
157
158
159
160
161
162
163
164
165
166
119
GND POWER AUDIO USB
(U)SIM SD TP LCM
CAMERA ANT UART GPIO
RESERVED
OTHERS
108
110
182
183
184
185
186
187
188
189
190
191
192
193
194
195
211
212
213
214
215
216
217
218
219
220
221
244
243
242
241
240
239
238
237
236
235
234
2
0
0
2
0
1
2
0
2
2
0
3
2
0
4
2
0
5
2
0
6
2
0
7
2
0
8
2
0
9
2
1
0
196
197
1
9
8
1
9
9
2
4
6
2
4
7
2
4
8
2
4
9
2
5
0
2
5
1
2
5
2
2
5
3
2
5
4
2
5
5
2
5
6
2
4
5
1
7
7
1
7
6
175
1
7
4
1
7
3
1
7
2
1
7
1
1
7
0
1
6
9
1
6
8
1
6
7
1
8
1
1
8
0
1
7
9
1
7
8
2
3
2
2
3
1
230
2
2
9
2
2
8
2
2
7
2
2
6
2
2
5
224
2
2
3
2
2
2
2
3
3
320
Figure 2: Pin Assignment (Top View)
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3.3. Pin Description
Table 6: I/O Parameters Definition
Type
Description
IO
Bidirectional
DI
Digital input
DO
Digital output
PI
Power input
PO
Power output
AI
Analog input
AO
Analog output
OD
Open drain
The following tables show the SC600Y&SC600T’s pin definitions and electrical characteristics.
Table 7: Pin Description
Power Supply
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
VBAT
36, 37,
38
PI/PO
Power supply for the
module
Vmax=4.4V
Vmin=3.55V
Vnorm=3.8V
It must be able to
provide sufficient
current up to 3.0A.
It is suggested to use
a TVS to increase
voltage surge
withstand capability.
VDD_RF
1, 2
PO
Connect to external
bypass capacitors to
eliminate voltage
fluctuation of RF part.
VOmax=4.4V
VOmin=3.55V
VOnorm=3.8V
Do not load
externally.
VPH_PWR
220, 221
PO
Power supply for
peripheral
Vmax=4.4V
Vmin=3.55V
It can provide a
maximum continuous
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Vnorm=3.8V
current of 1A
approximately.
VRTC
16
PI/PO
Power supply for
internal RTC circuit
VOmax=3.2V
VI=2.0V~3.25V
LDO5_1P8
9
PO
1.8V output power
supply
Vnorm=1.8V
IOmax=20mA
Power supply for
external GPIO’s pull
up circuits and level
shift circuit.
LDO10_2P8
11
PO
2.8V output power
supply
Vnorm=2.8V
IOmax=150mA
Power supply for
VDD of sensors and
TPs. Add a
1.0uF~4.7uF bypass
capacitor if used.
If unused, keep this
pin open.
LDO6_1P8
10
PO
1.8V output power
supply
Vnorm=1.8V
IOmax=300mA
Power supply for I/O
VDD of cameras,
LCDs and sensors.
Add a 1.0uF~2.2uF
bypass capacitor if
used.
If unused, keep this
pin open.
LDO17_2P85
12
PO
2.85V output power
supply
Vnorm=2.85V
IOmax=300mA
Power supply for
cameras and LCDs.
Add a 1.0uF~4.7uF
bypass capacitor if
used.
If unused, keep this
pin open.
LDO23_1P2
15
PO
1.2V output power
supply
Vnorm=1.2V
IOmax=600mA
Power supply for
DVDD of front
cameras.
Add a 1.0uF~2.2uF
bypass capacitor if
used.
If unused, keep this
pin open.
LDO2_1P1
13
PO
1.1V output power
supply
Vnorm=1.1V
IOmax=1200mA
Power supply for
DVDD of rear
cameras.
Add a 1.0uF~2.2uF
bypass capacitor if
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used.
If unused, keep this
pin open.
LDO22_2P8
14
PO
2.8V output power
supply
Vnorm=2.8V
IOmax=150mA
Power supply for
AVDD of cameras.
Add a 1.0uF~4.7uF
bypass capacitor if
used.
If unused, keep this
pin open.
GND
3, 4, 18,
20, 31,
34, 35,
40, 43,
47, 56,
62, 87,
98, 101,
112, 125,
128, 130,
133, 135,
148, 150,
159, 163,
170, 173,
176, 182,
193, 195,
219, 225,
243,
257~323
Ground
Audio Interfaces
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
MIC_BIAS
167
AO
Microphone bias
voltage
VO=1.6V~2.85V
MIC1_P
44
AI
Microphone positive
input for channel 1
MIC1_N
45
AI
Microphone negative
input for channel 1
MIC_GND
168
Microphone
reference ground
If unused, connect
this pin to the ground.
MIC2_P
46
AI
Microphone positive
input for headset
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MIC3_P
169
AI
Microphone positive
input for channel 3
EAR_P
53
AO
Earpiece positive
output
EAR_N
52
AO
Earpiece negative
output
SPK_P
55
AO
Speaker positive
output
SPK_N
54
AO
Speaker negative
output
HPH_R
51
AO
Headphone right
channel output
HPH_REF
50
AI
Headphone
reference ground
HPH_L
49
AO
Headphone left
channel output
HS_DET
48
AI
Headset insertion
detection
Pulled up internally.
USB Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
USB_VBUS
41, 42
PI/
PO
Charging power
input.
Power supply output
for OTG device.
USB/charger
insertion detection.
Vmax=10V
Vmin=4.0V
Vnorm=5.0V
USB_DM
33
IO
USB 2.0 differential
data bus (minus)
USB 2.0 standard
compliant
90Ω differential
impedance.
USB_DP
32
IO
USB 2.0 differential
data bus (plus)
USB_ID
30
AI
USB ID detection
High level by default.
USB_SS_RX
_P
171
AI
USB 3.0 differential
receive (plus)
USB 3.0 standard
compliant
90Ω differential
impedance.
USB_SS_RX
_M
172
AI
USB 3.0 differential
receive (minus)
USB_SS_TX
_P
174
AO
USB 3.0 differential
transmit (plus)
90Ω differential
impedance.
USB_SS_TX
_M
175
AO
USB 3.0 differential
transmit (minus)
USBC_CC2
223
AI/
USB Type-C control
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AO
configuration
channel 2
USBC_CC1
224
AI/
AO
USB Type-C control
configuration
channel 1
USB_SS_SEL
226
DO
USB Type-C switch
control
USB_OPT
217
AI
Type-C/ Micro USB
select control
Float, select Type-C.
Connect 1K to GND,
select Micro USB.
(U)SIM Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
USIM1_DET
145
DI
(U)SIM1 card
hot-plug detection
VILmax=0.63V
VIHmin=1.17V
Active Low.
Require external
pull-up to 1.8V.
If unused, keep this
pin open.
Disabled by default,
and can be enabled
through software
configuration.
USIM1_RST
144
DO
(U)SIM1 card reset
signal
VOLmax=0.4V
VOHmin=
0.8 × USIM1_VDD
USIM1_CLK
143
DO
(U)SIM1 card clock
signal
VOLmax=0.4V
VOHmin=
0.8 × USIM1_VDD
USIM1_DATA
142
IO
(U)SIM1 card data
signal
VILmax=
0.2 × USIM1_VDD
VIHmin=
0.7 × USIM1_VDD
VOLmax=0.4V
VOHmin=
0.8 × USIM1_VDD
USIM1_VDD
141
PO
(U)SIM1 card power
supply
1.8V (U)SIM:
Vmax=1.85V
Vmin=1.75V
2.95V (U)SIM:
Vmax=3.1V
Vmin=2.8V
Either 1.8V or 2.95V
(U)SIM card is
supported.
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USIM2_DET
256
DI
(U)SIM2 card
detection
VILmax=0.63V
VIHmin=1.17V
Active Low.
Need external pull-up
to 1.8V.
If unused, keep this
pin open.
Disabled by default,
and can be enabled
through software
configuration.
USIM2_RST
207
DO
(U)SIM2 card reset
signal
VOLmax=0.4V
VOHmin=
0.8 × USIM2_VDD
USIM2_CLK
208
DO
(U)SIM2 card clock
signal
VOLmax=0.4V
VOHmin=
0.8 × USIM2_VDD
USIM2_DATA
209
IO
(U)SIM2 card data
signal
VILmax=
0.2 × USIM2_VDD
VIHmin=
0.7 × USIM2_VDD
VOLmax=0.4V
VOHmin=
0.8 × USIM2_VDD
USIM2_VDD
210
PO
(U)SIM2 card power
supply
1.8V (U)SIM:
Vmax=1.85V
Vmin=1.75V
2.95V (U)SIM:
Vmax=3.1V
Vmin=2.8V
Either 1.8V or 2.95V
(U)SIM card is
supported.
UART Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
UART2_TXD
5
DO
UART2 transmit
data.
Debug port by
default.
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
If unused, keep these
pins open.
UART2_RXD
6
DI
UART2 receive
data.
Debug port by
default.
VILmax=0.63V
VIHmin=1.17V
UART4_TXD
7
DO
UART4 transmit
data
VOLmax=0.45V
VOHmin=1.35V
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UART4_RXD
8
DI
UART4 receive data
VILmax=0.63V
VIHmin=1.17V
UART5_RXD
198
DI
UART5 receive data
VILmax=0.63V
VIHmin=1.17V
UART5_TXD
199
DO
UART5 transmit
data
VOLmax=0.45V
VOHmin=1.35V
UART5_RTS
245
DO
UART5 request to
send
VOLmax=0.45V
VOHmin=1.35V
UART5_CTS
246
DI
UART5 clear to
send
VILmax=0.63V
VIHmin=1.17V
SD Card Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
SD_CLK
70
DO
High speed digital
clock signal of SD
card
1.8V SD card:
VOLmax=0.45V
VOHmin=1.4V
2.95V SD card:
VOLmax=0.37V
VOHmin=2.2V
SD_CMD
69
IO
Command signal of
SD card
1.8V SD card:
VILmax=0.58V
VIHmin=1.27V
VOLmax=0.45V
VOHmin=1.4V
2.95V SD card:
VILmax=0.73V
VIHmin=1.84V
VOLmax=0.37V
VOHmin=2.2V
SD_DATA0
68
IO
High speed
bidirectional digital
signal lines of SD
card
1.8V SD card:
VILmax=0.58V
VIHmin=1.27V
VOLmax=0.45V
VOHmin=1.4V
2.95V SD card:
VILmax=0.73V
VIHmin=1.84V
VOLmax=0.37V
SD_DATA1
67
IO
SD_DATA2
66
IO
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SD_DATA3
65
IO
VOHmin=2.2V
SD_DET
64
DI
SD card insertion
detection
VILmax=0.63V
VIHmin=1.17V
Active low.
SD_LDO11
63
PO
Power supply for SD
card
Vnorm=2.95V
IOmax=800mA
SD_LDO12
179
PO
1.8V/2.95V output
Vnorm=1.8V/2.95V
IOmax=50mA
Power supply for SD
card’s pull-up circuit.
TP (Touch Panel) Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
TP0_RST
138
DO
Reset signal of
touch panel (TP0)
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
Active low.
TP0_INT
139
DI
Interrupt signal of
touch panel (TP0)
VILmax=0.63V
VIHmin=1.17V
1.8V power domain.
TP0_I2C_SCL
140
OD
I2C clock signal of
touch panel (TP0)
1.8V power domain.
TP0_I2C_SDA
206
OD
I2C data signal of
touch panel (TP0)
1.8V power domain.
TP1_RST
136
DO
Reset signal of
touch panel (TP1)
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
Active low.
TP1_INT
137
DI
Interrupt signal of
touch panel (TP1)
VILmax=0.63V
VIHmin=1.17V
1.8V power domain.
TP1_I2C_SDA
204
OD
I2C data signal of
touch panel (TP1)
1.8V power domain.
TP1_I2C_SCL
205
OD
I2C clock signal of
touch panel (TP1)
1.8V power domain.
LCM Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
LCD_BL_A
21
PO
Current output for
LCD backlight
LCD_BL_K1
22
AI
Current sink for LCD
backlight
LCD_BL_K2
23
AI
Current sink for LCD
backlight
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LCD_BL_K3
24
AI
Current sink for LCD
backlight
LCD_BL_K4
25
AI
Current sink for LCD
backlight
PMU_MPP4
152
DO
PWM signal output
LCD0_RST
127
DO
LCD0 reset signal
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
Active low.
LCD0_TE
126
DI
LCD0 tearing effect
signal
VILmax=0.63V
VIHmin=1.17V
1.8V power domain.
LCD1_RST
113
DO
LCD1 reset signal
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
Active low.
LCD1_TE
114
DI
LCD1 tearing effect
signal
VILmax=0.63V
VIHmin=1.17V
1.8V power domain.
DSI0_CLK_N
116
AO
LCD0 MIPI clock
signal (negative)
DSI0_CLK_P
115
AO
LCD0 MIPI clock
signal (positive)
DSI0_LN0_N
118
AO
LCD0 MIPI lane 0
data signal (negative)
DSI0_LN0_P
117
AO
LCD0 MIPI lane 0
data signal (positive)
DSI0_LN1_N
120
AO
LCD0 MIPI lane 1
data signal (negative)
DSI0_LN1_P
119
AO
LCD0 MIPI lane 1
data signal (positive)
DSI0_LN2_N
122
AO
LCD0 MIPI lane 2
data signal (negative)
DSI0_LN2_P
121
AO
LCD0 MIPI lane 2
data signal (positive)
DSI0_LN3_N
124
AO
LCD0 MIPI lane 3
data signal (negative)
DSI0_LN3_P
123
AO
LCD0 MIPI lane 3
data signal (positive)
DSI1_CLK_N
103
AO
LCD1 MIPI clock
signal (negative)
DSI1_CLK_P
102
AO
LCD1 MIPI clock
signal (positive)
DSI1_LN0_N
105
AO
LCD1 MIPI lane 0
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data signal (negative)
DSI1_LN0_P
104
AO
LCD1 MIPI lane 0
data signal (positive)
DSI1_LN1_N
107
AO
LCD1 MIPI lane 1
data signal (negative)
DSI1_LN1_P
106
AO
LCD1 MIPI lane 1
data signal (positive)
DSI1_LN2_N
109
AO
LCD1 MIPI lane 2
data signal (negative)
DSI1_LN2_P
108
AO
LCD1 MIPI lane 2
data signal (positive)
DSI1_LN3_N
111
AO
LCD1 MIPI lane 3
data signal (negative)
DSI1_LN3_P
110
AO
LCD1 MIPI lane 3
data signal (positive)
Camera Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
CSI0_CLK_N
89
AI
MIPI clock signal of
rear camera
(negative)
CSI0_CLK_P
88
AI
MIPI clock signal of
rear camera (positive)
CSI0_LN0_N
91
AI
MIPI lane 0 data
signal of rear camera
(negative)
CSI0_LN0_P
90
AI
MIPI lane 0 data
signal of rear camera
(positive)
CSI0_LN1_N
93
AI
MIPI lane 1 data
signal of rear camera
(negative)
CSI0_LN1_P
92
AI
MIPI lane 1 data
signal of rear camera
(positive)
CSI0_LN2_N
95
AI
MIPI lane 2 data
signal of rear camera
(negative)
CSI0_LN2_P
94
AI
MIPI lane 2 data
signal of rear camera
(positive)
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CSI0_LN3_N
97
AI
MIPI lane 3 data
signal of rear camera
(negative)
CSI0_LN3_P
96
AI
MIPI lane 3 data
signal of rear camera
(positive)
CSI1_CLK_N
184
AI
MIPI clock signal of
depth camera
(negative)
CSI1_CLK_P
183
AI
MIPI clock signal of
depth camera
(positive)
CSI1_LN0_N
186
AI
MIPI lane 0 data
signal of depth
camera (negative)
CSI1_LN0_P
185
AI
MIPI lane 0 data
signal of depth
camera (positive)
CSI1_LN1_N
188
AI
MIPI lane 1 data
signal of depth
camera (negative)
CSI1_LN1_P
187
AI
MIPI lane 1 data
signal of depth
camera (positive)
CSI1_LN2_N
190
AI
MIPI lane 2 data
signal of depth
camera (negative)
Can be multiplexed
into differential data
of the fourth camera
(negative).
CSI1_LN2_P
189
AI
MIPI lane 2 data
signal of depth
camera (positive)
Can be multiplexed
into differential data
of the fourth camera
(positive).
CSI1_LN3_N
192
AI
MIPI lane 3 data
signal of depth
camera (negative)
Can be multiplexed
into differential clock
of the fourth camera
(negative).
CSI1_LN3_P
191
AI
MIPI lane 3 data
signal of depth
camera (positive)
Can be multiplexed
into differential clock
of the fourth camera
(positive).
CSI2_CLK_N
78
AI
MIPI clock signal of
front camera
(negative)
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CSI2_CLK_P
77
AI
MIPI clock signal of
front camera
(positive)
CSI2_LN0_N
80
AI
MIPI lane 0 data
signal of front camera
(negative)
CSI2_LN0_P
79
AI
MIPI lane 0 data
signal of front camera
(positive)
CSI2_LN1_N
82
AI
MIPI lane 1 data
signal of front camera
(negative)
CSI2_LN1_P
81
AI
MIPI lane 1 data
signal of front camera
(positive)
CSI2_LN2_N
84
AI
MIPI lane 2 data
signal of front camera
(negative)
CSI2_LN2_P
83
AI
MIPI lane 2 data
signal of front camera
(positive)
CSI2_LN3_N
86
AI
MIPI lane 3 data
signal of front camera
(negative)
CSI2_LN3_P
85
AI
MIPI lane 3 data
signal of front camera
(positive)
MCAM_MCLK
99
DO
Master clock signal of
rear camera
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
SCAM_MCLK
100
DO
Master clock signal of
front camera
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
MCAM_RST
74
DO
Reset signal of rear
camera
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
MCAM_PWDN
73
DO
Power down signal of
rear camera
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
SCAM_RST
72
DO
Reset signal of front
camera
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
SCAM_PWDN
71
DO
Power down signal of
front camera
VOLmax=0.45V
VOHmin=1.35V
1.8V power domain.
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CAM_I2C_SCL
75
OD
I2C clock signal of
camera
1.8V power domain.
CAM_I2C_SDA
76
OD
I2C data signal of
camera
1.8V power domain.
DCAM_MCLK
194
DO
Master clock signal of
depth camera
VOLmax=0.45V
VOHmin=1.35V
CAM4_MCLK
236
DO
Master clock signal of
fourth camera
VOLmax=0.45V
VOHmin=1.35V
DCAM_RST
180
DO
Reset signal of depth
camera
VOLmax=0.45V
VOHmin=1.35V
DCAM_PWDN
181
DO
Power down signal of
depth camera
VOLmax=0.45V
VOHmin=1.35V
DCAM_I2C_
SDA
197
OD
I2C data signal of
depth camera
1.8V power domain.
DCAM_I2C_
SCL
196
OD
I2C clock signal of
depth camera
1.8V power domain.
Keypad Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
PWRKEY
39
DI
Turn on/off the
module
VILmax=0.63V
VIHmin=1.17V
Pull-up to 1.8V
internally.
Active low.
VOL_UP
146
DI
Volume up
VILmax=0.63V
VIHmin=1.17V
If unused, keep this
pin open.
VOL_
DOWN
147
DI
Volume down
VILmax=0.63V
VIHmin=1.17V
If unused, keep this
pin open.
SENSOR_I2C Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
SENSOR_I2C_
SCL
131
OD
I2C clock signal of
external sensors
1.8V power domain.
SENSOR_I2C_
SDA
132
OD
I2C data signal of
external sensors
1.8V power domain.
ADC Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
PMI_ADC
153
AI
General purpose ADC
interface
Maximum input
voltage: 1.5V.
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PMU_MPP2
151
AI
General purpose ADC
interface
Maximum input
voltage: 1.7V.
Charging Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
BAT_PLUS
27
AI
Differential input
signal of battery
voltage detection
(plus)
Must be connected.
BAT_MINUS
28
AI
Differential input
signal of battery
voltage detection
(minus)
Must be connected.
Antenna Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
ANT_MAIN
19
IO
Main antenna
interface
50Ω impedance
ANT_DRX
149
AI
Diversity antenna
interface
ANT_GNSS
134
AI
GNSS antenna
interface
ANT_WIFI/BT
129
IO
Wi-Fi/BT antenna
interface
GPIO Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
GPIO_0
248
IO
GPIO
VILmax=0.63V
VIHmin=1.17V
VOLmax=0.45V
VOHmin=1.4V
GPIO_1
247
IO
GPIO
GPIO_2
201
IO
GPIO
GPIO_3
200
IO
GPIO
GPIO_33
238
IO
GPIO
GPIO_36
237
IO
GPIO
GPIO_42
252
IO
GPIO
GPIO_43
253
IO
GPIO
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GPIO_44
254
IO
GPIO
GPIO_45
255
IO
GPIO
GPIO_66
234
IO
GPIO
GPIO_89
232
IO
GPIO
GPIO_90
231
IO
GPIO
GPIO_96
230
IO
GPIO
GPIO_97
229
IO
GPIO
GPIO_98
177
IO
GPIO
GPIO_99
178
IO
GPIO
GPIO_105
242
IO
GRFC1
GRFC is only used
for RF Tuner control.
GPIO_107
241
IO
GRFC2
SPI Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
SPI_CS
58
DO
Chip selection signal
of SPI interface
Can be multiplexed
into UART6_CTS.
SPI_CLK
59
DO
Clock signal of SPI
interface
Can be multiplexed
into UART6_RTS.
SPI_MOSI
60
DO
Master out slave in of
SPI interface
Can be multiplexed
into UART6_TXD.
SPI_MISO
61
DI
Master in salve out of
SPI interface
Can be multiplexed
into UART6_RXD.
FP_SPI_CS
203
DO
Chip selection signal
of SPI interface
Can be multiplexed
into I2S_WS.
FP_SPI_CLK
250
DO
Clock signal of SPI
interface
Can be multiplexed
into I2S_SCK.
FP_SPI_MOSI
249
DO
Master out slave in of
SPI interface
Can be multiplexed
into I2S_D0.
FP_SPI_MISO
251
DI
Master in salve out of
SPI interface
Can be multiplexed
into I2S_D1.
Vibrator Drive Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
VIB_GND
160
AI
Vibrator GND
Connected to the
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(negative)
negative terminal of
vibrator.
VIB_DRV
161
AO
Vibrator drive
(positive)
Connected to the
positive terminal of
vibrator.
Flashlight Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
FLASH_LED1
26
AO
Flash/torch current
driver output
Support flash and
torch modes.
FLASH_LED2
162
AO
Flash/torch current
driver output
Emergency Download Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
USB_BOOT
57
DI
Force the module to
enter into emergency
download mode
Pulled up to
LDO5_1P8 during
power-up will force
the module to enter
into emergency
download mode.
Other Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
BAT_ID
17
AI
Battery type detection
If unused, keep this
pin open.
BAT_THERM
29
AI
Battery temperature
detection
Internally pulled up.
Externally connected
to GND via a 47K
NTC resistor.
GNSS_LNA_EN
202
DO
LNA enable control
For test purpose only.
If unused, keep this
pin open.
S1A
215
S1A and S1B are
connected together in
the module
S1B
216
S2A
211
S2A and S2B are
connected together in
the module
S2B
233
Reserved Interface
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Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
RESERVED
154, 155,
156, 157,
158, 164,
165, 166,
212, 213,
214, 218,
222, 235,
239, 240,
Reserved pins
Keep these pins
open.
3.4. Power Supply
3.4.1. Power Supply Pins
SC600Y&SC600T provide 3 VBAT pins , 2 VDD_RF pins and 2 VPH_PWR pins. VBAT pins are
dedicated for connection with an external power supply. VDD_RF pins are designed for module’s RF part,
and are used to connect bypass capacitors so as to eliminate voltage fluctuation of RF part. VPH_PWR
pins can supply power for peripherals, and it can provide a maximum continuous current of 1A
approximately.
3.4.2. Decrease Voltage Drop
The power supply range of the module is from 3.55V to 4.4V, and the recommended value is 3.8V. The
power supply performance, such as load capacity, voltage ripple, etc. directly influences the module’s
performance and stability. Under ultimate conditions, the module may have a transient peak current up to
3A. If the power supply capability is not sufficient, there will be voltage drops, and if the voltage drops
below 3.1V, the module will be powered off automatically. Therefore, please make sure the input voltage
will never drop below 3.1V.
3.1V
Voltage
3.8V
Input current
3A
Figure 3: Voltage Drop Sample
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To decrease voltage drop, a bypass capacitor of about 100µF with low ESR (ESR=0.7Ω) should be used,
and a multi-layer ceramic chip capacitor (MLCC) array should also be reserved due to its ultra-low ESR. It
is recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array,
and place these capacitors close to VBAT/VDD_RF/VPH_PWR pins. The width of VBAT trace should be
no less than 3mm. In principle, the longer the VBAT trace is, the wider it will be.
In addition, in order to get a stable power source, it is suggested to use a 0.5W TVS and place it as close
to the VBAT pins as possible to increase voltage surge withstand capability. The following figure shows
the structure of the power supply.
Module
VPH_PWR
VBAT
VBAT
C1
100uF
C6
100nFC733pFC810pF
+
+
C2
100nF
C5
NM
C3
33pF
C4
10pF
D1
VDD_RF
VPH_PWR
C
10
100nF
C
11
33pF
C
12
10pF
C9
+
NM
Figure 4: Star Structure of Power Supply
3.4.3. Reference Design for Power Supply
The power design for the module is very important, as the performance of module largely depends on the
power source. The power supply of SC600Y&SC600T should be able to provide sufficient current up to
3A at least. By default, it is recommended to use a battery to supply power for SC600Y&SC600T. But if
battery is not intended to be used, it is recommended to use a regulator for SC600Y&SC600T. If the
voltage difference between the input and output is not too high, it is suggested to use an LDO to supply
power for the module. If there is a big voltage difference between the input source and the desired output
(VBAT), a buck converter is preferred to be used as the power supply.
The following figure shows a reference design for +5V input power source which adopts an LDO
(MIC29502WU) from MICROCHIP. The typical output voltage is 3.8V and the maximum rated current is
5.0A.
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DC_IN
C1
C2
MIC29502WU U1
IN
OUT
EN
GND
ADJ
2 4
1
3
5
VBAT
100nF
C3
470uF
C4
100nF
R2
100K
47K
R3
470uF
470R
51K
R4
R1
1%
1%
Figure 5: Reference Circuit of Power Supply
1. It is recommended to switch off the power supply for module in abnormal state, and then switch on
the power to restart the module.
2. The module supports battery charging function by default. If the above power supply design is
adopted, please make sure the charging function is disabled by software, or connect VBAT to
Schottky diode in series to avoid the reverse current to the power supply chip.
3. When the battery power is reduced to 0%, the system will trigger automatic shutdown, so the design
of power supply should be consistent with the configuration of fuel gauge driver.
3.5. Turn on and off Scenarios
3.5.1. Turn on Module Using the PWRKEY
The module can be turned on by driving PWRKEY pin to a low level for at least 1.6s. PWRKEY pin is
pulled to 1.8V internally. It is recommended to use an open drain/collector driver to control the PWRKEY.
A simple reference circuit is illustrated in the following figure.
NOTES
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Turn on pulse
PWRKEY
4.7K
47K
>1.6s
R1
R2
Q1
R3
1K
Figure 6: Turn on the Module Using Driving Circuit
Another way to control the PWRKEY is using a button directly. A TVS component is indispensable to be
placed nearby the button for ESD protection. A reference circuit is shown in the following figure.
PWRKEY
S1
Close to S1
TVS
1K
Figure 7: Turn on the Module Using Keystroke
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The turning on scenario is illustrated in the following figure.
VBAT(Typ.:3.8V)
PWRKEY
>1.6s
Others
LDO5_1P8
38s
LDO6_1P8
61.2ms
Software
controlled
LDO17_2P85
Active
LDO10_2P8
Note2
Software
controlled
Figure 8: Timing of Turning on Module
1. The turn-on timing might be different from the above figure when the module powers on for the first
time.
2. Make sure that VBAT is stable before pulling down PWRKEY pin. The recommended time between
them is no less than 30ms. PWRKEY cannot be pulled down all the time.
3.5.2. Turn off Module
Pull down PWRKEY for at least 1s, and then choose to turn off the module when the prompt window
comes up.
Another way to turn off the module is to drive PWRKEY to a low level for at least 8s. The module will
execute forced shutdown. The forced power-down scenario is illustrated in the following figure.
NOTES
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VBAT
PWRKEY
Others
> 8
s
Power down
Figure 9: Timing of Turning off Module
3.6. VRTC Interface
The RTC (Real Time Clock) can be powered by an external power source through VRTC when the
module is powered down and there is no power supply for the VBAT. The external power source can be
rechargeable battery (such as coil cells) according to application demands. The following reference circuit
design when an external battery is utilized for powering RTC.
Coin Cell
Module
RTC
Core
VRTC
Figure 10: RTC Powered by Coin Cell
If RTC is ineffective, it can be synchronized through network after the module is powered on.
⚫ 2.0V~3.25V input voltage range and 3.0V typical value for VRTC, when VBAT is disconnected.
⚫ When powered by VBAT, the RTC error is 50ppm. When powered by VRTC, the RTC error is about
200ppm.
⚫ If the rechargeable battery is used, the ESR of battery should be less than 2K, and it is
recommended to use the MS621FE FL11E of SEIKO.
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3.7. Power Output
SC600Y&SC600T support output of regulated voltages for peripheral circuits. During application, it is
recommended to use parallel capacitors (33pF and 10pF) in the circuit to suppress high frequency noise.
Table 8: Power Description
Pin Name
Default Voltage (V)
Drive Current (mA)
Idle
LDO5_1P8
1.8
20
Keep
LDO6_1P8
1.8
300
/
LDO10_2P8
2.8
150
/
LDO17_2P85
2.85
300
/
LDO2_1P1
1.1
1200
/
LDO22_2P8
2.8
150
/
LDO23_1P2
1.2
600
/
SD_LDO12
1.8/2.95
50 / SD_LDO11
2.95
800
/
USIM1_VDD
1.8/2.95
50 / USIM2_VDD
1.8/2.95
50
/
3.8. Battery Charge and Management
SC600Y&SC600T modules support a fully programmable switch-mode Li-ion battery charge function. It
can charge single-cell Li-ion and Li-polymer battery. The battery charger of SC600Y&SC600T modules
supports trickle charging, pre-charge, constant current charging and constant voltage charging modes,
which optimize the charging procedure for Li-ion batteries.
⚫ Trickle charging: When the battery voltage is below 2.1V, a 75mA trickle charging current is applied
to the battery.
⚫ Pre-charge: When the battery voltage is charged up and is between 2.1V and 3.0V (the maximum
pre-charge voltage is 2.3V~3.0V programmable, 3.0V by default), the system will enter into
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pre-charge mode. The charging current is 450mA (100mA~450mA programmable, 450mA by
default).
⚫ Constant current mode (CC mode): When the battery voltage is increased to between the
maximum pre-charge voltage and 4.2V (3.6V~4.5V programmable, 4.2V by default), the system will
switch to CC mode. The charging current is programmable from 300mA~3000mA. The default
charging current is 500mA for USB charging and 2A for adapter.
⚫ Constant voltage mode (CV mode): When the battery voltage reaches the final value 4.2V, the
system will switch to CV mode and the charging current will decrease gradually. When the charging
current reduces to about 100mA, the charging is completed.
Table 9: Pin Definition of Charging Interface
Pin Name
Pin No.
I/O Description
Comment
USB_VBUS
41, 42
PI/PO
Charging power input.
Power supply output for OTG device.
USB/charger insertion detection.
Vmax=10V
Vmin=4.0V
Vnorm=5.0V
VBAT
36, 37,
38
PI/PO
Power supply for the module
Vmax=4.4V
Vmin=3.55V
Vnorm=3.8V
BAT_ID
17
AI
Battery type detection
If unused, keep this
pin open.
BAT_PLUS
27
AI
Differential input signal of battery voltage
detection (plus)
Must be connected.
BAT_MINUS
28
AI
Differential input signal of battery voltage
detection (minus)
Must be connected.
BAT_THERM
29
AI
Battery temperature detection
Internally pulled up.
Externally connected
to GND via a 47K
NTC resistor.
SC600Y&SC600T modules support battery temperature detection in the condition that the battery
integrates a thermistor (47K 1% NTC thermistor with B-constant of 4050K by default;
SDNT1608X473F4050FTF of SUNLORD is recommended) and the thermistor is connected to
BAT_THERM pin. If BAT_THERM pin is not connected, there will be malfunctions such as boot error,
battery charging failure, battery level display error, etc.
A reference design for battery charging circuit is shown as below.
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GND
BAT_THERM
VBAT
0R
100uF
NTC
VBAT
33pF
1uF
ESD
USB_VBUS
Adapter or USB
Module
Battery
C1 C2 C3
R1
D1
D2
BAT_PLUS
ESD
BAT_MINUS
GND
0805
Figure 11: Reference Design for Battery Charging Circuit
SC600Y&SC600T offer a fuel gauge algorithm that is able to accurately estimate the battery’s state by
current and voltage monitor techniques. Using precise measurements of battery voltage, current, and
temperature, the fuel gauge provides a dependable state of charge estimate throughout the entire life of
the battery and across a broad range of operating conditions. It effectively protects the battery from
over-discharging, and also allows users to estimate the battery life based on the battery level so as to
timely save important data before completely power-down.
Mobile devices such as mobile phones and handheld POS systems are powered by batteries. When
different batteries are utilized, the charging and discharging curve has to be modified correspondingly so
as to achieve the best effect.
If thermistor is not available in the battery, or adapter is utilized for powering the module, then there is only
a need for VBAT and GND connection. In this case, the system may be unable to detect the battery,
which will cause power-on failure. In order to avoid this, BAT_THERM should be connected to GND with a
47KΩ resistor. BAT_PLUS and BAT_MINUS must be connected, otherwise there may be abnormalities in
use of the module. Among them, BAT_PLUS and BAT_MINUS are used for battery level detection, and
they should be routed as differential pair to ensure accuracy.
3.9. USB Interface
SC600Y&SC600T provide one integrated Universal Serial Bus (USB) interface which complies with the
USB 3.0/2.0 specifications and supports super speed (5Gbps) on USB 3.0, high speed (480Mbps) on
USB 2.0 and full speed (12Mbps) modes. The USB interface supports USB OTG function, and is used for
AT command communication, data transmission, software debugging and firmware upgrade.
The following table shows the pin definition of USB interface.
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Table 10: Pin Definition of USB Interface
Pin Name
Pin No.
I/O
Description
Comment
USB_VBUS
41, 42
PI/PO
Charging power input;
Power supply output for OTG device;
USB/charger insertion detection.
Vmax=10V
Vmin=4.0V
Vnorm=5.0V
USB_DM
33
IO
USB 2.0 USB differential data bus
(minus)
Require differential
impedance of 90Ω
USB_DP
32
IO
USB 2.0 USB differential data bus
(plus)
USB_ID
30
AI
USB ID detection
High level by default
USB_SS_RX_P
171
AI
USB 3.0 differential receive (plus)
Require differential
impedance of 90Ω
USB_SS_RX_M
172
AI
USB 3.0 differential receive (minus)
USB_SS_TX_P
174
AO
USB 3.0 differential transmit (plus)
USB_SS_TX_M
175
AO
USB 3.0 differential transmit (minus)
USBC_CC2
223
AI/
AO
USB Type-C control configuration
channel 2
USBC_CC1
224
AI/
AO
USB Type-C control configuration
channel 1
USB_SS_SEL
226
DO
USB Type-C switch control
USB_OPT
217
AI
Type-C/ Micro USB select control
Float，select Type-C.
Connect 1K to GND,
select Micro USB.
USB_VBUS can be powered by USB power or adapter. It is used for USB connection detection and
power supply input for battery charging. Its input voltage ranges from 4.0V to 10.0V, and the typical value
is 5.0V. SC600Y&SC600T modules support charging management for a single cell Li-ion battery, but
varied charging parameters should be set for batteries with varied models or capacities. The maximum
charging current is up to 3.0A.
The module also supports USB On-The-Go (OTG) function, through using USB_ID pin to detect whether
the OTG device is attached: when USB_ID is kept open (high level by default), SC600Y&SC600T are in
USB slave mode; if USB_ID is connected to ground, it is in OTG mode and USB_VBUS is used to supply
power for peripherals with maximum output of 5V/1A.
The switch between Type-C and Micro USB is determined by USB_OPT of pin 217. If USB_OPT is
floating, It is only need to select Type-C. If USB_OPT connects to GND via 1K, It is only need to select
Micro USB .
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The following is a reference design for USB interface:
USB_DP
USB_DM
USB_VUSB
1
2
3
4
5
USB_DP
USB_DM
VUSB
USB_ID
GND
GND
GND
GND
GND
6
7 8
9
100nF
Module
C1
D1
D2 D3
ESD ESD ESD
USB_ID
USB_OPT
1K
R1
Figure 12: Micro USB Interface Reference Design
USB_DP
100nF
Module
C14
Switch
C2
C3
C4
C5
A0+
A0-
A1+
A0-
B0+
B0-
B1+
B1-
C0+
C0-
C1+
C1-
SEL
PD
USB_SS_TX_P
USB_SS_TX_M
USB_SS_RX_P
USB_SS_RX_M
USB_SS_SEL
R1
VDD
4.7uF
C1
VDD_3V
TX1+
TX1-
VBUS_ VBUS
CC
1
D+
D-
RX1-
RX1+
CC2
CC1
CC2
TX2+
TX2RX2+
RX2-
USB 3.0
C6
C7
C8
C9
C10
C11
C12
C13
USB_ DM
USB_ VBUS
R1
NM
USB_OPT
Figure 13: USB Type-C Interface Reference Design
In order to ensure USB performance, please follow the following principles while designing USB interface.
⚫ It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90Ω.
⚫ Pay attention to the influence of junction capacitance of ESD protection devices on USB data lines.
Typically, the capacitance value should be less than 2pF for USB 2.0 and less than 0.5pF for USB
3.0.
⚫ Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.
⚫ Keep the ESD protection devices as close as possible to the USB connector.
⚫ Make sure the trace length difference between USB 2.0 DM/DP differential pair and that between
USB 3.0 RX/TX differential pairs both do not exceed 0.7mm.
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Table 11: USB Trace Length Inside the Module
Pin No.
Signal
Length (mm)
Length Difference (DP-DM)
33
USB_DM
39.52
-0.45
32
USB_DP
39.07
171
USB_SS_RX_P
28.55
0.32
172
USB_SS_RX_M
28.23
174
USB_SS_TX_P
19.58
0.23
175
USB_SS_TX_M
19.35
3.10. UART Interfaces
The module provides the following four UART interfaces:
⚫ UART5: 4-wire UART interface, hardware flow control supported, 1.8V power domain
⚫ UART6: 4-wire UART interface, hardware flow control supported, multiplexed from SPI interface
⚫ UART2: 2-wire UART interface, used for debugging
⚫ UART4: 2-wire UART interface
The following table shows the pin definition of UART interfaces.
Table 12: Pin Definition of UART Interfaces
Pin Name
Pin No.
I/O
Description
Comment
UART2_TXD
5
DO
UART2 transmit data.
Debug port by default.
1.8V power domain.
If unused, keep these pins
open.
UART2_RXD
6
DI
UART2 receive data.
Debug port by default.
UART4_TXD
7
DO
UART4 transmit data
UART4_RXD
8
DI
UART4 receive data
UART5_RXD
198
DI
UART5 receive data
UART5_TXD
199
DO
UART5 transmit data
UART5_CTS
246
DI
UART5 clear to send
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UART5_RTS
245
DO
UART5 request to send
SPI_MISO
61
DI
UART6 receive data
SPI interface pin by default.
Can be multiplexed into
UART6_RXD.
SPI_MOSI
60
DO
UART6 transmit data
SPI interface pin by default.
Can be multiplexed into
UART6_TXD.
SPI_CS
58
DI
UART6 clear to send
SPI interface pin by default.
Can be multiplexed into
UART6_CTS.
SPI_CLK
59
DO
UART6 request to send
SPI interface pin by default.
Can be multiplexed into
UART6_RTS.
UART5 is a 4-wire UART interface with 1.8V power domain. A level translator chip should be used if
customers’ application is equipped with a 3.3V UART interface. A level translator chip TXS0104EPWR
provided by Texas Instruments is recommended.
The following figure shows a reference design.
VCCA
VCCB
OE
A1
A2
A3
A4
GND
B1
B2
B3
B4
LDO5_1P8
UART
5_ RTS
UART5_ RXD
UART
5_ CTS
UART5_ TXD
RXD_3.3V
CTS_3.3V
TXD_3.3V
VDD_3.3V
TXS0104 EPWR
C1
100pF
C2
U1
100
pF
RTS_3.3V
Figure 14: Reference Circuit with Level Translator Chip (for UART5)
The following figure is an example of connection between SC600Y&SC600T and PC. A voltage level
translator and a RS-232 level translator chip are recommended to be added between the module and PC,
as shown below:
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TXS0104 EPWR
RXD_3.3V
CTS_3.3V
VCCA
Module
GND
GND
1.8V
VCCB
3.3V
DIN 1
ROUT3
ROUT 2
ROUT1
DIN4
DIN3
DIN 2
DIN 5
FORCEON
3.3V
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
RIN3
RIN2
RIN1
VCC GND
OE
SN65C 3238 DB-9
RTS
TXD
CTS
RXD
GND
RTS_3.3V
UART5_TXD
UART5_RTS
UART5_RXD
UART5_CTS
TXD_1.8V
RTS_1.8V
RXD_1.8V
CTS_1.8V
/FORCEOFF
/INVALID
R1OUTB
TXD_3.3V
Figure 15: RS232 Level Match Circuit (for UART5)
UART2, UART4 and UART6 are similar to UART5. Please refer to UART5 reference circuit design for
UART2, UART4 and UART6’s.
3.11. (U)SIM Interfaces
SC600Y&SC600T provide two (U)SIM interfaces which both meet ETSI and IMT-2000 requirements.
Dual SIM Dual Standby is supported by default. Both 1.8V and 2.95V (U)SIM cards are supported, and
the (U)SIM interfaces are powered by the dedicated low dropout regulators from SC600Y&SC600T
modules.
Table 13: Pin Definition of (U)SIM Interfaces
Pin Name
Pin No.
I/O
Description
Comment
USIM1_DET
145
DI
(U)SIM1 card detection
Active Low.
Need external pull-up to 1.8V.
If unused, keep this pin open.
Disabled by default, and can be
enabled through software
configuration.
USIM1_RST
144
DO
(U)SIM1 card reset signal
NOTE
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USIM1_CLK
143
DO
(U)SIM1 card clock signal
USIM1_DATA
142
IO
(U)SIM1 card data signal
Pull up to USIM1_VDD with a 10K
resistor.
USIM1_VDD
141
PO
(U)SIM1 card power supply
Either 1.8V or 2.95V (U)SIM card
is supported.
USIM2_DET
256
DI
(U)SIM2 card insertion
detection
Active low.
Need external pull-up to 1.8V.
If unused, keep this pin open.
Disabled by default, and can be
enabled through software
configuration.
USIM2_RST
207
DO
(U)SIM2 card reset signal
USIM2_CLK
208
DO
(U)SIM2 card clock signal
USIM2_DATA
209
IO
(U)SIM2 card data signal
Pull-up to USIM2_VDD with a 10K
resistor.
USIM2_VDD
210
PO
(U)SIM2 card power supply
Either 1.8V or 2.95V (U)SIM card
is supported.
SC600Y&SC600T support (U)SIM card hot-plug via the USIM_DET pin, which is disabled by default and
can be enabled through software configuration. A reference circuit for (U)SIM interface with an 8-pin
(U)SIM card connector is shown as below.
USIM_ VDD
USIM_ RST
USIM_ CLK
USIM_ DATA
USIM_ DET
22R
LD05_1P8
100K
100nF
(U)SIM Card Connector
ESD
22pF
VCC
RST
CLK
IO
VPP
GND
USIM_ VDD
10K
Module
R1
R2
C1
22pF22pF
C2 C3 C 4
D1
22R
22R
R3
R4
R5
Figure 16: Reference Circuit for (U)SIM Interface with an 8-pin (U)SIM Card Connector
If there is no need to use USIM_DET, please keep it open. The following is a reference circuit for (U)SIM
interface with a 6-pin (U)SIM card connector.
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Module
USIM_ VDD
USIM_ RST
USIM_ CLK
USIM_ DATA
22R
22R
22R
100nF
ESD
22pF
VCC
RST
CLK IO
VPP
GND
10K
USIM_VDD
22pF
22pF
R1
C1
D1
R2
R3
R4
C2 C3 C4
USIM_ DET
(U)SIM Card Connector
Figure 17: Reference Circuit for (U)SIM Interface with a 6-pin (U)SIM Card Connector
In order to ensure good performance and avoid damage of (U)SIM cards, please follow the criteria below
in (U)SIM circuit design:
⚫ Keep placement of (U)SIM card connector as close to the module as possible. Keep the trace length
of (U)SIM card signals as less than 200mm as possible.
⚫ Keep (U)SIM card signals away from RF and VBAT traces.
⚫ A filter capacitor shall be reserved for USIM_VDD, and its maximum capacitance should not exceed
1uF. The capacitor should be placed near to (U)SIM card.
⚫ To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with ground. USIM_RST also needs ground protection.
⚫ In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic
capacitance not exceeding 50pF. The 22Ω resistors should be added in series between the module
and (U)SIM card so as to suppress EMI spurious transmission and enhance ESD protection. Please
note that the (U)SIM peripheral circuit should be close to the (U)SIM card connector.
⚫ The 22pF capacitors should be added in parallel on USIM_DATA, USIM_CLK and USIM_RST signal
lines so as to filter RF interference, and they should be placed as close to the (U)SIM card connector
as possible.
3.12. SD Card Interface
SC600Y&SC600T modules support SD 3.0 specifications. The pin definition of the SD card interface is
shown below.
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Table 14: Pin Definition of SD Card Interface
Pin Name
Pin No.
I/O Description
Comment
SD_LDO11
63
PO
Power supply for SD card
Vnorm=2.95V
IOmax=800mA
SD_LDO12
179
PO
SD card pull-up power
supply
Support 1.8V or 2.95V power supply.
The maximum drive current is 50mA.
SD_CLK
70
DO
High speed digital clock
signal of SD card
Control characteristic impedance as
50Ω.
SD_CMD
69
I/O
Command signal of SD card
SD_DATA0
68
I/O
High speed bidirectional
digital signal lines of SD
card
SD_DATA1
67
I/O
SD_DATA2
66
I/O
SD_DATA3
65
I/O
SD_DET
64
DI
SD card insertion detection
Active low.
A reference circuit for SD card interface is shown as below.
SD_CMD
120K
NM_51K
SD_DATA3
SD_DATA2
LDO5_1P8
SD_CLK
SD_DATA0
SD_DET
SD_DATA1
P1-DAT2
P2-CD/DAT3
P3-CMD
P4-VDD
P5-CLK
P8-DAT1
GND
P6-VSS
P7-DAT0
DETECTIVE
GND
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
SD_LDO11
33R
33R
33R
33R
33R
33R
1K
33pF
4.7uF
SD_LDO12
Module
R1 R2
R3 R4
R5
R6
NM_51K
NM_10K
NM_51K
NM_51K
R7
R8
R9
R10
R11
R12
R13
D1 D2
D3
D4 D5
D6
D7
D8
C1
C2
SD Card Connector
Figure 18: Reference Circuit for SD Card Interface
SD_LDO11 is a peripheral driver power supply for SD card. The maximum drive current is approximate
800mA. Because of the high drive current, it is recommended that the trace width is 0.5mm or above. In
order to ensure the stability of drive power, a 4.7uF and a 33pF capacitor should be added in parallel near
the SD card connector.
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CMD, CLK, DATA0, DATA1, DATA2 and DATA3 are all high speed signal lines. In PCB design, please
control the characteristic impedance of them as 50Ω, and do not cross them with other traces. It is
recommended to route the trace on the inner layer of PCB, and keep the same trace length for CLK, CMD,
DATA0, DATA1, DATA2 and DATA3. CLK additionally needs ground shielding.
Layout guidelines:
⚫ Control impedance as 50Ω±10%, and ground shielding is required.
⚫ The total trace length difference between CLK and other signal line traces should not exceed 1mm.
Table 15: SD Card Signal Trace Length Inside the Module
Pin No.
Signal
Length (mm)
Comment
70
SD_CLK
32.11
69
SD_CMD
32.11
68
SD_DATA0
32.11
67
SD_DATA1
32.11
66
SD_DATA2
32.11
65
SD_DATA3
32.11
3.13. GPIO Interfaces
SC600Y&SC600T have abundant GPIO interfaces with power domain of 1.8V. The pin definition is listed
below.
Table 16: Pin Definition of GPIO Interfaces
Pin Name
Pin No.
GPIO
Default Status
Comment
GPIO_0
248
GPIO_0
B-PD:nppukp 1)
GPIO_1
247
GPIO_1
B-PD:nppukp
Wakeup 2)
GPIO_2
201
GPIO_2
B-PD:nppukp
GPIO_3
200
GPIO_3
B-PD:nppukp
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UART2_TXD
5
GPIO_4
B-PD:nppukp
UART2_RXD
6
GPIO_5
B-PD:nppukp
TP1_I2C_SDA
204
GPIO_6
B-PD:nppukp
TP1_I2C_SCL
205
GPIO_7
B-PD:nppukp
TP1_RST
136
GPIO_8
B-PD:nppukp
TP1_INT
137
GPIO_9
B-PD:nppukp
Wakeup
TP0_I2C_SDA
206
GPIO_10
B-PD:nppukp
TP0_I2C_SCL
140
GPIO_11
B-PD:nppukp
UART4_TXD
7
GPIO_12
B-PD:nppukp
UART4_RXD
8
GPIO_13
B-PD:nppukp
Wakeup
SENSOR_I2C_SDA
132
GPIO_14
B-PD:nppukp
SENSOR_I2C_SCL
131
GPIO_15
B-PD:nppukp
UART5_TXD
199
GPIO_16
B-PD:nppukp
UART5_RXD
198
GPIO_17
B-PD:nppukp
Wakeup
UART5_CTS
246
GPIO_18
B-PD:nppukp
UART5_RTS
245
GPIO_19
B-PD:nppukp
SPI_MOSI
60
GPIO_20
B-PD:nppukp
SPI_MISO
61
GPIO_21
B-PD:nppukp
Wakeup
SPI_CS
58
GPIO_22
B-PD:nppukp
SPI_CLK
59
GPIO_23
B-PD:nppukp
LCD0_TE
126
GPIO_24
B-PD:nppukp
LCD1_TE
114
GPIO_25
B-PD:nppukp
Wakeup
MCAM_MCLK
99
GPIO_26
B-PD:nppukp
SCAM_MCLK
100
GPIO_27
B-PD:nppukp
DCAM_MCLK
194
GPIO_28
B-PD:nppukp
Wakeup
CAM_I2C_SDA
76
GPIO_29
B-PD:nppukp
CAM_I2C_SCL
75
GPIO_30
B-PD:nppukp
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DCAM_I2C_SDA
197
GPIO_31
B-PD:nppukp
Wakeup
DCAM_I2C_SCL
196
GPIO_32
B-PD:nppukp
GPIO_33
238
GPIO_33
B-PD:nppukp
GPIO_36
237
GPIO_36
B-PD:nppukp
Wakeup
MCAM_PWDN
73
GPIO_39
B-PD:nppukp
MCAM_RST
74
GPIO_40
B-PD:nppukp
GPIO_42
252
GPIO_42
B-PD:nppukp
Wakeup
GPIO_43
253
GPIO_43
B-PD:nppukp
Wakeup
GPIO_44
254
GPIO_44
B-PD:nppukp
Wakeup
GPIO_45
255
GPIO_45
B-PD:nppukp
Wakeup
LCD0_RST
127
GPIO_61
B-PD:nppukp
TP0_RST
138
GPIO_64
B-PD:nppukp
TP0_INT
139
GPIO_65
B-PD:nppukp
Wakeup
GPIO_66
234
GPIO_66
B-PD:nppukp
VOL_UP
146
GPIO_85
B-PD:nppukp
Wakeup
LCD1_RST
113
GPIO_87
B-PD:nppukp
Wakeup
GPIO_89
232
GPIO_89
B-PD:nppukp
GPIO_90
231
GPIO_90
B-PD:nppukp
Wakeup
GPIO_96
230
GPIO_96
B-PD:nppukp
GPIO_97
229
GPIO_97
B-PD:nppukp
Wakeup
GPIO_98
177
GPIO_98
B-PD:nppukp
GPIO_99
178
GPIO_99
B-PD:nppukp
GPIO_105
242
GPIO_105
B-PD:nppukp
GRFC is only
used for RF
Tuner control
GPIO_107
241
GPIO_107
B-PD:nppukp
CAM4_MCLK
236
GPIO_128
B-PD:nppukp
SCAM_RST
72
GPIO_129
B-PD:nppukp
SCAM_PWDN 3)
71
GPIO_130
B-PD:nppukp
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DCAM_RST
180
GPIO_131
B-PD:nppukp
Wakeup
DCAM_PWDN 3)
181
GPIO_132
B-PD:nppukp
Wakeup
SD_DET
64
GPIO_133
B-PD:nppukp
Wakeup
FP_SPI_CLK
250
GPIO_135
B-PD:nppukp
FP_SPI_CS
203
GPIO_136
B-PD:nppukp
FP_SPI_MOSI
249
GPIO_137
B-PD:nppukp
Wakeup
FP_SPI_MISO
251
GPIO_138
B-PD:nppukp
Wakeup
USB_SS_SEL
226
GPIO_139
B-PD:nppukp
Wakeup
1.
1)
B: Bidirectional digital with CMOS input; PD: nppukp = default pulldown with programmable options
following the colon (:).
2.
2)
Wakeup: interrupt pins that can wake up the system.
3.
3)
SCAM_PWDN and DCAM_PWDN cannot be pulled up when the module starts up.
4. More details about GPIO configuration, please refer to document [2].
3.14. I2C Interfaces
SC600Y&SC600T provide five I2C interfaces. As an open drain output, each I2C interface should be
pulled up to 1.8V voltage. The SENSOR_I2C interface supports only sensors of the aDSP architecture.
CAM/DCAM_I2C bus is controlled by Linux Kernel code and supports connection to video output related
devices.
Table 17: Pin Definition of I2C Interfaces
Pin Name
Pin No
I/O Description
Comment
TP0_I2C_SCL
140
OD
I2C clock signal of touch panel
Used for TP0
TP0_I2C_SDA
206
OD
I2C data signal of touch panel
TP1_I2C_SCL
205
OD
I2C clock signal of touch panel
Used for TP1
TP1_I2C_SDA
204
OD
I2C data signal of touch panel
NOTES
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CAM_I2C_SCL
75
OD
I2C clock signal of camera
Used for
cameras
CAM_I2C_SDA
76
OD
I2C data signal of camera
DCAM_I2C_SCL
196
OD
I2C clock signal of depth camera
Used for depth
cameras
DCAM_I2C_SDA
197
OD
I2C data signal of depth camera
SENSOR_I2C_SCL
131
OD
I2C clock signal for external
sensor
Used for external
sensors
SENSOR_I2C_SDA
132
OD
I2C data signal for external sensor
3.15. I2S Interface
SC600Y&SC600T provide one I2S interface. The I2S interface is multiplexed from FP_SPI, with power
domain of 1.8V .
Table 18: Pin Definition of I2S Interface
Pin Name
Pin No
I/O Description
Comment
FP_SPI_CS
203
DO
Chip selection signal of
SPI interface
SPI interface pin by default.
Can be multiplexed into I2S_WS.
FP_SPI_CLK
250
DO
Clock signal of SPI
interface
SPI interface pin by default.
Can be multiplexed into I2S_SCK.
FP_SPI_MOSI
249
DO
Master out slave in of SPI
interface
SPI interface pin by default.
Can be multiplexed into I2S_D0.
FP_SPI_MISO
251
DI
Master in salve out of SPI
interface
SPI interface pin by default.
Can be multiplexed into I2S_D1.
LCD1_TE
114
DI
Tearing effect signal
LCM interface pin by default.
Can be multiplexed into
I2S_MCLK_A.
GPIO_66
234
DI/DO
General GPIO
GPIO by default. Can be
multiplexed into I2S_MCLK_B.
3.16. SPI Interfaces
SC600Y&SC600T provide two SPI interfaces which only support master mode. The two interfaces are
typically applied for fingerprint identification.
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Table 19: Pin Definition of SPI Interfaces
Pin Name
Pin No
I/O Description
Comment
SPI_CS
58
DO
Chip selection signal of SPI interface
Can be multiplexed
into UART6_CST.
SPI_CLK
59
DO
Clock signal of SPI interface
Can be multiplexed
into UART6_RTS.
SPI_MOSI
60
DO
Master out slave in of SPI interface
Can be multiplexed
into UART6_TXD.
SPI_MISO
61
DI
Master in salve out of SPI interface
Can be multiplexed
into UART6_RXD.
FP_SPI_CS
203
DO
Chip selection signal of SPI interface
Used for fingerprint
identification by
default. Can be
multiplexed into I2S
interface.
FP_SPI_CLK
250
DO
Clock signal of SPI interface
FP_SPI_MOSI
249
DO
Master out slave in of SPI interface
FP_SPI_MISO
251
DI
Master in salve out of SPI interface
3.17. ADC Interfaces
SC600Y&SC600T provide two analog-to-digital converter (ADC) interfaces, and the pin definition is
shown below.
Table 20: Pin Definition of ADC Interfaces
Pin Name
Pin No.
I/O Description
Comment
PMI_ADC
153
AI
General purpose ADC
interface
Maximum input voltage: 1.5V.
PMU_MPP2
151
AI
General purpose ADC
interface
Maximum input voltage: 1.7V.
The resolution of the ADC is up to 15 bits.
3.18. Vibrator Drive Interface
The pin definition of vibrator drive interface is listed below.
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Table 21: Pin Definition of Vibrator Drive Interface
Pin Name
Pin No
I/O Description
Comment
VIB_GND
160
AI
Vibrator GND (negative)
Connected to the negative
terminal of avibrator.
VIB_DRV
161
AO
Vibrator drive (positive)
Connected to the positive
terminal of vibrator.
The Vibrator is driven by an exclusive circuit, and a reference circuit design is shown below.
1uF
Module
VIB+
Motor
VIB-
C2
33pF
C1
VIB_DRV
D1
VIB_GND
Figure 19: Reference Circuit for Vibrator Connection
3.19. LCM Interfaces
SC600Y&SC600T modules provide two LCM interfaces, and supports dual LCDs with WUXGA
(1900×1200) display. The interfaces support high speed differential data transmission, with up to eight
lanes.
Table 22: Pin Definition of LCM Interfaces
Pin Name
Pin No.
I/O
Description
Comment
LDO6_1P8
10
PO
1.8V output power supply
for LCM logic circuit and
DSI
LDO17_2P85
12
PO
2.85V output power supply
for LCM analog circuits
PMU_MPP4
152
DO
PWM signal output
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LCD_BL_A
21
PO
Current output for LCD
backlight
LCD_BL_K1
22
AI
Current sink for LCD
backlight
LCD_BL_K2
23
AI
Current sink for LCD
backlight
LCD_BL_K3
24
AI
Current sink for LCD
backlight
LCD_BL_K4
25
AI
Current sink for LCD
backlight
LCD0_RST
127
DO
LCD0 reset signal
Active low.
LCD0_TE
126
DI
LCD0 tearing effect signal
LCD1_RST
113
DO
LCD1 reset signal
Active low.
LCD1_TE
114
DI
LCD1 tearing effect signal
DSI0_CLK_N
116
AO
LCD0 MIPI clock signal
(negative)
DSI0_CLK_P
115
AO
LCD0 MIPI clock signal
(positive)
DSI0_LN0_N
118
AO
LCD0 MIPI lane 0 data
signal (negative)
DSI0_LN0_P
117
AO
LCD0 MIPI lane 0 data
signal (positive)
DSI0_LN1_N
120
AO
LCD0 MIPI lane 1 data
signal (negative)
DSI0_LN1_P
119
AO
LCD0 MIPI lane 1 data
signal (positive)
DSI0_LN2_N
122
AO
LCD0 MIPI lane 2 data
signal (negative)
DSI0_LN2_P
121
AO
LCD0 MIPI lane 2 data
signal (positive)
DSI0_LN3_N
124
AO
LCD0 MIPI lane 3 data
signal (negative)
DSI0_LN3_P
123
AO
LCD0 MIPI lane 3 data
signal (positive)
DSI1_CLK_N
103
AO
LCD1 MIPI clock signal
(negative)
DSI1_CLK_P
102
AO
LCD1 MIPI clock signal
(positive)
DSI1_LN0_N
105
AO
LCD1 MIPI lane 0 data
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signal (negative)
DSI1_LN0_P
104
AO
LCD1 MIPI lane 0 data
signal (positive)
DSI1_LN1_N
107
AO
LCD1 MIPI lane 1 data
signal (negative)
DSI1_LN1_P
106
AO
LCD1 MIPI lane 1 data
signal (positive)
DSI1_LN2_N
109
AO
LCD1 MIPI lane 2 data
signal (negative)
DSI1_LN2_P
108
AO
LCD1 MIPI lane 2 data
signal (positive)
DSI1_LN3_N
111
AO
LCD1 MIPI lane 3 data
signal (negative)
DSI1_LN3_P
110
AO
LCD1 MIPI lane 3 data
signal (positive)
The following are the reference designs for LCM interfaces.
DSI0_CLK_P
LEDA
NC
LEDK
LPTE
NC (SDA-TP)
VIO18
NC (VTP-TP)
DSI0_LN3_P
LCD0_TE
LCD0_ RST
DSI0_LN3_N
DSI0_LN2_P
DSI0_CLK_N
DSI0_LN2_N
RESET
LCD_ID
NC (SCL-TP)
NC (RST-TP)
NC (EINT-TP)
GND
VCC28
GND
MIPI_TDP3
MIPI_TDN3
GND
MIPI_TDP2
MIPI_TDN2
GND
MIPI_TDP1
MIPI_TDN1
GND
LDO17_2P85
LDO 6_1P8
LCD_BL_A
LCD_BL_K1
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
MIPI_TDP0
MIPI_TDN0
GND
MIPI_TCP
MIPI_TCN
29
28
30
3
4
5
6
3
4
5
6
3
4
5
6
3
4
5
6
DSI0_LN1_N
DSI0_LN1_P
DSI0_LN0_N
DSI0_LN0_P
1
2
3
4
5
6
11
1
2
1
2
1
2
1
2
100nF4.7uF
1uF
Module
LCM
FL1
FL2
FL3
FL4
FL5
EMI filter
C3C2C1
NC
GND
GND
GND
GND
PMI_MPP1
31
32
33
34
LCD_BL_K2
Figure 20: Reference Circuit Design for LCM0 Interface
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DSI1_CLK_P
LEDA
NC
LEDK
LPTE
NC (SDA-TP)
VIO18
NC (VTP-TP)
DSI1_LN3_P
LCD1_TE
LCD1_RST
DSI1_LN3_N
DSI1_LN2_P
DSI1_CLK_N
DSI1_LN2_N
RESET
LCD_ID
NC (SCL-TP)
NC (RST-TP)
NC (EINT-TP)
GND
VCC28
GND
MIPI_TDP3
MIPI_TDN3
GND
MIPI_TDP2
MIPI_TDN2
GND
MIPI_TDP1
MIPI_TDN1
GND
LDO17_2P 85
LDO6_1P8
LCM1_LED+
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
MIPI_TDP0
MIPI_TDN0
GND
MIPI_TCP
MIPI_TCN
29
28
30
3
4
5
6
3
4
5
6
3
4
5
6
3
4
5
6
DSI1_LN1_N
DSI1_LN1_P
DSI1_LN0_N
DSI1_LN0_P
1
2
3
4
5
6
11
1
2
1
2
1
2
1
2
100nF4.7 uF
1 uF
Module
LCM
FL1
FL2
FL3
FL4
FL5
EMI filter
C3C2C1
NC
GND
GND
GND
GND
PMU_MPP2
31
32
33
34
LCM1_LED-
Figure 21: Reference Circuit Design for LCM1 Interface
MIPI are high speed signal lines. It is recommended that common-mode filters should be added in series
near the LCM connector, so as to improve protection against electromagnetic radiation interference.
When compatible design with other displays is required, please connect the LCD_ID pin of LCM to the
module’s ADC pin, and please note that the output voltage of LCD_ID cannot exceed the voltage range of
ADC pin.
Backlight driving circuits should be designed for LCMs. SC600 provides backlight driving output which
can be used to drive LCM backlight WLEDs directly. The features are listed below:
⚫ Use the high voltage output (LCD_BL_A) for powering WLED strings, and the output voltage can be
configured from VBAT to 29.5V.
⚫ Support 4 current sinks (LCD_BL_K1, LCD_BL_K2, LCD_BL_K3, LCD_BL_K4,), with maximum sink
current up to 25mA for each.
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⚫ Power two strings of WLEDs (about 16 WLEDs) with two current sink drivers, or power four strings of
WLEDs (about 28 WLEDs) with four current sink drivers.
⚫ The frequency of PWM can be configured by software to adjust the backlight brightness.
LCM0 uses the internal backlight driving circuit provided by SC600Y&SC600T by default. LCM1 can use
the internal circuit or an external backlight driving circuit according to customers’ demands. The following
is a reference design for LCM1 external backlight driving circuit where PMU_MPP4 is used to adjust the
backlight brightness.
152
LCM1_LED+
PMU_MPP4
Module
2.2uF
Backlight
Driver
LCM1_LED-
VBAT
C1
Figure 22: Reference Design of LCM1 External Backlight Driving Circuit
3.20. Touch Panel Interfaces
SC600Y&SC600T provide two I2C interfaces for connection with Touch Panel (TP), and also provides the
corresponding power supply and interrupt pins. The pin definition of touch panel interfaces is illustrated
below.
Table 23: Pin Definition of Touch Panel Interfaces
Pin Name
Pin No
I/O
Description
Comment
LDO10_2P8
11
PO
2.8V output power supply for TP
VDD power
Vnorm=2.8V
IOmax=150mA
LDO6_1P8
10
PO
1.8V output power supply
Pull-up power supply of I2C
Vnorm=1.8V
IOmax=300mA
TP0_INT
139
DI
Interrupt signal of touch panel (TP0)
TP0_RST
138
DO
Reset signal of touch panel (TP0)
Active low
TP0_I2C_
SCL
140
OD
I2C clock signal of touch panel
(TP0)
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TP0_I2C_
SDA
206
OD
I2C data signal of touch panel (TP0)
TP1_INT
137
DI
Interrupt signal of touch panel (TP1)
TP1_RST
136
DO
Reset signal of touch panel (TP1)
Active low
TP1_I2C_
SCL
205
OD
I2C clock signal of touch panel
(TP1)
TP1_I2C_
SDA
204
OD
I2C data signal of touch panel (TP1)
A reference design for touch panel interfaces is shown below.
TP_RST
TP_I2C_SCL
TP_I2C_SDA
TP_INT
1
2
3
4
5
6
2.2K
2.2K
LDO 6_1P8
4.7uF
100nF
Module
RESET 1.8V
SCL 1.8V
SDA 1.8V
INT 1.8V
GND
VDD 2.8V
TP
R2
R1
C1 C2
D1 D2
D3
D4
D5
LDO10_2P8
Figure 23: Reference Circuit Design for Touch Panel Interfaces
TP is powered by LDO10_2P8 by default and LDO10_2P8 can output 150mA current. It is recommended
to use an external LDO power supply if dual-TP or other applications need to be supported.
3.21. Camera Interfaces
Based on standard MIPI CSI input interface, SC600Y&SC600T modules support 3 cameras (4-lane +
4-lane + 4-lane) or 4 cameras (4-lane + 4-lane + 2-lane + 1-lane), with maximum pixels up to 21MP for
SC600Y-XX and 24MP for SC600T-XX. The video and photo quality are determined by various factors
such as camera sensor, camera lens quality, etc.
NOTE
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Table 24: Pin Definition of Camera Interfaces
Pin Name
Pin No.
I/O
Description
Comment
LDO2_1P1
13
PO
1.1V output power supply
for digital core circuit of
rear camera
Vnorm=1.1V
IOmax=1200mA
LDO6_1P8
10
PO
1.8V output power supply
for digital I/O circuit of
camera
Vnorm=1.8V
IOmax=300mA
LDO17_2P85
12
PO
2.85V output power supply
auto focus circuit
Vnorm=2.85V
IOmax=300mA
LDO22_2P8
14
PO
2.8V output power supply
for AVDD of cameras
Vnorm=2.8V
IOmax=150mA
LDO23_1P2
15
PO
1.2V output power supply
for digital core circuit of
front camera
Vnorm=1.2V
IOmax=600mA
CSI0_CLK_N
89
AI
MIPI clock signal of rear
camera (negative)
CSI0_CLK_P
88
AI
MIPI clock signal of rear
camera (positive)
CSI0_LN0_N
91
AI
MIPI lane 0 data signal of
rear camera (negative)
CSI0_LN0_P
90
AI
MIPI lane 0 data signal of
rear camera (positive)
CSI0_LN1_N
93
AI
MIPI lane 1 data signal of
rear camera (negative)
CSI0_LN1_P
92
AI
MIPI lane 1 data signal of
rear camera (positive)
CSI0_LN2_N
95
AI
MIPI lane 2 data signal of
rear camera (negative)
CSI0_LN2_P
94
AI
MIPI lane 2 data signal of
rear camera (positive)
CSI0_LN3_N
97
AI
MIPI lane 3 data signal of
rear camera (negative)
CSI0_LN3_P
96
AI
MIPI lane 3 data signal of
rear camera (positive)
CSI1_CLK_N
184
AI
MIPI clock signal of depth
camera (negative)
CSI1_CLK_P
183
AI
MIPI clock signal of depth
camera (positive)
CSI1_LN0_N
186
AI
MIPI lane 0 data signal of
depth camera (negative)
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CSI1_LN0_P
185
AI
MIPI lane 0 data signal of
depth camera (positive)
CSI1_LN1_N
188
AI
MIPI lane 1 data signal of
depth camera (negative)
CSI1_LN1_P
187
AI
MIPI lane 1 data signal of
depth camera (positive)
CSI1_LN2_N
190
AI
MIPI lane 2 data signal of
depth camera (negative)
Can be multiplexed into
differential data of the fourth
camera (negative)
CSI1_LN2_P
189
AI
MIPI lane 2 data signal of
depth camera (positive)
Can be multiplexed into
differential data of the fourth
camera (positive)
CSI1_LN3_N
192
AI
MIPI lane 3 data signal of
depth camera (negative)
Can be multiplexed into
differential clock of the
fourth camera (negative)
CSI1_LN3_P
191
AI
MIPI lane 3 data signal of
depth camera (positive)
Can be multiplexed into
differential clock of the
fourth camera (positive)
CSI2_CLK_N
78
AI
MIPI clock signal of front
camera (negative)
CSI2_CLK_P
77
AI
MIPI clock signal of front
camera (positive)
CSI2_LN0_N
80
AI
MIPI lane 0 data signal of
front camera (negative)
CSI2_LN0_P
79
AI
MIPI lane 0 data signal of
front camera (positive)
CSI2_LN1_N
82
AI
MIPI lane 1 data signal of
front camera (negative)
CSI2_LN1_P
81
AI
MIPI lane 1 data signal of
front camera (positive)
CSI2_LN2_N
84
AI
MIPI lane 2 data signal of
front camera (negative)
CSI2_LN2_P
83
AI
MIPI lane 2 data signal of
front camera (positive)
CSI2_LN3_N
86
AI
MIPI lane 3 data signal of
front camera (negative)
CSI2_LN3_P
85
AI
MIPI lane 3 data signal of
front camera (positive)
MCAM_MCLK
99
DO
Master clock signal of rear
camera
SCAM_MCLK
100
DO
Master clock signal of front
camera
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MCAM_RST
74
DO
Reset signal of rear
camera
MCAM_PWDN
73
DO
Power down signal of rear
camera
SCAM_RST
72
DO
Reset signal of front
camera
SCAM_PWDN
71
DO
Power down signal of front
camera
CAM_I2C_SCL
75
OD
I2C clock signal of camera
CAM_I2C_SDA
76
OD
I2C data signal of camera
DCAM_MCLK
194
DO
Clock signal of depth
camera
CAM4_MCLK
236
DO
Master clock signal of
fourth camera
DCAM_RST
180
DO
Reset signal of depth
camera
DCAM_PWDN
181
DO
Power down signal of
depth camera
DCAM_I2C_SDA
197
OD
I2C data of depth camera
DCAM_I2C_SCL
196
OD
I2C clock of depth camera
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The following is a reference circuit design for two-camera applications.
Rear camera connector
MCAM_PWDN
MCAM_MCLK
CAM_I2C_SDA
CAM_I2C_SCL
SCAM_RST
SCAM_PWDN
SCAM_MCLK
CSI0_ CLK_P
CSI0_ CLK_N
CSI2_ CLK_P
CSI2_ CLK_N
LDO6_1P8
LDO2_1P1
LDO22_2P8
2.2K
2.2K
Front camera connector
4.7uF
1uF
1uF
MCAM_RST
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
LDO17_2P85
AVDD
AF_VDD
DVDD
DOVDD
1uF
CSI0_LN0_P
CSI0_LN0_N
CSI0_LN1_P
CSI0_LN1_N
CSI0_LN2_P
CSI0_LN2_N
CSI0_LN3_P
CSI0_LN3_N
CSI2_LN0_P
CSI2_LN0_N
CSI2_LN1_P
CSI2_LN1_N
CSI2_LN2_P
CSI2_LN2_N
CSI2_LN3_P
CSI2_LN3_N
LDO23_1P2
DVDD
1uF
4.7uF
4.7uF
AVDD
DOVDD
Figure 24: Reference Circuit Design for Two-Camera Applications
CSI0 is used for rear camera, CSI1 is used for depth camera, and CSI2 is used for front camera.
NOTE
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The following is a reference circuit design for three-camera applications.
Rear camera connector
MCAM_PWDN
MCAM_MCLK
CAM_I2C_SDA
CAM_I2C_SCL_
CSI0_LN3_P
CSI0_LN3_N
CSI0_LN2_P
CSI0_LN2_N
CSI0_LN1_P
CSI0_LN1_N
CSI0_LN0_P
CSI0_LN0_N
SCAM_ RST
SCAM_ PWDN
SCAM_ MCLK
CSI1_CLK_P
CSI1_CLK_N
CSI1_LN0_P
CSI1_LN0_N
CSI2_LN1_P
CSI2_LN1_N
CSI2_LN0_P
CSI2_LN0_N
CSI0_CLK_P
CSI0_CLK_N
CSI2_CLK_P
CSI2_ CLK_N
LDO6_1P8
LDO22_2P8
2.2K
2.2K
Front camera connector
1uF
4.7 uF
4.7uF
1uF
1uF
4.7uF
MCAM_RST
DCAM_PWDN
DCAM_MCLK
DCAM_I2C_SDA_
DCAM_I2C_SCL
DCAM_RST
Depth camera connector
LDO17_2P85
AVDD
AF_VDD
DVDD
DOVDD
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI
LDO2_1P1
1uF
LDO23_1P2
2.2K
2.2K
DVDD
EMI
EMI
4.7
1uF
uF
AVDD
DOVDD
Figure 25: Reference Circuit Design for Three-Camera Applications
CSI1 data lines CSI1_LN2_P, CSI_LN2_N, CSI_LN3_P and CSI_LN3_N can be multiplexed into MIPI
signals for the fourth camera in four-camera application.
NOTE
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3.21.1. Design Considerations
⚫ Special attention should be paid to the pin definition of LCM/camera connectors. Assure the
SC600Y&SC600T and the connectors are correctly connected.
⚫ MIPI are high speed signal lines, supporting maximum data rate up to 2.1Gbps. The differential
impedance should be controlled as 100Ω. Additionally, it is recommended to route the trace on the
inner layer of PCB, and do not cross it with other traces. For the same group of DSI or CSI signals, all
the MIPI traces should keep the same length. In order to avoid crosstalk, it is recommended to
maintain the intra-lane spacing as trace width and the inter-lane spacing as two times of the trace
width. Any cut or hole on GND reference plane under MIPI signals should be avoided.
⚫ It is recommended to select a low capacitance TVS for ESD protection and the recommended
parasitic capacitance is below 1pF.
⚫ Route MIPI traces according to the following rules:
a) The total trace length should not exceed 305mm;
b) Control the differential impedance as 100Ω±10%;
c) Control intra-lane length difference within 0.67mm;
d) Control inter-lane length difference within 1.3mm.
Table 25: MIPI Trace Length Inside the Module
Pin No.
Pin Name
Length (mm)
Length Difference (P-N)
116
DSI0_CLK_N
20.82
-0.45
115
DSI0_CLK_P
20.37
118
DSI0_LN0_N
24.84
0
117
DSI0_LN0_P
24.84
120
DSI0_LN1_N
24.85
-0.03
119
DSI0_LN1_P
24.82
122
DSI0_LN2_N
25.94
0.24
121
DSI0_LN2_P
26.18
124
DSI0_LN3_N
29.31
0.2
123
DSI0_LN3_P
29.51
103
DSI1_CLK_N
9.52
-0.05
102
DSI1_CLK_P
9.47
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105
DSI1_LN0_N
10.27
-0.11
104
DSI1_LN0_P
10.16
107
DSI1_LN1_N
11.75
-0.17
106
DSI1_LN1_P
11.58
109
DSI1_LN2_N
14.86
-0.36
108
DSI1_LN2_P
14.5
111
DSI1_LN3_N
15.73
0.15
110
DSI1_LN3_P
15.88
89
CSI0_CLK_N
16.54
0.03
88
CSI0_CLK_P
16.57
91
CSI0_LN0_N
17.47
-0.07
90
CSI0_LN0_P
17.4
93
CSI0_LN1_N
12.13
-0.05
92
CSI0_LN1_P
12.08
95
CSI0_LN2_N
9.56
0.14
94
CSI0_LN2_P
9.7
97
CSI0_LN3_N
8.73
0.13
96
CSI0_LN3_P
8.86
184
CSI1_CLK_N
20.32
-0.23
183
CSI1_CLK_P
20.09
186
CSI1_LN0_N
12.09
0.57
185
CSI1_LN0_P
12.66
188
CSI1_LN1_N
11.33
0.37
187
CSI1_LN1_P
11.70
190
CSI1_LN2_N
5.86
0.19
189
CSI1_LN2_P
6.05
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192
CSI1_LN3_N
10.49
-0.43
191
CSI1_LN3_P
10.06
78
CSI2_CLK_N
22.00
0.17
77
CSI2_CLK_P
22.17
80
CSI2_LN0_N
22.07
-0.07
79
CSI2_LN0_P
22.00
82
CSI2_LN1_N
22.54
-0.49
81
CSI2_LN1_P
22.05
84
CSI2_LN2_N
22.03
-0.11
83
CSI2_LN2_P
21.92
86
CSI2_LN3_N
21.90
0.59
85
CSI2_LN3_P
22.49
3.21.2. Flashlight Interfaces
SC600Y&SC600T modules support 2 flash LED drivers, with maximal output current up to 1.5A per
channel in flash mode and 300mA in torch mode. The default output current is 1A in flash mode and
300mA in torch mode.
Table 26: Pin Definition of Flashlight Interfaces
Pin Name
Pin No.
I/O
Description
Comment
FLASH_LED1
26
AO
Flash/torch drive signal output
FLASH_LED2
162
AO
Flash/torch drive signal output
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A reference circuit design is shown below.
Module
D2
FLASH_LED1
D1
FLASH_LED2
Figure 26: Reference Circuit Design for Flashlight Interfaces
3.22. Sensor Interfaces
SC600Y&SC600T modules support communication with sensors via I2C interface, and it supports various
sensors such as acceleration sensor, gyroscopic sensor, compass, optical sensor, temperature sensor.
Table 27: Pin Definition of Sensor Interfaces
Pin Name
Pin No.
I/O
Description
Comment
SENSOR_I2C_SCL
131
OD
I2C clock signal of external sensor
SENSOR_I2C_SDA
132
OD
I2C data signal of external sensor
GPIO_43
253
DI
Interrupt signal of optical sensor
GPIO_44
254
DI
Interrupt signal of direction sensor
(compass)
GPIO_42
252
DI
Interrupt signal of acceleration sensor
GPIO_45
255
DI
Interrupt signal of gyroscopic sensor
3.23. Audio Interfaces
SC600Y&SC600T modules provide three analog input channels and three analog output channels. The
following table shows the pin definition.
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Table 28: Pin Definition of Audio Interfaces
Pin Name
Pin No.
I/O
Description
Comment
MIC1_P
44
AI
Microphone positive input for channel 1
MIC1_N
45
AI
Microphone negative input for channel 1
MIC_GND
168
Microphone reference ground
If unused, connect this
pin to the ground.
MIC2_P
46
AI
Microphone positive input for headset.
MIC3_P
169
AI
Microphone positive input for channel 2
MIC_BIAS
167
AO
Microphone bias voltage
EAR_P
53
AO
Earpiece positive output
EAR_N
52
AO
Earpiece negative output
SPK_P
55
AO
Speaker positive output
SPK_N
54
AO
Speaker negative output
HPH_R
51
AO
Headphone right channel output
HPH_REF
50
AI
Headphone reference ground
HPH_L
49
AO
Headphone left channel output
HS_DET
48
AI
Headset insertion detection
High level by default.
⚫ The module offers three audio input channels, including one differential input pair and two
single-ended channels. The three sets of MICs are integrated with internal bias voltage.
⚫ The output voltage range of MIC_BIAS is programmable between 1.6V and 2.85V, and the maximum
output current is 3mA.
⚫ The earpiece interface uses differential output.
⚫ The loudspeaker interface uses differential output as well. The output channel is available with a
Class-D amplifier whose maximum output power is 1.5W when load is 8Ω.
⚫ The headphone interface features stereo left and right channel output, and headphone insertion
detection function is supported.
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3.23.1. Reference Circuit Design for Microphone Interfaces
MIC1_P
ECM-MIC
R2
R1
Module
D1
MIC1_N
33pF
C1
0R
0R
R3
0R
Figure 27: Reference Circuit Design for Analog ECM-type Microphone
MIC3_P
33pF
MEMS-MIC
R2
R1
C2
Module
MIC_ GND
0R
C1
MIC_ BIAS
1
2
3
4
F1
D1
OUT
GND
GND
VDD
100nF
C4
0R
33pF
Figure 28: Reference Circuit Design for MEMS-type Microphone
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3.23.2. Reference Circuit Design for Earpiece Interface
EAR_P
EAR_N
R2
33pF
33pF
33pF
C2
C3
C1
R1
Module
D1
D2
0R
0R
Figure 29: Reference Circuit Design for Earpiece Interface
3.23.3. Reference Circuit Design for Headphone Interface
20K
ESD
MIC_GND
MIC2_P
HPH_L
HS_DET
HPH_R
HPH_REF
33pF
Module
R1
0R
3
6
4
5
2
1
33pF 33pF
C3
C4 C5
F3
F2
F1
D1 D2 D3
D4
F4
R2
R3
0R
Figure 30: Reference Circuit Design for Headphone Interface
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3.23.4. Reference Circuit Design for Loudspeaker Interface
EARP
EA
RN
F2
SPK_P
SPK_N
33pF
33pF
C1
C2
F1
Module
D1 D2
Figure 31: Reference Circuit Design for Loudspeaker Interface
3.23.5. Audio Interfaces Design Considerations
It is recommended to use the electret microphone with dual built-in capacitors (e.g. 10pF and 33pF) for
filtering out RF interference, thus reducing TDD noise. The 33pF capacitor is applied for filtering out RF
interference when the module is transmitting at EGSM900. Without placing this capacitor, TDD noise
could be heard. The 10pF capacitor here is used for filtering out RF interference at DCS1800. Please note
that the resonant frequency point of a capacitor largely depends on the material and production technique.
Therefore, customers would have to discuss with their capacitor vendors to choose the most suitable
capacitor for filtering out high-frequency noises.
The severity degree of the RF interference in the voice channel during GSM transmitting largely depends
on the application design. In some cases, EGSM900 TDD noise is more severe; while in other cases,
DCS1800 TDD noise is more obvious. Therefore, a suitable capacitor can be selected based on the test
results. Sometimes, even no RF filtering capacitor is required.
In order to decrease radio or other signal interference, RF antennas should be placed away from audio
interfaces and audio traces. Power traces cannot be parallel with and also should be far away from the
audio traces.
The differential audio traces must be routed according to the differential signal layout rule.
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3.24. Emergency Download Interface
USB_BOOT is an emergency download interface. Pull up to LDO5_1P8 during power-up will force the
module enter into emergency download mode. This is an emergency option when there are failures such
as abnormal startup or operation. For convenient firmware upgrade and debugging in the future, please
reverse the reference circuit design shown as below.
LDO5_1P8
S1
Module
USB_BOOT
R1
10K
Figure 32: Reference Circuit Design for Emergency Download Interface
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4 Wi-Fi and BT
SC600Y&SC600T modules provide a shared antenna interface ANT_WIFI/BT for Wi-Fi and Bluetooth
(BT) functions. The interface impedance is 50Ω. External antennas such as PCB antenna, sucker
antenna and ceramic antenna can be connected to the module via the interface, so as to achieve Wi-Fi
and BT functions.
4.1. Wi-Fi Overview
SC600Y&SC600T modules support 2.4GHz and 5GHz dual-band WLAN wireless communication based
on IEEE 802.11a/b/g/n/ac standard protocols. The maximum data rate is up to 433Mbps.
The features are as below:
⚫ Support Wake-on-WLAN (WoWLAN)
⚫ Support ad hoc mode
⚫ Support WAPI SMS4 hardware encryption
⚫ Support AP mode
⚫ Support Wi-Fi Direct
⚫ Support MCS 0-7 for HT20 and HT40
⚫ Support MCS 0-8 for VHT20
⚫ Support MCS 0-9 for VHT40 and VHT80
4.1.1. Wi-Fi Performance
The following table lists the Wi-Fi transmitting and receiving performance of SC600Y&SC600T modules.
Table 29: Wi-Fi Transmitting Performance
Standard
Rate
Output Power
2.4GHz
802.11b
1Mbps
16dBm±2.5dB
802.11b
11Mbps
16dBm±2.5dB
802.11g
6Mbps
16dBm±2.5dB
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Table 30: Wi-Fi Receiving Performance
802.11g
54Mbps
14dBm±2.5dB
802.11n HT20
MCS0
15dBm±2.5dB
802.11n HT20
MCS7
13dBm±2.5dB
802.11n HT40
MCS0
14dBm±2.5dB
802.11n HT40
MCS7
13dBm±2.5dB
5GHz
802.11a
6Mbps
14dBm±2.5dB
802.11a
54Mbps
13dBm±2.5dB
802.11n HT20
MCS0
15dBm±2.5dB
802.11n HT20
MCS7
13dBm±2.5dB
802.11n HT40
MCS0
15dBm±2.5dB
802.11n HT40
MCS7
13dBm±2.5dB
802.11ac VHT20
MCS0
15dBm±2.5dB
802.11ac VHT20
MCS8
13dBm±2.5dB
802.11ac VHT40
MCS0
14dBm±2.5dB
802.11ac VHT40
MCS9
13dBm±2.5dB
802.11ac VHT80
MCS0
13dBm±2.5dB
802.11ac VHT80
MCS9
12dBm±2.5dB
Standard
Rate
Sensitivity
2.4GHz
802.11b
1Mbps
-94.5
802.11b
11Mbps
-87
802.11g
6Mbps
-89
802.11g
54Mbps
-71.5
802.11n HT20
MCS0
-88.5
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Reference specifications are listed below:
⚫ IEEE 802.11n WLAN MAC and PHY, October 2009 + IEEE 802.11-2007 WLAN MAC and PHY, June
2007
⚫ IEEE Std 802.11b, IEEE Std 802.11d, IEEE Std 802.11e, IEEE Std 802.11g, IEEE Std 802.11i: IEEE
802.11-2007 WLAN MAC and PHY, June 2007
4.2. BT Overview
SC600Y&SC600T modules support BT4.2 (BR/EDR+BLE) specifications, as well as GFSK, 8-DPSK,
π/4-DQPSK modulation modes.
⚫ Maximally support up to 7 wireless connections
⚫ Maximally support up to 3.5 piconets at the same time
⚫ Support one SCO or eSCO (Extended Synchronous Connection Oriented) connection
The BR/EDR channel bandwidth is 1MHz, and can accommodate 79 channels. The BLE channel
bandwidth is 2MHz, and can accommodate 40 channels.
802.11n HT20
MCS7
-70
802.11n HT40
MCS0
-85
802.11n HT40
MCS7
-67
5GHz
802.11a
6Mbps
-90
802.11a
54Mbps
-71.5
802.11n HT20
MCS0
-86dBm
802.11n HT20
MCS7
-67dBm
802.11n HT40
MCS0
-84dBm
802.11n HT40
MCS7
-64dBm
802.11ac VHT20
MCS8
-68dBm
802.11ac VHT40
MCS9
-62dBm
802.11ac VHT80
MCS9
-58dBm
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Table 31: BT Data Rate and Versions
Version
Data rate
Maximum Application Throughput
Comment
1.2
1Mbit/s
> 80Kbit/s
2.0+EDR
3Mbit/s
> 80Kbit/s
3.0+HS
24Mbit/s
Reference to 3.0+HS
4.0
24Mbit/s
Reference to 4.0 LE
Reference specifications are listed below:
⚫ Bluetooth Radio Frequency TSS and TP Specification 1.2/2.0/2.0 + EDR/2.1/2.1+ EDR/3.0/3.0 + HS,
August 6, 2009
⚫ Bluetooth Low Energy RF PHY Test Specification, RF-PHY.TS/4.0.0, December 15, 2009
4.2.1. BT Performance
The following table lists the BT transmitting and receiving performance of SC600Y&SC600T modules.
Table 32: BT Transmitting and Receiving Performance
Transmitter Performance
Packet Types
DH5
2-DH5
3-DH5
Transmitting Power
10dBm±2.5dB
8dBm±2.5dB
8dBm±2.5dB
Receiver Performance
Packet Types
DH5
2-DH5
3-DH5
Receiving Sensitivity
-91dBm
-92dBm
-86dBm
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5 GNSS
SC600Y&SC600T modules integrate a Qualcomm IZat™ GNSS engine (Gen 8C) which supports multiple
positioning and navigation systems including GPS, GLONASS and BeiDou. With an embedded LNA, the
module provides greatly improved positioning accuracy.
5.1. GNSS Performance
The following table lists the GNSS performance of SC600Y&SC600T modules in conduction mode.
Table 33: GNSS Performance
Parameter
Description
Typ.
Unit
Sensitivity (GNSS)
Cold start
-144
dBm
Reacquisition
-155
dBm
Tracking
-155
dBm
TTFF (GNSS)
Cold start
35
s
Warm start
30
s
Hot start
<5
s
Static Drift (GNSS)
CEP-50
<80
m
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5.2. GNSS RF Design Guidelines
Bad design of antenna and layout may cause reduced GNSS receiving sensitivity, longer GNSS
positioning time, or reduced positioning accuracy. In order to avoid these, please follow the design rules
listed below:
⚫ Maximize the distance between the GNSS RF part and the GPRS RF part (including trace routing
and antenna layout) to avoid mutual interference.
⚫ In user systems, GNSS RF signal lines and RF components should be placed far away from high
speed circuits, switched-mode power supplies, power inductors, the clock circuit of single-chip
microcomputers, etc.
⚫ For applications with harsh electromagnetic environment or high ESD-protection requirements, it is
recommended to add ESD protective diodes for the antenna interface. Only diodes with ultra-low
junction capacitance such as 0.5pF can be selected. Otherwise, there will be effects on the
impedance characteristic of RF circuit loop, or attenuation of bypass RF signal may be caused.
⚫ Control the impedance of either feeder line or PCB trace as 50Ω, and keep the trace length as short
as possible.
⚫ Refer to Chapter 6.3 for GNSS antenna reference circuit designs.
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6 Antenna Interfaces
SC600Y&SC600T provide four antenna interfaces for main antenna, Rx-diversity/MIMO antenna, GNSS
antenna, and Wi-Fi/BT antenna, respectively. The antenna ports have an impedance of 50Ω.
6.1. Main/Rx-diversity Antenna Interfaces
The pin definition of main/Rx-diversity antenna interfaces is shown below.
Table 34: Pin Definition of Main/Rx-diversity Antenna Interfaces
Pin Name
Pin No.
I/O
Description
Comment
ANT_MAIN
19
IO
Main antenna interface
50Ω impedance
ANT_DRX
149
AI
Diversity and MIMO
antenna interface
50Ω impedance
The operating frequencies of SC600Y&SC600T modules are listed in the following table.
Table 35: SC600Y-JP*/SC600T-JP* Module Operating Frequencies
3GPP Band
Receive
Transmit
Unit
WCDMA B1
2110~2170
1920~1980
MHz
WCDMA B6
875~885
830~840
MHz
WCDMA B8
925~960
880~915
MHz
WCDMA B19
875~890
830~845
MHz
LTE-FDD B1
2110~2170
1920~1980
MHz
LTE-FDD B3
1805~1880
1710~1785
MHz
LTE-FDD B5
869~894
824~849
MHz
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LTE-FDD B8
925~960
880~915
MHz
LTE-FDD B11
1475.9~495.9
1427.9~1447.9
MHz
LTE-FDD B18
860~875
815~830
MHz
LTE-FDD B19
875~890
830~845
MHz
LTE-TDD B21
1495.9~1510.9
1447.9~1462.9
MHz
LTE-TDD B26
758~788
703~733
MHz
LTE-FDD B28A
758~788
703~733
MHz
LTE-FDD B28B
773~803
718~748
MHz
LTE-TDD B41 1)
2496~2690
2496~2690
MHz
Table 36: SC600Y-EM*/SC600T-EM* Module Operating Frequencies
3GPP Band
Receive
Transmit
Unit
GSM850
869~894
824~849
MHz
EGSM900
925~960
880~915
MHz
DCS1800
1805~1880
1710~1785
MHz
PCS1900
1930~1990
1850~1910
MHz
WCDMA B1
2110~2170
1920~1980
MHz
WCDMA B2
1930~1990
1850~1910
MHz
WCDMA B4
2110~2155
1710~1755
MHz
WCDMA B5
871~892
826~847
MHz
WCDMA B8
925~960
880~915
MHz
LTE-FDD B1
2110~2170
1920~1980
MHz
LTE-FDD B2
1930~1990
1850~1910
MHz
LTE-FDD B3
1805~1880
1710~1785
MHz
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LTE-FDD B5
869~894
824~849
MHz
LTE-FDD B7
2620~2690
2500~2570
MHz
LTE-FDD B8
925~960
880~915
MHz
LTE-FDD B20
791~821
832~862
MHz
LTE-FDD B28A
758~788
703~733
MHz
LTE-FDD B28B
773~803
718~748
MHz
LTE-TDD B38
2570~2620
2570~2620
MHz
LTE-TDD B39
1880~1920
1880~1920
MHz
LTE-TDD B40
2300~2400
2300~2400
MHz
LTE-TDD B41 1)
2496~2690
2496~2690
MHz
Table 37: SC600Y-NA*/SC600T-NA* Module Operating Frequencies
3GPP Band
Receive
Transmit
Unit
WCDMA B2
1930~1990
1850~1910
MHz
WCDMA B4
2110~2155
1710~1755
MHz
WCDMA B5
871~892
826~847
MHz
LTE-FDD B2
1930~1990
1850~1910
MHz
LTE-FDD B4
2110~2155
1710~1755
MHz
LTE-FDD B5
869~894
824~849
MHz
LTE-FDD B7
2620~2690
2500~2570
MHz
LTE-FDD B12
729~746
699~716
MHz
LTE-FDD B13
746~756
777~787
MHz
LTE-FDD B14
758~768
788~798
MHz
LTE-FDD B17
734~746
704~716
MHz
LTE-FDD B25
1930~1995
1850~1915
MHz
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LTE-FDD B26
859~894
814~849
MHz
LTE-FDD B66
2110~2200
1710~1780
MHz
LTE-FDD B71
617 – 652
663 – 698
MHz
LTE-TDD B41 1)
2496~2690
2496~2690
MHz
1.
1)
The bandwidth of LTE-TDD B41 for SC600Y-EM*/SC600T-EM*、SC600Y-JP*/SC600T-JP*、
SC600Y-NA*/SC600T-NA* is 200MHz (2496MHz~2690MHz), and the corresponding channel ranges
from 39650 to 41589.
6.1.1. Main and Rx-diversity Antenna Interfaces Reference Design
A reference circuit design for main and Rx-diversity antenna interfaces is shown as below. A π-type
matching circuit should be reserved for better RF performance, and the π-type matching components
(R1/C1/C2, R2/C3/C4) should be placed as close to the antennas as possible. The capacitors are not
mounted by default and resistors are 0Ω.
ANT_MAIN
R1 0R
C1
Module
Main
antenna
NM
C2
NM
R2 0R
C3
Diversity
antenna
NM
C4
NM
ANT_DRX
Figure 33: Reference Circuit Design for Main and Rx-diversity Antenna Interfaces
NOTES
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6.1.2. Reference Design of RF Layout
For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
the height from the reference ground to the signal layer (H), and the clearance between RF traces and
grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic
impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB
structures.
Figure 34: Microstrip Design on a 2-layer PCB
Figure 35: Coplanar Waveguide Design on a 2-layer PCB
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Figure 36: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground)
Figure 37: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground)
In order to ensure RF performance and reliability, the following principles should be complied with in RF
layout design:
⚫ Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to
50Ω.
⚫ The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully
connected to ground.
⚫ The distance between the RF pins and the RF connector should be as short as possible, and all the
right angle traces should be changed to curved ones.
⚫ There should be clearance under the signal pin of the antenna connector or solder joint.
⚫ The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around
RF traces and the reference ground could help to improve RF performance. The distance between
the ground vias and RF traces should be no less than two times as wide as RF signal traces (2*W).
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For more details about RF layout, please refer to document [3].
6.2. Wi-Fi/BT Antenna Interface
The pin definition of Wi-Fi/BT antenna interfaces and operating frequencies is shown below.
Table 38: Pin Definition of Wi-Fi/BT Antenna Interface
Pin Name
Pin No.
I/O
Description
Comment
ANT_WIFI/BT
129
IO
Wi-Fi/BT antenna interface
50Ω impedance
Table 39: Wi-Fi/BT Frequency
Type
Frequency
Unit
802.11a/b/g/n/ac
2402~2482
5180~5825
MHz
BT4.2 LE
2402~2480
MHz
A reference circuit design for Wi-Fi/BT antenna interface is shown as below. A π-type matching circuit is
recommended to be reserved for better RF performance. The capacitors are not mounted by default and
resistors are 0Ω.
ANT_WIFI/BT
R1 0R
C1
Module
NM
C2
NM
Figure 38: Reference Circuit Design for Wi-Fi/BT Antenna Interface
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6.3. GNSS Antenna Interface
The pin definition of GNSS antenna interfaces and operating frequencies is shown below.
Table 40: Pin Definition of GNSS Antenna
Pin Name
Pin No.
I/O
Description
Comment
ANT_GNSS
134
AI
GNSS antenna Interface
50Ω impedance
GNSS_LNA_EN
202
DO
LNA enable control
For test purpose only.
If unused, keep it open.
Table 41: GNSS Frequency
Type
Frequency
Unit
GPS
1575.42±1.023
MHz
GLONASS
1597.5~1605.8
MHz
BeiDou
1561.098±2.046
MHz
6.3.1. Recommended Circuit for Passive Antenna
GNSS antenna interface supports passive ceramic antennas and other types of passive antennas. A
reference circuit design is given below.
Passive
Antenna
Module
ANT_GNSS
NM
C1
C2
R1
C4
NM
0R
Figure 39: Reference Circuit Design for GNSS Passive Antenna
When the passive antenna is placed far away from the module (that is, the antenna trace is long), it is
recommended to add an external LNA circuit for better GNSS receiving performance, and the LNA should
be placed close to the antenna.
NOTE
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