Philips TDA1305T Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA1305T

Stereo 1fs data input up-sampling
filter with bitstream continuous dual
DAC (BCC-DAC2)

Preliminary specification
Supersedes data of September 1994
File under Integrated Circuits, IC01

1995 Dec 08

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

FEATURES

• Easy application

• 16fs Finite-duration Impulse-Response (FIR)

filter incorporated

• Selectable system clock (f

• I2S-bus serial input format (at f

16, 18 or 20 bits serial input mode (at f

• Slave-mode clock system

• Cascaded 4-stage digital filter incorporating 2-stage FIR

filter, linear interpolator and sample-and-hold

• Smoothed transitions before and after muting
(soft mute)

• Digital de-emphasis filter for three sampling rates of
32 kHz, 44.1 kHz and 48 kHz

• 12 dB attenuation via the attenuation input control

• Double speed mode

• 2nd order noise shaper

• 96 (f

= 384fs) or 128 (f

sys

in normal speed mode

• 48 (f

= 384fs) or 64 (f

sys

in double speed mode

• Bitstream continuous calibration concept

• Small outline SO28 package

• Voltage output 1.5 V (RMS) at line drive level

• Low total harmonic distortion

• No zero crossing distortion

• Inherently monotonic

• No analog post filtering required

• Superior signal-to-noise ratio

• Wide dynamic range (18-bit)

• Single rail supply (3.4 to 5.5 V).

) 256fs or 384f

sys

= 256fs) or LSB fixed

sys

= 256fs) times oversampling

sys

= 256fs) times oversampling

sys

sys

s

= 384fs)

bitstream converter for low signals while large signals are
generated using the dynamic continuous calibration
technique, thus resulting in low power consumption, small
chip size and easy application.

The TDA1305T is a dual CMOS DAC with up-sampling
filter and noise shaper. The combination of high
oversampling up to 16f
continuous calibration conversion ensures that only simple
1st order analog post filtering is required.

The TDA1305T supports the I2S-bus data input mode with
word lengths of up to 20 bits (at f
fixed serial data input format with word lengths of 16, 18
and 20 bits (at f
increase the oversampling rate to 16 times. A
sample-and-hold function increases the oversampling rate
to 96 times (f
2nd order noise shaper converts this oversampled data to
a bitstream for the 5-bit DACs.

The DACs are of the continuous calibration type and
incorporate a special date coding. This ensures an
extremely high signal-to-noise ratio, superior dynamic
range and immunity to process variation and component
ageing.

Two on-board operational amplifiers convert the
digital-to-analog current to an output voltage. Externally
connected capacitors perform the required 1st order
filtering so that no further post filtering is required.

TDA1305T

, 2nd order noise shaping and

s

= 256fs) and the LSB

sys

= 384fs). Four cascaded FIR filters

sys

= 384fs) or 128 times (f

sys

sys

= 256fs). A

GENERAL DESCRIPTION

The TDA1305T is a new generation of filter-DAC which
features a unique combination of bitstream and continuous
calibration techniques. The converter functions as a

The unique combination of bitstream and continuous
calibration techniques, together with a high degree of
analog and digital integration, results in a single filter-DAC
with 18-bit dynamic range, high linearity and simple low
cost application.

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA1305T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1

1995 Dec 08 2

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with

TDA1305T

bitstream continuous dual DAC (BCC-DAC2)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDD

V

DDA

V

DDO

I

DDD

I

DDA

I

DDO

V

FS(rms)

(THD + N)/S total harmonic distortion

S/N signal-to-noise ratio at

BR

ns

BR

ds

f

sys

TC

FS

T

amb

digital supply voltage note 1 3.4 5.0 5.5 V
analog supply voltage note 1 3.4 5.0 5.5 V
operational amplifier

note 1 3.4 5.0 5.5 V

supply voltage
digital supply current V

DDD

=5V;

− 30 − mA

at code 00000H

analog supply current V

DDA

=5V;

− 5.5 8 mA

at code 00000H

operating amplifier supply
current

full-scale output voltage

V

=5V;

DDO

at code 00000H
V

DDD=VDDA=VDDO

− 6.5 9 mA

= 5 V 1.425 1.5 1.575 V

(RMS value)

at 0 dB signal level −−90 −81 dB

plus noise-to-signal ratio

− 0.003 0.009 %

at −60 dB signal level −−44 −40 dB

− 0.63 0.1 %

bipolar zero

at −60 dB signal level;
A-weighted

A-weighting;
at code 00000H

−−46 − dB

− 0.5 − %

100 108 − dB

input bit rate at data input fs= 48 kHz; normal speed −− 3.072 Mbits
input bit rate at data input fs= 48 kHz; double speed −− 6.144 Mbits
system clock frequency 6.4 − 18.432 MHz
full scale temperature

−±100 × 10−6−
coefficient at analog
outputs (VOL and VOR)

operating ambient

−30 − +85 °C
temperature

Note

1. All V

and VSS pins must be connected to the same supply.

DD

1995 Dec 08 3

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

BLOCK DIAGRAM

TDA1305T

Fig.1 Block diagram.

1995 Dec 08 4

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

PINNING

SYMBOL PIN DESCRIPTION

V

DDA

V

SSA

TEST1 3 test input; pin should be connected

BCK 4 bit clock input
WS 5 word select input
DATA 6 data input
CLKS1 7 clock selection1 input
CLKS2 8 clock selection2 input
V

SSD

V

DDD

TEST2 11 test input; pin should be connected

SYSCLKI 12 system clock input
n.c. 13 not connected (this pin should be left

n.c. 14 not connected (this pin should be left

V

SSD

SYSCLKO 16 system clock output
DEEM1 17 de-emphasis on/off; f

DEEM2 18 de-emphasis on/off; f

MUSB 19 mute input (active LOW)
DSMB 20 double-speed mode input

ATSB 21 12 dB attenuation input

VOL 22 left channel output
FILTCL 23 capacitor for left channel 1st order

FILTCR 24 capacitor for right channel 1st order

VOR 25 right channel output
V

ref

V

SSO

V

DDO

1 analog supply voltage
2 analog ground

to ground (internal pull-down
resistor)

9 digital ground

10 digital supply voltage

to ground (internal pull-down
resistor)

open-circuit)

open-circuit)

15 digital ground

32 kHz,

DEEM

44 kHz and 48 kHz

32 kHz,

DEEM

44 kHz and 48 kHz

(active LOW)

(active LOW)

filter function should be connected
between pins 22 and 23

filter function should be connected
between pins 25 and 24

26 internal reference voltage for output

channels (0.5VDD)
27 operational amplifier ground
28 operational amplifier supply voltage

TDA1305T

Fig.2 Pin configuration.

1995 Dec 08 5

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with

TDA1305T

bitstream continuous dual DAC (BCC-DAC2)

FUNCTIONAL DESCRIPTION

The TDA1305T CMOS digital-to-analog bitstream
converter incorporates an up-sampling filter and noise
shaper which increase the oversampling rate of 1fs input
data to 96fs (f

= 192fs) or 128fs (f

sys

= 256fs) in the

sys

normal speed mode. In the double speed mode the
oversample rate of 1fs input data is increased to 48f
(f

= 384fs) or 64fs (f

sys

= 256fs). This oversampling,

sys

s

together with the 5-bit DAC, enables the filtering required
for waveform smoothing and out-of-band noise reduction
to be achieved by simple 1st order analog post filtering.

System clock and data input format

The TDA1305T accommodates slave mode only, this

provide a system clock of 256 or 384f
48 kHz). The system frequency is selectable by means of
pin CLKS1 and pin CLKS2. The SYSCLKO output (pin 16)
provides the system clock for external use.

The TDA1305T supports the following data input modes:

• I2S-bus with data word lengths of up to 20 bits
(at f

= 256fs).

sys

• LSB fixed serial format with data word lengths of 16, 18
and 20 bits (at f

= 384fs). As this format idles on the

sys

MSB it is necessary to know how many bits are being
transmitted.

The input format is shown in Fig.3. Left and right
data-channel words are time-multiplexed.

means that in all applications the system devices must

Table 1 Data input format and system clock.

TEST1 CLKS1 CLKS2 DATA INPUT FORMAT

000I

2

S up to 20 bits 256f
0 0 1 LSB fixed 16 bits 384f
0 1 0 LSB fixed 18 bits 384f
0 1 1 LSB fixed 20 bits 384f

SYSTEM

CLOCK

s
s
s
s

DATA

CLOCK

>20 256f

24 384f
24 384f

24 384f
1 0 0 reserved −−−
1 0 1 LSB fixed 16 bits 384f
1 1 0 LSB fixed 18 bits 384f
1 1 1 LSB fixed 20 bits 384f

s
s
s

32 384f

32 384f

32 384f

(fs= 32, 44.1 or

s

(1)

SYSCLKO

s
s
s
s

s
s
s

Note

1. Number of clock pulses within half an audio sample.

1995 Dec 08 6