Datasheet TDA1305T Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA1305T

Stereo 1fs data input up-sampling
filter with bitstream continuous dual
DAC (BCC-DAC2)

Preliminary specification
Supersedes data of September 1994
File under Integrated Circuits, IC01

1995 Dec 08

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

FEATURES

• Easy application

• 16fs Finite-duration Impulse-Response (FIR)

filter incorporated

• Selectable system clock (f

• I2S-bus serial input format (at f

16, 18 or 20 bits serial input mode (at f

• Slave-mode clock system

• Cascaded 4-stage digital filter incorporating 2-stage FIR

filter, linear interpolator and sample-and-hold

• Smoothed transitions before and after muting
(soft mute)

• Digital de-emphasis filter for three sampling rates of
32 kHz, 44.1 kHz and 48 kHz

• 12 dB attenuation via the attenuation input control

• Double speed mode

• 2nd order noise shaper

• 96 (f

= 384fs) or 128 (f

sys

in normal speed mode

• 48 (f

= 384fs) or 64 (f

sys

in double speed mode

• Bitstream continuous calibration concept

• Small outline SO28 package

• Voltage output 1.5 V (RMS) at line drive level

• Low total harmonic distortion

• No zero crossing distortion

• Inherently monotonic

• No analog post filtering required

• Superior signal-to-noise ratio

• Wide dynamic range (18-bit)

• Single rail supply (3.4 to 5.5 V).

) 256fs or 384f

sys

= 256fs) or LSB fixed

sys

= 256fs) times oversampling

sys

= 256fs) times oversampling

sys

sys

s

= 384fs)

bitstream converter for low signals while large signals are
generated using the dynamic continuous calibration
technique, thus resulting in low power consumption, small
chip size and easy application.

The TDA1305T is a dual CMOS DAC with up-sampling
filter and noise shaper. The combination of high
oversampling up to 16f
continuous calibration conversion ensures that only simple
1st order analog post filtering is required.

The TDA1305T supports the I2S-bus data input mode with
word lengths of up to 20 bits (at f
fixed serial data input format with word lengths of 16, 18
and 20 bits (at f
increase the oversampling rate to 16 times. A
sample-and-hold function increases the oversampling rate
to 96 times (f
2nd order noise shaper converts this oversampled data to
a bitstream for the 5-bit DACs.

The DACs are of the continuous calibration type and
incorporate a special date coding. This ensures an
extremely high signal-to-noise ratio, superior dynamic
range and immunity to process variation and component
ageing.

Two on-board operational amplifiers convert the
digital-to-analog current to an output voltage. Externally
connected capacitors perform the required 1st order
filtering so that no further post filtering is required.

TDA1305T

, 2nd order noise shaping and

s

= 256fs) and the LSB

sys

= 384fs). Four cascaded FIR filters

sys

= 384fs) or 128 times (f

sys

sys

= 256fs). A

GENERAL DESCRIPTION

The TDA1305T is a new generation of filter-DAC which
features a unique combination of bitstream and continuous
calibration techniques. The converter functions as a

The unique combination of bitstream and continuous
calibration techniques, together with a high degree of
analog and digital integration, results in a single filter-DAC
with 18-bit dynamic range, high linearity and simple low
cost application.

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA1305T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1

1995 Dec 08 2

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with

TDA1305T

bitstream continuous dual DAC (BCC-DAC2)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDD

V

DDA

V

DDO

I

DDD

I

DDA

I

DDO

V

FS(rms)

(THD + N)/S total harmonic distortion

S/N signal-to-noise ratio at

BR

ns

BR

ds

f

sys

TC

FS

T

amb

digital supply voltage note 1 3.4 5.0 5.5 V
analog supply voltage note 1 3.4 5.0 5.5 V
operational amplifier

note 1 3.4 5.0 5.5 V

supply voltage
digital supply current V

DDD

=5V;

− 30 − mA

at code 00000H

analog supply current V

DDA

=5V;

− 5.5 8 mA

at code 00000H

operating amplifier supply
current

full-scale output voltage

V

=5V;

DDO

at code 00000H
V

DDD=VDDA=VDDO

− 6.5 9 mA

= 5 V 1.425 1.5 1.575 V

(RMS value)

at 0 dB signal level −−90 −81 dB

plus noise-to-signal ratio

− 0.003 0.009 %

at −60 dB signal level −−44 −40 dB

− 0.63 0.1 %

bipolar zero

at −60 dB signal level;
A-weighted

A-weighting;
at code 00000H

−−46 − dB

− 0.5 − %

100 108 − dB

input bit rate at data input fs= 48 kHz; normal speed −− 3.072 Mbits
input bit rate at data input fs= 48 kHz; double speed −− 6.144 Mbits
system clock frequency 6.4 − 18.432 MHz
full scale temperature

−±100 × 10−6−
coefficient at analog
outputs (VOL and VOR)

operating ambient

−30 − +85 °C
temperature

Note

1. All V

and VSS pins must be connected to the same supply.

DD

1995 Dec 08 3

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

BLOCK DIAGRAM

TDA1305T

Fig.1 Block diagram.

1995 Dec 08 4

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

PINNING

SYMBOL PIN DESCRIPTION

V

DDA

V

SSA

TEST1 3 test input; pin should be connected

BCK 4 bit clock input
WS 5 word select input
DATA 6 data input
CLKS1 7 clock selection1 input
CLKS2 8 clock selection2 input
V

SSD

V

DDD

TEST2 11 test input; pin should be connected

SYSCLKI 12 system clock input
n.c. 13 not connected (this pin should be left

n.c. 14 not connected (this pin should be left

V

SSD

SYSCLKO 16 system clock output
DEEM1 17 de-emphasis on/off; f

DEEM2 18 de-emphasis on/off; f

MUSB 19 mute input (active LOW)
DSMB 20 double-speed mode input

ATSB 21 12 dB attenuation input

VOL 22 left channel output
FILTCL 23 capacitor for left channel 1st order

FILTCR 24 capacitor for right channel 1st order

VOR 25 right channel output
V

ref

V

SSO

V

DDO

1 analog supply voltage
2 analog ground

to ground (internal pull-down
resistor)

9 digital ground

10 digital supply voltage

to ground (internal pull-down
resistor)

open-circuit)

open-circuit)

15 digital ground

32 kHz,

DEEM

44 kHz and 48 kHz

32 kHz,

DEEM

44 kHz and 48 kHz

(active LOW)

(active LOW)

filter function should be connected
between pins 22 and 23

filter function should be connected
between pins 25 and 24

26 internal reference voltage for output

channels (0.5VDD)
27 operational amplifier ground
28 operational amplifier supply voltage

TDA1305T

Fig.2 Pin configuration.

1995 Dec 08 5

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with

TDA1305T

bitstream continuous dual DAC (BCC-DAC2)

FUNCTIONAL DESCRIPTION

The TDA1305T CMOS digital-to-analog bitstream
converter incorporates an up-sampling filter and noise
shaper which increase the oversampling rate of 1fs input
data to 96fs (f

= 192fs) or 128fs (f

sys

= 256fs) in the

sys

normal speed mode. In the double speed mode the
oversample rate of 1fs input data is increased to 48f
(f

= 384fs) or 64fs (f

sys

= 256fs). This oversampling,

sys

s

together with the 5-bit DAC, enables the filtering required
for waveform smoothing and out-of-band noise reduction
to be achieved by simple 1st order analog post filtering.

System clock and data input format

The TDA1305T accommodates slave mode only, this

provide a system clock of 256 or 384f
48 kHz). The system frequency is selectable by means of
pin CLKS1 and pin CLKS2. The SYSCLKO output (pin 16)
provides the system clock for external use.

The TDA1305T supports the following data input modes:

• I2S-bus with data word lengths of up to 20 bits
(at f

= 256fs).

sys

• LSB fixed serial format with data word lengths of 16, 18
and 20 bits (at f

= 384fs). As this format idles on the

sys

MSB it is necessary to know how many bits are being
transmitted.

The input format is shown in Fig.3. Left and right
data-channel words are time-multiplexed.

means that in all applications the system devices must

Table 1 Data input format and system clock.

TEST1 CLKS1 CLKS2 DATA INPUT FORMAT

000I

2

S up to 20 bits 256f
0 0 1 LSB fixed 16 bits 384f
0 1 0 LSB fixed 18 bits 384f
0 1 1 LSB fixed 20 bits 384f

SYSTEM

CLOCK

s
s
s
s

DATA

CLOCK

>20 256f

24 384f
24 384f

24 384f
1 0 0 reserved −−−
1 0 1 LSB fixed 16 bits 384f
1 1 0 LSB fixed 18 bits 384f
1 1 1 LSB fixed 20 bits 384f

s
s
s

32 384f

32 384f

32 384f

(fs= 32, 44.1 or

s

(1)

SYSCLKO

s
s
s
s

s
s
s

Note

1. Number of clock pulses within half an audio sample.

1995 Dec 08 6

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

1995 Dec 08 7

Fig.3 Input formats.

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

Mute

Soft mute is controlled by the MUSB at pin 9. When the
input is active LOW the value of the samples is decreased
smoothly to zero following a cosine curve. To step down
the value of the data 32 coefficients are used, each one
being used 31 times before stepping onto the next. When
MUTE is released (pin 19 = HIGH), the samples are
returned to the full level again following a cosine curve with
the same coefficients being used in the reverse order.
Mute is synchronized to prevent operation in the middle of
a word.

De-emphasis

A digital de-emphasis is implemented for three sample
rates (32, 44.1 and 48 kHz). By selecting DEEM1 and
DEEM2 de-emphasis can be applied by means of a FIR
filter. Time constants of the de-emphasis are 50 µs and
15 µs. De-emphasis is synchronized to prevent operation
in the middle of a word. The de-emphasis deviation from
ideal 50 µs and 15 µs de-emphasis is given in Table 4.

Oversampling filter (normal-speed mode)

In the normal-speed mode the oversampling filter
consists of:

• A 91st order half-band low-pass FIR filter which

• A 23rd order quarter band low-pass FIR filter which

• A linear interpolation section which increases the

• A sample-and-hold section which provides another

Pass-band ripple and stop-band attenuation for
normal-speed are given in Table 3.

Oversampling filter (double-speed mode)

TDA1305T

increases the oversampling rate from 1 time to 2 times.

increases the oversampling rate from 2 times to 8 times.

oversampling rate to 16 times. This removes the
spectral components around 8fs.

6 times oversampling to 96 times. The zero-order hold
characteristic of this sample-and-hold section plus the
1st order analog filtering remove the spectral
components around 16fs.

Table 2 De-emphasis.

DEEM1 DEEM2 CONDITION

0 0 de-emphasis disabled
0 1 de-emphasis for f
1 0 de-emphasis for f
1 1 de-emphasis for f

Attenuation

Attenuation is controlled by the
the input is active LOW the sample is multiplied by a
coefficient that provides 12 dB attenuation. If the input is
HIGH the multiplication factor is 1. Attenuation is
synchronized to prevent operation in the middle of a word.

Double-speed mode

Double speed is controlled by the
When the input is active LOW the device operates in the
double-speed mode.

ATSB input (pin 21). When

DSMB input (pin 20).

= 32 kHz

s

= 4.1 kHz

s

= 48 kHz

s

In the double-speed mode the oversampling filter
consists of:

• A 51st order half-band low-pass FIR filter which
increases the oversampling rate from 1 time to 2 times.

• A 7th order half-band low-pass FIR filter which
increases the oversampling rate from 2 times to 4 times.

• A linear interpolation section which increases the
oversampling rate to 8 times. This removes the spectral
components around 4f

• A sample-and-hold section which provides another
6 times oversampling to 48 times. The zero-order hold
characteristic of this sample-and-hold section plus the
1st order analog filtering remove the spectral
components around 8fs.

Pass-band ripple and stop-band attenuation for
double-speed are given in Table 3.

.

s

1995 Dec 08 8

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

Noise shaper

In the normal speed mode the 2nd order digital noise
shaper operates at 96fs (f
(f

= 256fs). The digital noise shaper operates at 48f

sys

(f

= 384fs) or 64fs (f

sys

sys

= 384fs) or 128f

sys

s

s

= 256fs) in double-speed mode. It
shifts in-band quantization noise to frequencies well above
the audio band. This noise shaping technique used in
combination with a special data coding enables extremely
high signal-to-noise ratios to be achieved. The noise
shaper outputs a 5-bit pulse duration modulation (PDM)
bitstream signal to the DAC.

Continuous calibration DAC

The dual 5-bit DAC uses the continuous calibration
technique. This method, based on charge storage,
involves exact duplication of a single reference current
source. In the TDA1305T, 32 such current sources plus
1 spare source are continuously calibrated. The spare
source is included to allow continuous converter operation.

The DAC receives a 5-bit data bitstream from the noise
shaper. This data is then converted so that only small
currents are switched to the output during digital silence

(input 00000H). Using this technique extremely high
signal-to-noise performance is achieved.

Operational amplifiers

High precision, low-noise amplifiers together with the
internal conversion resistors R
the converter output current to a voltage capable of driving
a line output. This voltage is available at VOL and VOR
(1.5 V RMS typical).

Connecting external capacitors CEXT1 and CEXT2
between FILTCL and VOL and between FILTCR and VOR
respectively provides the required 1st order post filtering
for the left and right channels (see Fig.1). The
combinations of R
CEXT2 determine the 1st order fall-off frequencies.

Internal reference circuitry

Internal reference circuitry ensures that the output voltage
signal is proportional to the supply voltage, thereby
maintaining maximum dynamic range for supply voltages
from 3.4 to 5.5 V and making the circuit also suitable for
battery-powered applications.

with CEXT1 and R

CONV1

CONV1

TDA1305T

and R

CONV2

CONV2

convert

with

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
V
T
T
T
V

DDD
DDA
DDO
xtal
stg
amb
es

digital supply voltage − 7.0 V
analog supply voltage − 7.0 V
operational amplifier supply voltage − 7.0 V
maximum crystal temperature − +150 °C
storage temperature −65 +150 °C
ambient operating temperature −30 +85 °C
electrostatic handling note 1 −2000 +2000 V

note 2 −200 +200 V

Notes

1. Human body model; C = 100 pF, R = 1500 Ω, V = 2000 V, 3 pulses positive and 3 pulses negative.

2. Machine model; C = 200 pF, R = 10 Ω, L = 0.5 µH.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 75 K/W

1995 Dec 08 9

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with

TDA1305T

bitstream continuous dual DAC (BCC-DAC2)

QUALITY SPECIFICATION

In accordance with

Handbook”

. The handbook can be ordered using the code 9398 510 63011.

DIGITAL CHARACTERISTICS

= 3.4 to 5.5 V; VSS=0V; T

V

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDD

I

DDD

V

DDA

I

DDA

V

DDO

I

DDO

RR ripple rejection to V

System clock input

f

sys

V

IL

V

IH

I

 input leakage current note 4 −−10 µA

LI

C

i

T

cy

Digital inputs; WS, BCK, DATA,

V

IL

V

IH

I

 input leakage current note 4 −−10 µA

LI

C

i

Digital output; CDEC

V

OL

V

OH

t

r

t

f

C

L

“SNW-FQ-611E”

. The number of this quality specification can be found in the

= −40 to +85 °C; unless otherwise specified.

amb

“Quality Reference

digital supply voltage note 1 3.4 5.0 5.5 V
digital supply current V

DDD

=5V;

− 30 40 mA

at code 00000H
analog supply voltage note 1 3.4 5.0 5.5 V
analog supply current V

DDA

=5V;

− 5.5 8 mA

at code 00000H
operational amplifier supply

note 1 3.4 5.0 5.5 V
voltage

operational amplifier supply
current

DDA

system frequency f

LOW level input voltage note 3 −0.5 − 0.2V
HIGH level input voltage note 3 0.8V

V

DDO

=5V;

− 6.5 9 mA

at code 00000H

note 2 − 25 − dB

f

sys
sys

= 384f
= 256f

s
s

9.6 16.93 18.4 MHz

6.4 11.29 12.28 MHz
V

DD

DD

− VDD+ 0.5 V

input capacitance −−10 pF
clock cycle time f

f

sys
sys

= 384f
= 256f

s
s

104 59.1 54.2 ns
156 88.6 81.3 ns

DSMB, MUSB, DEEM1, DEEM2, ATSB, CLKS1, CLKS2, TEST1 and TEST2

LOW level input voltage note 3 −0.5 − 0.3V
HIGH level input voltage note 3 0.7V

DD

− VDD+ 0.5 V

DD

V

input capacitance −−10 pF

LOW level output voltage IOL= 0.4 mA 0 − 0.5 V
HIGH level output voltage IOH= −0.2 mA VDD− 0.5 − V

DD

V

output rise time note 5 −−20 ns
output fall time note 5 −−20 ns
load capacitance −−30 pF

1995 Dec 08 10

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with

TDA1305T

bitstream continuous dual DAC (BCC-DAC2)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Serial input data timing (see Fig.4)

f

BCK

bit-clock input (data input
rate) frequency

f

WS

t

r

t

f

t

H

t

L

t

su

t

h

t

suWS

t

hWS

word select input frequency normal speed 25 44.1 48 kHz

rise time −−20 ns
fall time −−20 ns
bit clock time HIGH 55 −−ns
bit clock time LOW 55 −−ns
data set-up time 40 −−ns
data hold time 10 −−ns
word select set-up time 40 −−ns
word select hold time 10 −−ns

Notes

1. All VDD and VSS pins must be connected externally to the same supply.

2. V

= 1% of supply voltage; f

ripple

capacitor (C

EXT3

ripple

in Fig.1) connected to V

3. Minimum VIL and maximum VIHare peak values to allow for transients.

4. I

measured at VI= 0 V; I

LImni

measured at VI= 5.5 V.

LImax

5. Reference levels = 10% and 90%.

f
f

sys
sys

= 384f
= 256f

s
s

− 48f

− 64f

s
s

− MHz

− MHz

double speed 50 88.2 96 kHz

= 100 Hz. Ripple rejection RR to V

. The value here assumes that C

ref

is dependent on the value of the external

DDA

=1µF.

EXT3

ANALOG CHARACTERISTICS

V

DD=VDDA=VDDO

=5V; VSS=0V; T

=25°C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Reference values

V
R

ref

CONV

reference voltage level 2.45 2.5 2.55 V
current-to-voltage

1.6 2.2 2.8 kΩ

conversion resistor

Analog outputs

RES resolution −− 18 bit
V

FS(rms)

full-scale output voltage

1.425 1.5 1.575 V
(pins 23 and 25)
(RMS value)

V

OFF

output voltage DC offset with

−80 −65 −50 mV
respect to reference voltage
level V

ref

TC

FS

full scale temperature

−±100 × 10−6−
coefficient

1995 Dec 08 11

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with

TDA1305T

bitstream continuous dual DAC (BCC-DAC2)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

S/N signal-to-noise ratio at

bipolar zero

α

cs

δV

 unbalance between outputs − 0.2 0.3 dB

O

 dynamic output impedance − 10 −Ω

Z

O

R

L

C

L

Notes

1. Measured with a 1 kHz, 0 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured
over a bandwidth of 20 Hz to 20 kHz.

2. Measured with a 1 kHz, -60 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured
over a bandwidth of 20 Hz to 20 kHz. For 16-bit input signals, the performance is limited to the theoretical maximum.

3. Measured with a 1 kHz, -60 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured
over a bandwidth of 20 Hz to 20 kHz and filtered with a A-weighted characteristic. For 16-bit input signals, the
performance is limited to the theoretical maximum.

4. Measured with a sine wave from 20 Hz to 20 kHz generated at a sampling rate of 48 kHz. The (THD + N)/S
measured over a bandwidth of 20 Hz to 20 kHz.

channel separation 85 100 − dB

output load resistance 3 −−kΩ
output load capacitance −− 200 pF

at 0 dB input level;
note 1

at −60 dB input level;
note 2

at −60 dB input level;
A-weighted; note 3

at 0 dB input level;
(20 Hz to 20 kHz);
note 4

A weighted;
at code (00000H)

−−90 −81 dB

− 0.003 0.009 %

−−44 −40 dB

− 0.63 1.0 %

−−46 − dB

− 0.5 − %

−−90 −81 dB

− 0.003 0.003 %

100 108 − dB

TEST AND APPLICATION INFORMATION
Filter characteristics (theoretical values)
Table 3 Normal speed filter characteristics.

ITEM SAMPLE FREQUENCY RANGE CONDITIONS CHARACTERISTICS

Pass band 44.1 kHz 0 to 20 kHz 0 ±0.025 dB

32 kHz 14.5 to 15 kHz −0.15 dB (min.)

Stop band 44.1 kHz 24.1 to 150 kHz typical −60 dB (max.)

worst case −57 dB (max.)

150 kHz to infinity typical −57 dB (max.)

worst case −47 dB (max.)

32 kHz 17 to 17.5 kHz −40 dB (max.)

1995 Dec 08 12

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

De-emphasis filter characteristics (theoretical values)
Table 4 De-emphasis deviation from ideal 50 µs to 15 µs de-emphasis network.

ITEM SAMPLE FREQUENCY RANGE CHARACTERISTICS

Gain deviation 44.1 and 48 kHz 0 to 18 kHz 0 ±0.05 dB

18 to 20 kHz 0.12 dB (max.)

32 kHz 0 to 13 kHz 0 ±0.06 dB

13 to 15 kHz 0.22 dB (max.)

Phase deviation 44.1 and 48 kHz 0 to 15 kHz 10 deg (max.)

15 to 20 kHz 15 deg (max.)

32 kHz 0 to 9 kHz 10 deg (max.)

9 to 15 kHz 16 deg (max.)

Double-speed characteristics
Table 5 Double-speed filter characteristics.

ITEM RANGE CONDITIONS CHARACTERISTICS

Pass band 0 to 17 kHz 0 ±0.075 dB

17 to 20 kHz −0.3 dB (min.)

Stop band 24.1 to 150 kHz typical −47 dB (max.)

worst case −45 dB (max.)

150 kHz to infinite typical −33 dB (max.)

worst case −25 dB (max.)

TDA1305T

Fig.4 Timing of input signals.

1995 Dec 08 13

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

APPLICATION INFORMATION

TDA1305T

Fig.5 Application diagram.

1995 Dec 08 14

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

A typical application diagram is illustrated in Fig.5. The left
and right channel outputs can drive a line output directly.
The series inductor (L) in the digital supply line, though not
strictly necessary, helps to reduce crosstalk between the
digital and analog circuits.

In Fig.6 measurements were taken with an 18-bit sine
wave generated at a sampling rate of 48 kHz. The
(THD + N)/S was measured over a bandwidth of
20 Hz to 20 kHz. The graph was constructed from average

measurement values of a small amount of engineering
samples. No guarantee for typical values is implied.

In Fig.6 measurements were taken with an 18-bit sine
wave generated at a sampling rate of 48 kHz. The
(THD + N)/S was measured over a bandwidth of
20 Hz to 20 kHz and filtered with A-weighted
characteristics. The graph was constructed from average
measurement values of a small amount of engineering
samples. No guarantee for typical values is implied.

TDA1305T

(1) Level = −60 dB.
(2) Level = 0 dB.

Fig.6 Total harmonic distortion as a function of signal frequency.

1995 Dec 08 15

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

TDA1305T

Fig.7 Total harmonic distortion as a function of signal level; (A-weighted).

1995 Dec 08 16

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

PACKAGE OUTLINE

SO28: plastic small outline package; 28 leads; body width 7.5 mm

D

c

y

Z

28

15

TDA1305T

SOT136-1

E

H

E

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

max.

2.65

0.10

A

1

0.30

0.10

0.012

0.004

A2A3b

2.45

0.25

2.25

0.096

0.01

0.089

p

0.49

0.36

0.019

0.014

0.32

0.23

0.013

0.009

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

18.1

7.6

17.7

7.4

0.71

0.30

0.69

0.29

14

w M

b

p

scale

eHELLpQ

1.27

0.050

10.65

10.00

0.419

0.394

1.4

0.055

Q

A

2

0.043

0.016

A

1.1

0.4

L

p

L

0.25 0.1

0.01

(A )

1

detail X

1.1

0.25

1.0

0.043

0.01

0.039

A

3

θ

ywv θ

Z

0.9

0.4

0.035

0.004

0.016

o

8

o

0

OUTLINE
VERSION

SOT136-1

IEC JEDEC EIAJ

075E06 MS-013AE

REFERENCES

1995 Dec 08 17

EUROPEAN

PROJECTION

ISSUE DATE

95-01-24
97-05-22

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

Reflow soldering

Reflow soldering techniques are suitable for all SO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

(order code 9398 652 90011).

Wave soldering

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward

• The longitudinal axis of the package footprint must be

• The package footprint must incorporate solder thieves at

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

TDA1305T

pressure followed by a smooth laminar wave) soldering
technique should be used.

parallel to the solder flow.

the downstream end.

1995 Dec 08 18

Philips Semiconductors Preliminary specification

Stereo 1fs data input up-sampling filter with

TDA1305T

bitstream continuous dual DAC (BCC-DAC2)

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1995 Dec 08 19

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. [phone], Fax. [phone]

Brazil: Rua do Rocio 220 - 5

CEP: 04552-903-SÃO PAULO-SP, Brazil,
P.O. Box 7383 (01064-970),
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS:

Tel. [phone], Fax. [phone]

Chile: Av. Santa Maria 0760, SANTIAGO,

Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,

77621 BOGOTA, Tel. [phone],
Fax. [phone]

Denmark: Prags Boulevard 80, PB 1919, DK-2300

COPENHAGEN S, Tel. [phone], Fax. [phone]

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex,
Tel. [phone], Fax. [phone]

Germany: P.O. Box 10 51 40, 20035 HAMBURG,

Tel. [phone], Fax. [phone]

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone] 911, Fax. [phone]

India: Philips INDIA Ltd, Shivsagar Estate, A Block,

Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. [phone], Fax. [phone]

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS S.r.l.,

Piazza IV Novembre 3, 20124 MILANO,
Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
Fax. [phone]

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. [phone], Fax. [phone]

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

South Africa: S.A. PHILIPS Pty Ltd.,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430, Johannesburg 2000,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,

Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. [phone], Fax. [phone]

Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165,

252148 KIEV, Tel.[phone], Fax. [phone]

United Kingdom: Philips Semiconductors LTD.,

276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. [phone], Fax. [phone]

United States:811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD47 © Philips Electronics N.V. 1995

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

513061/50/02/pp20 Date of release: 1995 Dec 08
Document order number: 9397 750 00517