OKI MSM6562B-xx Datasheet
E2B0035-27-Y3
¡ Semiconductor MSM6562B-xx
¡ Semiconductor
This version: Nov. 1997
Previous version: Mar. 1996
MSM6562B-xx
DOT MATRIX LCD CONTROLLER DRIVER
GENERAL DESCRIPTION
The MSM6562B-xx controls a character type dot matrix LCD in combination with an 8-bit or 4bit microcontroller.
The MSM6562B-xx can control a display of up to 40 characters. With the display data serial
transfer function, the MSM6562B-xx, when used in combination with the character extension IC
(MSM5259), can control a maximum of 80 characters.
FEATURES
• Easy interface with an 8-bit or 4-bit microcontroller.
• Dot matrix LCD controller driver for 5 ¥ 7 dots font or 5 ¥ 10 dots font.
• Automatic power ON reset.
• 16 COMMON signal drivers and 100 SEGMENT signal drivers are built in.
• Can control up to 80 characters when used in combination with MSM5259.
• Built-in character generator ROM for 160 characters with 5 ¥ 7 dots font and 32 characters with
5 ¥ 10 dots font.
• Character patterns can be programmed by CG RAM. (5 ¥ 8 dots font: 8 kinds, 5 ¥ 11 dots font:
4 kinds)
• 1/8 duty (1 line; 5 ¥ 7 dots + cursor), 1/11 duty (1 line; 5 ¥ 10 dots + cursor), or 1/16 duty (2
lines; 5 ¥ 7 dots + cursor) selectable.
• Built-in RC oscillation circuit by an external resistor or an internal resistor.
• Built-in bias dividing resistors for LCD driving.
• Built-in contrast adjusting circuit.
• Bidirectional transfer available on segment output.
• Aluminum pad chip (Product name: MSM6562B-xx)
xx indicates code number.
1/50
BLOCK DIAGRAM
¡ Semiconductor MSM6562B-xx
2/50
V
V
OSC
OSC
OSC
R/W
RS
RS
DB0 - DB
DB4 - DB
DD
V
V
V3'
V
V
V
V5'
L
SS
CP
DF
1
R
2
E
0
1
4
3
4
7
T
1
T
2
T
3
1
2
3
4
5
Timing
generation
circuit
Input/
output
buffer
8
Test
circuit
voltage dividing circuit
LCD bias
5
Instruction
5
Contrast
register
(IR)
Data
register
(DR)
Busy flag
(BF)
register
(CR)
7
88
Instruction
decoder
(ID)
7
Cursor blink
control
Character
generator
RAM
5
Parallel/ serial
conversion
16-bit
shift
register
COMMON
16 16
signal
driver
COM
1 - 16
(CG RAM)
8
8
5
Character generator
ROM (CG ROM)
100-bit shift register
100-bit latch
100
100
SEGMENT signal driver
100
SEG
1 - 100
8
Address
counter
(ADC)
7
Display data
RAM
(DD RAM)
DO
SHL
SHL
0
1
¡ Semiconductor MSM6562B-xx
INPUT AND OUTPUT CONFIGURATION
V
DD
V
DD
V
DD
V
DD
P
N
Applied to Pin E. Applied to Pins R/W, RS0 and RS1.
V
DD
Applied to Pins T1, T2 and T3.
V
DD
P
N
V
DD
P
N
Applied to DB
- DB7.
0
P
N
V
DD
P
N
Applied to DO, CP, L and DF.
P
N
3/50
¡ Semiconductor MSM6562B-xx
PIN DESCRIPTIONS
Symbol Description
R/W
RS0, RS
1
E
- DB
DB
0
7
OSC1, OSC2,
OSC
R
COM1 - COM
SEG1 - SEG
SHL0, SHL
100
1
DO Data output pin to send serial data to the character extension IC.
CP Clock output pin to transfer the serial data to the character extension IC.
L Latch output pin to latch the transferred data to the character extension IC.
DF Output pin for the alternating signal (DF, display frequency) required for an LCD display.
V
DD
V
SS
V1 - V5, V3' Bias voltage input pins to drive an LCD and bias setting pin. (Built-in bias dividing resistor)
V5' Contrast adjusting voltage output pin.
Read/write selection input pin.
"H": Read, and "L": Write
Register selection input pins.
RS0 "H" RS1 "H": Data register
RS0 "L" RS1 "H": Instruction register
RS0 "L" RS1 "L": Contrast register
Input pin for data input/output between CPU and MSM6562B-xx and for activating
instruction.
Input/output pins for data send/receive between CPU and MSM6562B-xx.
Clock oscillating pins required for internal operation upon receipt of CPU instruction and
the LCD drive signal.
When oscillated by an external resistor, connect a resistor between OSC
When oscillated by a built-in resistor, connect OSC
LCD COMMON signal output pins.
16
and OSC2 externally.
R
LCD SEGMENT signal output pins.
Input pins to control the transfer direction of the SEGMENT signal output data. See table below.
Power supply pin.
Ground pin.
1/4 bias : Connect V
1/5 bias : Connect V
Since V
V
SS
value depends on V5 voltage, connect a variable resistor between V5 pin and
LCD
potential or connect V5 pin and V5' pin to adjust V
and V3. Leave V3' open.
2
and V3'.
3
LCD
.
and OSC2.
1
SHL
SHL
0
1
LL
LH
HL
HH
Segment data transfer direction
SEG1ÆSEG
SEG
100
ÆSEG
100
1
SEG1ÆSEG50fiSEG
SEG
ÆSEG
100
1
100
ÆSEG
51
4/50
¡ Semiconductor MSM6562B-xx
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage
Supply voltage for LCD
display
Input voltage
Junction temperature
Storage temperature
Symbol
V
DD
V1, V2, V3,
, V
V
4
5
V
I
T
j
T
STG
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
—
—
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage
LCD driving voltage
Operating temperature
*1 This voltage should be applied to VDD – V5.
Voltages applicable to V1, V2, V3 and V4 are as follows:
V1 = VDD – 1/4 (VDD – V5)
V2 = V3 = VDD – 1/2 (VDD – V5)
V4 = VDD – 3/4 (VDD – V5)
Symbol
V
DD
V
LCD
op
Condition
– V
V
DD
VDD – V
—
1/4 bias
SS
1/5 bias
SS
—T
*
*
1
2
Rating
–0.3 to + 7.0
–0.3 to V
–0.3 to V
150
–55 to + 150
Range
4.5 to 5.5
3.0 to 5.5
3.0 to 5.5
–30 to +85
DD
DD
+ 0.3
+ 0.3
3
*
3
*
Unit
V
V
V
°C
°C
Unit
V
V
V
°C
Applicable Pin
VDD, V
SS
V
, V2, V3,
1
, V
V
4
5
R / W, RS1,
, E,
RS
0
- DB
DB
0
7
OSC
1
—
—
Applicable Pin
VDD, V
SS
, V
V
DD
5
—
*2 This voltage should be applied to VDD – V5.
Voltages applicable to V1, V2, V3 and V4 are as follows:
V1 = VDD – 1/5 (VDD – V5)
V2 = VDD – 2/5 (VDD – V5)
V3 = VDD – 3/5 (VDD – V5)
V4 = VDD – 4/5 (VDD – V5)
*3 The relation of VDD > V1 > V
≥ V
(=V3') > V4 > V
2
3
(High ¨Æ Low)
LCD driving voltage can be adjusted by varying V5.
However, V5 cannot be used under VSS voltage.
≥ V
5
must be kept.
SS
5/50
¡ Semiconductor MSM6562B-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 4.5 to 5.5V, Ta = -30 to +85°C)
Parameter
"H" input voltage
"H" input voltage
"L" input voltage
"H" output voltage
"L" output voltage
"H" output voltage
"L" output voltage
COM voltage drop
Symbol
V
IH1
IL1
V
IH2
V
IL2
V
OH1
V
OL1
V
OH2
V
OL2
V
C
Condition
I
= –0.205mA
O
= 1.6mA
I
O
= –40mA
I
O
= 40mA
I
O
I
= ± 40mA
O
(Note 1)
—
Min.
2.2
Typ.—Max.
V
— –0.3 — 0.6
—
—
V
0.9V
DD
– 0.8
–0.3
2.4
—
—
—
DD
—V
—
—
—
—
—
—
0.8
—
0.4
—
0.1V
2.3
DD
DD
DD
Unit
V
V"L" input voltage V
V
V
V
V
V
V
V
Applied Pin
R/W, RS
0
DB0 - DB
OSC
SHL0, SHL
DB0 - DB
DO, CP, L,
DF, OSC
COM1 - COM
, RS1, E,
7
1
1
7
2
16
SEG voltage drop
Input leakage current
"H" input current
"L" input current I
Supply current
LCD driving bias
resistance
Variable range by built-in
variable resistor for LCD
driving voltage
V
S
I
IL
I
IH2
IO = ± 40mA
(Note 1)
= V
V
I
DD
VI = V
SS
VI = V
DD
Except the current flowing
to the pull-up resistor and
output driving MOS.
VDD = 5.0V
IL2
I
DD
LBR kW
V
LCD MAX
V
LCD MIN
= V
V
I
SS
V
= 5.0V
DD
E = "L" level, SHL
Built-in R
clock input to OSC
External clock frequency (f
270kHz.
R/W, RS
open.
Output pins are all no load. Except
bias current for LCD driving.
(Note 2, 3, 4)
, SHL1 = "L" level
0
oscillation or external
f
.
1
) is
IN
, RS1, and DB0 to DB7 are
0
—
V
= 5.0V, 1/5 bias
DD
VDD = 5.0V, 1/5 bias
—
—
—
—
—
—
3.0
1
–1
—— 2mA
–34
–83
–204
—— 1
248
4.6 — —
— — 3.7
V
mA
mA
mA
mA
V
SEG1 - SEG
E, SHL0, SHL
R/W, RS0, RS1,
VDD – V1, V1 – V
V2 – V3', V3 – V
V
DD
DB0 - DB
V
DD
V4 – V
– V5 (V5')
100
7
5
1
2
4
LCD driving bias voltage
(external input)
V
V
LCD1
LCD2
– V
V
DD
(Note 5)
5
1/5 bias
1/4 bias
3.0 — 5.5
3.0 — 5.5
V
VDD, V1, V2, V3,
V
', V
, V
3
4
5
6/50
¡ Semiconductor MSM6562B-xx
(Note 1) Applies to the voltage drop (VC) from VDD, V1, V4 and V5 to each COMMON pin
(COM1 to COM16) as well as to voltage drop (VS) from VDD, V2, V3 and V5 to each
SEG pin (SEG1 to SEG
) when 40mA is flowed through one COM or SEG pin.
100
When output level is at VDD, V1, or V2 level, 40mA is flowed out, while 40mA is
flowed in when the output level is at V3, V4 or V5 level.
This occurs when 5V is input to VDD, V1 and V2 , and 0V is input to V3, V4 and
V5.
(Note 2) Applies to the current value flowed in the pin VDD, in the case of VDD = 5V,
VSS = 0V, V1, V2 = 5V, V3, V4, V5 = 0V and V5' is open.
(Note 3) Built-in Rf oscillation circuit
OSC
1
Minimum wiring is required between OSCR and OSC2.
OSC
OSC
R
2
Leave OSC1 open.
(Note 4) External clock input circuit
Input pulse
OSC
OSC
OSC
1
R
2
Leave OSCR and OSC2 open.
(Note 5) Input the voltage to V5. (However, V5 cannot be used under VSS voltage.)
N (number of LCD lines)
Pin
V
1
V
2
V
3
V
4
V
5
1-line mode
Bias : 1/4
V
LCD
VDD –
4
V
LCD
VDD –
2
V
LCD
VDD –
2
3V
VDD – V
LCD
4
LCD
VDD –
2-line mode
Bias : 1/5
V
LCD
VDD –
5
2V
VDD – V
LCD
5
3V
LCD
5
4V
LCD
5
LCD
VDD –
VDD –
VDD –
At 1/4 bias : Connect V2 and V3 externally and leave V3' open.
At 1/5 bias : Connect V3 and V3' externally.
V
is the LCD driving voltage. (For N [number of LCD lines], refer to
LCD
the explanation of the Function setting instruction of the instruction code.)
7/50
¡ Semiconductor MSM6562B-xx
y
AC Characteristics
Parameter Symbol Condition Unit
R
= 120 kW ± 2%
Rf clock oscillation
frequency
f
External clock frequency f
External clock duty f
External clock rise time t
External clock fall time t
Built-in Rf clock
oscillation frequency
f
OSC1
IN
duty
rf
ff
OSC2
f
(Note 1)
OSC
and OSC2 are open.
R
Input a pulse to OSC
(Note 4)
(Note 2)
(Note 3)
(Note 3)
OSC
is open.
1
Connect OSC
(Note 5)
and OSC2.
R
(Note 1)
OSC
OSC
OSC
1
R
R
2
f
Minimum wiring is required between OSC1 and Rf and
between OSC2 and Rf.
Leave OSCR open.
Min. Typ. Max.
.
1
R
= 120kW ± 2%
f
Applicable Pin
kHz175 270 350
kHz125 — 480
%45 50 55
ms— — 0.2
ms— — 0.2
kHz140 280 480
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
1
2
1
1
1
1
1
R
2
(Note 2)
t
HW
V
DD
f
IN
2
V
DD
2
waveform
f
= t
dut
/(tHW + tLW) ¥ 100 (%)
HW
(Note 3) Applies to the pulse to be input to OSC
V
– 0.8V
DD
f
IN
0.8V
V
– 0.8V
DD
0.8V
waveform
t
rf
t
ff
(Note 4) See Note 4 to "DC Characteristics."
t
LW
Applies to the pulse to be
input to OSC
V
DD
1
2
.
1
Applies to the pulse to be
input to OSC
1
(Note 5) See Note 3 to "DC Characteristics."
8/50
¡ Semiconductor MSM6562B-xx
Switching Characteristics
1. Timing for input from the CPU (write operation)
= 4.5 to 5.5V, Ta = –30 to +85°C)
(V
DD
Parameter Symbol
R/W, RS0 and RS1 setup time
E "H" pulse width
R/W, RS
and RS1 hold time
0
E rise time
E fall time
E "L" pulse width
E cycle time
DB
to DB7 input data setup time
0
DB
to DB7 input data hold time
0
RS1,
0
R/W
E
Min. Typ. Max. Unit
t
B
t
W
t
A
t
r
t
f
t
L
t
C
t
I
t
H
V
IH1
V
IL1
V
IL1
t
B
t
L
V
IL1
V
IL1
40
220
10
—
—
210
500
100
10
t
r
V
IH1
—
—
—
—
—
—
—
—
—
t
t
W
f
V
IH1
t
I
—
—
—
20
20
—
—
—
—
V
IH1
V
IL1
V
IL1
t
A
V
IL1
t
H
ns
ns
ns
ns
ns
ns
ns
ns
ns
DB
0-7
V
IH1
Input data
V
IL1
t
c
V
IH1
V
IL1
9/50
¡ Semiconductor MSM6562B-xx
2. Timing for output to the CPU (read operation)
= 4.5 to 5.5V, Ta = –30 to +85°C)
(V
DD
Parameter Symbol
R/W, RS0 and RS1 setup time
E "H" pulse width
R/W, RS
and RS1 hold time
0
E rise time
E fall time
E "L" pulse width
E cycle time
DB
to DB7 data ouput delay time
0
DB
to DB7 data ouput hold time
0
RS1,
0
R/W
Min. Typ. Max. Unit
t
B
t
W
t
A
t
r
t
f
t
L
t
C
t
D
t
O
V
IH1
V
IL1
V
IL1
40
220
10
—
—
210
500
—
20
—
—
—
—
—
—
—
—
—
—
—
—
20
20
—
—
150
—
V
IH1
V
IL1
V
IL1
ns
ns
ns
ns
ns
ns
ns
ns
ns
DB
t
t
B
t
E
0-7
V
IL1
L
V
IL1
r
V
IL1
t
c
t
W
t
D
V
OH1
V
OL1
t
f
V
IH1
Output data
t
A
V
IL1
t
O
V
OH1
V
OL1
10/50
¡ Semiconductor MSM6562B-xx
3. Timing for output to character extension IC
(V
= 4.5 to 5.5V, Ta = –30 to +85°C)
DD
Parameter Symbol
CP "H" pulse width
CP "L" pulse width
DO setup time
DO hold time
L clock setup time
L clock hold time
L "H" pulse width
DF delay time
DO
V
OH2
CP
t
HW1
Min. Typ. Max. Unit
t
HW1
t
LW
t
S
t
DH
t
SU
t
HO
t
HW2
t
M
V
OH2
V
OL2
t
LW
V
OH2
V
OL2
t
S
V
OH2
V
OL2
800
800
300
300
500
100
800
–1000
V
OH2
V
OH2
t
DH
V
OL2
t
SU
—
—
—
—
—
—
—
—
V
OH2
t
HO
—
—
—
—
—
—
—
1000
ns
ns
ns
ns
ns
ns
ns
ns
L
DF
V
OH2
t
HW2
V
OH2
V
OL2
t
M
V
OH2
11/50
¡ Semiconductor MSM6562B-xx
FUNCTIONAL DESCRIPTION
1. Instruction Register (IR), Data Register (DR), Contrast Register (CR)
These three registers are selected by the register selector pins, RS0 and RS1.
When RS0 and RS1 are "H" level input, the DR is selected and when RS0 = "L" level input and RS
= "H", the IR is selected. On the other hand, when RS0 and RS1 are "L" level input, the CR is
selected. (When RS0 = "H" level input and RS1 = "L", the registers are ignored.)
The IR is used to store the address codes for the display data RAM (DD RAM) or character
generator RAM (CG RAM) and instruction codes.
The IR can be written into, but not be read out by the microcomputer (CPU).
The CR can be used to read out and write. The CR values provide 0 to 1F (hexadecimal) and when
this value is 0, V
1F.) Therefore, the contrast can be adjusted by varying the CR value (providing that V5 and V5'
are connected).
The DR is used to write into/read out the data to/from the DD RAM or CG RAM.
The data written to the DR by the CPU is automatically written to the DD RAM or CG RAM as
an internal operation.
When an address code is written to the IR, the data (of the specified address) is automatically
transferred from the DD RAM or CG RAM to the DR. By having the CPU subsequently read the
DR (from the DR data), it is possible to verify the DD RAM or CG RAM data.
After the writing of the DR by the CPU, the DD RAM or CG RAM of the next address is selected
to be ready for the next CPU writing. Likewise, after the reading out of the DR by the CPU, the
DD RAM or CG RAM data is read out by the DR to be ready for the next CPU reading.
Write/read to and from the three registers is carried out by the READ/WRITE (R/W) pin.
is lowest. On the other hand, when it is 1F, it is highest. (The initial value is
LCD
1
Table 1 Register and R/W pins function table
R/W RS
LLH
HLH
LHH
HHH
LLL
HLL
0
RS
1
IR write
Read of busy flag (BF) and address counter (ADC)
DR write
DR read
CR write
CR read
Function
2. Busy Flag (BF)
When the busy flag output is at "H", it indicates that the MSM6562B-xx is engaged in internal
operation.
When the busy flag is at "H" level, any new instruction is ignored.
When R/W = "H", RS0 = "L", and RS1 = "H", the busy flag is output from DB7.
New instruction should be input when BF is "L" level.
When the busy flag is set to "H", the output code of the address counter (ADC) are undefined.
12/50
¡ Semiconductor MSM6562B-xx
3. Address Counter (ADC)
The address counter (ADC) allocates the address for the DD RAM and CG RAM and also for the
cursor display.
When the instruction code for the DD RAM address or CG RAM address setting is input to the
IR, after deciding whether it is the DD RAM or CG RAM, the address code is transferred from
the IR to the ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM,
the ADC is automatically incremented (decremented) by 1 as its internal operation.
The data of the ADC is output to DB0 - DB6 under the conditions that R/W = "H", RS0 = "L", RS
= "H" and BF = "L".
4. Timing Generator Circuit
This circuit generates timing signals used for internal operations upon receipt of CPU instruction. It also generates timing signals for activating such internal circuits as the DD RAM, CG RAM
and CG ROM.
It is so designed that the internal operation caused by accessing from the CPU will not interfere
with the internal operation caused by the LCD display.
Consequently, when data is written from the CPU to DD RAM no ill effect, e.g., flickering occurs
in portions other than the display where the data is written.
In addition, the circuit generates transfer signals to the character extension IC (MSM5259).
1
13/50
¡ Semiconductor MSM6562B-xx
5. Display Data RAM (DD RAM)
This RAM is used to store the display data of 8-bit character codes (see Table 2).
DD RAM address corresponds to the display position of the LCD. The correspondence between
the two is described in the following.
DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:
ADC
(Example)
When DD RAM address
is 2A
DB
6
MSB LSB
Hexadecimal notation
LLHLHLH
2
Hexadecimal notation
A
DB
0
1-1) Correspondence between address and display position in the 1-line display mode
79 80First digit 2345
00 01 02 03 04 4E 4F
MSB LSB
Display position
DD RAM address (hex.)
1-2) When the MSM6562B-xx alone is used, up to 20 characters can be displayed from the
first digit to the twentieth digit.
19 20First digit 2 3 4
00 01 02 03 12 13
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
19 20First digit 2 3 4
(Display shifted to right)
(Display shifted to left)
4F 00 01 02 11 12
19 20First digit 2 3 4
01 02 03 04 13 14
14/50
¡ Semiconductor MSM6562B-xx
1-3) When the MSM6562B-xx is used with one MSM5259, up to 28 characters can be
displayed from the first digit to the twenty-eighth digit as shown below:
00 01 02 03 12 13
When the display is shifted by instruction, the correspondence between the
LCD display and DD RAM address changes as shown below:
(Display shifted to right)
(Display shifted to left)
19 20First digit 2 3 4
1421152216231724182519261A271B
MSM6562B-xx display
19 20First digit 2 3 4
4F 00 01 02 11 12 13 14 15 16 17 18 19 1A
MSM6562B-xx display
01 02 03 04 13 14 15 16 17 18 19 1A 1B 1C
MSM5259 display
21 22 23 24 25 26 27 28
MSM5259 display
28
1-4) Since the MSM6562B-xx has a DD RAM with a capacity of 80 characters, up to 8 devices
of MSM5259 can be connected to MSM6562B-xx so that 80 characters can be displayed.
First
digit 2 3 4
00 01 02 03 12 13
MSM6562B-xx display
19 20
28
1421152216231724182519261A271B
MSM5259 (1) display
29 30 77 78 79 80
1C 1D 4C 4D 4E 4F
MSM5259
(2)-(7) display
i.e., O
MSM5259
(8) display
(Only the half of the
segment output pins,
to O20, are used.)
1
15/50
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