NXP TEA5767HN Schematic [ru]

TEA5767HN

Low-power FM stereo radio for handheld applications

Rev. 05 — 26 January 2007 Product data sheet

1. General description

The TEA5767HN is a single-chip electronically tuned FM stereo radio for low-voltage applications with fully integrated Intermediate Frequency (IF) selectivity and demodulation. The radio is completely adjustment-free and only requires a minimum of small and low cost external components. The radio can be tuned to the European, US, and Japanese FM bands.

2. Features

n High sensitivity due to integrated low-noise RF input ampliﬁer n FM mixer forconversion to IF of the US/Europe (87.5 MHz to 108 MHz) and Japanese

(76 MHz to 91 MHz) FM band

n Preset tuning to receive Japanese TV audio up to 108 MHz n RF Automatic Gain Control (AGC) circuit n LC tuner oscillator operating with low cost ﬁxed chip inductors n FM IF selectivity performed internally n No external discriminator needed due to fully integrated FM demodulator n Crystal reference frequency oscillator; the oscillator operates with a 32.768 kHz clock

crystal or with a 13 MHz crystal and with an externally applied 6.5 MHz reference frequency

n Phase-locked loop (PLL) synthesizer tuning system n I2C-bus and 3-wire bus, selectable via pin BUSMODE n 7-bit IF counter output via the bus n 4-bit level information output via the bus n Soft mute n Signal dependent mono to stereo blend [Stereo Noise Cancelling (SNC)] n Signal dependent High Cut Control (HCC) n Soft mute, SNC and HCC can be switched off via the bus n Adjustment-free stereo decoder n Autonomous search tuning function n Standby mode n Two software programmable ports n Bus enable line to switch the bus input and output lines into 3-state mode

NXP Semiconductors

3. Quick reference data

Table 1. Quick reference data

CCA=VCCD=VCC(VCO)

for V

the emf value is given; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

CCA

CC(VCO)

CCD

CCA

CC(VCO)

CCD

FM(ant)

amb

FM overall system parameters; see

−200

+200

AFL

AFR

analog supply voltage Voltage-Controlled

Oscillator (VCO) supply voltage

digital supply voltage analog supply current operating; V

VCO supply current operating; V

digital supply current operating; V

FM input frequency 76 - 108 MHz ambient temperature V

RF sensitivity input voltage

low side 200 kHz selectivity

high side 200 kHz selectivity

left audio frequency output voltage

right audio frequency output voltage

= 2.7 V; T

TEA5767HN

Low-power FM stereo radio for handheld applications

=25°C; AC values are given in RMS;

amb

[1]

2.5 3.0 5.0 V

[1]

2.5 3.0 5.0 V

[1]

2.5 3.0 5.0 V

= 3 V 6.0 8.4 10.5 mA

CCA

Standby mode; V

CC(VCO)

Standby mode; V

CCD

Standby mode; V

bus enable line HIGH 30 56 80 µA bus enable line LOW 11 19 26 µA

CCA=VCC(VCO)=VCCD

2.5 V to 5 V

Figure 13

fRF= 76 MHz to 108 MHz; ∆f = 22.5 kHz; f (S+N)/N = 26 dB; de-emphasis = 75 µs; L = R; B

= 300 Hz to 15 kHz

∆f=−200 kHz; f

= 76 MHz to 108 MHz

tune

∆f = +200 kHz; f

= 76 MHz to 108 MHz

tune

VRF=1mV; L=R; ∆f = 22.5 kHz; f de-emphasis = 75 µs

=3V - 3 6 µA

CCA

= 3 V 560 750 940 µA

CC(VCO)

=3V - 1 2 µA

= 3 V 2.1 3.0 3.9 mA

=3V

CCD

−10 - +75 °C

- 2 3.5 µV

= 1 kHz;

mod

[2]

32 36 - dB

[2]

39 43 - dB

60 75 90 mV

= 1 kHz;

mod

60 75 90 mV

= 1 kHz;

mod

Product data sheet Rev. 05 — 26 January 2007 2 of 40

NXP Semiconductors

TEA5767HN

Low-power FM stereo radio for handheld applications

Table 1. Quick reference data

CCA=VCCD=VCC(VCO)

for V

the emf value is given; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

(S+N)/N maximum signal plus

noise-to-noise ratio

cs(stereo)

stereo channel separation

THD total harmonic

distortion

[1] V [2] Low side and high side selectivity can be switched by changing the mixer from high side to low side LO

, V

CCA

injection.

CC(VCO)

4. Ordering information

Table 2. Ordering information

Type number Package

TEA5767HN HVQFN40 plastic thermal enhanced very thin quad ﬂat package;

…continued

= 2.7 V; T

=25°C; AC values are given in RMS;

amb

VRF=1mV; L=R; ∆f = 22.5 kHz; f

mod

= 1 kHz;

54 60 - dB

de-emphasis = 75 µs; B

= 300 Hz to 15 kHz

VRF= 1 mV; R = L = 0 or R = 0

24 30 - dB and L = 1 including 9 % pilot; ∆f = 75 kHz; f

mod

= 1 kHz; data byte 3 bit 3 = 0; data byte 4 bit 1 = 1

=1mV; L=R;

∆f = 75 kHz; f

mod

= 1 kHz;

- 0.4 1 %

de-emphasis = 75 µs

and V

must not differ by more than 200 mV.

CCD

Name Description Version

SOT618-1

no leads; 40 terminals; body 6 × 6 × 0.85 mm

Product data sheet Rev. 05 — 26 January 2007 3 of 40

Product data sheet Rev. 05 — 26 January 2007 4 of 40

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5. Block diagram

NXP Semiconductors

CCA

FM antenna

22 nF

4.7 Ω

100 pF

47 nF 47 nF 33 nF

LIMDEC2

29 28 27 26 25

22 µF

27 pF 47 pF

4.7 nF

gain

AGND

CCA

RFI1

RFGND

RFI2

TAGC

LOOPSW

I/Q-MIXER

1st FM

35 36

TUNING SYSTEM

CPOUT VCOTANK2 V

39 nF10 nF

10 kΩ

100 kΩ

AGC

VCO

VCOTANK1

D1L3D2

GAIN

STABILIZATION

RESONANCE

AMPLIFIER

IF CENTRE

FREQUENCY

ADJUST

programmable divider output

reference frequency divider output

CC(VCO)

LIMDEC1 TIFC V

LIMITER

LEVEL

ADC

6789 DGND CLOCK

12 Ω

CCD

47 nF

DEMODULATOR

COUNTER

ref

MUX

I2C-BUS

AND

3-WIRE BUS

CCD

22 nF

TEA5767HN

PROGRAMMABLE

DATAV

ref

POWER SUPPLY

SOFTWARE

PORT

pilot

mono

MPXO TMUTE

SOFT MUTE

MPX

DECODER

1, 10, 20, 21, 30, 31, 40

n.c.

33 nF

AFR

24 23 22

SDS

CRYSTAL

OSCILLATOR

mhc283

AFL

18 17

15 14

13 12 11

PILFIL

33 kΩ

PHASEFIL XTAL2

pull

XTAL1

SWPORT2 SWPORT1

BUSENABLE BUSMODE WRITE/READ

1 nF

22 nF

(1)

10 kΩ

comp

(1)

32.768 kHz or

13 MHz

CCA

Low-power FM stereo radio for handheld applications

TEA5767HN

The component list is given in Section 16.

(1) C

comp

and C

data depends on crystal speciﬁcation.

pull

Fig 1. Block diagram

47 Ω

22 nF

CC(VCO)

NXP Semiconductors

6. Pinning information

6.1 Pinning

TEA5767HN

Low-power FM stereo radio for handheld applications

terminal 1

index area

n.c. n..c.

CPOUT LIMDEC2 VCOTANK1 LIMDEC1 VCOTANK2 TIFC

CC(VCO)

DGND MPXO

CCD

DATA V

CLOCK

n.c.

LOOPSW

TAGC

RFI2

403938373635343332 1 30 2 29 3 28 4 27 5 26 6 25 7 24 8 23 9 22

10 21

TEA5767HN

111213141516171819

SWPORT1

BUSMODE

BUSENABLE

WRITE/READ

Transparent top view

CCA

RFGND

RFI1

XTAL1

XTAL2

SWPORT2

Fig 2. Pin conﬁguration

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

n.c. 1 not connected CPOUT 2 charge pump output of synthesizer PLL VCOTANK1 3 VCO tuned circuit output 1 VCOTANK2 4 VCO tuned circuit output 2 V

CC(VCO)

DGND 6 digital ground V

CCD

DATA 8 bus data line input/output CLOCK 9 bus clock line input n.c. 10 not connected WRITE/READ 11 write/read control input for the 3-wire bus BUSMODE 12 bus mode select input BUSENABLE 13 bus enable input SWPORT1 14 software programmable port 1 SWPORT2 15 software programmable port 2 XTAL1 16 crystal oscillator input 1

5 VCO supply voltage

7 digital supply voltage

gain

AGND

n.c. 31

n.c.

PILFIL

PHASEFIL

ref

TMUTE

AFR

AFL

n.c.

001aab363

Product data sheet Rev. 05 — 26 January 2007 5 of 40

NXP Semiconductors

TEA5767HN

Low-power FM stereo radio for handheld applications

Table 3. Pin description

Symbol Pin Description

XTAL2 17 crystal oscillator input 2 PHASEFIL 18 phase detector loop ﬁlter PILFIL 19 pilot detector low-pass ﬁlter n.c. 20 not connected n.c. 21 not connected V

AFL

AFR

TMUTE 24 time constant for soft mute MPXO 25 FM demodulator MPX signal output V

ref

TIFC 27 time constant for IF center adjust LIMDEC1 28 decoupling IF limiter 1 LIMDEC2 29 decoupling IF limiter 2 n.c. 30 not connected n.c. 31 not connected I

gain

AGND 33 analog ground V

CCA

RFI1 35 RF input 1 RFGND 36 RF ground RFI2 37 RF input 2 TAGC 38 time constant RF AGC LOOPSW 39 switch output of synthesizer PLL loop ﬁlter n.c. 40 not connected

22 left audio frequency output voltage 23 right audio frequency output voltage

26 reference voltage

32 gain control current for IF ﬁlter

34 analog supply voltage

…continued

7. Functional description

7.1 Low-noise RF ampliﬁer

The Low Noise Ampliﬁer (LNA) input impedance together with the LC RF input circuit deﬁnes an FM band ﬁlter. The gain of the LNA is controlled by the RF AGC circuit.

7.2 FM mixer

The FM quadrature mixer converts the FM RF (76 MHz to 108 MHz) to an IF of 225 kHz.

7.3 VCO

The varactor tuned LC VCO provides the Local Oscillator (LO) signal for the FM quadrature mixer. The VCO frequency range is 150 MHz to 217 MHz.

Product data sheet Rev. 05 — 26 January 2007 6 of 40

NXP Semiconductors

7.4 Crystal oscillator

The crystal oscillator can operate with a 32.768 kHz clock crystal or a 13 MHz crystal. The temperature drift of standard 32.768 kHz clock crystals limits the operational temperature range from −10 °Cto+60°C.

The PLL synthesizer can be clocked externally with a 32.768 kHz, a 6.5 MHz or a 13 MHz signal via pin XTAL2.

The crystal oscillator generates the reference frequency for:

• The reference frequency divider for the synthesizer PLL

• The timing for the IF counter

• The free-running frequency adjustment of the stereo decoder VCO

• The center frequency adjustment of the IF ﬁlters

7.5 PLL tuning system

The PLL synthesizer tuning system is suitable to operate with a 32.768 kHz or a 13 MHz reference frequency generated by the crystal oscillator or applied to the IC from an external source. The synthesizer can also be clocked via pin XTAL2 at 6.5 MHz. The PLL tuning system can perform an autonomous search tuning function.

TEA5767HN

Low-power FM stereo radio for handheld applications

7.6 RF AGC

The RF AGC prevents overloading and limits the amount of intermodulation products created by strong adjacent channels.

7.7 IF ﬁlter

Fully integrated IF ﬁlter.

7.8 FM demodulator

The FM quadrature demodulator has an integrated resonator to perform the phase shift of the IF signal.

7.9 Level voltage generator and analog-to-digital converter

The FM IF analog level voltage is converted to 4 bits digital data and output via the bus.

7.10 IF counter

The IF counter outputs a 7-bit count result via the bus.

7.11 Soft mute

The low-pass ﬁltered level voltage drives the soft mute attenuator at low RF input levels. The soft mute function can be switched off via the bus.

7.12 MPX decoder

The PLL stereo decoder is adjustment-free. The stereo decoder can be switched to mono via the bus.

Product data sheet Rev. 05 — 26 January 2007 7 of 40

NXP Semiconductors

7.13 Signal dependent mono to stereo blend

With a decreasing RF input levelthe MPX decoder blends from stereo to mono to limit the output noise. The continuous mono to stereo blend can also be programmed via the bus to an RF level depending switched mono to stereo transition. Stereo Noise Cancelling (SNC) can be switched off via the bus.

7.14 Signal dependent AF response

The audio bandwidth will be reduced with a decreasing RF input level. This function can be switched off via the bus.

7.15 Software programmable ports

Two software programmable ports (open-collector) can be addressed via the bus. The port 1 (pin SWPORT1) function can be changed with write data byte 4 bit 0

(see Table 13). Pin SWPORT1 is then output for the ready ﬂag of read byte1.

7.16 I2C-bus and 3-wire bus

TEA5767HN

Low-power FM stereo radio for handheld applications

The 3-wire bus and the I2C-bus operate with a maximum clock frequency of 400 kHz. Before any READ or WRITE operation the pin BUSENABLE has to be HIGH for at

least 10 µs. The I2C-bus mode is selected when pin BUSMODE is LOW, when pin BUSMODE is HIGH

the 3-wire bus mode is selected.

Product data sheet Rev. 05 — 26 January 2007 8 of 40

NXP Semiconductors

TEA5767HN

Low-power FM stereo radio for handheld applications

Power on:

Mute, stand-by activated All other status is random Complete initialization by

microprocessor is required

upwards?

yes

IF frequency

OK?

Write enable

activated?

yes

Reset bit counter:

Bits are clocked into the

receive register

Completed bytes are written to

the destinastion register

Use value of tuning memory:

Write result to the programmable divider (also available at the bus)

Wait 10 ms. Have the signal level

available at the bus

Search Mode?

Signal

level OK?

yes

Reset IF counter and enable counting

Wait for result

Have the result available for the bus

Search Mode?

yesyes

Add 100 kHz to the tuning memory

Upper tuning limit exceeded?

yes

no no

Set 'band limit' flag

Lower tuning limit exceeded?

Set 'found' flagSubstract 100 kHz to the tuning memory

001aae346

Fig 3. Flowchart auto search or preset

Product data sheet Rev. 05 — 26 January 2007 9 of 40

NXP Semiconductors

Low-power FM stereo radio for handheld applications

8. I2C-bus, 3-wire bus and bus-controlled functions

8.1 I2C-bus speciﬁcation

TEA5767HN

Information about the I2C-bus can be found in the brochure

it” (order number 9398 393 40011)

The standard I2C-bus speciﬁcation is expanded by the following deﬁnitions:

IC address: 110 0000b Structure of the I2C-bus logic: slave transceiver Subaddresses are not used The maximum LOW-level input and the minimum HIGH-level input are speciﬁed to

0.2V The pin BUSMODE must be connected to ground to operate the IC with the I2C-bus.

Remark: The I2C-bus operates at a maximum clock frequency of 400 kHz. It is not allowed to connect the IC to an I2C-bus operating at a higher clock rate.

and 0.45V

CCD

8.1.1 Data transfer

Data sequence: address, byte 1, byte 2, byte 3, byte 4 and byte 5 (the data transfer has to be in this order). The Least Signiﬁcant Bit (LSB) = 0 of the address indicates a WRITE operation to the TEA5767HN.

Bit 7 of each byte is considered as the Most Signiﬁcant Bit (MSB) and has to be transferred as the ﬁrst bit of the byte.

The data becomes valid bitwise at the appropriate falling edge of the clock. A STOP condition after any byte can shorten transmission times.

respectively.

CCD

“The I2C-bus and how to use

When writing to the transceiver by using the STOP condition before completion of the whole transfer:

• The remaining bytes will contain the old information

• If the transfer of a byte is not completed, the new bits will be used, but a new tuning

cycle will not be started

The IC can be switched into a low current Standby mode with the standby bit; the bus is then still active. The standby current can be reduced by deactivating the bus interface (pin BUSENABLE LOW). If the bus interface is deactivated (pin BUSENABLE LOW) without the Standby mode being programmed, the IC maintains normal operation, but is isolated from the bus lines.

The software programmable output (SWPORT1) can be programmed to operate as a tuning indicator output. As long as the IC has not completed a tuning action, pin SWPORT1 remains LOW. The pin becomes HIGH, when a preset or search tuning is completed or when a band limit is reached.

The reference frequency divider of the synthesizer PLL is changed when the MSB in byte 5 is set to logic 1. The tuning system can then be clocked via pin XTAL2 at 6.5 MHz.

Product data sheet Rev. 05 — 26 January 2007 10 of 40

NXP Semiconductors

8.1.2 Power-on reset

At Power-on reset the mute is set, all other bits are set to LOW.To initialize the IC all bytes have to be transferred.

8.2 I2C-bus protocol

TEA5767HN

Low-power FM stereo radio for handheld applications

(1)

(1) S = START condition. (2) A = acknowledge. (3) P = STOP condition.

ADDRESS (WRITE) DATA BYTE(S)

(2)

(3)

001aae347

Fig 4. Write mode

(1)

(1) S = START condition. (2) A = acknowledge.

ADDRESS (READ) DATA BYTE 1

(2)

001aae348

Fig 5. Read mode

Table 4. IC address byte

IC address Mode

[1]

1100000R/

[1] Read or write mode:

a) 0 = write operation to the TEA5767HN. b) 1 = read operation from the TEA5767HN.

Product data sheet Rev. 05 — 26 January 2007 11 of 40

NXP Semiconductors

SDA

TEA5767HN

Low-power FM stereo radio for handheld applications

SCL

HD;STA

SU;BUSEN

BUSENABLE

tf = fall time of both SDA and SCL signals: 20+ 0.1Cb < tf < 300 ns, where Cb = capacitive load on bus line in pF. tr = rise time of both SDA and SCL signals: 20 + 0.1Cb < tf < 300 ns, where Cb = capacitive load on bus line in pF. t

= hold time (repeated) START condition. After this period, the ﬁrst clock pulse is generated: > 600 ns.

HD;STA

= HIGH period of the SCL clock: > 600 ns.

HIGH

= LOW period of the SCL clock > 1300 ns.

LOW

= set-up time for a repeated START condition: > 600 ns.

SU;STA

= data hold time: 300 ns < t

HD;DAT

Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal. t

= data set-up time: t

SU;DAT

= set-up time for STOP condition: > 600 ns.

SU;STO

= bus free time between a STOP and a START condition: > 600 ns.

BUF

Cb = capacitive load of one bus line: < 400 pF. t

SU;BUSEN

HO;BUSEN

= bus enable set-up time: t = bus enable hold time: t

Remark: The terms SDA and SCL are the corresponding terms used by the I2C-bus for the DATA and CLOCK signals respectively.

Fig 6. I2C-bus timing diagram

HD;DAT

< 900 ns.

SU;STA

HD;STA

> 100 ns. If ASIC is used in a standard mode I2C-bus system, t

SU;BUSEN

HO;BUSEN

> 10 µs.

LOW

SU;DAT

HIGH

SU;DAT

SU;STO

SU;DAT

BUF

> 250 ns.

HO;BUSEN

001aae349

8.3 3-wire bus speciﬁcation

The 3-wire bus controls the write/read, clock and data lines and operates at a maximum clock frequency of 400 kHz.

Hint: By using the standby bit the IC can be switched into a low current Standby mode. In Standby mode the IC must be in the WRITE mode. When the IC is switched to READ mode, during standby, the IC will hold the data line down. The standby current can be reduced by deactivating the bus interface (pin BUSENABLE LOW). If the bus interface is deactivated (pin BUSENABLE LOW) without the Standby mode being programmed, the IC maintains normal operation, but is isolated from the clock and data line.

8.3.1 Data transfer

Data sequence: byte 1, byte 2, byte 3, byte 4 and byte 5 (the data transfer has to be in this order).

Product data sheet Rev. 05 — 26 January 2007 12 of 40

NXP Semiconductors

A positive edge at pin WRITE/READ enables the data transfer into the IC. The data has to be stable at the positive edge of the clock. Data maychange while the clock is LOW and is written into the IC on the positive edge of the clock. Data transfer can be stopped after the transmission of new tuning information with the ﬁrst two bytes or after each following byte.

A negative edge at pin WRITE/READ enables the data transfer from the IC. The WRITE/READ pin changes while the clock is LOW. With the negative edge at pin WRITE/READ the MSB of the ﬁrst byte occurs at pin DATA.

The bits are shifted on the negative clock edge to pin DATA and can be read on the positive edge.

To do two consecutive read or write actions, pin WRITE/READ has to be toggled for at least one clock period. When a search tuning request is sent, the IC autonomously starts searching the FM band; the search direction and search stop level can be selected. When a station with a ﬁeld strength equal to or greater than the stop level is found, the tuning system stops and the ready ﬂag bit is set to HIGH. When, during search, a band limit is reached, the tuning system stops at the band limit and the band limit ﬂag bit is set to HIGH. The ready ﬂag is also set to HIGH in this case.

TEA5767HN

Low-power FM stereo radio for handheld applications

The reference frequency divider of the synthesizer PLL is changed when the MSB in byte 5 is set to logic 1. The tuning system can then be clocked via pin XTAL2 at 6.5 MHz.

8.3.2 Power-on reset

At Power-on reset the mute is set, all other bits are random. To initialize the IC all bytes have to be transferred.

8.4 Writing data

WRITE_READ

CLOCK

W(write)

50 %

su(clk)

50 % 50 %

su(write)

h(write)

DATA

Fig 7. 3-wire bus write data

Product data sheet Rev. 05 — 26 January 2007 13 of 40

50 %

valid data

mhc250

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