Fig 9 Top View of Production Test Pattern.........................................................................26
Fig 10 Test points Located Between UEM and UPP...........................................................26
Fig 11 RF Frequency Block Plan.........................................................................................46
Fig 12 Power distribution ....................................................................................................47
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NPW-1
System ModulePAMS Technical Documentation
Abbreviations
ACCHAnalog Control Channel
A/DAnalog to Digital conversion
AMPSAdvanced Mobile Phone System
ANSIAmerican National Standards Institute
ASICApplication Specific Integrated Circuit
AVCHAnalog V oice Channel
BBBase Band
CSDCircuit Switched Data
CSPChipped Scale Package. The same as uBGA.
CTIACellular Telecommunications Industry Associat ion
D/ADigital to Analog conversion
DCCHDi gi tal Control Channel
DSPDigital Signal Processing
DTCHDigital Traffic Channel
EDMSEl ectronic Data Management System
EFREnhanced Full Rate (codec)
FCCFederal Communications Commission
IRInfrared
IrDAInfrared Data Association
IrMCInfrared Mobile Communications
IrOBEXIrDA Object Exchange Protocol
ISInterim Standard
ISAIntelligent Software Architecture
LEDLight Emitting Diode
MCUMicro Control Unit / Master Control Unit
MO/MTMobile Originated/Mobile Terminated (SMS)
OOROut Of Range (mode)
OTAOver The Air (+ service like Programming etc.)
PCPer sonal Computer (PC Suite = PC program for phone memory function support)
PWBPrinted Wired Board
PWMPulse Width Modulation
RFRadio Frequency
SARSpecific Absorption Rate
SCFSoftware Component Factory
SMDSurface Mount Device
SMSShort Message Service
SPRStandard Product Requirement
TDDText Device for the Deaf
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PAMS Technical DocumentationSystem Module
TDMATime Division Multiple Access. Here: US digital cellular system.
TIATelecommunications Industry Association
TTYTeletype
UEMUniversal Energy Management, a Baseband ASIC.
UPPUniversal Phone Processor, a Baseband ASIC.
VCTCXOVol tage Controlled temperature Compensated Crystal Oscill ator
WAPWireless Application Protocol (Browser)
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NPW-1
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2
3
4
5
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System ModulePAMS Technical Documentation
Transceiver NPW-1
Introduction
The NPW-1 is a dual band transceiver unit designed for TDMA800/1900 networks. The
transceiver consists of the engine module (WS8) and the various assembly parts.
The transceiver has a full graphic display and the user interface is based o n a jack style
UI with two soft keys. An internal antenna is used in the phone, and there is no connection to an external antenna. The transceiver also has a low leakage tolerant earpiece and
an omnidirectional microphone that provides excellent audio quality.
An integrated infrared (IR) link provides c onnection betwee n tw o NPW-1 transceiv ers or
between a transceiver and a PC (internal da ta), or a transceiver and a printer.
Figure 1: Interconnect ing Diagram
TRANSCEIVER
ANT
RF Switch
LCD DRIVER
B & W
display
BACKLIGHT
BACKLIGHT
✉
RF
☎
6
9
0#
ENGINE
U S ER IN TE RF A CE
AUDIO
(discr)
BUZZER
VIBRA
MIC
E xt. Aud io
Accesso ries
BB
Pr o d .T E ST I/F
INF RA RE D
Module
BSI
BTemp
BATTERY
CHARGER
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PAMS Technical DocumentationSystem Module
Operational Modes
Below is a list of the phone’s different ope rational modes:
1Power Off mode
2Normal Mode (Power controlled by cellular SW, includes various Active and Idle
Both the analog and digital modes have different states c ontrolled by the Cellular
SW. Some examples are Idle State (on ACCH), Camping (on DCCH), Scanning, Con-
versation, NSPS (No Service Power Save, previously OOR = Out of Range).
3Local mode (both Cellular SW and UI SW non active)
4Test mode (Cellular SW active but UI SW non active)
Environmental Specifications
Normal and extreme voltages
Voltage range:
•nominal battery voltage: 3.6 V
•maximum battery voltage: 5.0 V
•minimum battery voltage: 3.1 V
Temperature Conditions
Temperature range:
•ambient temperature: -30...+ 60 ×C
•PWB temperature: -30...+85 ×C
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NPW-1
System ModulePAMS Technical Documentation
•storage temperature range: -40 to + 85 ×C
All of the EIA/TIA-136-270A requirements are not exactly specified over the temperature
range. For example, the RX sensitivity requirement is 3dB lower over the –30 - +60 °C
range.
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NPW-1
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PAMS Technical DocumentationSystem Module
Engine Module
Baseband Module
The core part of the transceiver’s baseband (see the figure below) consists of 2 ASICs, the
UEM and UPP, and flash memory. The following sections illustrate and explain these
parts in detail.
Figure 2: System Block Diagram (simple)
PA suppl
RFIC CTRL
SAFARI
RFCLK
19.44MHz
UPP
RF Supplies
RF RX/T
UEM
PURX
RF RX/T
SLEEPCLOCK
32kHz
CBUS/DBUS
UDIO
IR
EAR
MIC
BUZZER
BATTERY
BB Supplies
IBR
MEMADDA
MEMCON
FLASH
KLIGHT/ DLIGH
PWR ON
BASEBAND
EXTERNAL AUDIO
CHARGER CONNECTION
System Connector
UEM
Introduction to UEM
UEM is the Universal Energy Management IC for digital hand portable phones. In addition to energy management, it performs all the base band’s mixed-signal functions.
Most UEM pins have 2kV ESD protection, and those signals considered to be more easily
exposed to ESD, have 8kV protection within the UEM. These kinds of signals are (1) all
audio signals, (2) headset signals, (3) BSI, (4) Btemp, (5) Fbus and (6) Mbus signals.
Issue 1 10/01ãNokia CorporationPage 11
NPW-1
System ModulePAMS Technical Documentation
Regulators
The UEM has six regulators for baseband power supplies and seven regulators for RF
power supplies. The VR1 regulator has two outputs: (1) VR1a and (2) VR1b. In addition to
these, there are two current generators - IPA1 and IPA2 - for biasing purposes.
A bypass capacitor (1uF) is required for each regulator output to ensure stability.
Reference voltages for regulat ors require exter nal 1uF capacitors. Vref25RF is the refer-
ence voltage for the VR2 regulator, Vref25BB is the reference voltage for the VANA,
VFLASH1, VFLASH2, VR1 regulators, Vref278 is the re ference voltage for the VR3, VR4,
VR5, VR6, VR7 regulators, and VrefRF01 is the reference voltage for the VIO, VCORE regulators and for the radio frequency (RF).
The VANA regulator supplies the baseband’s (BB) internal and external analog cir cuitry.
It is disabled in the Sleep mode.
The Vflash1 regulator supplie s the LCD, the IR-module and the digital parts of th e UEM
and Safari asic. It is enabled during startup an d goes into the low Iq-mode when in the
Sleep mode.
The VIO regulator supplies both the e xternal and internal logic circuit ries. It is used by
the LCD, flash, bluetooth and UPP. The regulator goes into the low Iq-mode when in theSleep mode.
The VCORE regulator supplies the DSP and the core part of the UPP. The voltage is programmable and the startup default is 1.5V. The regulator goes into the low Iq-mode
when in the Sleep mode.
The VSIM regulator supplies the SIM card. NOT USED IN NPW-1.
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The VR1 regulator uses tw o LDOs and a charge pump. The charge pump requires one
external 1uF capacitor in the Vpump pin and a 220nF flying capacitor between the CCP
and CCN pins. In practice, the 220nF flying capacitor is f ormed by 2 x 100nF capacitors
that are parallel to each other. The VR1 regulator is used by the Safari RF ASIC.
The VR2 regulator is used to supply the (1) external RF parts, (2) lower band up converter, (3) TX power detector module and (4) Safari. In light load situatio ns, the VR2 regulator can be set to the low Iq-mode.
The VR3 regulator supplies the VCTCXO and Safari in the RF. It is always enabled when
the UEM is active. When the UEM is in the Sleep mode, the VR3 is disabled.
The VR4 regulator supplies the RX frontends (LNA and RX mixers).
The VR5 regulator supplies the lower band PA. In light load situations, the VR5 regulator
can be set to the low Iq-mode.
The VR6 regulator supplies the higher band PA and TX amplifier. In light load situations,
the VR6 regulator can be set to the low Iq-mode.
The VR7 regulator supplies the VCO and Safari. In light load situations, the VR7 regulator
can be set to the low Iq-mode.
The IPA1 and IPA2 are programmable current generators. A 27kW/1%/100ppm external
resistor is used to improve the accuracy of the output current. The IPA1 is used by the
lower PA band and IPA2 is used by the higher PA band.
RF Interface
The interface between the baseband and the RF section is also handled by the UEM. It
provides A/D and D/A conversion of the in-pha se and quadrature receive and transmit
signal paths. It also provides A/D and D/ A conve rsions of receiv ed and transmitte d audio
signals to and from the UI section. The UEM supplies the analog AFC signal to the RF section, according to the UPP DSP digital control.
Charging Control
The CHACON block of the UEM asics controls charging. The needed functions for the
charging controls are the (1) pwm-controlled battery charging switch, (2) charger-monitoring circuitry, (3) battery voltage monitori ng circuitry and (4) RTC supply circuitry for
backup battery charging (Not used in NPW-1). In addition to these, external components
are needed for EMC protection of the charger input to the baseband module.
Digital Interface
Data transmission between the U EM and the UPP is impleme nted using two seri al connections, DBUS (programmable clock) for DSP and CBUS (1.0MHz GSM and 1.08MHz
TDMA) for MCU. The UEM is a dual voltage circuit: the digital parts are run from 1.8V
and the analog parts are run from 2.78V. The Vbat (3,6V) voltage regulators's input is
also used.
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Audio Codec
The baseband supports two external microphone input ar eas and one external ea rphone
output. The input can be taken from an internal microphone, a headset microphone or
from an external microphone signal source through a headset connector. The output for
the internal earpiece is a dual-ended type output, and the dif ferential output is capable
of driving 4Vpp to the earpiece with a 60 dB minimum signal as the total distortion ratio.
The input and output signal source se lection and gain control is performed inside the
UEM Asic, according to the c ontrol messages from the UPP. A buzzer a nd an external
vibra alert control signal are gener ated by the UEM with separate PWM outputs.
UI Drivers
There is a single output driver for the buzzer, vibra, display and keyboard LEDs and the IR
in the side of the UEM. These generate PWM square wave for the various devices.
IR interface
The IR interface is designed and implemented into th e UEM. The low frequency mode of
the IR module covers speeds up to 115.2 kbit/s. The device (Vis hay) tr ansc eiv ers inte gra te
a sensitive receiver and a built-in power driver. The combination of a thin, long resistive
and inductive wiring should be avoided. The input (Txd, SD/M ode) and the output Rxd
should be directly coupled to the I/O circuit. The VBAT regulator supplies the power to
transmit the LED and serial resistor limits’ current. Upon receiving infrared data to IR
LED, it goes straight to the UEM via the RXD line. The Vflash1 is the power supply for the
IR module, except for transmission.The IR module has one control pin to control the shut
down. The control lever shifter is used to change the proper voltage for shutdown to the
IR module from the UPP.
AD Converters
The UEM is equipped with a 11-channel analog to digital converter. Some AD converter
channels (LS, KEYB1-2) are not used in NPW-1. The AD converters are calibrated in the
production line.
UPP
Introduction
NPW-1 uses the UPPv4M ASIC. The RAM size is 4M. The processor architecture consists
of both the DSP and the MCU processors.
Blocks
The UPP is internally partitioned into two main parts: (1) the Brain and (2) the Body.
1The Processor and Memory System (that is, the Processor cores, Mega-cells,
internal memories, perip herals and external memory inter face) is known as the
Brain.
The Brain consists of the following blocks: (1) the DSP Subsystem (DSPSS), (2) the
MCU Subsystem (MCUSS), (3) the emulation control EMUCtl, (4) the program/
data RAM PDRAM and (5) the Brain Peripherals–subsystem (BrainPer).
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2The NMP custom cellular logic functions are known as the Body.
The Body contains interfaces and functions needed fo r interfacing other baseband and RF parts. The body consists of, fo r example, the following sub-blocks:
(1) MFI, (2) SCU, (3) CTSI , (4) RxModem, ( 5) Acc IF, (6) UIF, (7) C oder, (8) BodyIF, (9)
PUP.
Flash Memory
Introduction
The NPW-1 transceiver uses a 32 Mbit flash as its e xte rnal memor y. The VIO regulator is
used as a power supply for normal in-system op eration. An accelerated program/erase
operation can be obtained by supplying Vpp of 12 volt to the flash device.
The device has two read modes: asynchronous and burst. The Burst read mode is utilized
in NPW-1, except for the start-up, when the asynchronous read mode is used for a short
time.
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NPW-1
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User Interface Hardware
LCD
Introduction
NPW-1 uses a black & white GD46 84x48 full dot matrix graphical display . There are two
suppliers for this LCD: Seiko Epson and Philips. The LCD module includes the LCD glass,
the LCD COG-driver, an elastomer connector and a metal frame. The LCD module is
included in the lightguide assembly module.
Interface
The LCD is controlled by the UI SW and the control signals are from the UPP asic. The VIO
and Vflash1 regulators supply the LCD with power.
The LCD has an internal voltage booster and a booster capacitor is required between
Vout and GND.
Pin 3 (Vss9) is the LCD driver’s ground and Pin 9 (GND) is used to ground the metal
frame.
Keyboard
Introduction
The NPW-1 keyboard style follows the Nokia Jack style, without side keys for volume
control. The PWR key is integrated so that it is part of the IR window and located on top
of the phone.
Figure 3: Placement of keys.
Power Key
All signals for the keyboard come from the UPP asic, except PWRONX line for the power
key signal which is connect ed dir ectly to t he U EM. The pr essing o f the PWR k ey gro und s
the PWRONX line and the UEM generate s an inter rupt to U OO, which is then re cognized
as a PWR key press.
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Keys
Other keys are detected so that w hen a key is pressed down, the metal dome connects
one S-line and one R-line of the UPP to the GND and creat es an interrupt for the SW.
This kind of detection is also known as metaldome detection. The matrix of how lines are
connected and which lines are used for differen t keys is described in the Table 1. The Sline S0 and R-line R5 are not used at all.
Table 2: Matrix of Key Detection Lines
S0S1S2S3S4
Returns /
Scans
R0NCNCSendEndNC
R1NCSoft leftUpDownSoft right
R2NC147*
R3NC2580
where NC = Not Connected
Lights
Introduction
NPW-1 has 10 LEDs for lighting purposes. Six of them are for the keyboard and four for
the display. The LED type is Osram LGM470, green light emitting and SMD through hole
mounted.
Interfaces
The display lights are controlled by a Dlight signal from the UEM. The Dlight output is the
PWM signal, which is used to control the average current going through the LEDs. When
the battery voltage changes, the new PWM v alue is written onto the PWM register. In
this way, the brightness of the lights remains the same with all battery voltages within
range. The frequency of the signal is fixed at 128Hz.
The keyboard lights are controlled by the Klight signal from the UEM. The Klight output is
also a PWM signal and is used in the same way as Dlight.
R4NC369#
R5NCNCNCNCNC
Technical Information
Each LED requires a hole in t he PWB, in which the body of the LED locates in hole and
terminals are soldered on the component side of the module PWB. The LEDs have a white
plastic body around the diode, and this directs the emitted light better to the UI-side.
The current for the LCD lights is limited by the resistor between the Vbatt and LEDs. For
the keyboard lights there are resistors in parallel.
Issue 1 10/01ãNokia CorporationPage 17
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