Description
ACIAccessory Control Interface
ADCAnalog Digital Connector
ARMAdvanced RISC Machines
ASIC Application Specific Integrated Circuit
ATRAnswer To Reset
BB Baseband
BL-5CBattery type.
BSIBattery Size Indicator
CbusControl bus (internal phone interface between UPP-UEM)
CCSCustomer Care Service
CPHCopenhagen, Denmark
CTICover Type Indicator
CTSIClock Timing Sleep and Interrupt
DbusDSP controlled bus (Internal phone interface between UPP-UEM)
DCDirect Current
DCT4.0Digital Core Technology, generation 4.0
DSP Digital Signal Processor
DUT Device under test
EADExternal Accessory Detection
EMC Electro Magnetic Compatibility
ESD Electro Static Discharge
FbusFast Bus, asynchronous message bus connected to DSP (communica-
tions bus)
FCIFunctional cover interface
FPCFlexible printed circuit
FR Full Rate
GENIOGeneral Purpose Input/Output
GSMGlobal System Mobile
HW Hardware
IF Interface
IHF Integrated Hands Free
IMEI International Mobile Equipment Identity
LCD Liquid Crystal Display
LDOLow Drop Out
LED Light Emitting Diode
Li-IonLithium Ion battery
LionBattery program
LN Lotus Notes
LPRF Low Power Radio Frequency
MALTMedium And Loud Transducer
MbusAsynchronous message bus connected to MCU (phone control interface).
Slow message bus for control data.
MCUMicro Controller Unit
NO_SUPPLYUEM state where UEM has no supply what so ever
NRTNokia Ringing Tones
NTCNegative temperature Coefficient, temperature sensitive resistor used as
a temperature sensor.
PAPower Amplifier (RF)
PDAPersonal Digital Assistant
PDMPulse Density Modulation
PDRAMProgram/Data RAM
Phoenix SW tool of DCT4.x
PLLPhase locked loop
PnPHFPlug and Play Handsfree
PUPGeneral Purpose IO (PIO), USARTS and Pulse Width Modulators
PWB Printed Wired Board
PWR_OFFUEM state where phone is off
PWRONXSignal from power on key.
R&DResearch and development
RESETUEM state where regulators are enabled
RTCUEM internal Real Time Clock
SARAMSingle Access RAM
SIM Subscriber Identification Module
SLEEPUEM power saving state controlled by UPP
SPRStandard Product Requirements
SRAMStatic RAM
STISerial Trace Interface
SW Software
TBSFThrough the Board Side Firing
TDBTo Be Defined
TITexas Instruments
UEMUniversal Energy Management
UI User Interface
UPPUniversal Phone Processor
VBATMain battery voltage
VCHARCharger input voltage
VCHARDETCharger detection threshold level
VMSTR+, VM-
This document specifies the baseband module for the Nokia 2600. The baseband module includes the baseband engine chipset, the UI components and the acoustical p arts for the transceiver.
Nokia 2600 is a hand-portable dualband 900/1800MHz or Low band/High ba nd phon e, featuring the DCT4 generation baseband (UEM/UPP) and RF (MJOELNER) circuitry.
■ Technical summary
The baseband module contains 2 main ASICs named the UEM and UPP. The baseband module furthermore contains a Flash IC of 32Mbit. The baseband is based on the DCT4 engine program.
Figure 1:Baseband block diagram
PA Supply
RF Supplies
RF RX/TX
SIM
Flashlight
EAR
MIC
speaker
Buzzer
IHF
UI
Battery
Baseband
UEM
External Audio
Charger connection
DLIGHT
SLEEPCLK
32kHz
CBUS/
DBUS
BB
Supplies
Mjoelner
26MHz
UPP
RFBUS
FLASH
MEMADDA
M
VIBRA
DCT4 Janette connector
DCT4 connector
MBus/FBus
The UEM supplies both the baseband module as well as the RF module with a series of voltage
regulators. Both the RF and Baseband modules are supplied with regulated voltages of 2.78 V
and 1.8V. UEM includes 6 linear LDO (low drop-out) regulators for baseband and 7 regulators
for RF. The UEM is furthermore supplying the baseband SIM interface with a programmable
voltage of either 1.8 V or 3.0 V. The core of the UPP is supplied with a programmable voltage
of 1.0 V, 1.3 V, 1.5 V or 1.8 V.
UPP operates from a 26MHz clock, coming from the RF ASIC MJOELNER, the 26 MHz clock
is internally divided by two, to the nominal system clock of 13MHz. DSP and MCU contain
phase locked loop (PLL) clock multipliers, which can multiply the system.
The UEM contains a real-time clock, sliced down from the 32768 Hz crystal oscillator. The
32768 Hz clock is fed to the UPP as a sleep clock.
The communication between the UEM and the UPP is done via the bi-directional serial busses
CBUS and DBUS. The CBUS is controlled by the MCU and operates at a speed of 1 MHz set
by SW. The DBUS is controlled by the DSP and operates at a speed of 13 MHz. Both processors are located in the UPP.
The UEM ASIC mainly handles the interface between the baseband and the RF section. UEM
provides A/D and D/A conversion of the in-phase and quadrature receive and transmit signal
paths and also A/D and D/A conversions of received and transmitted audio signals to and from
the user interface. The UEM supplies the analog signals to RF section according to the UPP
DSP digital control.
RF ASIC MJOELNER is controlled through UPP RFBUS serial interface. There are also separate signals for PDM coded audio. Digital speech processing is handled by the DSP inside UPP
ASIC. UEM is a dual voltage circuit, the digital parts are running from the baseband sup ply 1.8V
and the analog parts are running from the analog supply 2.78V, also VBAT is directly used by
some blocks.
The baseband supports both internal and external microphone inputs and speaker outputs.
The transceiver module is implemented on 6 layer selective OSP/Gold coated PWB.
■ Modes of operation
baseband has six different operating modes (in normal mode):
•No_Supply
•Power_off
•Acting_Dead
•Active
•Sleep
•Charging
Additionally two modes exist for product verification: 'testmode' and 'local mode'.
No supply
In No_Supply mode, the phone has no supply voltage. This mode is due to disconnection of
main battery or low battery voltage level.
Phone is exiting from No_Supply mode when sufficient battery vo ltage level is detected. Battery
voltage can rise either by connecting a new battery with VBA T > V
er and charging the battery above V
In this state the phone is powered of f, but supplie d. VRTC regu lator is active (enable d) having
supply voltage from main battery . Note, the RTC status in PWR_OFF mode depends on whether RTC was enabled or not when entering PWR_OFF. From Power_off mode UEM enters RESET mode (after 20ms delay), if any of following statements is true (logical OR –function):
– Power_on button detected (PWROFFX)
– charger connection detected (VCHARDET)
– RTC_ALARM detected
The Phone enters POWER_OFF mode from all the other modes except NO_SUPPL Y if internal
watchdog elapses.
Acting dead
If the phone is off when the charger is connected, the phone is powered on but enters a state
called”Acting Dead”, in this mode no RF parts a re powered. To the user, the phone acts as if it
was switched off. A battery-charging alert is given and/or a battery charging indication on the
display is shown to acknowledge the user that the battery is being charged.
Active
In the active mode the phone is in normal operation, scanning for channels, listening to a base
station, transmitting and processing information. There are several sub-states in the active
mode depending on if the phone is in burst reception, burst transmission, if DSP is working etc.
In active mode the RF regulators are controlled by SW writing into UEM’s registers wanted settings: VR1A/B must be kept disabled. VR2 can be enabled or forced into low quiescent current
mode. VR3 is always enabled in active mode. VR4 -VR7 can be enabled, disabled or forced
into low quiescent current mode.
Sleep mode
Sleep mode is entered when both MCU and DSP are in stand-by mode. Sleep is controlled by
both processors. When SLEEPX low signal is detected UEM enters SLEEP mode. VCORE,
VIO and VFLASH1 regulators are put into low quiescent current mode. All RF regulators, except VR2, are disabled in SLEEP. When SLEEPX=1 is detected UEM enters ACTIVE mode
and all functions are activated.
The sleep mode is exited either by the expiration of a sleep clock counter in the UEM or by
some external interrupt, generated by a charger connection, key press, headset connection
etc.
In sleep mode the main oscillator (26MHz) is shut down and the 32 kHz sleep clock oscillator
is used as reference clock for the baseband.
Charging
Charging can be performed in parallel with any other operating mode. A BSI resistor inside the
battery pack indicates the battery type/size. The resistor value corresponds to a specific battery
capacity and technology.
The battery voltage, temperature, size and current are measured by the UEM controlled by th e
charging software running in the UPP.
The charging control circuitry (CHACON) inside the UEM controls the charging current delivered from the charger to the battery. The battery voltage rise is limited by turning the UEM
switch off when the battery voltage has rea ched VBATLim (programmable charging cut-off limits 3.6V / 5.0V / 5.25V). Charging current is monitored by measuring the volt age drop across a
220 mOhm resistor.
According to the GSM specifications, a GSM-device must work correctly if it is powered by
his nominal voltage +/-15%. The UEM hardware shut down is from 3.10V and below. The Energy Managment of the phone is shutting down the phone at 3.20V in order to perform a correct
shutdown of the phone. Above 3.20V + tolerances, at 3.21V, the phone is still fullfilling all the
GSM requirements. The Nominal voltage is therefore set at 3.80V. During fast charging of an
empty battery voltages between 4.20 and 4.60 might appear for a short while.
The interface between the baseband and the RF can be divided into three categories:
- The digital interface from the UPP to the RF ASIC (Mjoelner). The serial digital interface is
used to control the operation of the different blocks in the RF ASICs.
- The analogue interface between UEM and the RF. The analogue interface consists of RX and
TX converter signals. The power amplifier control signal TXC and the AFC signal comes as well
from the UEM.
- Reference clock interface between Mjoelner and UPP which supplies the 26Mhz system clock
for the UPP.
■ Internal signals and connections
The tables below describe internal signals. The signal names can be found on the schematic
for the PWB.
Audio
Table 8: Internal microphone
SignalMin.
MIC1P (Differential input P)-5mV-G=0dB1kΩ to MIC1B
Nokia 2600 is designed to support fully differential external audio accessory connection. A
headset and PnPHF can be directly connected to system connector.
The earpiece selected is a 8-mm dynamic earpiece from PSS with a nominal impedance of 32
W. The earpiece acou stics will be designed to be type approved by type 3.2, low leak artificial
ear (Ear Simulator Type 4195, Low Leakage).
The earpiece will be mounted into the UI-shield assembly, the sealing of the back and front volume will be implemented in the UI-shield by die casting. This sealing part will also provide the
sealing against the A-cover.
To achieve a small dynamic range of the earpiece frequency response, a helmholtz resonator
is implemented in front of the speaker membrane, the resonance frequency of the helmholtz
resonator is approximately 4 kHz.
T o improve the leak t olerance of the earpiece design leak holes will be implemented. The holes
will provide a leak from the A-cover to the internal phone volume.
Dust and water shield is used to reduce the total dynamics of the frequency response by atte nuating the resonance, it will also protect the earpiece from pollution with dust and swarfs.
The earpiece circuit includes only a few components:
two 10 ohm in order to have a stable output
an EMC filter
Figure 4:Earpiece interface
Placed in top of
PWB, near
earpiece
EARP
EARN
UEM
EARP
EARN
Placed near UEM
10
ohm
10
ohm
Microphone
An omni directional microphone is used. The microphone is placed in the system connector
sealed in its rubber gasket. The sound port is provided in the system connector.
Figure 5:Bottom connector including the microphone
The microphone connection comprises a differen tial bias circuit, driven directly from the MICB1
bias output with external RC-filters.
The RC filter (220 Ω, 4.7µF) is scaled to provide damping at 217 Hz.
The keyboard PWB layout consists of a grounded outer ring and an inner pad.
Power key is integrated in keypad. For the schematic diagram of the keyboard kindly refer to
All lines are configured as input, when there is no key pressed. When a key is pressed, the
specific line where the key is placed is pulled low. This genera tes an interrupt to the MCU and
the MCU now starts its scanning procedure. When the key has been detected all the keypadregister inside the UPP is reset and it's ready receiving new interrupt.
The baseband memory module consists of external burst flash memory 4Mbyte (32Mbit). The
UPP contains internal SRAM with 2 Mbit (optional: 2M). The UPP will not be covered here.
■ SIM interface
The whole SIM interface is located in the two ASICs, UPP and UEM.
The SIM interface in the UEM contains power up/down, port gating, card detect, dat a receiving,
ATR-counter, registers and level shifting buffers logic. The SIM interface is the electrical interface between the Subscriber Identity Module Card (SIM Card) and mobile phone (via UEM device).
Figure 8:SIM interface
SIM
C5 C6 C7
C1C2C3
From Battery Type
contact
C8
C4
BSI
SIMDATA
SIMCLK
SIMRST
VSIM
UEM
SIMIF
register
UEM
digital
logic
Vibra
The e-vibra is placed in the bottom part of the PWB.
The test pattern is placed on engine PWB, for service purposes, same test pattern is used for
after sales purposes as well.
Through MBUS or FBUS connections, the phone HW can be tested by PC software (Phoenix).
The test points are listed in the A3 size schematic diagrams
■ Connections to baseband
The flash programming box, FPS8, is connected to the baseband using a galvanic connector
or test pads for galvanic connection.
FBUS interface
FBUS is an asynchronous data bus having separate TX and RX signals. Default bit rate of the
bus is 115.2 kbit/s. FBUS is mainly used for controlling phone when flashing.
MBUS interface
MBUS interface is used for controlling the phone in service. It is bi-directional serial bus between the phone and PC. The default transmission speed is 9.6 kbit/s.
In the following general descriptions different colours are used in the block diagram. The Low
band signal route is shown in red, theHigh band route in green and the common signal lines
are shown in blue.
■ Receiver signal path
The signal from the antenna pad is routed to the RX/TX switch (Z700). If no control voltage is
present at V ANT2 and V ANT1 the switch works as a diplexer and the low ba nd signal is passed
through the RX/TX switch to GSM-RX and theHigh band signal is passed to DCS-RX.
Figure 10: Receiver signal path
From the RX/TX switch the low band signal is routed to the SA W filte r (Z602). The front end of
Mjoelner is divided into a LNA and Pre-Gain amplifier before the mixers.
The output from the mixer is feed to Baseband part of Mjoelner where the signals amplified in
the BBAMP and low pass filtered in LPF1 before the DC compensation circuits in DCN1. The
DCN1 output is followed by a controlled attenuator and a se cond lowp ass filter LPF2. The ou tput from LPF2 is feed to the BB for demodulation.
TheHigh band signal chain is similar to low band, the SAW filter numbered Z601.
The I/Q signal from the BB is routed to the modulators for bothLow band and 1900 MHz. The
output of the modulators is either terminated in a SAW filter (Z603) for Low band or a balun
forHigh band. Both signals are amplified in buffers.
The amplitude limited signal is then amplified in the PA (N700) where the gain control takes
place. The TX signal from the couplers is fed to the RX/TX switch, used to select which signal
to route to the antenna.
Figure 11:Transmitter signal path
■ PLL
The PLL supplies Local Oscillator (LO) signals for the RX and TX-mixers. All blocks for the PLL
except for the VCO, reference X-tal and loop filter is located in the Mjoelner IC.
The reference frequency is generated by a 26MHz V olt age Controlled X-tal Oscillator (VCXO)
which is located in the Mjoelner IC. Only the X-tal is external. 26MHz is supplied to BB where
a divide-by-2 circuit (located in the UPP IC) generates the BB-clock at 13MHz. The reference
frequency is supplied to the reference divider (RDIV) where the frequency is divided by 65. The
output of RDIV (400kHz) is used as reference clock for the Phase Detector (ϕ).
The PLL is a feedback control system controlling the phase and frequency of the LO-signal.
Building blocks for the PLL include: Phase detector, Charge Pump, Voltage Controlled Oscillator (VCO), N-Divider and loop filter . As mentioned earlier only the VCO and loop filter is external
to the Mjoelner IC.
The VCO (G600) is the component that actually generates the LO-frequency. Based on the
control voltage input the VCO generates a single-ended RF output. The signal is then dif ferentiated through a balun. This signal is fed to the Prescaler and N-divider in Mjoelner.
The divider output is supplied to the phase detector which compares the frequency and phase
to the 400kHz reference clock. Based on this comparison the phase detector controls the
charge pump to either charge or discharge the capacitors in the loop filter. By charging/discharging the loop filter the control voltage to the VCO changes and the LO-frequency will
change. Therefore the PLL keeps the LO-frequency locked to the 26MHz VCXO frequency.
The loop filter consists of the following components: C639-C641 and R618-R619.
The PLL is operating at twice the channel center frequency when transmitting or receiving in
the PCN band. For the EGSM band the PLL is operating at 4-times the channel frequency.
Therefore divide-by-2 and divide-by-4 circuits are inserted between the PLL output and LO-inputs to the PCN and EGSM mixers.
Table 13: Frequency plan
ItemGSM850 EGSM900 GSM1800 GSM1900
Receive
frequency
range
Transmit
frequency
range
Duplex
spacing
Channel
spacing
Number of
channels
All power supplies for the RF Unit are generated in the UEM IC (D200). All power outputs from
this IC has a decoupling capacitor at which the supply voltage can be checked.
The power supply configuration is described in the block diagram below:
Figure 12: Power supply configuration
The names in bold
within the Mjoelner and the VCO refers to pin names on the respective ICs (N600, G600).