Nokia 252 RF Block 04

After Sales Technical Documentation

NHA–5 Series Transceivers

Chapter 4
RF Block

Issue2 03/00

NHA–5

After Sales

RF Block

CONTENTS

RF Block Description 4 – 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver 4 – 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RX Synthesizer 4 – 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RX Loop Filter 4 – 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RX VCO 4 – 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX Synthesizer 4 – 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX VCO 4 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX Loop Filter 4 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter 4 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Regulators 4 – 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Connections between RF and BB Sections 4 – 7. . . . . . . . . . . . . . . .

Block Diagram of Baseband 4 – 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Technical Documentation

Page No

Block Diagram of NASTA 4 – 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block Diagram of MUUMI 4 – 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block Diagram of Baseband Power Distribution 4 – 11. . . . . . . . . . . . .

Circuit Diagram Blocks of Baseband Section 4 – 12. . . . . . . . . . . . . . .

Circuit Diagram Blocks of Baseband Section 4 – 13. . . . . . . . . . . . . . .

Circuit Diagram of MCU & EEPROM (Version:9.0 Edit: 87) 4 – 14. . .
Circuit Diagram of MCU & EEPROM (Version:11.0 Edit:9.3) 4 – 15. .

Circuit Diagram of Audio (Version:9.0 Edit: 138) 4 – 16. . . . . . . . . . . . .

Circuit Diagram of Audio (Version:11.0 Edit:143) 4 – 17. . . . . . . . . . . .

Circuit Diagram of Power Supply (Version:9.0 Edit:119) 4 – 18. . . . . .

Circuit Diagram of Power Supply (Version:11.0 Edit:127) 4 – 19. . . . .

Circuit Diagram of User Interface (Version:9.0 Edit: 83) 4 – 20. . . . . .

Circuit Diagram of User Interface (Version:11.0 Edit:87) 4 – 21. . . . . .

Block Diagram of RF Section 4 – 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Distribution Diagram of RF Section 4 – 23. . . . . . . . . . . . . . . . . .

Circuit Diagram of RF Section (version 9.0) 4 – 24. . . . . . . . . . . . . . . .

Circuit Diagram of RF Section (version 11.0) 4 – 25. . . . . . . . . . . . . . .

Layout Diagrams (version 09) 4 – 26. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Layout Diagrams (version 11) 4 – 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Part List of JRC1 (Issue: 2.10) 4 – 28. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Part List of JRC4 4 – 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 4 – 2

Issue2 03/00

After Sales

NHA–5

Technical Documentation

RF Block Description

Receiver

The receiver is a dual–conversion superheterodyne using two intermedi­ate frequencies, 45 MHz and 450 kHz.

The RF signal from the duplexer RX port is applied to the RF amplifier.
The amplifier is realized with transistor V700. Amplifier stage input match­ing is accomplished by C701. R700 and R701 are used for biasing. Out­put matching is carried out by Z03 and Z04. Components C702 and C703
are used for RF bypassing. The RF amplifier and the IF circuit are con­nected in series with R702 so that the same supply current is passed
through both stages.

Next the signal is filtered with Z703. The filter is followed by a single bal­anced diode mixer, realized with Z701, Z711, Z712, C709, C716 and
V701.

RF Block

After the mixer the 45 MHz IF signal is filtered with crystal filter Z702. The
matching between mixer and the filter is realized with L706 and C706.
Next the IF signal is amplified by V703. Input matching is realized with
C714, L702 and L705. The biasing is realized with R713, R714 and R710.
From the amplifier the IF–signal is applied to the second mixer.

The second mixer, the LO buffer transistor, IF amplifier and quadrature
detector are all integrated in the circuit N700. The second LO frequency,

44.55 MHz, is third harmonic off the VCXO frequency. LO signal is real­ized with tank circuit C719 and L710. After the mixer the 450 kHz IF sig­nal is filtered with ceramic filter Z704. Between the filter and IF amplifier is
a band–pass filter consisting of C728, L709 and C730. The IF amplifier
output signal is phase shifted by resonance circuit C727, C723, R712 and
L704. After this the signal is fed to a quadrature detector.

Signal DAF is low pass filtered by R716 and C734. The DAF, RSSI and
2nd IF signal (450 kHz) are fed to the audio/logic unit.

RX Synthesizer

The first injection frequency is generated by a digital phase locked loop
(PLL). The output frequency of the loop (LO) is obtained from a voltage–
controlled oscillator (VCO) V602. The bandwidth of the PLL can be varied
by dataword programming. The VCO output signal is amplified by transis­tor V601 and fed to the receiver mixer via Z06. The injection level re­quired by the receiver mixer is about +3 dBm. In addition, the signal is fed
to the dualsynthesizer circuit N650 and via R625 to a LO amplifier which
is realized with V661.

The overall divisor of the chain is selected according to the desired chan­nel.

Issue2 03/00

Page 4 – 3

NHA–5

After Sales

RF Block

The internal dividers of N650 are programmed with 17 bits, which are
transferred serially on the SDATA (synthesizer data) line from the proces­sor into an internal shift register also locating in N650. Data transfer is
timed with SCLK clock pulses.

The divided frequency is compared with a highly stable reference fre­quency by a phase comparator in the PLL circuit (N650). The phase
comparator controls the VCO frequency by means of a d.c. voltage
through the loop filter so as to keep the divided frequency applied to the
phase comparator equal to the fixed reference frequency.

The reference frequency is 30 kHz. This reference frequency is obtained
from The voltage controlled crystal oscillator (VCXO). The oscillator fre­quency is 14.85 MHz. The VCXO frequency is divided by 495.

RX Loop Filter

Phase comparator output is pin 3. If the VCO frequency is too high, the
output goes low and discharge integrating capacitor C618. After this, the
DC control voltage and the VCO frequency will decrease.

Technical Documentation

If the VCO frequency is too low, the output goes high and charge the inte­grating capacitor C618. Thereafter the DC control voltage and the VCO
frequency will go up.

Output pulses from the phase detector have to be supplied to the loop fil­ter. The function of the integrator is to convert positive and negative
pulses to DC voltage. The remaining ripple and AC components are fil­tered in the lowpass filter. The integrator comprises components R610,
C619, C624 and C618. The lowpass filter consists of R608 and C616.

RX VCO

The VCO is a Clapp type oscillator. The oscillator’s resonant frequency is
determined by the circuitry Z600, C604, V603,C601, C614, C611, C612
and C613. The center frequency of the VCO is adjusted by changing
amount of constant current generated by V100 in BB section. The VCO
signal is amplified by buffer amplifier V601. This amplifier produces a lev­el of –5 dBm to the synthesizer N650 and amplifier V661 in TX synthesiz­er via R625. The same buffer V601 produces +3 dBm level to the first
mixer via Z06.

TX Synthesizer

Page 4 – 4

The transmitter synthesizer generates a frequency modulated transmitter
signal for the transmitter section.

The TX offset synthesizer consists of a 90 MHz PLL circuit, passive loop
filter and a 90 MHz VCO equipped with a chip coil resonator. The band­width of the PLL can be varied by dataword programming. Modulation is
brought to the VCO.

Issue2 03/00

After Sales

NHA–5

Technical Documentation

The TX signal is obtained by mixing the signals of offset synthesizer and
RX synthesizer with a single balanced diode mixer. From the mixer the
–10 dBm level is fed to the amplifier. The TX signal is filtered with a SAW
filter before inputting it to the transmitter.

TX VCO

The VCO is a Clapp type oscillator. The oscillator’s resonance frequency
is determined by the circuitry L651, C659, V659, C663, C630, C631 and
C675. The center frequency of the resonance circuit is not adjustable (By
increasing or decreasing the capacitor C659 the resonance frequency
can be changed). The VCO signal is amplified by V657 and fed to the
prescaler and to the mixer.

TX Loop Filter

Output pulses from the phase detector N650 pin 17 have to be supplied
to the loop filter. The integrator, which is constituted of R674, C680 and
C683, converts positive and negative pulses to d.c. voltage. The remain­ing ripple is filtered in the low–pass filter accomplished by R672 and
C665.

RF Block

Transmitter

The transmitter is realized with four discrete transistors. The modulated
RF signal from the TX synthesizer is applied to the input transistor V660
of the transmitter. V660 amplifies the signal for the power control stage
V803, which is biased to B–class. The power level is controlled by the col­lector voltage of V803. Transistors V804 and V805 are biased to C–class
and amplify the RF signal to the desired output power level. The amplified
RF signal is fed through a low–pass filter to the duplex filter. The harmon­ics of the transmitter are reduced by the duplex filter. A voltage propor­tional to the output power is rectified from a directional coupler by d.c.
biased Schottky diode V801. This rectified voltage is fed to a differential
amplifier which consists of double transistor V809. There is a negative
feedback from the rectified voltage to the bias voltage of diode V801 con­sisting of transistor V810 and associated components. The purpose of ar­ranging the feedback is to suppress the rectified voltage to a range below
3 volts. The reference voltage is filtered from the PWM signal TXC by
R814 and C826. The differential amplifier adjusts the collector voltage of
the transistor V803 so that the reference voltage and the voltage propor­tional to the output power are equal. The transmitter is switched on when
TXE goes high (logic 1), which enables the transmitter power control cir­cuit by transistor V808 and the first stage of the transmitter. When the
transmitter is inactive (TXE low) the RF level from the transmitter is re­duced below –60 dBm.

The rectified voltage, which is proportional to the power output signal, is
fed along TXI line through R820 to the BB–unit. This TXI line (TX power
on Indicator) is used to avoid false transmission.

Issue2 03/00

Page 4 – 5

NHA–5

After Sales

RF Block

Regulators

Transistors V901 and V902 form a voltage regulator for RF parts. It is
realized with discrete transistors because the output noise has to be very
low. The 3.3 V reference voltage (VREF) comes from the logic module.
This regulated voltage goes directly to RX part and also to RX synthesiz­er. TX synthesizer get it’s supply voltage via a switch. The switch is real­ized with transistors V651 and V654.It is controlled over digital line TXS
from the logic module.

Technical Documentation

Page 4 – 6

Issue2 03/00

After Sales

NHA–5

Technical Documentation

RF Block

Connections between RF and BB Sections (Version: 4.0 Edit: 66)

Issue2 03/00

Page 4 – 7

NHA–5

After Sales

RF Block

Block Diagram of Baseband

NASTA

DAF

D/A

IF
CTR

SPEECH

DATA/ST

CLK
DIV

SAT

DATA

SYNBIAS
RXBIAS

14.85 MHz

MOD

AFC

IF

CTR

CLK

GEN

SAT

DET

MAN

DPLL

DEC

MCU INTERFACE

HF
DET

Technical Documentation

EARPHONE

EAR

VBAT

XEARON

MIC

MICROPHONE

VOTE

SMUX

SMUX

DATA/
ST
ENCODE

XMIC

XEAR

BUZZER

VC

4.8V

NTC

Battery
pack

–VMOD

TXE,TXS,TXC

SLE,SDATA,SCLK

Charge
switch
control

VBAT

BTEMP
BSI

ON/OFF

VCO
NEG VOLT
TRIM

–VLCD

XEARON

RXV(3:0)

RF CONTROLS

HOOK, EXT_RF

Charger

det,crl

VB det
RESET
PWR ON

WDOG

MUUMI

VBSW
VCSW

BTEMP
BSI
RSSI
TXI
RFTEMP
XMIC/ID

RESET,PWRON

MBUS

2.4MHz

WDOG
TIMER

ITU
16 BIT
TIMERS

INTERRUPT
CONTROL

A/D
10 BIT
8 CH

2 kbytes

TXD,XPWROFF

VL=3.3V

VA=3.3V

VREF=3.3V

H8/3047

H8/300
CPU

ROM
96K

RAM
4K

SCL,SDA

EEPROM

VCSW
VBSW

ND0–7,NA0–3
_NCS,_WR,_RD

_NINT

DMA

REFRESH
CONTRL

TPC,
TIMING
PATTERN CRL

SCI

SERIAL

IFCE

2 CHAN

80 kHz

RS,R/W,E,
DB0–3

LIGHTS

ROW0–5

BUZZ_DRIVE

COM1–7,COM9–15,COMMK

SEG1–60

LCD–

CONTROLLER

KEYBOARD

COL0–3

HOOK

EXT_RF

XEAR

XMIC

ACCESSORY

CONNECTOR

–VLCDout

MBUS

HOOK
EXT_RF

XEAR
XMIC

BENA
V_OUT

Page 4 – 8

Issue2 03/00

Issue2 03/00

MIC

BIMIC

CMIC
XMIC

50

2.4

REF

14.85 MHz>500 pp

CLKIN

CLKOUT

IF

(450 kHz)

MICAM

DTMF GEN

GND GEN

OSC

IFAMP

REF GEN

CLKGEN

TXMUX TXATT MICTRI TXBP

XCLR

TMODE

CLKLCD CLKMCU

TSEL

CLOCKDIV

MCS1&2

IFCNTR

MANDEC

Nom–dev

50 71

ATTO

COMI

CWCI

COMO

COMPR LIM1

sideari

BCH

INT
CLOCKS

VOTE

TIMER

EMPI

SMUX

CORR

100

EMPO LPIN

PREEM LIM2 TXLP TXTRI

MANEN

STATUS BITS

TR

Par/Ser

SYNBIAS

CONTROL BITS

RXBIAS
TOUT

CREG

Max–dev

aloop

DATA

GEN

SAT

GEN

ST

GEN

SUM

TXTRI

SATFIL
HFBP
SATCOMP
DATAC
CAMPBO

Extended

210

Data–dev

WTRFIL

ATST

ATOUT

D/St 1640 pp
Sat 410/435 pp

210

MOD

loop

Block Diagram of NASTA

After Sales

Technical Documentation

VDD1
VDD2
VSS2
VDA1
VSA1
VDA2
VSA2
VSS1

DAF

50

D 398 pp
Sat 99/100 pp

Page 4 – 9

DATAC

D 792 pp

dtmf

RXTRI RXAAF

100

DPLL

loop

DATVAL

RXMUX

aloop

XCSXRDXWRXINT A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7

SATFIL,6kHz SATCOMP SATDET

360

RXFIL

71

FILO

EXP VOL

EAMPBO

EXPI

EWCI

EXPO

4

50

VOLI

INTERFACE

HF

CONTR

RXATT ACC

Level: AMPS/TACS (mVrms)
All levels: (mV)
( ) : Not use now

EAR

64 pins Tqfp

50

EARP

50

EARM

EVGND

XEAR

50

VDD1

XRD

XCS

A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0

VDD2

1 2 3 4 5 6 7 8 9 1011 1213141516

63CLKMCU

64XWR

18 XCLR

17 TOUT

61CLKIN

62CLKLCD

20 TSEL

19 TMODE

59ATOUT

60CLKOUT

22 SYNBIAS

21 XINT

57VSS1

58BUZZ

NASTA

24 IF

23 RXBIAS

56VSA1

25 VSS2

55MOD

26 VSA2

sideari

SIDEAR

AFC

dtmf

D/A

8 bit

BUZZ DRIV

DACO

BUZZ

(1500 pp)
(3000 pp)

49COMI

50COMO

51EMPI

52EMPO

53LPIN

54ATST

48474645444342414039383736353433

VDA1

ATTO
XMIC
CMIC
BIMIC
MIC
REF
SIDEAR
DACO
CWCI
EARP
EARM
EVGND
XEAR
VOLI

VDA2

32 EXPO

31 EWCI

30 EAMPBO

29 EXPI

28 FILO

27 DAF

RF Block

NHA–5

NHA–5

After Sales

RF Block

Block Diagram of MUUMI

VBAT1

1

VBAT2

22

VBAT3

5

M2BUSIN

11

760k



Technical Documentation

70k

40k

VBATSW

M2BUSOUT

17

12

VL

23

15

21

13

14

3

PWM

VCHAR

PWRONX

PWROFFX

TEST

VBAT

760k

32k

760k

760k

CHARGER

CTRL

LOGIC

LOW VBAT
& CHARGER
DETECT

PWR ON/OFF
&
RESET LOGIC

Creset

20

16

Coff

BANDGAP
REF

VL_ENA
VA_ENA

VREF_ENA

VSW_ENA

VCHAR

24

GND1

GND2

19

GND3

7





VA

2

VREF

CHRGSW

PURX

PWRONXBUFF

VCHARSW

Cref

4

8

10

9

18

6

Page 4 – 10

Issue2 03/00

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NHA–5

Technical Documentation

Block Diagram of Baseband Power Distribution

VBVC

VL

MUUMI

VA

NASTA

Microcontroller

VREF

LCD
controller

EEPROM

RF Block

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Page 4 – 11

NHA–5

After Sales

RF Block

Technical Documentation

Circuit Diagram of MCU & EEPROM (Version:4.0 Edit: 113)

Page 4 – 12

Issue2 03/00