– H8/3047 16–bit single chip microcontroller with 96 kbytes ROM
(EPROM) and 4 kbytes RAM
– NASTA modem and audio ASIC
– External audio amplifier with on/off control and buzzer driver circuit
– MUUMI power supply (and control), ASIC and discrete charge switch
control logic
– serial I2C–bus 2 kbytes EEPROM with 16 bytes one time program-
mable electrical serial number (ESN) area
– NJU6428 LCD controller with 2* VL negative voltage generation is lo-
cated in the separate display module
Baseband Block
The baseband block diagram illustrates the baseband module connections and interface to charger, battery and display module.
Microcontroller
NHA–5 microcontroller is a H8/3047 that is operating in single–chip advanced mode (mode 7) 96 kbyte address space. The MCU operating
clock (=2.4 MHz) is generated on NASTA.
Microcontroller includes 2 serial channels, 5 pcs 16–bit timer units(ITU)
with PWM and interval capability, 10–bit A/D–converter with 8 channels,
watchdog timer and refresh timer. Serial channel 0 is used for asynchronous M2BUS–communication and channel 1 is used for synchronous
synthesizer interface. Four timer units are used for pulse width modulation (PWM) outputs: buzzer control(BUZZ_DRIVE) ITU0, charge control
(CSWPWM) ITU1, TX power control (TXC) ITU2 and vibrating battery
control ITU3. M2BUS net free interrupt reserves one timer unit ITU4. Keyboard interface reserves 10 I/O–lines: 4 column outputs (COL3–0) and 6
row inputs. Different power on/off switch is connected through MUUMI circuit to MCU input PWRON.
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Baseband Block
Input/Output Ports of MCU
All input/output pins are used as I/O–ports. NASTA address and data bus
is connected to I/O–pins.
Port 1
Pin namePin use description
P10/A0NA0, NASTA address bus ,output
P11/A1NA1, NASTA address bus ,output
P12/A2NA2, NASTA address bus ,output
P13/A3NA3, NASTA address bus ,output
P14/A4NCS
P15/A5NRD, NASTA read control output
P16/A6NWR
P17/A7
P27/A15LIGHTS, Keyboard and display illumination on/off=1/0
control output
Pin namePin use description
P30/D8ND0, NASTA data bus,I/O
P31/D9ND1, NASTA data bus,I/O
P32/D10ND2, NASTA data bus,I/O
P33/D11ND3, NASTA data bus,I/O
P34/D12ND4, NASTA data bus,I/O
P35/D13ND5, NASTA data bus,I/O
P36/D14ND6, NASTA data bus,I/O
P37/D15ND7, NASTA data bus,I/O
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Technical Documentation
Port 4
Pin namePin use description
P40/D0SLE, Synthesizer latch enable
(pullup used, when input)
(pullup used, when input)
(pullup used ,when input)
(pullup used ,when input)
Port 6
Pin namePin use description
P60/WAITDB0, LCD controller data bus,I/O
P61/BREQDB1, LCD controller data bus,I/O
P62/BACK
P63/AS
P64/RDE, LCD controller bus enable control output
P65/HWRR/W, LCD controller bus read/write control output
P66/LWRRS, LCD controller register select control output
DB2, LCD controller data bus,I/O
DB3, LCD controller data bus,I/O
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Port 7
Pin namePin use description
P70/AN0VBSW, Battery (VBAT) voltage measurement input
P71/AN1VCSW, Charger voltage measurement input
P72/AN2BSI, Battery size indication
P73/AN3BTEMP, Battery temperature measurement,
P74/AN4RSSI, Receiver Signal Strength Indication
P75/AN5TXI, Transmitter power indication
P76/AN6RFTEMP, RF temperature measurement
P77/AN7XMIC, external audio and accessory identification
input
Pin namePin use description
P80/RFS/IRQ0NINT, Interrupt from NASTA
P81/CS3
P82/CS2
P83/CS1/IRQ3unused output
P84/CS0unused output
Pin namePin use description
P90/TxD0MBUS out
P91/TxD1SDATA,Synthesizer serial data output
P92/RxD0MBUS in
P93/RxD1SDA, serial EEPROM IIC–bus data
P94/SCK0/IRQ4
P95/SCK1/IRQ5SCLK, serial data clock output to synthesizers
/IRQ1HOOK, HOOK on=1/off=0 status, accessory
connect interrupt (falling edge)
/IRQ2EXT_RF, 0=external antenna in use, input
(not used in C1, configure as output)
SCL, serial EEPROM IIC–bus clock
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Technical Documentation
Port A
Pin namePin use description
PA0XEARON, external audio amplifier on/off=1/0 and hands
PA1/TCLKBLCDCLK, 80 kHz clock input for slow clock PWM to timer
PA2/TIOCA0BUZZ_DRIVE, Buzzer drive output from timer unit 0, level
PA3/TIOCB0unused output
PA4/TIOCA1CSWPWM, Charger PWM control output (Timer unit 1)
PA5/TIOCB1XPWROFF, Power off and watchdog clear control output,
PA6/TIOCA2TXC, Transmitter power control PWM output (Timer unit
2)
PA7/TIOCB2RXV3, RX VCO aligning output
Port B
Baseband Block
free mute (on=0) control
unit 1
adjust with PWM
watchdog cleared on falling edge
Pin namePin use description
PB0/TP8/TIOCA3vibrating battery driver
(connected to BTEMP)
PB1/TP9/TIOCB3ABC/PWR key input, =0 when ABC/PWR key pressed
PB2/TP10/TIOCA4unused output
PB3/TP11/TIOCB4MBUSNF, MBUS net free timer input (Timer unit 4)
PB4/TP12/TOCXA4 unused output
PB5/TP13/TOCXB4 unused output
PB6/TP14unused output
PB7/TP15unused output
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A/D Converter of MCU
A/D converter has 10 bit resolution with ±8 LSB absolute accuracy and
3.3 V ±3% reference voltage input. All 8 analog inputs can be multiplexed
to A/D converter input. The A/D conversion time is 134 CPU clock cycles
maximum (CKS=1) and input sampling time is 40 clock cycles.
Description of Input Channels
Channel 0: WBSW, Battery Voltage Measurement
Battery voltage can be measured from 4 V to 9.075 V nominal with 3.3 V
reference voltage. The absolute accuracy is low because of the reference
3 % accuracy and A/D converter ±8 LSB accuracy. This battery voltage
measurement offset error must be calibrated with input voltage 4.8 V. The
A/D conversion result can be calculated from equation:
A/D readout = 1024 * (VBSW* ( 4/11))/VREF VREF=3.3 V
For example (voltage, min/nom/max A/D value):
4.3 V456...484...515cut off limit/idle
4.8 V509...541...575battery voltage reference trim
6.8 V 722...767...815high battery charging voltage limit
Technical Documentation
Channel 1: VCSW, Charger Voltage Measurement
Charger voltage can be measured up to 21.6 V nominal. The A/D conversion result can be calculated from equation:
A/D readout = 1024 * (VCSW*(18/118))/VREF VREF=3.3 V
For example:
4.8 V198...227...257Charger voltage reference trim
10 V413...473...536–
11 V661...757...859Max charger voltage
Channel 2: BSI, Battery Size Indication
Battery capacity can be defined with BSI resistor value calculated from
equation:
BSI = 12.1 kΩ / ((4 mAh * 1023)/ C) –1)
A/D readout gives battery capacity from equation:
Battery temperature measurement is implemented with 47 kΩ NTC and
47 kΩ pullup resistor. The A/D conversion readout can be calculated from
equation:
A/D readout= 1024* ( R
NTC
/( R
NTC
+47kΩ))
For example:
5 °C705...743...780
25 °C486...512...537
45 °C289...305...320
Channel 4: RSSI, Receive Signal Strength
Receiving signal strength is proportional to input voltage / A/D–readout.
Typical value for noise level signal strength is 0.2 V = 0062= 03E H and
for maximum signal strength is 2.4 V = 0744 = 2E8 H. Input value for –90
dBm RF input level is typically 1.16 V= 0360 = 168 H . RF input level
change of 1 dBm equals about 24 mV= 7.5 A/D steps.
Baseband Block
Channel 5: TXI, Transmitter Power Level Indication
Transmitter power level indication is used to monitor the transmitted power level. A/D input is used to check, if TX power is on or off. The limit for
check is 1.0 V, which is equal to 320 as A/D readout.
Channel 6: RFTEMP, RF VCXO Temperature Measure
VCXO module temperature measurement is based on CMOS temperature sensor chip with linear – 8.1 mV/K voltage output. The nominal output voltage of sensor IC is at +30 °C 1.497 V. One degree temperature
change is equal to 2.5 A/D quantisize steps.
For example:
–20 °C549...589...636
+30 °C429...464...508
+80 °C304...336...376
Channel 7: ID, Accessory Identification Input
Accessory identification is included in XMIC signal d.c. voltage level = ID
analog input. This d.c. voltage level is defined by pullup resistor. Compact
HF unit and headset adapter can be recognized from this input:
LCD controller interface to microcontroller is a 4–bit parallel type including
4 bidirectional data lines DB3–0 (port 63–60), register select control RS
(port 66) output, read/write control R/W (port 65) output and bus enable
control E (port 64) output. Data lines DB3–0 and control signals RS
,R/W must be set to high state during standby operation because of the
pullup resistors in LCD controller. LCD controller resetting requires clock
during _RESET active low . This
clock is created with LCD controller internal RC–oscillator changing
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Baseband Block
LCDCLK
output from NASTA to 3–state.
Interface between microcontroller and NASTA circuit is bidirectional 8–bit
parallel type with 4 address lines. Address, data and control lines are
used in microcontroller as I/O–port pins. Data lines direction must be controlled with microcontroller data direction register. Interface includes address outputs NA3–0 (port 1), data inputs (read) / outputs (write) ND7–0
(port 3), chip select control output NCS
NRD (port 15) , write control output NWR (port 16) and interrupt input
NINT (port 80) . If NASTA circuit is not selected , control signals
(read,write and chip select) must be in high state and data lines must be
outputs.
The serial I2C–bus interface EEPROM is connected to MCU I/O–pins:
SDA (serial data) to port 93 and SCL (serial clock) to port 94.
MCU SLEEP Mode Operation
Technical Documentation
(port 14), read control output
Audio
Microcontroller is driven to sleep mode by software in order to save power. In sleep mode all I/O–pins,RAM and CPU registers are held. Timers,
clock and supporting functions are active. MCU exits from sleep mode by
interrupt: NASTA modem interrupt, MBUS serial communication interface
interrupt (SCI 0) or operating system timer interrupt (refresh controller
timer).
The main audio and modem operations are included in NASTA ASIC circuit. NASTA includes following operations:
– AMPS/TACS modem with extended standby operation
– all RX/TX audio filters, compander, limiters, mute switches
– microphone amplifier, ceramic earpiece amplifier, accessory audio output
(XEAR) and input (XMIC).
– DTMF generator.
– IF counter and 8–bit D/A–output for AFC control
– voltage controlled oscillator and clock generation
The NASTA circuit is connected to MCU with 8–bit parallel bus and interrupt request line.
The 14.85 MHz clock input is generated in RF module voltage controlled
crystal oscillator (VCXO). This input clock is used to synthesize 4.8 MHz
clock to NASTA internal circuits. NASTA creates 2.4 MHz clock to microcontroller (CLKMCU) and 80 kHz clock to LCD controller. The buzzer driver amplifier is driven by MCU PWM output. The buzzer volume level is
adjusted with pulse width. The accessory audio output line XEAR is driven by transistor pair (V53) buffer. The buffer is short circuit protected with
47 ohm series resistor and has on/off (mute) control from MCU output
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Technical Documentation
(XEARON). This XEAR buffer amplifier outputs more than 1.6 V DC voltage to control accessory audio to mute off state. Accessory audio input
XMIC is connected also with low pass filter (R52 and C70) to MCU
A/D–converter input. This accessory identification input (ID) is used to
recognize the connected accessory type and check, if accessory is connected or not.
NASTA RX Signal Paths
The incoming audio, data and SAT (Supervisory Audio Tone) analog signal (DAF = N2 pin 27) is connected through the RX trimmer and the anti
alias filter to modem data comparator input, to 6 kHz bandpass type SAT
filter input and to receive audio filter.
The data from the anti alias filter is connected through the comparator to
a Manchester decoder, which decodes Manchester data to the NRZ (Non
Return to Zero) format.Modem is synchronized to the receiving data with
a digital phase locked loop and a word synchronization detection block.
Data validity is continuously detected, and this information is used internally when word synchronization detection is accepted.The serial data
from the Manchester decoder is 3/5 majority voted, BCH–decoded, corrected and shifted to receiver register. The Receiver timing block extracts
the data from received frames on control and voice channels and generates data transfer interrupts . It maintains bit and word synchronization
during different frames and passes the synchronization status forward to
the status register.
Baseband Block
The SAT signal is filtered and amplified with a bandpass filter . Signal is
converted to digital square wave signal with a comparator .SAT detection
is done with a digital PLL/detection circuitry. The regenerated SAT is then
fed to transmit summing block.
RX audio signal is selected with the input mux. Other possibilities is to select DTMF or RX mute. RX audio signal is filtered with a de–emphasis
and bandpass filter. Signal is fed through amplitude expander 1:2 (EXP).
RX volume level is controlled with amplifier in the range –20 ... +17.5
dB.Hands free control block includes a bandpass filter, window comparator and controller for RX TX attenuators. RX hands free attenuator has
selectable minimum gain from –30...–21 dB to max 0 dB. RX and TX attenuation sum is always constant at HF use (30...21 dB). Side tone is
added to earphone signal. The audio signal is fed either to earphone amplifier output (EARM, EARP) or to accessory audio amplifier output
(XEAR).
NASTA TX Signal Paths
The data to be transmitted will be loaded into the transmitting data register. From the transmit data register the 8 bit data is transformed to serial
data which is fed to the Manchester encoder and then to the summing
block output (MOD, N2 pin 55).
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Microphone signal is fed to microphone amplifier input (MIC, N2 pin 43).
NASTA has a control for microphone bias current output (BIMIC, N2 pin
44). Signal source can be selected with the input multiplexer: microphone,
accessory input (XMIC, N2 pin 46) or internal dtmf generator. TX hands
free attenuator has selectable minimum gain from –30...–21 dB to maximum 0 dB. Signal is going to trimmer, which is tuned for nominal speech
deviation or DTMF level. Signal is filtered in the TX audio bandpass filter.
Signal is fed through amplitude compressor 2:1 to the first limiter for low
frequency amplitude limiting. Signal is then pre–emphasised and limited
again. Signal is lowpass filtered and fed to trimmer for speech maximum
deviation tuning. It is fed to the TX summing block to be summed with
data, ST and SAT signals.
DTMF generator generates dual and single tones for RX and TX lines.
Tolerance of DTMF frequencies is ±1.5 %.
User Interface
Technical Documentation
Power
The user interface includes interface to display module and keyboard with
illumination. The display module is connected with 16 pin connector. The
display module interface includes 4 bit data bus (DB(3:0)), bus enable
(E), read/write (R_W), register select (RS), reset (_RESET) and 80 kHz
clock input to LCD–controller (LCDCLK). The keyboard illumination includes 12 LEDs and 2 transistor(V42, V43) drivers. Keyboard consists of
6*4 matrix and different ABC/PWR–key and PWR–switch. The keyboard
interface to microcontroller includes 4 column outputs from MCU
(COL(3:0)), 6 row inputs (ROW(5:0)), ABC/PWR–key input (ABCKEY)
and PWR–switch input (PWRON).
Module goes to power on state always, when either ABC/PWR–key or
PWR switch is pressed. The software decides, if ABC/PWR–key is active
power key or not. This and other key variations is defined by software.
The baseband power supplying circuit MUUMI includes:
– 3 pcs 3.3 V regulated outputs
– VL = Logic voltage for digital circuits
– VA = Analog voltage for analog circuits
– VREF = Reference voltage for A/D converter and RF regulator
– switched outputs of battery (VBSW) and charger voltage (VCSW)
measurement to MCU A/D–converter
– battery voltage detection and reset logic
– charger switch control output used to limit battery voltage VBAT < 8.0V
– power on/off switch input (XPWRON), buffered output to MCU
(PWRON)
– watchdog timer using oscillator in COFF pin, cleared by falling edge input in PWROFFX, elapsing time for WD timer is 1...3 seconds
– M2BUS open drain output driver
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Technical Documentation
The charge switch driving circuit is implemented with discrete components. This circuit includes transient voltage protection, soft charge
switching, low voltage battery charging and battery disconnecting with
charger connected protection. This circuit also limits battery voltage when
charger is connected to protect MUUMI and TX transistors.
Power Circuit Operation
The NHA–5 power circuitry has three different operating modes: POWER
OFF, RESET and POWER ON. In POWER OFF state MUUMI regulator
outputs are disabled and reset control output signal (PURX) is active low.
MUUMI internal oscillator at pin COFF is working in all operating modes.
MUUMI goes through short RESET state (100 ms) to POWER ON–
state, if PWR–button is pressed or charger voltage input is connected to
charging input VC (charging voltage detection in MUUMI input VCHAR is
level active). In RESET–state regulator outputs VL, VA and VREF are active and PURX–signal is active low. If battery voltage VBAT is lower than
4.1 V (3.9 V...4.3 V) the circuit cannot go to POWER ON state. MUUMI
goes also to RESET state, when battery voltage is falling below 3.9 V (3.7
V...4.1 V). This situation is possible, when battery is fully discharged or
battery is disconnected.
Baseband Block
In POWER ON mode all regulator outputs are active and MUUMI reset
signal output PURX is inactive high. Microcontroller XPWROFF–output
signal clears at falling edge the watchdog inside MUUMI. If the watchdog
is not cleared, MUUMI goes to POWER OFF state. When the charger is
connected and battery voltage is higher than 4.1 V, module stays in POWER ON mode.
The microcontroller controls battery charging with CSWPWM output and
MUUMI limits the maximum battery voltage to 7.6 V with CHRGSW–output.
No current flows from charger (VC) to battery, if MCU output CSWPWM is
active low and _RESET signal is inactive high. The battery is charged
also, when charger is connected and _RESET signal is active low. The
charging circuit charges the battery during RESET to higher than 4.3 V
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Baseband Block
MBUS Hardware Description
MBUS hardware interface consists of serial communication interface
channel inside MCU, net free timer (MCU), open drain output driver
(MUUMI), 4.7 kΩ pull–up resistor and protection/filtering resistor/capacitors. MBUS voltage levels are based to 3.3 V supply voltage.
N1 (MUUMI)
M2BUSIN
11
asychronous data
output from MCU
(pin 12)
760k
M2BUSOUT
Technical Documentation
received data input to
MCU(pin 14) and net
free timer input to MCU
12
(pin 5)
Bidirectional MBUS
signal to system
connector
ESN Description
The Electrical Serial Number can be programmed only once and cannot
be manipulated in the field. The custom EEPROM circuit includes 16 bytes one time programmable (OTP) part for the ESN. The ESN component
is a SO–8 package soldered to main printed circuit board.
The software of the microcontroller is not alterable and cannot even be
read, because of the microcontroller security option. The microcontroller
program memory is either OTP or mask type.
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Technical Documentation
Baseband Block
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