Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation
to know the specification of quality grade on the devices and its recommended applications.
Caution The EPROM versions of the µPD78P4038Y are not intended for use in mass-produced products;
they do not have reliability high enough for such purposes. Their use should be restricted to
functional evaluation in experiment or trial manufacture.
Remark ××× is ROM code suffix.
2
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
: Product under mass production
: Product under preparation
Standard Products Development
µ
PD78P4038Y
µ
PD784026
A/D converters,
16-bit timers, and
power management
functions have been
enhanced.
ASSP Development
µ
PD784955
DC inverter control
Connectable to the I
µ
PD784038Y
µ
PD784038
Internal memory has been expanded.
Pin-compatible with the PD784026
Connectable to the multimaster I
PD784216Y
µ
µ
PD784216
100 pins
I/O has been enhanced.
Internal memory has been expanded.
µ
PD784054
µ
PD784046
Built-in 10-bit A/D converter
2
C bus
µ
2
C bus
Connectable to the multimaster I
µ
PD784225Y
µ
PD784225
80 pins
ROM correction function has been added.
Connectable to the multimaster I
µ
PD784218Y
µ
PD784218
Internal memory has been expanded.
ROM correction function has been added.
2
C bus
2
C bus
µ
PD784908
Built-in IEBus
µ
PD784915
Software servo control
Built-in analog circuit for VCR
Timers have been enhanced.
TM
controller
µ
PD784937
Functions of the PD784908 have been enhanced.
Internal memory has been expanded.
ROM correction function has been added.
128 Kbytes (Can be changed to 48 K, 64 K, or 96 Kbytes by software)
4,352 bytes (Can be changed to 2,048 or 3,584 bytes by software)
Program and data: 1 Mbyte
64
8
56
54
APPENDIX C RELATED DOCUMENTS..........................................................................................67
6
µ
PD78P4038Y
1. DIFFERENCES BETWEEN µPD78P4038Y AND MASKED ROM PRODUCTS
The µPD78P4038Y is produced by replacing the masked ROM in the µPD784035Y, µPD784036Y, µPD784037Y,
or µPD784038Y with PROM to which data can be written. The functions of the µPD78P4038Y are the same as those
of the µPD784035Y, µPD784036Y, µPD784037Y, or µPD784038Y except for the PROM specification such as writing
and verification, except that the PROM size can be changed to 48 K, 64 K, or 96 Kbytes, and except that the internal
RAM size can be changed to 2,048 or 3,584 bytes.
Table 1-1 shows the differences between these products.
µ
Table 1-1. Differences between the
PD78P4038Y and Masked ROM Products
Product Name
Item
Internal program
memory
Internal RAM
Package
µ
PD78P4038Y
• 128-Kbyte
PROM
• Can be changed
to 48 K, 64 K, or
96 Kbytes by
IMS
A8-A19: Address bus
AD0-AD7: Address/data bus
ANI0-ANI7: Analog input
ANO0, ANO1 : Analog output
ASCK, ASCK2 : Asynchronous serial clock
ASTB: Address strobe
DD: Analog power supply
AV
AVREF1-AVREF3 : Reference voltage
SS: Analog ground
AV
CI: Clock input
CLKOUT: Clock output
HLDAK: Hold acknowledge
HLDRQ: Hold request
INTP0-INTP5 : Interrupt from peripherals
NMI: Non-maskable interrupt
P00-P07: Port 0
P10-P17: Port 1
P20-P27: Port 2
P30-P37: Port 3
P40-P47: Port 4
P50-P57: Port 5
P60-P67: Port 6
P70-P77: Port 7
PWM0, PWM1 : Pulse width modulation output
RD: Read strobe
REFRQ: Refresh request
RESET: Reset
RxD, RxD2: Receive data
SCK0-SCK2: Serial clock
SCL: Serial clock
SDA: Serial data
SI0-SI2: Serial input
SO0-SO2: Serial output
TEST: Test
TO0-TO3: Timer output
TxD, TxD2: Transmit data
Function
Timer output
Input of a count clock for timer/counter 2
Serial data input (UART0)
Serial data input (UART2)
Serial data output (UART0)
Serial data output (UART2)
Baud rate clock input (UART0)
Baud rate clock input (UART2)
Serial data I/O (2-wire serial I/O, I2C bus)
Serial data input (3-wire serial I/O0)
Serial data input (3-wire serial I/O1)
Serial data input (3-wire serial I/O2)
Serial data output (3-wire serial I/O0)
Serial data output (3-wire serial I/O1)
Serial data output (3-wire serial I/O2)
Serial clock I/O (3-wire serial I/O0)
Serial clock I/O (3-wire serial I/O1)
Serial clock I/O (3-wire serial I/O2)
Serial clock I/O (2-wire serial I/O, I2C bus)
External interrupt request–
• Input of a count clock for timer/counter 1
• Capture/trigger signal for CR11 or CR12
• Input of a count clock for timer/counter 2
• Capture/trigger signal for CR22
• Input of a count clock for timer/counter 2
• Capture/trigger signal for CR21
• Input of a count clock for timer/counter 0
• Capture/trigger signal for CR02
–
Input of a conversion start trigger for A/D converter
Time multiplexing address/data bus (for connecting external memory)
High-order address bus (for connecting external memory)
High-order address bus during address expansion (for connecting external memory)
Strobe signal output for reading the contents of external memory
Strobe signal output for writing on external memory
Wait signal insertion
Refresh pulse output to external pseudo static memory
Input of bus hold request
Output of bus hold response
Latch timing output of time multiplexing address (A0-A7) (for connecting
Chip reset
Crystal input for system clock oscillation (A clock pulse can also be input
to the X1 pin.)
Analog voltage inputs for the A/D converter
Analog voltage inputs for the D/A converter
Application of A/D converter reference voltage
Application of D/A converter reference voltage
Positive power supply for the A/D converter
Ground for the A/D converter
Positive power supply of the port part
Positive power supply except for the port part
Ground of the port part
Ground except for the port part
Directly connect to VSS0. (The TEST pin is for the IC test.)
Notes 1. The potential of the VDD0 pin must be equal to that of the VDD1 pin.
2. The potential of the VSS0 pin must be equal to that of the VSS1 pin.
Function
4.2 Pins for PROM Programming Mode (V
4.2.1 Pin functions
Pin Name
VPP
RESET
A0-A16
D0-D7
CE
OE
PGM
VDD
VSS
I/O
–
Input
I/O
Input
–
–
PROM programming mode selection
High voltage input during program write or verification
PROM programming mode selection
Address bus
Data bus
PROM enable input/program pulse input
Read strobe input to PROM
Program/program inhibit input during PROM programming mode
Positive power supply
GND
PP≥ +5 V or +12.5 V, RESET = L)
Function
15
µ
PD78P4038Y
4.2.2 Pin functions
PP (Programming power supply): Input
(1) V
Input pin for setting the µPD78P4038Y to the PROM programming mode. When the input voltage on this pin
is +5 V or more and when RESET input goes low, the µPD78P4038Y enters the PROM programming mode.
When CE is made low for V
PROM cell selected by A0 to A16.
(2) RESET (Reset): Input
Input pin for setting the
when the input voltage on the VPP pin goes +5 V or more, the µPD78P4038Y enters the PROM programming
mode.
(3) A0 to A16 (Address bus): Input
Address bus that selects an internal PROM address (0000H to 1FFFFH)
(4) D0 to D7 (Data bus): I/O
Data bus through which a program is written on or read from internal PROM
PP = +12.5 V and OE = high, program data on D0 to D7 can be written into the internal
µ
PD78P4038Y to the PROM programming mode. When input on this pin is low, and
(5) CE (Chip enable): Input
This pin inputs the enable signal from internal PROM. When this signal is active, a program can be written or
read.
(6) OE (Output enable): Input
This pin inputs the read strobe signal to internal PROM. When this signal is made active for CE = low, a onebyte program in the internal PROM cell selected by A0 to A16 can be read onto D0 to D7.
(7) PGM (Program): Input
The input pin for the operation mode control signal of the internal PROM.
Upon activation, writing to the internal PROM is enabled.
Upon inactivation, reading from the internal PROM is enabled.
DD
(8) V
Positive power supply pin
SS
(9) V
Ground potential pin
16
4.3 I/O Circuits for Pins and Handling of Unused Pins
Table 4-1 describes the types of I/O circuits for pins and the handling of unused pins.
Figure 4-1 shows the configuration of these various types of I/O circuits.
Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)
Input state: To be connected to VDD0
Output state: To be left open
To be connected to VDD0 or VSS0
To be connected to VDD0
Input state: To be connected to VDD0
Output state: To be left open
To be connected to VDD0
Input state: To be connected to VDD0
Output state: To be left open
Input state: To be connected to VDD0 or VSS0
Output state: To be left open
To be left open
17
Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)
µ
PD78P4038Y
Pin
RESET
TEST
AVREF1-AVREF3
AVSS
AVDD
I/O Circuit Type
2
1-A
–
I/O
Input
Recommended Connection Method for Unused Pins
–
To be connected to VSS0 directly
To be connected to VSS0
To be connected to VDD0
Caution When the I/O mode of an I/O alternate-function pin is unpredictable, connect the pin to V
through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin
becomes higher than that of the low level input at power-on or when I/O is switched by software).
Remark Since type numbers are consistent in the 78K Series, those numbers are not always serial in each
product. (Some circuits are not included.)
DD0
18
Figure 4-1. I/O Circuits for Pins
µ
PD78P4038Y
Type 1-AType 2-C
V
DD0
P
IN
N
V
SS0
Type 2
IN
Schmitt trigger input with hysteresis characteristics
Type 5-H
Schmitt trigger input with hysteresis characteristics
Type 4-B
Data
DD0
V
P
OUT
Output
disable
N
V
SS0
Push-pull output which can output high impedance
(both the positive and negative channels are off.)
IN
Pull-up
enable
Data
Output
disable
Input
enable
VDD0
V
DD0
Pull-up
enable
P
P
V
DD0
P
IN/OUT
N
V
SS0
Type 8-C
Pull-up
enable
Output
disable
Type 10-B
Pull-up
enable
Open
drain
Output
disable
Data
Data
Type 12
V
DD0
P
V
DD0
P
Analog output
voltage
IN/OUT
P
OUT
N
N
V
SS0
Type 20-A
V
DD0
V
DD0
Data
P
Output
V
DD0
disable
P
IN/OUT
N
V
SS0
Comparator
+
–
(Threshold voltage)
AV
AV
SS
REF
P
IN/OUT
N
V
SS0
P
N
Input
enable
19
µ
PD78P4038Y
5. INTERNAL MEMORY SWITCHING (IMS) REGISTER
This register enables the software to avoid using part of the internal memory. The IMS register can be set to
establish the same memory mapping as used in ROM products that have different internal memory (ROM and RAM)
configurations.
The IMS register is set using 8-bit memory operation instructions.
PD784035Y, µPD784036Y, µPD784037Y, or µPD784038Y).
Same as the PD784038Y
Same as the PD784037Y
Same as the PD784036Y
Same as the PD784035Y
Address
0FFFCH
Memory Size
µ
µ
µ
µ
After Reset
FFH
R/W
But the action is not affected if the write command to the IMS is executed to the mask ROM product.
W
20
µ
PD78P4038Y
6. PROM PROGRAMMING
The µPD78P4038Y has an on-chip 128-KB PROM device for use as program memory. When programming, set
the VPP and RESET pins for PROM programming mode. See (2) in Chapter 2 with regard to handling of other, unused
pins.
6.1 Operation Mode
PROM programming mode is selected when +5 V or +12.5 V is added to the V
to the RESET pin. This mode can be set to operation mode by setting the CE pin, OE pin, and PGM pin as shown
in Table 6-1 below.
In addition, the PROM contents can be read by setting read mode.
Set OE to H to set high impedance for data output and output disable mode.
µ
Consequently, if several
select data output from any of the devices.
(3) Standby mode
Set CE to H to set standby mode.
In this mode, data output is set to high impedance regardless of the OE setting.
(4) Page data latch mode
At the beginning of page write mode, set CE to H, PGM to H, and OE to L to set page data latch mode.
In this mode, 1 page (4 bytes) of data are latched to the internal address/data latch circuit.
(5) Page write mode
After latching the address and data for one page (4 bytes) using page data latch mode, adding a 0.1 ms program
pulse (active, low) to the PGM pin with both CE and OE set to H causes page write to be executed. Later, setting
both CE and OE to L causes program verification to be executed.
If programming is not completed after one program pulse, the write and verify operations may be repeated X times
(where X ≤ 10).
PD78P4038Y devices are connected to a data bus, the OE pins can be controlled to
(6) Byte write mode
Adding a 0.1 ms program pulse (active, low) to the PGM pin with both CE and OE set to H causes byte write
to be executed. Later, setting OE to L causes program verification to be executed.
If programming is not completed after one program pulse, the write and verify operations may be repeated X times
(where X ≤ 10).
(7) Program verify mode
Set CE to L, PGM to H, and OE to L to set program verify mode. Use verify mode for verification following each
write operation.
(8) Program inhibit mode
µ
Program inhibit mode is used to write to a single device when several
parallel to OE , VPP, and D0 to D7 pins.
Use the page write mode or byte write mode described above for each write operation. Write operations cannot
be done for devices in which the PGM pin has been set to H.
PD78P4038Y devices are connected in
22
6.2 PROM Write Sequence
Figure 6-1. Page Program Mode Flowchart
Start
Address = G
V
DD
= +6.5 V, V
Address = Address + 1
Address = Address + 1
X = 0
Latch
Latch
PP
= +12.5 V
µ
PD78P4038Y
Address = Address + 1
Address = Address + 1
0.1 ms program pulse
No
DD
= 4.5-5.5 V, V
V
Pass
Latch
Latch
X = X + 1
Verify 4 bytes
Pass
Address = N ?
Yes
PP
Verify all bytes
All pass
= V
No
X = 10 ?
Fail
DD
Fail
Yes
Remark G = Start address
N = Program end address
Write end
Defective
23
A2-A16
A0, A1
D0-D7
V
PP
V
DD
V
PP
V
DD
VDD+1.5
DD
V
Figure 6-2. Page Program Mode Timing
Page data latchPage programProgram verify
Data inputData output
µ
PD78P4038Y
CE
PGM
OE
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
24
Figure 6-3. Byte Program Mode Flowchart
Start
Address = G
DD
= +6.5 V, V
V
X
= 0
PP
= +12.5 V
µ
PD78P4038Y
Address = Address + 1
Remark G = Start address
N = Program end address
0.1 ms program pulse
No
Pass
Address = N ?
V
DD
= 4.5-5.5 V, V
Verify all bytes
= 10 ?
X
No
Yes
= X + 1
X
Verify
Fail
Pass
Yes
PP
= V
DD
Fail
All pass
Write endDefective
25
A0-A16
Figure 6-4. Byte Program Mode Timing
ProgramProgram verify
µ
PD78P4038Y
V
V
CE
PGM
OE
D0-D7
PP
DD
V
PP
V
DD
VDD+1.5
V
DD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Data inputData output
Cautions 1. Add V
2. Do not allow VPP to exceed +13.5 V including overshoot.
3. Reliability problems may result if the device is inserted or pulled out while +12.5 V is applied
26
DD before VPP, and turn off the VDD after VPP.
at VPP.
6.3 PROM Read Sequence
Follow this sequence to read the PROM contents to an external data bus (D0 to D7).
µ
PD78P4038Y
(1) Set the RESET pin to low level and add +5 V to the V
other, unused pins.
(2) Add +5 V to the VDD and VPP pins.
(3) Input the data address to be read to pins A0 to A16.
(4) Set read mode.
(5) Output the data to pins D0 to D7.
Figure 6-5 shows the timing of steps (2) to (5) above.
Figure 6-5. PROM Read Timing
A0-A16
CE (input)
OE (input)
Address input
PP pin. See (2) in Chapter 2 with regard to handling of
D0-D7
Hi-ZHi-Z
Data output
27
µ
PD78P4038Y
7. ERASURE CHARACTERISTICS (µPD78P4038YKK-T ONLY)
Data written in the µPD78P4038YKK-T program memory can be erased (FFH); therefore users can write other
data in the memory.
To erase the written data, expose the erasure window to light with a wavelength shorter than approx. 400 nm. Normally,
ultraviolet light with a wavelength of 254 nm is employed. The amount of light required to completely erase the data
is as follows:
2
• Intensity of ultraviolet light × erasing time: 57.6 W•s/cm
• Erasing time: About 80 minutes (When using a 12,000 µW/cm2 ultraviolet lamp. It may, however, take more time
due to lamp deterioration, dirt on the erasure window, or the like.)
The ultraviolet lamp should be placed within 2.5 cm from the erasure window during erasure. In addition, if a filter
is attached to the ultraviolet lamp, remove the filter before erasure.
min.
8. PROTECTIVE FILM COVERING THE ERASURE WINDOW (µPD78P4038YKK-T ONLY)
To prevent EPROM from being erased inadvertently by light other than that from the lamp used for erasing EPROM,
or to prevent the internal circuits other than EPROM from malfunctioning by light, stick a protective film on the erasure
window except when EPROM is to be erased.
9. QUALITY
The µPD78P4038YKK-T is not intended for use in mass-produced products; they do not have reliability high enough
for such purposes. Their use should be restricted to functional evaluation in experiment or trial manufacture.
10. SCREENING ONE-TIME PROM PRODUCTS
NEC cannot execute a complete test of one-time PROM products (µPD78P4038YGC-3B9, µPD78P4038YGC8BT, and µPD78P4038YGK-BE9) due to their structure before shipment. It is recommended that you screen (verify)
PROM products after writing necessary data into them and storing them at 125°C for 24 hours.
28
µ
PD78P4038Y
11. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
ParameterSymbolConditionsRatingUnit
Supply voltageVDD–0.5 to +7.0V
AVDDAVSS to VDD + 0.5V
AVSS–0.5 to +0.5V
Input voltageVI1–0.5 to VDD + 0.5V
VI2TEST/VPP pin and–0.5 to +13.5V
P21/INTP0/A9 pin in PROM
programming mode
Output voltageVO–0.5 to VDD + 0.5V
Output low currentIOLAt one pin15mA
Total of all output pins100mA
Output high currentIOHAt one pin–10mA
Total of all output pins–100mA
A/D converter reference inputAVREF1–0.5 to VDD + 0.3V
voltage
D/A converter reference input
voltage
Operating ambient temperatureTA–40 to +85°C
Storage temperatureTstg–65 to +150°C
AVREF2–0.5 to VDD + 0.3V
AVREF3–0.5 to VDD + 0.3V
Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the
product; if the rated value of any of the parameters in the above table is exceeded, even
momentarily, the quality of the product may deteriorate. Always use the product within its rated
values.
29
OPERATING CONDITIONS
• Operating ambient temperature (TA): –40 to +85°C
• Rise time and fall time (t
r, tf) (at pins which are not specified) : 0 to 200
• Power supply voltage and clock cycle time: See Figure 11-1.
Figure 11-1. Power Supply Voltage and Clock Cycle Time
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
Note 2
MIN.
2.2
-0.3
2.4
6.25
4.5
12.2
TYP.
6.5
5.0
12.5
VPP = VDDP
10
10
5
1.0
MAX.
VDDP + 0.3
0.8
±10
0.45
±10
6.75
5.5
12.8
40
40
50
100
Unit
V
V
µ
A
V
V
µ
A
V
V
V
V
mA
mA
mA
µ
A
Notes 1. Symbols for the corresponding µPD27C1001A
2. The V
DDP represents the VDD pin as viewed in the programming mode.
50
µ
PD78P4038Y
AC PROGRAMMING CHARACTERISTICS (T
PROM Write Mode (Page Program Mode)
Note 1
Parameter
Address setup time
CE set time
Input data setup time
Address hold time
Input data hold time
Output data hold time
VPP setup time
VDDP setup time
Initial program pulse width
OE set time
Valid data delay time from OE
OE pulse width in the data latch
PGM setup time
CE hold time
OE hold time
Symbol
tVDS
tPGMS
tAS
tCES
tDS
tAH
tAHL
tAHV
tDH
tDF
tVPS
Note 2
tPW
tOES
tOE
tLW
tCEH
tOEH
A = 25 ± 5°C, VSS = 0 V)
Conditions
MIN.
0.095
TYP.
2
2
2
2
2
0
2
0
2
2
0.1
2
1
1
2
2
2
MAX.
130
0.105
2
Unit
µ
µ
µ
µ
µ
µ
µ
ns
µ
µ
ms
µ
ns
µ
µ
µ
µ
s
s
s
s
s
s
s
s
s
s
s
s
s
s
Notes 1. These symbols (except tVDS) correspond to those of the corresponding µPD27C1001A.
µ
2. For
PD27C1001A, read tVDS as tVCS.
51
PROM Write Mode (Byte Program Mode)
Note 1
Parameter
Address setup time
CE set time
Input data setup time
Address hold time
Input data hold time
Output data hold time
VPP setup time
VDDP setup time
Initial program pulse width
OE set time
Valid data delay time from OE
Symbol
tVDS
tAS
tCES
tDS
tAH
tDH
tDF
tVPS
Note 2
tPW
tOES
tOE
ConditionsMAX.
MIN.
2
2
2
2
2
0
2
2
0.095
2
TYP.
0.1
1
Notes 1. These symbols (except tVDS) correspond to those of the corresponding µPD27C1001A.
2. For µPD27C1001A, read tVDS as tVCS.
µ
PD78P4038Y
Unit
µ
s
µ
s
µ
s
µ
s
µ
s
130
0.105
2
ns
µ
µ
ms
µ
ns
s
s
s
PROM Read Mode
Parameter
Data output time from address
Delay from CE ↓ to data output
Delay from OE ↓ to data output
Data hold time to OE↑ or CE ↑
Data hold time to address
Note 2
Symbol
tACC
tCE
tOE
tDF
tOH
Conditions
CE = OE = VIL
OE = VIL
CE = VIL
CE = VIL or OE = VIL
CE = OE = VIL
Note 1
Notes 1. These symbols correspond to those of the corresponding
2. tDF is the time measured from when either OE or CE reaches VIH, whichever is faster.
MIN.
0
0
µ
PD27C1001A.
TYP.
1
1
MAX.
200
2
2
60
Unit
ns
µ
µ
ns
ns
s
s
52
PROM Write Mode Timing (Page Program Mode)
Page data latchPage programProgram verify
A2-A16
t
V
V
DDP
CE
PGM
OE
AS
A0, A1
t
DS
D0-D7
PP
V
V
DDP
+ 1.5
V
Hi-ZHi-ZHi-Z
t
VPS
V
PP
DDP
t
VDS
DDP
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
LW
t
AHL
t
DH
Data input
t
PGMS
µ
PD78P4038Y
t
AHV
t
DF
Data
t
OE
output
t
CES
t
CEH
t
PW
t
OES
t
AH
t
OEH
53
PROM Write Mode Timing (Byte Program Mode)
ProgramProgram verify
A0-A16
t
AS
µ
PD78P4038Y
t
DF
D0-D7
V
PP
V
V
DDP
+ 1.5
V
DDP
V
CE
PGM
OE
Cautions 1. V
2. VPP including overshoot must not exceed +13.5 V.
3. Plugging in or out the board with the V
reliability.
Hi-ZHi-ZHi-Z
t
DS
PP
V
DDP
DDP
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
DDP must be applied before VPP, and must be cut after VPP.
t
t
t
t
VPS
VDS
CES
DS
Data input
t
PW
t
DH
t
OES
PP pin supplied with 12.5 V may adversely affect its
t
OE
Data output
t
AH
PROM Read Mode Timing
A0-A16
CE
OE
D0-D7
Notes 1. For reading within t
DF is the time measured from when either OE or CE reaches VIH, whichever is faster.
2. t
54
Valid address
t
CE
Note 2
t
Note 1
t
ACC
Hi-ZHi-Z
ACC, the delay of the OE input from falling edge of CE must be within tACC-tOE.
Note 1
t
OE
t
OH
Data output
DF
12. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x14)
µ
PD78P4038Y
A
B
61
60
41
40
CD
80
1
20
21
F
G
M
H
I
P
J
K
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
Each lead centerline is located within 0.06
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
K
C
D
W
G
F
Z
ITEMMILLIMETERSINCHES
A
B
C
D
F
G
H
I
J
K
Q
R
S
TR 2.0R 0.079
U
U12.10.083
W
Z0.100.004
14.0±0.2
13.6
13.6
14.0±0.2
1.84
3.6 MAX.
0.45±0.10
0.06
0.65 (T.P.)
1.0±0.15
C 0.3
0.825
0.825
9.0
0.75±0.15
M
IH
J
X80KW-65A-1
0.551±0.008
0.535
0.535
0.551±0.008
0.072
0.142 MAX.
+0.004
0.018
–0.005
0.003
0.024 (T.P.)
+0.007
0.039
–0.006
C 0.012
0.032
0.032
0.354
+0.006
0.030
–0.007
Q
80
1
S
R
58
µ
PD78P4038Y
13. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the µPD78P4038Y.
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting
Technology Manual (C10535E).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under
different conditions.
Table 13-1. Soldering Conditions for Surface-Mount Devices (1/2)
Peak package’s surface temperature: 235°C
Reflow time: 30 seconds or less (210°C or more)
Maximum allowable number of reflow processes: 2
Exposure limit: 7 days
afterward)
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be
baked before unpacking.
Peak package’s surface temperature: 215°C
Reflow time: 40 seconds or less (200°C or more)
Maximum allowable number of reflow processes: 2
Exposure limit: 7 days
afterward)
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be
baked before unpacking.
Terminal temperature: 300°C or less
Heat time: 3 seconds or less (for one side of a device)
Note
(10 hours of pre-baking is required at 125°C
Note
(10 hours of pre-baking is required at 125°C
Symbol
IR35-107-2
VP15-107-2
–
Note Maximum number of days during which the product can be stored at a temperature of 25°C and a relative
humidity of 65% or less after dry-pack package is opened.
Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
60
µ
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78P4038Y.
See also (5).
(1) Language processing software
RA78K4Assembler package for all 78K/IV Series models
CC78K4C compiler package for all 78K/IV Series models
DF784038Device file for µPD784038Y Subseries models
CC78K4-LC compiler library source file for all 78K/IV Series models
(2) PROM write tools
PG-1500PROM programmer
PA-78P4026GCProgrammer adaptor, connects to PG-1500
PA-78P4038GK
PA-78P4026KK
PG-1500 controllerControl program for PG-1500
PD78P4038Y
(3) Debugging tools
• When using the in-circuit emulator IE-78K4-NS
IE-78K4-NSIn-circuit emulator for all 78K/IV Series models
IE-70000-MC-PS-BPower supply unit for IE-78K4-NS
IE-70000-98-IF-CInterface adapter when the PC-9800 series computer (other than a notebook)
is used as the host machine
IE-70000-CD-IFPC card and interface cable when a PC-9800 series notebook is used as the
host machine
IE-70000-PC-IF-CInterface adapter when the IBM PC/ATTM or compatible is used as the host
machine
IE-784038-NS-EM1
NP-80GCEmulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types)
NP-80GK
EV-9200GC-80Socket for mounting on target system board made for 80-pin plastic QFP
TGK-080SDWAdapter for mounting on target system board made for 80-pin plastic TQFP
EV-9900Tool used to remove the µPD78P4038YKK-T from the EV-9200GC-80
ID78K4-NSIntegrated debugger for IE-78K4-NS
SM78K4-NSSystem simulator for all 78K/IV Series models
DF784038Device file for µPD784038Y Subseries models
Note
Note
Emulation board for evaluating µPD784038Y Subseries models
Emulation probe for 80-pin plastic TQFP (GK-BE9 type)
(GC-3B9 and GC-8BT types)
(fine pitch) (GK-BE9 type)
Note Under development
61
µ
PD78P4038Y
• When using the in-circuit emulator IE-784000-R
IE-784000-RIn-circuit emulator for all 78K/IV Series models
IE-70000-98-IF-BInterface adapter when the PC-9800 series computer (other than a notebook)
IE-70000-98-IF-Cis used as the host machine
IE-70000-98N-IFInterface adapter and cable when a PC-9800 series notebook is used as the
host machine
IE-70000-PC-IF-BInterface adapter when the IBM PC/AT or compatible is used as the host
IE-70000-PC-IF-Cmachine
IE-78000-R-SV3Interface adapter and cable when the EWS is used as the host machine
Note
Note
Emulation board for evaluating µPD784038Y Subseries models
Conversion board for 80 pins to use the IE-784038-NS-EM1 on the
IE-784000-R. The board is not needed when the conventional product
IE-784038-R-EM1 is used.
µ
PD784038Y Subseries
(GC-3B9 and GC-8BT types)
(fine pitch) (GK-BE9 type)
IE-784038-NS-EM1
IE-784038-R-EM1
IE-78400-R-EMEmulation board for all 78K/IV Series models
IE-78K4-R-EX2
EP-78230GC-REmulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types)
EP-78054GK-REmulation probe for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) for all
EV-9200GC-80Socket for mounting on target system board made for 80-pin plastic QFP
TGK-080SDWAdapter for mounting on target system board made for 80-pin plastic TQFP
EV-9900Tool used to remove the µPD78P4038YKK-T from the EV-9200GC-80
ID78K4Integrated debugger for IE-784000-R
SM78K4System simulator for all 78K/IV Series models
DF784038Device file for µPD784038Y Subseries models
Note Under development
(4) Real-time OS
RX78K/IVReal-time OS for 78K/IV Series models
MX78K4OS for 78K/IV Series models
62
µ
PD78P4038Y
(5) Notes when using development tools
• The ID78K-NS, ID78K4, and SM78K4 can be used in combination with the DF784038.
• The CC78K4 and RX78K/IV can be used in combination with the RA78K4 and DF784038.
• The NP-80GC is a product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult the NEC sales
representative for purchasing.
• The TGK-080SDW is a product from TOKYO ELETECH CORPORATION.
Refer to: Daimaru Kogyo, Ltd.
Tokyo Electronic Components Division (03-3820-7112)
Osaka Electronic Components Division (06-244-6672)
• The host machines and operating systems corresponding to each software are shown below.
PC-9800 Series [WindowsTM]HP9000 Series 700TM [HP-UXTM]
IBM PC/AT and Compatibles [Windows]
Note
Note
Note
Note
Note
SPARCstationTM [SunOSTM]
–
Note Software under MS-DOS
63
µ
PD78P4038Y
APPENDIX B
CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER (TGK-080SDW)
(1) Conversion socket (EV-9200GC-80) package drawings and recommended pattern to mount the socket
Connect the µPD78P4038YKK-T (80-pin ceramic WQFN (14 × 14 mm)) and EP-78230GC-R to the circuit board
in combination with the EV-9200GC-80.
Figure B-1. Package Drawings of EV-9200GC-80 (Reference) (unit: mm)
Based on EV-9200GC-80
(1) Package drawing (in mm)
E
D
C
No.1 pin index
A
B
EV-9200GC-80
1
F
M
NO
R
J
S
L
K
Q
P
64
G
H
I
EV-9200GC-80-G0E
ITEMMILLIMETERSINCHES
A
B
C
D
E
F
G
H
I
J
K
L
M
O
N
P
Q
R
S
18.0
14.4
14.4
18.0
4-C 2.0
0.8
6.0
16.0
18.7
6.0
16.0
18.7
8.2
8.0
2.5
2.0
0.35
φ
2.3
1.5
0.709
0.567
0.567
0.709
4-C 0.079
0.031
0.236
0.63
0.736
0.236
0.63
0.736
0.323
0.315
0.098
0.079
0.014
φ
0.091
0.059
µ
PD78P4038Y
Figure B-2. Recommended Pattern to Mount EV-9200GC-80 on a Substrate (Reference) (unit: mm)
Based on EV-9200GC-80
(2) Pad drawing (in mm)
G
J
K
F
E
D
L
C
B
A
HI
EV-9200GC-80-P1E
ITEMMILLIMETERSINCHES
+0.001
–0.002
+0.001
–0.002
0.776
0.591
0.591
0.776
0.236
0.236
0.014
φ
0.093
φ
0.091
φ
0.062
+0.003
–0.002
+0.003
–0.002
+0.001
–0.001
+0.001
–0.002
+0.001
–0.002
A
B
C
D
E
F
G
H
I
J
K
L
Caution
19.7
15.0
0.65±0.02 × 19=12.35±0.05
0.65±0.02 × 19=12.35±0.05
15.0
19.7
6.0±0.05
6.0±0.05
0.35±0.02
φ
2.36±0.03
φ
2.3
φ
1.57±0.03
Dimensions of mount pad for EV-9200 and that for target
0.026 × 0.748=0.486
0.026 0.748=0.486
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING
TECHNOLOGY MANUAL" (C10535E).
PD784038Y Sub-Series Special Function Registers–U11090J
78K/IV Series User's Manual, InstructionU10905EU10905J
78K/IV Series Instruction Summary Sheet–U10594J
78K/IV Series Instruction Set–U10595J
78K/IV Series Application Note, Software Basic–U10095J
Documents Related to Development Tools (User's Manual)
Document NameDocument No.
EnglishJapanese
RA78K4 Assembler PackageOperationU11334EU11334J
LanguageU11162EU11162J
RA78K Series Structured Assembler PreprocessorU11743EU11743J
CC78K4 SeriesOperationU11572EU11572J
LanguageU11571EU11571J
CC78K Series Library Source FileU12322EU12322J
PG-1500 PROM ProgrammerU11940EU11940J
PG-1500 Controller PC-9800 Series (MS-DOSTM) BaseEEU-1291EEU-704
PG-1500 Controller IBM PC Series (PC DOSTM) BaseU10540EEEU-5008
IE-78K4-NSTo be releasedU13356J
soon
IE-784000-REEU-1534U12903J
IE-784038-NS-EM1PlannedPlanned
IE-784038-R-EM1U11383EU11383J
EP-78230EEU-1515EEU-985
EP-78054GK-REEU-1468EEU-932
SM78K4 System Simulator Windows BaseReferenceU10093EU10093J
SM78K Series System Simulator
ID78K4-NS Integrated DebuggerReferenceU12796EU12796J
ID78K4 Integrated Debugger Windows BaseReferenceU10440EU10440J
ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base
External Parts User Open
Interface Specifications
ReferenceU11960EU11960J
U10092EU10092J
Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.
67
µ
PD78P4038Y
Documents Related to Software to Be Incorporated into the Product (User’s Manual)
Document NameDocument No.
EnglishJapanese
78K/IV Series Real-Time OSBasicU10603EU10603J
InstallationU10604EU10604J
Debugger–U10364J
OS for 78K/IV Series MX78K4Basic–U11779J
Other Documents
Document NameDocument No.
EnglishJapanese
IC PACKAGE MANUALC10943X
Semiconductor Device Mounting Technology ManualC10535EC10535J
Quality Grades on NEC Semiconductor DeviceC11531EC11531J
NEC Semiconductor Device Reliability/Quality Control SystemC10983EC10983J
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Semiconductor Device Quality Control/Reliability Handbook–C12769J
Guide for Products Related to Microcomputer: Other Companies–U11416J
C11892EC11892J
Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.
68
µ
PD78P4038Y
NOTES FOR CMOS DEVICES
1PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to
be taken for PW boards with semiconductor devices on it.
2HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
69
µ
PD78P4038Y
Caution This product contains an I2C bus interface circuit.
When using the I
2
C bus interface, notify its use to NEC when ordering custom code. NEC can
guarantee the following only when the customer informs NEC of the use of the interface:
Purchase of NEC I
these components in an I
2
C components conveys a license under the Philips I2C Patent Rights to use
2
C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
IEBus and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are registered trademarks or trademarks of Microsoft Corporation in the United States
and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.
70
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829
J98. 2
µ
PD78P4038Y
71
µ
PD78P4038Y
Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated
in this document.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed:µPD78P4038YKK-T
The customer must judge the need for license:µPD78P4038YGC-3B9, µPD78P4038YGC-×××-3B9,
µ
PD78P4038YGC-8BT
µ
PD78P4038YGK-BE9, µPD78P4038YGK-×××-BE9
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
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