NEC UPD78P4038Y DATA SHEET

查询UPD78P4038Y供应商

16/8-BIT SINGLE-CHIP MICROCONTROLLER

The µPD78P4038Y, 78K/IV Series' product, is a one-time PROM or EPROM version of the µPD784035Y,

µ

PD784036Y, µPD784037Y, and µPD784038Y with internal masked ROM.

Since user programs can be written to PROM, this microcontroller is best suited for evaluation in system

development, manufacture of small quantities of multiple products, and fast start-up of applications.

For specific functions and other detailed information, consult the following user's manual.
This manual is required reading for design work.

µ

PD784038, 784038Y Sub-Series User's Manual, Hardware : U11316E

78K/IV Series User's Manual, Instruction : U10905E

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD78P4038Y

FEATURES

• Compatible with the

µ

PD78P238, µPD78P4026, and µPD78P4038

• Internal PROM: 128 Kbytes

•

µ

PD78P4038YKK-T : EPROM (best suited for system evaluation)

•

µ

PD78P4038YGC-3B9 : PROM (best suited for manufacture of small quantities)

µ

PD78P4038YGC-8BT: PROM (best suited for manufacture of small quantities)

µ

PD78P4038YGK-BE9: PROM (best suited for manufacture of small quantities)

• Internal RAM: 4,352 bytes

• Supply voltage: VDD = 2.7 to 5.5 V

• QTOP

ORDERING INFORMATION

TM

microcomputer

Remark The QTOP microcomputer is a microcomputer with a built-in one-time PROM that is totally supported

by NEC. The support includes writing application programs, marking, screening, and verification.

Part number Package Internal ROM

µ

PD78P4038YGC-3B9 80-pin plastic QFP (14 × 14 × 2.7 mm) One-time PROM

µ

PD78P4038YGC-8BT 80-pin plastic QFP (14 × 14 × 1.4 mm) One-time PROM

µ

PD78P4038YGC-×××-3B9 80-pin plastic QFP (14 × 14 mm) One-time PROM

µ

PD78P4038YGK-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm) One-time PROM

µ

PD78P4038YGK-×××-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm) One-time PROM

µ

PD78P4038YKK-T 80-pin ceramic WQFN (14 × 14 mm) EPROM

(QTOP microcomputer)

(QTOP microcomputer)

In this reference, all ROM components that are common to one-time PROM and EPROM are referred to as

PROM.

The information in this document is subject to change without notice.

Document No. U10742EJ2V0DS00 (2nd edition)
Date Published July 1998 J CP(K)
Printed in Japan

The mark shows major revised points.

©

1995

µ

PD78P4038Y

QUALITY GRADE

Part number Package Quality grade

µ

PD78P4038YGC-3B9 80-pin plastic QFP (14 × 14 × 2.7 mm) Standard (for general electronic equipment)

µ

PD78P4038YGC-8BT 80-pin plastic QFP (14 × 14 × 1.4 mm) Standard (for general electronic equipment)

µ

PD78P4038YGC-×××-3B9 80-pin plastic QFP (14 × 14 × 1.4 mm) Standard (for general electronic equipment)

µ

PD78P4038YGK-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Standard (for general electronic equipment)

µ

PD78P4038YGK-×××-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Standard (for general electronic equipment)

µ

PD78P4038YKK-T 80-pin ceramic WQFN (14 × 14 mm) Not applied (for function evaluation)

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation
to know the specification of quality grade on the devices and its recommended applications.

Caution The EPROM versions of the µPD78P4038Y are not intended for use in mass-produced products;

they do not have reliability high enough for such purposes. Their use should be restricted to
functional evaluation in experiment or trial manufacture.

Remark ××× is ROM code suffix.

2

78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM

: Product under mass production

: Product under preparation

Standard Products Development

µ

PD78P4038Y

µ

PD784026

A/D converters,
16-bit timers, and
power management
functions have been
enhanced.

ASSP Development

µ

PD784955

DC inverter control

Connectable to the I

µ

PD784038Y

µ

PD784038

Internal memory has been expanded.
Pin-compatible with the PD784026

Connectable to the multimaster I

PD784216Y

µ
µ

PD784216

100 pins
I/O has been enhanced.
Internal memory has been expanded.

µ

PD784054

µ

PD784046

Built-in 10-bit A/D converter

2

C bus

µ

2

C bus

Connectable to the multimaster I

µ

PD784225Y

µ

PD784225

80 pins
ROM correction function has been added.

Connectable to the multimaster I

µ

PD784218Y

µ

PD784218

Internal memory has been expanded.
ROM correction function has been added.

2

C bus

2

C bus

µ

PD784908

Built-in IEBus

µ

PD784915

Software servo control
Built-in analog circuit for VCR
Timers have been enhanced.

TM

controller

µ

PD784937

Functions of the PD784908 have been enhanced.
Internal memory has been expanded.
ROM correction function has been added.

Connectable to the multimaster I

µ

PD784928Y

µ

PD784928

Functions of the PD784915 have been enhanced.

µ

2

C bus

µ

3

FUNCTIONS

µ

PD78P4038Y

(1/2)

Item

Number of basic instructions
(mnemonics)

General-purpose register
Minimum instruction

execution time
Internal

memory

Memory space
I/O ports

Additional
function

Note

pins

Real-time output ports
Timer/counter

PWM outputs
Serial interface

A/D converter
D/A converter

PROM
RAM

Total
Input
Input/output
Pins with pull-

up resistor
LED direct

drive outputs
Transistor

direct drive

Functions

113

8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping)
125 ns/250 ns/500 ns/1,000 ns (at 32 MHz)

128 Kbytes (Can be changed to 48 K, 64 K, or 96 Kbytes by software)
4,352 bytes (Can be changed to 2,048 or 3,584 bytes by software)
Program and data: 1 Mbyte
64
8
56
54

24

8

4 bits × 2, or 8 bits × 1
Timer/counter 0: Timer register × 1 Pulse output capability

Capture register × 1 • Toggle output
Compare register × 2 • PWM/PPG output

• One-shot pulse output

Timer/counter 1: Timer register × 1 Pulse output capability

Capture register × 1 • Real-time output (4 bits × 2)
Capture/compare register × 1
Compare register × 1

Timer/counter 2: Timer register × 1 Pulse output capability

Capture register × 1 • Toggle output
Capture/compare register × 1 • PWM/PPG output
Compare register × 1

Timer 3 : Timer register × 1

Compare register × 1
12-bit resolution × 2 channels
UART/IOE (3-wire serial I/O): 2 channels (incorporating baud rate generator)

CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus): 1 channel
8-bit resolution × 8 channels
8-bit resolution × 2 channels

Note Additional function pins are included in the I/O pins.

4

µ

PD78P4038Y

(2/2)

Item
Clock output
Watchdog timer
Standby
Interrupt

Supply voltage
Package

Hardware source
Software source
Nonmaskable
Maskable

Functions
Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port)
1 channel
HALT/STOP/IDLE mode
24 (17 internal, 7 external (sampling clock variable input: 1))
BRK instruction, BRKCS instruction, operand error
1 internal, 1 external
16 internal, 6 external

• 4-level programmable priority

• 3 operation statuses: vectored interrupt, macro service, context switching

VDD = 2.7 to 5.5 V
80-pin plastic QFP (14 × 14 × 2.7 mm)

80-pin plastic QFP (14 × 14 × 1.4 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin ceramic WQFN (14 × 14 mm)

5

µ

PD78P4038Y

CONTENTS

1. DIFFERENCES BETWEEN µPD78P4038Y AND MASKED ROM PRODUCTS .................... 7

2. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 8

3. BLOCK DIAGRAM ..................................................................................................................... 11

4. LIST OF PIN FUNCTIONS......................................................................................................... 12

4.1 Pins for Normal Operating Mode................................................................................................. 1 2

4.2 Pins for PROM Programming Mode (V

4.2.1 Pin functions .................................................................................................................. 15

4.2.2 Pin functions .................................................................................................................. 16

4.3 I/O Circuits for Pins and Handling of Unused Pins.................................................................. 17

PP ≥ +5 V or +12.5 V, RESET = L) .............................. 15

5. INTERNAL MEMORY SWITCHING (IMS) REGISTER ............................................................ 20

6. PROM PROGRAMMING ............................................................................................................ 21

6.1 Operation Mode .............................................................................................................................. 21

6.2 PROM Write Sequence.................................................................................................................. 23

6.3 PROM Read Sequence .................................................................................................................. 27

7. ERASURE CHARACTERISTICS (µPD78P4038YKK-T ONLY) ............................................... 28

8. PROTECTIVE FILM COVERING THE ERASURE WINDOW (µPD78P4038YKK-T ONLY) .. 28

9. QUALITY..................................................................................................................................... 28

10. SCREENING ONE-TIME PROM PRODUCTS .......................................................................... 28

11. ELECTRICAL CHARACTERISTICS ......................................................................................... 29

12. PACKAGE DRAWINGS ............................................................................................................. 55

13. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 59

APPENDIX A DEVELOPMENT TOOLS .......................................................................................... 61

APPENDIX B CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER

(TGK-080SDW) .......................................................................................................... 64

APPENDIX C RELATED DOCUMENTS.......................................................................................... 67

6

µ

PD78P4038Y

1. DIFFERENCES BETWEEN µPD78P4038Y AND MASKED ROM PRODUCTS

The µPD78P4038Y is produced by replacing the masked ROM in the µPD784035Y, µPD784036Y, µPD784037Y,
or µPD784038Y with PROM to which data can be written. The functions of the µPD78P4038Y are the same as those
of the µPD784035Y, µPD784036Y, µPD784037Y, or µPD784038Y except for the PROM specification such as writing
and verification, except that the PROM size can be changed to 48 K, 64 K, or 96 Kbytes, and except that the internal
RAM size can be changed to 2,048 or 3,584 bytes.

Table 1-1 shows the differences between these products.

µ

Table 1-1. Differences between the

PD78P4038Y and Masked ROM Products

Product Name

Item
Internal program

memory

Internal RAM

Package

µ

PD78P4038Y

• 128-Kbyte
PROM

• Can be changed
to 48 K, 64 K, or
96 Kbytes by
IMS

• 4,352-byte
internal RAM

• Can be changed
to 2,048 or 3,584
bytes by IMS

• 80-pin plastic QFP (14 × 14 × 2.7 mm)

• 80-pin plastic QFP (14 × 14 × 1.4 mm)

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

80-pin ceramic
WQFN
(14 × 14 mm)

µ

PD784035Y

• 48-Kbyte
masked ROM

• 2,048-byte internal RAM

µ

• 64-Kbyte

masked ROM

PD784036Y

µ

PD784037Y

• 96-Kbyte
masked ROM

• 3,584-byte
internal RAM

µ

PD784038Y

• 128-Kbyte
masked ROM

• 4,352-byte
internal RAM

7

2. PIN CONFIGURATION (TOP VIEW)

(1) Normal operating mode

• 80-pin plastic QFP (14 × 14 × 2.7 mm)

µ

PD78P4038YGC-3B9, µPD78P4038YGC-×××-3B9

• 80-pin plastic QFP (14 × 14 × 1.4 mm)

µ

PD78P4038YGC-8BT

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

µ

PD78P4038YGK-BE9, µPD78P4038YGK-×××-BE9

• 80-pin ceramic WQFN (14 × 14 mm)

µ

PD78P4038YKK-T

µ

PD78P4038Y

P32/SCK0/SCL

P33/SO0/SDA

P34/ TO0
P35/TO1
P36/TO2
P37/TO3

RESET

V

DD1

X2
X1

SS1

V
P00
P01
P02
P03
P04
P05
P06
P07

P67/REFRQ/HLDAK

REF3AVREF2

P31/ TxD/SO1

P30/RxD/SI1

P27/SI0

P26/INTP5

P25/INTP4/ASCK/SCK1

P24/INTP3

P23/INTP2/CI

P22/INTP1

P21/INTP0

P20/NMI

AV

ANO1

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

ANO0

AVSSAV

REF1AVDD

P77/ANI7

P76/ANI6

P75/ANI5

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0

DD0

V
P17
P16
P15

X

D2/SO2

P14/T

X

D2/SI2

P13/R
P12/ASCK2/SCK2
P11/PWM1
P10/PWM0

Note

TEST
V

SS0

ASTB/CLKOUT
P40/AD0
P41/AD1
P42/AD2

P51/A9

P64/RD

P65/ WR

P63/A19

P66/ WAIT/HLDRQ

P62/A18

P61/A17

P60/A16

P57/A15

P56/A14

P55/A13

P54/A12

P53/A11

P52/A10

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

Note Connect the TEST pin to VSS0 directly.

8

µ

PD78P4038Y

A8-A19 : Address bus
AD0-AD7 : Address/data bus
ANI0-ANI7 : Analog input
ANO0, ANO1 : Analog output
ASCK, ASCK2 : Asynchronous serial clock
ASTB : Address strobe

DD : Analog power supply

AV
AVREF1-AVREF3 : Reference voltage

SS : Analog ground

AV
CI : Clock input
CLKOUT : Clock output
HLDAK : Hold acknowledge
HLDRQ : Hold request
INTP0-INTP5 : Interrupt from peripherals
NMI : Non-maskable interrupt
P00-P07 : Port 0
P10-P17 : Port 1
P20-P27 : Port 2
P30-P37 : Port 3
P40-P47 : Port 4
P50-P57 : Port 5

P60-P67 : Port 6
P70-P77 : Port 7
PWM0, PWM1 : Pulse width modulation output
RD : Read strobe
REFRQ : Refresh request
RESET : Reset
RxD, RxD2 : Receive data
SCK0-SCK2 : Serial clock
SCL : Serial clock
SDA : Serial data
SI0-SI2 : Serial input
SO0-SO2 : Serial output
TEST : Test
TO0-TO3 : Timer output
TxD, TxD2 : Transmit data

DD0, VDD1 : Power supply

V
VSS0, VSS1 : Ground
WAIT : Wait
WR : Write strobe
X1, X2 : Crystal

9

(2) PROM programming mode

• 80-pin plastic QFP (14 × 14 × 2.7 mm)

µ

PD78P4038YGC-3B9, µPD78P4038YGC-×××-3B9

• 80-pin plastic QFP (14 × 14 × 1.4 mm)

µ

PD78P4038YGC-8BT

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

µ

PD78P4038YGK-BE9, µPD78P4038YGK-×××-BE9

• 80-pin ceramic WQFN (14 × 14 mm)

µ

PD78P4038YKK-T

Open

VSS

A9

µ

PD78P4038Y

SS

V

Open

VSS

DD

Open

V

(L)

Open

RESET

V

Open

(L)

VSS

D0
D1
D2
D3
D4
D5
D6
D7
(L)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1
2
3
4
5
6
7

DD

8

9
10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

PGM

CE

OE

(L)

A15

A14

A13

A12

A11

A8A7A6A5A4

A10

A16

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

A3

Open

VDD
(L)

Open

PP

V
VSS
Open
A0
A1
A2

Caution L : Connect these pins separately to the V

SS pins through 10-kΩ pull-down resistors.

VSS : To be connected to the ground.
Open : Nothing should be connected on these pins.
RESET: Set a low-level input.

A0-A16 : Address bus RESET : Reset
CE : Chip enable V

DD : Power supply

D0-D7 : Data bus VPP : Programming power supply
OE : Output enable V

SS : Ground

PGM : Program

10

3. BLOCK DIAGRAM

NMI

INTP0-INTP5

INTP3

TO0
TO1

Programmable
interrupt
controller

Timer/counter 0

(16 bits)

UART/IOE2

Baud-rate
generator

UART/IOE1

Baud-rate
generator

µ

PD78P4038Y

X

D/SI1

R
T

X

D/SO1

ASCK/SCK1

X

D2/SI2

R

X

D2/SO2

T
ASCK2/SCK2

INTP0

INTP1

INTP2/CI

TO2
TO3

P00-P03
P04-P07

PWM0
PWM1

ANO0
ANO1

AV

REF2

AV

REF3

Timer/counter 1

(16 bits)

Timer/counter 2

(16 bits)

Timer 3

(16 bits)

Real-time
output port

PWM

D/A
converter

78 K/IV

CPU core

(RAM 512 bytes)

RAM

(3,840 bytes)

PROM

(128 Kbytes)

Clocked
serial
interface

Clock output

Bus
interface

Port 0

Port 1

Port 2

Port 3

Port 4

SCK0/SCL
SO0/SDA
SI0

ASTB/CLKOUT
AD0-AD7

A8-A15
A16-A19

RD
WR
WAIT/HLDRQ
REFRQ/HLDAK

Note

D0-D7

Note

A0-A16

Note

CE

Note

OE

Note

PGM
P00-P07

P10-P17

P20-P27

P30-P37

P40-P47

ANI0-ANI7

AV

AV

REF1

AV

INTP5

Port 5

DD

Port 6

P50-P57

P60-P67

A/D

SS

converter

Watchdog
timer

Port 7

System
control

P70-P77

RESET
TEST
X1
X2

Note

PP

V
V

DD0

, V

DD1

V

SS0

, V

SS1

Note In the PROM programming mode.

11

4. LIST OF PIN FUNCTIONS

4.1 Pins for Normal Operating Mode

(1) Port pins (1/2)

µ

PD78P4038Y

Pin

P00-P07

P10
P11
P12
P13
P14
P15-P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34-P37
P40-P47

I/O
I/O

I/O

Input

I/O

I/O

Alternate-Function

–

PWM0
PWM1
ASCK2/SCK2
RXD2/SI2
TXD2/SO2

–
NMI
INTP0
INTP1
INTP2/CI
INTP3
INTP4/ASCK/SCK1
INTP5
SI0
RXD/SI1
TXD/SO1
SCK0/SCL
SO0/SDA
TO0-TO3
AD0-AD7

Function

Port 0 (P0):

• 8-bit I/O port.

• Functions as a real-time output port (4 bits × 2).

• Inputs and outputs can be specified bit by bit.

• The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

• Can drive a transistor.
Port 1 (P1):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

• Can drive LED.

Port 2 (P2):

• 8-bit input-only port.

• P20 does not function as a general-purpose port (nonmaskable

interrupt). However, the input level can be checked by an interrupt
service routine.

• The use of the pull-up resistors can be specified by software for pins
P22 to P27 (in units of 6 bits).

• The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by
CSIM1.

Port 3 (P3):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Port 4 (P4):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

• Can drive LED.

12

(1) Port pins (2/2)

µ

PD78P4038Y

Pin

P50-P57

P60-P63
P64
P65
P66
P67
P70-P77

I/O
I/O

I/O

I/O

Alternate-Function

A8-A15

A16-A19
RD
WR
WAIT/HLDRQ
REFRQ/HLDAK
ANI0-ANI7

Function

Port 5 (P5):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

• Can drive LED.
Port 6 (P6):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

• The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Port 7 (P7):

• 8-bit I/O port.

• Inputs and outputs can be specified bit by bit.

13

(2) Non-port pins (1/2)

µ

PD78P4038Y

Pin
TO0-TO3
CI
RXD
RXD2
TXD
TXD2
ASCK
ASCK2
SDA
SI0
SI1
SI2
SO0
SO1
SO2
SCK0
SCK1
SCK2
SCL
NMI
INTP0

INTP1

INTP2

INTP3

INTP4
INTP5
AD0-AD7
A8-A15
A16-A19
RD
WR
WAIT
REFRQ
HLDRQ
HLDAK
ASTB

CLKOUT

I/O

Output

Input
Input

Output

Input

I/O

Input

Output

I/O

Input

I/O
Output
Output
Output
Output

Input

Output

Input
Output
Output

Output

Alternate-Function
P34-P37
P23/INTP2
P30/SI1
P13/SI2
P31/SO1
P14/SO2
P25/INTP4/SCK1
P12/SCK2
P33/SO0
P27
P30/RXD
P13/RXD2
P33/SDA
P31/TXD
P14/TXD2
P32/SCL
P25/INTP4/ASCK
P12/ASCK2
P32/SCK0
P20
P21

P22

P23/CI

P24

P25/ASCK/SCK1
P26
P40-P47
P50-P57
P60-P63
P64
P65
P66/HLDRQ
P67/HLDAK
P66/WAIT
P67/REFRQ
CLKOUT

ASTB

Function
Timer output
Input of a count clock for timer/counter 2
Serial data input (UART0)
Serial data input (UART2)
Serial data output (UART0)
Serial data output (UART2)
Baud rate clock input (UART0)
Baud rate clock input (UART2)
Serial data I/O (2-wire serial I/O, I2C bus)
Serial data input (3-wire serial I/O0)
Serial data input (3-wire serial I/O1)
Serial data input (3-wire serial I/O2)
Serial data output (3-wire serial I/O0)
Serial data output (3-wire serial I/O1)
Serial data output (3-wire serial I/O2)
Serial clock I/O (3-wire serial I/O0)
Serial clock I/O (3-wire serial I/O1)
Serial clock I/O (3-wire serial I/O2)
Serial clock I/O (2-wire serial I/O, I2C bus)
External interrupt request –

• Input of a count clock for timer/counter 1

• Capture/trigger signal for CR11 or CR12

• Input of a count clock for timer/counter 2

• Capture/trigger signal for CR22

• Input of a count clock for timer/counter 2

• Capture/trigger signal for CR21

• Input of a count clock for timer/counter 0

• Capture/trigger signal for CR02

–

Input of a conversion start trigger for A/D converter
Time multiplexing address/data bus (for connecting external memory)
High-order address bus (for connecting external memory)
High-order address bus during address expansion (for connecting external memory)
Strobe signal output for reading the contents of external memory
Strobe signal output for writing on external memory
Wait signal insertion
Refresh pulse output to external pseudo static memory
Input of bus hold request
Output of bus hold response
Latch timing output of time multiplexing address (A0-A7) (for connecting

external memory)
Clock output

14

(2) Non-port pins (2/2)

µ

PD78P4038Y

Pin
RESET
X1
X2
ANI0-ANI7
ANO0, ANO1
AVREF1
AVREF2, AVREF3
AVDD
AVSS

Note 1

VDD0

Note 1

VDD1

Note 2

VSS0

Note 2

VSS1
TEST

I/O
Input
Input

–

Input

Output

–

Alternate-Function

–
–

P70-P77

–
–

Chip reset
Crystal input for system clock oscillation (A clock pulse can also be input

to the X1 pin.)
Analog voltage inputs for the A/D converter

Analog voltage inputs for the D/A converter
Application of A/D converter reference voltage
Application of D/A converter reference voltage
Positive power supply for the A/D converter
Ground for the A/D converter
Positive power supply of the port part
Positive power supply except for the port part
Ground of the port part
Ground except for the port part
Directly connect to VSS0. (The TEST pin is for the IC test.)

Notes 1. The potential of the VDD0 pin must be equal to that of the VDD1 pin.

2. The potential of the VSS0 pin must be equal to that of the VSS1 pin.

Function

4.2 Pins for PROM Programming Mode (V

4.2.1 Pin functions

Pin Name

VPP

RESET
A0-A16
D0-D7
CE
OE
PGM
VDD
VSS

I/O

–

Input

I/O

Input

–
–

PROM programming mode selection
High voltage input during program write or verification

PROM programming mode selection
Address bus
Data bus
PROM enable input/program pulse input
Read strobe input to PROM
Program/program inhibit input during PROM programming mode
Positive power supply
GND

PP ≥ +5 V or +12.5 V, RESET = L)

Function

15

µ

PD78P4038Y

4.2.2 Pin functions

PP (Programming power supply): Input

(1) V

Input pin for setting the µPD78P4038Y to the PROM programming mode. When the input voltage on this pin
is +5 V or more and when RESET input goes low, the µPD78P4038Y enters the PROM programming mode.
When CE is made low for V
PROM cell selected by A0 to A16.

(2) RESET (Reset): Input

Input pin for setting the
when the input voltage on the VPP pin goes +5 V or more, the µPD78P4038Y enters the PROM programming
mode.

(3) A0 to A16 (Address bus): Input

Address bus that selects an internal PROM address (0000H to 1FFFFH)

(4) D0 to D7 (Data bus): I/O

Data bus through which a program is written on or read from internal PROM

PP = +12.5 V and OE = high, program data on D0 to D7 can be written into the internal

µ

PD78P4038Y to the PROM programming mode. When input on this pin is low, and

(5) CE (Chip enable): Input

This pin inputs the enable signal from internal PROM. When this signal is active, a program can be written or
read.

(6) OE (Output enable): Input

This pin inputs the read strobe signal to internal PROM. When this signal is made active for CE = low, a one­byte program in the internal PROM cell selected by A0 to A16 can be read onto D0 to D7.

(7) PGM (Program): Input

The input pin for the operation mode control signal of the internal PROM.
Upon activation, writing to the internal PROM is enabled.
Upon inactivation, reading from the internal PROM is enabled.

DD

(8) V

Positive power supply pin

SS

(9) V

Ground potential pin

16

4.3 I/O Circuits for Pins and Handling of Unused Pins

Table 4-1 describes the types of I/O circuits for pins and the handling of unused pins.
Figure 4-1 shows the configuration of these various types of I/O circuits.

Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)

µ

PD78P4038Y

Pin

P00-P07
P10/PWM0

P11/PWM1
P12/ASCK2/SCK2
P13/RXD2/SI2
P14/TXD2/SO2
P15-P17
P20/NMI
P21/INTP0
P22/INTP1
P23/INTP2/CI
P24/INTP3
P25/INTP4/ASCK/SCK1

P26/INTP5
P27/SI0
P30/RXD/SI1
P31/TXD/SO1
P32/SCK0/SCL
P33/SO0/SDA
P34/TO0-P37/TO3
P40/AD0-P47/AD7
P50/A8-P57/A15
P60/A16-P63/A19
P64/RD
P65/WR
P66/WAIT/HLDRQ
P67/REFRQ/HLDAK
P70/ANI0-P77/ANI7

ANO0, ANO1
ASTB/CLKOUT

I/O Circuit Type

5-H

8-C
5-H

2

2-C

8-C

2-C

5-H

10-B

5-H

20-A

12
4-B

I/O
I/O

Input

I/O

Input

I/O

I/O

Output

Recommended Connection Method for Unused Pins

Input state: To be connected to VDD0
Output state: To be left open

To be connected to VDD0 or VSS0

To be connected to VDD0

Input state: To be connected to VDD0
Output state: To be left open

To be connected to VDD0

Input state: To be connected to VDD0
Output state: To be left open

Input state: To be connected to VDD0 or VSS0
Output state: To be left open

To be left open

17

Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)

µ

PD78P4038Y

Pin
RESET
TEST
AVREF1-AVREF3
AVSS
AVDD

I/O Circuit Type

2
1-A

–

I/O

Input

Recommended Connection Method for Unused Pins

–
To be connected to VSS0 directly
To be connected to VSS0

To be connected to VDD0

Caution When the I/O mode of an I/O alternate-function pin is unpredictable, connect the pin to V

through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin
becomes higher than that of the low level input at power-on or when I/O is switched by software).

Remark Since type numbers are consistent in the 78K Series, those numbers are not always serial in each

product. (Some circuits are not included.)

DD0

18

Figure 4-1. I/O Circuits for Pins

µ

PD78P4038Y

Type 1-A Type 2-C

V

DD0

P

IN

N

V

SS0

Type 2

IN

Schmitt trigger input with hysteresis characteristics

Type 5-H

Schmitt trigger input with hysteresis characteristics

Type 4-B

Data

DD0

V

P

OUT

Output
disable

N

V

SS0

Push-pull output which can output high impedance
(both the positive and negative channels are off.)

IN

Pull-up
enable

Data

Output
disable

Input
enable

VDD0

V

DD0

Pull-up
enable

P

P

V

DD0

P

IN/OUT

N

V

SS0

Type 8-C

Pull-up
enable

Output
disable

Type 10-B

Pull-up
enable

Open
drain
Output
disable

Data

Data

Type 12

V

DD0

P

V

DD0

P

Analog output
voltage

IN/OUT

P

OUT

N

N

V

SS0

Type 20-A

V

DD0

V

DD0

Data

P

Output

V

DD0

disable

P

IN/OUT

N

V

SS0

Comparator

+
–

(Threshold voltage)

AV

AV

SS

REF

P

IN/OUT

N

V

SS0

P

N

Input
enable

19

µ

PD78P4038Y

5. INTERNAL MEMORY SWITCHING (IMS) REGISTER

This register enables the software to avoid using part of the internal memory. The IMS register can be set to
establish the same memory mapping as used in ROM products that have different internal memory (ROM and RAM)
configurations.

The IMS register is set using 8-bit memory operation instructions.

A RESET input sets the IMS register to FFH.

Figure 5-1. Internal Memory Switching (IMS) Register

76543210

IMS IMS7 IMS6

IMS5

IMS4 IMS3 IMS2 IMS1 IMS0

The IMS is not contained in a mask ROM product (

IMS0-7

FFH
EEH

DCH
CCH

µ

PD784035Y, µPD784036Y, µPD784037Y, or µPD784038Y).

Same as the PD784038Y
Same as the PD784037Y

Same as the PD784036Y
Same as the PD784035Y

Address
0FFFCH

Memory Size

µ
µ

µ
µ

After Reset

FFH

R/W

But the action is not affected if the write command to the IMS is executed to the mask ROM product.

W

20

µ

PD78P4038Y

6. PROM PROGRAMMING

The µPD78P4038Y has an on-chip 128-KB PROM device for use as program memory. When programming, set
the VPP and RESET pins for PROM programming mode. See (2) in Chapter 2 with regard to handling of other, unused
pins.

6.1 Operation Mode

PROM programming mode is selected when +5 V or +12.5 V is added to the V
to the RESET pin. This mode can be set to operation mode by setting the CE pin, OE pin, and PGM pin as shown
in Table 6-1 below.

In addition, the PROM contents can be read by setting read mode.

Table 6-1. PROM Programming Operation Mode

Pin RESET VPP VDD CE OE PGM D0-D7

Operation Mode
Page data latch L +12.5 V +6.5 V H L H Data input
Page write H H L High impedance

PP pin or low-level input is added

Byte write L H L Data input
Program verify L L H Data output
Program inhibit × H H High impedance

× LL
Read +5 V +5 V L L H Data output
Output disable L H × High impedance
Standby H ××High impedance

Remark × = L or H

21

µ

PD78P4038Y

(1) Read mode

Set CE to L and OE to L to set read mode.

(2) Output disable mode

Set OE to H to set high impedance for data output and output disable mode.

µ

Consequently, if several
select data output from any of the devices.

(3) Standby mode

Set CE to H to set standby mode.
In this mode, data output is set to high impedance regardless of the OE setting.

(4) Page data latch mode

At the beginning of page write mode, set CE to H, PGM to H, and OE to L to set page data latch mode.
In this mode, 1 page (4 bytes) of data are latched to the internal address/data latch circuit.

(5) Page write mode

After latching the address and data for one page (4 bytes) using page data latch mode, adding a 0.1 ms program
pulse (active, low) to the PGM pin with both CE and OE set to H causes page write to be executed. Later, setting
both CE and OE to L causes program verification to be executed.
If programming is not completed after one program pulse, the write and verify operations may be repeated X times
(where X ≤ 10).

PD78P4038Y devices are connected to a data bus, the OE pins can be controlled to

(6) Byte write mode

Adding a 0.1 ms program pulse (active, low) to the PGM pin with both CE and OE set to H causes byte write
to be executed. Later, setting OE to L causes program verification to be executed.
If programming is not completed after one program pulse, the write and verify operations may be repeated X times
(where X ≤ 10).

(7) Program verify mode

Set CE to L, PGM to H, and OE to L to set program verify mode. Use verify mode for verification following each
write operation.

(8) Program inhibit mode

µ

Program inhibit mode is used to write to a single device when several
parallel to OE , VPP, and D0 to D7 pins.
Use the page write mode or byte write mode described above for each write operation. Write operations cannot
be done for devices in which the PGM pin has been set to H.

PD78P4038Y devices are connected in

22