NEC UPD75218GF-XXX-3BE, UPD75218CW-XXX Datasheet
Major changes in this version are indicated by stars (★) in the margins.
4-BIT SINGLE-CHIP MICROCOMPUTER
The µPD75218 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, ROM, RAM,
I/O ports, an FIP controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM pulses,
a serial interface and a vectored interrupt function integrated on a single chip.
It is most suitable for applications which use fluorescent display tubes as display devices and require the timer/
watch function and high-speed interrupt servicing, such as VCR, CD and ECR. It can help to provide the unit with
many functions and to decrease performance costs.
The
µ
PD75218 has larger ROM and RAM capacity than its predecessor, µPD75217. So several codes required
before have been reduced to only one code in the
µ
PD75218 specifications.
The one-time PROM product,
µ
PD75P218 and various development tools (IE-75001-R, assembler, etc.) are
available for system development evaluation or small production.
The following manual provides detailed description of the functions of the
µ
PD75218. Be sure to read this manual
when you design an application system.
µ
PD75218 User’s Manual: IEU-692
FEATURES
• On-chip large-capacity ROM and RAM
• Program memory (ROM): 32K × 8 bits
• Data memory (RAM) : 1K × 4 bits
• Architecture equal to that of an 8-bit microcomputer
• High-speed operation: Minimum instruction execution time : 0.67
µ
s (when the microcomputer operates at
6.0 MHz)
• Instruction execution time variable function realizing a wide range of operating voltages
• On-chip programmable fluorescent indication panel (FIP) controller/driver
• Timer function : 4 ch
• 14-bit PWM output capability with the voltage synthesizer type electronic tuner
• Buzzer output capability
• Interrupt function with importance attached to applications
• For power-off detection
• For reception of remote-controller signal
• Product with an on-chip PROM :
µ
PD75P218 (on-chip EPROM : WQFN package)
µ
PD75218
MOS INTEGRATED CIRCUIT
DATA SHEET
The information in this document is subject to change without notice.
Document No. IC-3035
(O. D. No. IP-8484)
Date Published November 1993 P
Printed in Japan
© NEC Corporation 1993
2
µ
PD75218
ORDERING INFORMATION
Part number Package Quality grade
µ
PD75218CW-××× 64-pin plastic shrink DIP (750 mil) Standard
µ
PD75218GF-×××-3BE 64-pin plastic QFP (14 × 20 mm) Standard
Remark ××× is a ROM code.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications
LIST OF FUNCTIONS
ROM: 32640 × 8 bits, RAM: 1024 × 4 bits
• CMOS input : 8 lines
• CMOS I/O : 20 lines (LED drive: 8 lines)
• CMOS output : 1 line (PWM/pulse output)
• P-ch open-drain output with high withstand voltage and high current: 4 lines (LED drive)
• 0.67 µs, 1.33 µs, 10.7 µs (with main system clock operating at 6.0 MHz)
• 0.95 µs, 1.91 µs, 15.3 µs (with main system clock operating at 4.19 MHz)
• 122 µs (with subsystem clock operating at 32.768 kHz)
• Number of segments : 9 to 16 segments
• Number of digits : 9 to 16 digits
• Dimmer function : 8 levels
• Mask option for pull-down resistors
• Key scan interrupt generation
• Timer/pulse generator : 14-bit PWM output enabled
• Watch timer : Buzzer output enabled
• Timer/event counter
• Basic interval timer : Watchdog timer application capability
• MSB start/LSB start switchable
• Serial bus configuration capability
External : 3, Internal : 5
External : 1, Internal : 1
• Ceramic/crystal oscillator for main system clock oscillation : 6.0 MHz standard
• Ceramic/crystal oscillator for main system clock oscillation : 4.19 MHz standard
• Crystal oscillator for subsystem clock oscillation : 32.768 kHz standard
• High withstand-voltage port (pull-down resistor)
• Port 6 (pull-down resistor)
–40 to +85 °C
2.7 to 6.0 V (standby data hold : 2.0 to 6.0 V)
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14 × 20 mm)
Item Function
Built-in memory
I/O line (including FIP dual-
function pins and excluding
FIP dedicated pins)
Instruction cycle
FIP controller/driver
Timer
Serial interface
Vectored interrupt
Test input
System clock oscillator
Mask option
Operating temperature range
Operating supply voltage
Package
®
4 channels
33 lines
3
µ
PD75218
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 5
2. BLOCK DIAGRAM ...................................................................................................................... 6
3. PIN FUNCTIONS ........................................................................................................................ 7
3.1 PORT PINS ...................................................................................................................................... 7
3.2 NON-PORT PINS ............................................................................................................................ 8
3.3 PIN INPUT/OUTPUT CIRCUIT LIST .............................................................................................. 9
3.4 HANDLING UNUSED PINS ........................................................................................................... 10
3.5 NOTES ON USE OF THE P00/INT4 PIN AND RESET PIN ......................................................... 11
3.6 NOTES ON USE OF THE XT1, XT2 AND P50 PIN ...................................................................... 11
4. MEMORY CONFIGURATION .................................................................................................... 12
5. PERIPHERAL HARDWARE FUNCTIONS .................................................................................. 15
5.1 PORTS.............................................................................................................................................. 15
5.2 CLOCK GENERATOR...................................................................................................................... 16
5.3 BASIC INTERVAL TIMER ............................................................................................................... 17
5.4 WATCH TIMER .............................................................................................................................. 18
5.5 TIMER/EVENT COUNTER ............................................................................................................. 19
5.6 TIMER/PULSE GENERATOR ......................................................................................................... 20
5.7 SERIAL INTERFACE ....................................................................................................................... 21
5.8 FIP CONTROLLER/DRIVER ............................................................................................................ 23
6. INTERRUPT FUNCTIONS .......................................................................................................... 24
7. STANDBY FUNCTIONS ............................................................................................................. 26
8. RESET FUNCTIONS ................................................................................................................... 27
9. INSTRUCTION SET .................................................................................................................... 29
10. MASK OPTION SELECTION ...................................................................................................... 38
11. APPLICATION BLOCK DIAGRAM ............................................................................................. 39
11.1 VCR TIMER TUNER ........................................................................................................................ 39
11.2 COMPACT DISK PLAYER .............................................................................................................. 40
11.3 ECR ................................................................................................................................................... 41
4
µ
PD75218
12. ELECTRICAL SPECIFICATIONS ............................................................................................... 42
13. CHARACTERISTIC CURVES (FOR REFERENCE) ..................................................................... 53
14. PACKAGE DIMENSIONS ........................................................................................................... 55
15. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 57
APPENDIX A FUNCTIONS OF µPD752×× SERIES PRODUCTS ................................................ 58
APPENDIX B DEVELOPMENT TOOLS......................................................................................... 59
APPENDIX C RELATED DOCUMENTS ........................................................................................ 60
★
★
★
5
µ
PD75218
1. PIN CONFIGURATION (TOP VIEW)
S3
S2
S1
S0
P00/INT4
P01/SCK
P02/SO
P03/SI
P10/INT0
P11/INT1
P12/INT2
P13/TI0
P20
P21
P22
P23/BUZ
P30
P31
P32
P33
P60
P61
P62
P63
P40
P41
P42
P43
PPO
X1
X2
V
SS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
DD
S4
S5
S6
S7
S8
S9
V
PRE
VLOAD
T15/S10
T14/S11
T13/S12/PH0
T12/S13/PH1
T11/S14/PH2
T10/S15/PH3
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
RESET
P53
P52
P51
P50
XT2
XT1
P41
P42
P43
PPO
X1
X2
V
SS
XT1
XT2
P50
P51
P52
P53
32
31
30
29
28
27
26
25
24
23
22
21
20
P01/SCK
P00/INT4
S0
S1
S2
S3
V
DD
S4
S5
S6
S7
S8
S9
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10111213141516171819
52
53
54
55
56
57
58
59
60
61
62
63
64
P40
P63
P62
P61
P60
P33
P32
P31
P30
P23/BUZ
P22
P21
P20
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI
P02/SO
RESET
T0T1T2T3T4T5T6T7T8
T9
V
PRE
T10/S15/PH3
T11/S14/PH2
T12/S13/PH1
T13/S12/PH0
T14/S11
T15/S10
V
LOAD
PD75218CW-× × ×
µ
PD75218GF-× × ×-3BE
µ
6
µ
PD75218
2. BLOCK DIAGRAM
Basic interval
timer
Timer/event
counter #0
Timer/pulse
generator
INTBT
INTT0
INTTPG
Serial interface
Interrupt control
INTSIO
TI0/P13
PPO
SI/P03
SO/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT4/P00
BUZ/P23
Watch timer
INTW f
X
/2
N
Clock divider
System clock
generator
Sub Main
Standby control
XT1 XT2 X1 X2 V
DDVSS
RESET
CPU clock
Program counter (15)
ROM
Program memory
32640 × 8 bits
Decode and control
RAM
Data memory
General register
Bank
SP(8)
CY
ALU
Port 0 4 P00–P03
Port 1 4 P10–P13
Port 2 4 P20–P23
Port 3 4 P30–P33
Port 4 4 P40–P43
Port 5 4 P50–P53
Port 6 4 P60–P63
FIP
controller/
driver
10 T0–T9
4
T10/S15/PH3–
T13/S12/PH0
2
T14/S11,
T15/S10
10
S0–S9
V
PRE
V
LOAD
Port H 4 PH0–PH3
INTKS
1024 × 4 bits
SBS(4)
Φ
7
µ
PD75218
Input
Input
Input
Input/
output
B
F
G
B
INT4
SCK
SO
SI
INT0
INT1
INT2
TI0
–––
–––
–––
BUZ
–––
–––
–––
–––
T13/S12
T12/S13
T11/S14
T10/S15
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30 to P33
P40 to P43
P50 to P53
P60 to P63
PH0
PH1
PH2
PH3
3. PIN FUNCTIONS
3.1 PORT PINS
Pin I/O After reset
Input / output
circuit type
Note
Function
Dualfunction pin
8-bit
I/O
Input/output
Input/output
4-bit input port (PORT0) ×
Input
B
Input
4-bit input port (PORT1)
4-bit input/output port (PORT2)
Input
E
×
Programmable 4-bit input/ output port (PORT3).
Input/output specifiable in 1-bit units.
Input/
output
Input
E
Input/
output
4-bit input/output port (PORT4).
LED direct drive capability.
●● Input
E
Input/
output
4-bit input/output port (PORT5).
LED direct drive capability.
Input
E
Input/
output
Programmable 4-bit input/output port (PORT6).
Input/output specifiable in 1-bit units.
On-chip pull-down resistor available (mask
option). Suitable for key input.
×
Input V
Output
4-bit P-ch open-drain output port with high
withstand voltage and high current (PORTH).
LED direct drive capability. On-chip pull-down
resistor available (mask option).
×
I
Note The circuit-type codes enclosed in circles indicate that the corresponding circuits have a Schmitt-triggered
input.
Low level
(with an onchip pulldown resistor)
or high
impedance.
Noise elimination function available
Noise elimination function available
8
µ
PD75218
Pin I/O
Dualfunction pin
Function
After reset
FIP controller/
driver output
pins.
Pull-down
resistor can
be incorporated in bit
units (mask
option).
T0 to T9
T10/S15 to
T13/S12
Output
–––
PH3 to PH0
Low level
(with an onchip pulldown
resistor ) or
high
impedance
(without a
pull-down
resistor)
I
3.2 NON-PORT PINS
Output pins with high withstand voltage
and high current also used for digit/segment output
Extra pins can be used as PORTH.
Output pins with high withstand voltage
and high current for digit output
T14/S11,
T15/S10
–––
Output pins with high withstand voltage
and high current also used for digit/
segment output
Static output also possible.
S9
S0 to S8
High withstand-voltage output for segment
output. Static output also possible.
High withstand-voltage output for segment
output
F
High
impedance
PPO
Output
Input
––– Timer/pulse generator pulse output
External event pulse input for timer/event counter
P13
Serial clock input/output
TI0
SCK
Serial data output or serial data input/output
Serial data input or normal input
Edge-detected vectored interrupt input (rising and falling
edge detection).
INT0
INT1
SO
SI
INT4
Input/output
Input
Input
Input
P01
P02
P03
P00
P10
P11
Edge-detected vectored interrupt input with noise
elimination function (detection edge selection possible).
Edge-detected testable input (rising edge detection).
Fixed frequency output (for buzzer or system clock
trimming).
Input
Input/output
P12
P23BUZ
X1 Input –––
D
Input
B
Input
G
Input
B
B
B
B
Input
E
Input/output
INT2
Crystal/ceramic connection pin for main system clock
oscillation.
External clock input to X1 and its inverted clock input to
X2.
B
Crystal connection pin for subsystem clock oscillation.
External clock input to XT1. Leave XT2 open.
XT1
Input
FIP controller/driver output buffer power supply.
FIP controller/driver pull-down resistor connection pin.
XT2 –––
–––
System reset input (low level active).
RESET
VPRE
Input
–––
Positive power supply.
VLOAD
VDD
–––
–––
I
I
GND potential.
–––
VSS
X2
–––
–––
–––
––––––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Note The circuit-type codes enclosed in circles indicate that the corresponding circuits have a Schmitt-triggered
input.
–––
★
Input / output
circuit type
Note
–––
–––
–––
9
µ
PD75218
3.3 PIN INPUT/OUTPUT CIRCUIT LIST
Type A
Type B
Type D
Type E
Type F
Type G
Type V
Type I
V
DD
P-ch
N-ch
IN
IN
V
DD
P-ch
N-ch
OUT
Data
Output
disable
Data
Output
disable
Type D
IN/OUT
Type A
Data
Output
disable
Type D
IN/OUT
Type B
Data
Output
disable
Type D
IN/OUT
Type A
V
DD
P-ch
N-ch
IN/OUT
Data
P-ch output
disable
Type B
V
DD
P-ch
N-ch
OUT
Data
V
DD
P-ch
V
LOAD
V
PRE
CMOS-specified input buffer
Schmitt trigger input having hysteresis characteristics
Push-pull output which can be set to high-impedance output
(off for both P-ch and N-ch)
Input/output circuit consisting of type D push-pull output
and type A input buffer
Pull-down resistor
(Mask option)
Pull-down
resistor
(Mask option)
Input/output circuit capable of switching between push-pull
output and N-ch open-drain output (with P-ch off).
Input/output circuit consisting of type D push-pull output
and type B schmitt trigger input
10
µ
PD75218
3.4 HANDLING UNUSED PINS
P00/INT4
P01/SCK
P02/SO
P03/SI
P10/INT0 to P12/INT2
P13/TI0
P20 to P22
P23/BUZ
P30 to P33
P40 to P43
P50 to P53
P60 to P63
PPO
S0 to S9
T15/S10 to T14/S11
T0 to T9
T10/S15/PH3 to T13/S12/PH0
XT1
XT2
VLOAD when there is no on-
chip load resistor
Connect to VSS
Connect to VSS or VDD
Connect to VSS
Input state : Connect to VSS or VDD
Output state : Leave open
Leave open
Connect to VSS or VDD
Leave open
Connect to VSS or VDD
Recommended connectionPin
11
µ
PD75218
• Connecting a diode between the pins and VDD
• Connecting a capacitor between the pins and VDD
3.6 NOTES ON USE OF THE XT1, XT2 AND P50 PIN
When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source
clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched
between high and low the minimum number of times (once/second or less).
If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because
of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch
becomes fast).
If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the
P50 pin as shown below.
3.5 NOTES ON USE OF THE P00/INT4 PIN AND RESET PIN
P00/INT4 and RESET pins have the function (especially for IC test) to test
µ
PD75218 internal operations in addition
to the functions described in sections 3.1 and 3.2.
The test mode is set when a voltage larger than V
DD is applied to one of these pins. If noise larger than VDD is
applied in normal operation, the test mode may be set thereby adversely affecting normal operation.
Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins,
if cables for the related signals are routed in parallel, wiring noise larger than V
DD may be applied to the P00/INT4
and RESET pins causing errors.
Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure
against noise using the following external components.
V
DD
V
DD
P00/INT4, RESET
V
DD
V
DD
P00/INT4, RESET
XT1
32.768 kHz
0.0068 F
µ
XT2
P50
PD75218
µ
12
µ
PD75218
4. MEMORY CONFIGURATION
• Program memory (ROM): 32640 words × 8 bits
• 0000H and 0001H: Vector table which contains the program start address after reset
• 0002H to 000FH : Vector table which contains the program start addresses when interrupts occur
• 0020H to 007FH : Table area referenced by a GETI instruction
• Data memory
• Data area : 1024 words × 4 bits (000H to 3FFH)
• Peripheral hardware area : 128 words × 4 bits (F80H to FFFH)
13
µ
PD75218
Internal reset start address
Branch address
speci-
fied in
BRCB !caddr
instruction
MBE RBE
Internal reset start address
INTBT/INT4 start address
MBE RBE
INTBT/INT4 start address
MBE RBE
INT0 start address
INT0 start address
MBE RBE
INT1 start address
INT1 start address
MBE RBE
INTSO start address
INTSO start address
MBE RBE
INTT0 start address
INTT0 start address
MBE RBE
INTTPG start address
INTTPG start address
MBE RBE
INTKS start address
INTKS start address
GETI instruction reference table
0000H
0002H
0004H
0006H
0008H
000AH
000CH
000EH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
4000H
4FFFH
5000H
5FFFH
6000H
6FFFH
7000H
7F7FH
Branch address
specified in CALL !addr
instruction
Branch/call
address specified
in GETI instruction
Entry address
specified in
CALLF !faddr
instruction
Branch address
specified in
BRCB !caddr
instruction
Branch address
specified in BRA !addr
instruction
Branch address
specified in CALLA !addr
instruction
Relative branch address
specified in BR $addr
instruction (–15 to –1,
+2 to +16)
Branch address
specified in BR !addr
instruction
(low-order 8 bits)
(high-order 6 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
Branch address
speci-
fied in
BRCB !caddr
instruction
Branch address
speci-
fied in
BRCB !caddr
instruction
Branch address
speci-
fied in
BRCB !caddr
instruction
Branch address
speci-
fied in
BRCB !caddr
instruction
Branch address
speci-
fied in
BRCB !caddr
instruction
Branch address
speci-
fied in
BRCB !caddr
instruction
Fig. 4-1 Program Memory Map
Caution The start address of an interrupt vector shown above consists of 14 bits. So the start address must be
set within a 16K-byte space (0000H to 3FFFH).
Remark In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC changed
is enabled by BR PCDE and BR PCXA instructions.
14
µ
PD75218
Fig. 4-2 Data Memory Map
(32 × 4)
Data memory
000H
01FH
020H
2FFH
300H
3 FFH
F80H
FFFH
256 × 4
256 × 4
128 × 4
0
2
15
Stack
area
General
register
area
Data area
Static RAM
(1024 × 4)
Peripheral
hardware area
Not contained
256 × 4
256 × 4
1
3
0FFH
100H
1FFH
200H
Memory bank
(64 × 4)
1C0H
1BFH
Display
data
memory,
etc.
15
µ
PD75218
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
The
µ
PD75218 has the following three types of I/O port:
• 8 CMOS input pins (PORT0 and PORT1)
• 20 CMOS I/O pins (PORT2, PORT3, PORT4, PORT5, and PORT6)
• 4 P-ch open-drain output pins with high withstand voltage and high current (PORTH)
Total: 32 pins
Table 5-1 Functions of Ports
Remarks
Port
Always read or test possible irrespective of the dual-function
pin operating mode.
Always read or test possible, P10 and P11 are inputs with the
noise elimination function.
Can be set to the input or output mode in 4-bit units.
Ports 4 and 5 can input/output data in pairs in 8-bit units.
Ports 4 and 5 can directly drive LEDs.
Can be set bit-wise to the input or output mode. Port 6 can
incorporate a pull-down resistor by mask option.
P-ch open-drain output port with high withstand voltage and
high current. Can drive an FIP and LED directly. Can
incorporate a pull-down resistor in bit units by mask option.
Shares the pins with SI, SO, SCK
and INT4.
Shares the pins with INT0 to
INT2 and TI0.
P23 shares the pin with BUZ.
Shares the pins with T10/S15 to
T13/S12.
Operation and feature
Function
4-bit input
PORT0
PORT1
PORT2
PORT4
PORT5
PORT3
PORT6
4-bit
input/output
PORTH
4-bit output
16
µ
PD75218
5.2 CLOCK GENERATOR
Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control
register (SCC).
The main system clock or subsystem clock can be selected.
The instruction execution time is variable.
0.67
µ
s, 1.33 µs, 10.7 µs (main system clock: 6.0 MHz)
0.95
µ
s, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)
122 µs (subsystem clock: 32.768 kHz)
Fig. 5-1 Clock Generator Block Diagram
Note Instruction execution
Remarks 1. f
X = Main system clock frequency
2. f
XT = Subsystem clock frequency
3. f
XX = System clock frequency
4. Φ = CPU clock
5. PCC: Processor clock control register
6. SCC: System clock control register
7. 1 clock cycle (t
CY) of Φ is 1 machine cycle of an instruction. For tCY, see ”AC Characteristics“ in
Chapter 12.
★
XT1
XT2
X1
X2
f
XT
f
X
SCC
PCC
HALT
Note
STOP
Note
HALT F/F
STOP F/F
4
QS
R
S
R
1/4
1/8 to 1/4096
SCC3
SCC0
PCC0
PCC1
PCC2
PCC3
Q
Selector
f
XX
1/2 1/6
Frequency divider
Selector
Watch timer
Timer/pulse
generator
Subsystem
clock generator
Main system
clock generator
Oscillation
stop
Frequency
divider
• FIP controller
• Basic interval timer (BT)
• Timer/event counter
• Serial interface
• Watch timer
• INT0 noise eliminator
• CPU
• INT0 noise eliminator
• INT1 noise eliminator
Wait release signal from BT
RES signal (internal reset)
Standby release signal from
interrupt control circuit
PCC2 and
PCC3
clear
Internal bus
Φ
17
µ
PD75218
5.3 BASIC INTERVAL TIMER
The basic interval timer has the following functions:
• Interval timer operation to generate reference time
• Watchdog timer application to detect inadvertent program loop
• Wait time select and count upon standby mode release
• Count contents read
Fig. 5-2 Basic Interval Timer Configuration
Note Instruction execution
Internal bus
f
XX
/2
5
fXX/2
7
fXX/2
12
From clock
generator
4
BTM3 BTM2 BTM1 BTM0 BTM
MPX
BT IRQBT
Set
BT interrupt
request flag
Clear Clear
Basic interval timer
(8-bit frequency divider)
Wait release
signal during
standby release
8
3
Vectored
interrupt
request
signal
f
XX
/2
9
SET1
Note
18
µ
PD75218
5.4 WATCH TIMER
The
µ
PD75218 incorporates one channel of watch timer. The watch timer has the following functions:
• Sets the test flag (IRQW) at 0.5 sec intervals.
The standby mode can be released by IRQW.
• 0.5 second interval can be set with the main system clock and subsystem clock.
• The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection.
• The fixed frequencies (2.048 kHz) can be output to the P23/BUZ pin for use to generate buzzer sound
and trim the system clock oscillator frequency.
• Since the frequency divider can be cleared, the watch can be started from zero second.
Fig. 5-3 Watch Timer Block Diagram
Remark Values when f
XX is 4.194304 MHz and fXT is 32.768 kHz are indicated in parentheses.
Caution When the main system clock operates at 6.0 MHz, a time interval of 0.5 second cannot be produced.
Before producing this time interval, the main system clock must be changed to the subsystem clock.
8
Internal bus
WM7 WM6 WM5 WM4 WM2 WM1 WM0
P23
output
latch
Port 2
input/output
mode
PORT2.3 Bit 2 of PMGB
P23/BUZ
Output buffer
Selector
Frequency divider
Clear
(2.048 kHz)
2
14
f
W
2
7
f
W
(256 Hz : 3.91 ms)
f
W
(32.768 kHz)
Selector
WM
From
clock
generator
16
f
W
128
f
XX
(32.768 kHz)
f
XT
(32.768 kHz)
INTW
IRQW
set signal
2 Hz
0.5 sec
WM3
19
µ
PD75218
5.5 TIMER/EVENT COUNTER
The
µ
PD75218 incorporates one channel of timer/event counter. The timer/event counter has the following
functions:
• Program interval timer operation
• Event counter operation
• Count state read function
Fig. 5-4 Timer/Event Counter Block Diagram
Note Instruction execution
P13/TI0
Input buffer
From clock
generator
MPX
TMn6 TMn5 TMn4 TMn3 TMn2
SET1
Note
TM0
Timer operation start
CP
Count register (8)
Clear
8
Comparator (8)
8
8
Modulo register (8)
8
8
Internal bus
TMOD0
Match
IRQT0
clear
T0
TMn7 TMn1 TMn0
INTT0
IRQT0
set signal
(See Fig. 5-1.)
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