NEC UPD17P204GC-002-3BH, UPD17P204GC-001-3BH, UPD17P203AGC-003-3BH, UPD17P203AGC-002-3BH, UPD17P203AGC-001-3BH Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD17P203A, 17P204

4-BIT SINGLE-CHIP MICROCONTROLLER WITH STATIC RAM

AND 3-CHANNEL TIMER FOR INFRARED REMOTE CONTROLLER

DESCRIPTION

µ

PD17P203A and µPD17P204 are variations of µPD17203A and µPD17204 respectively and are equipped

with a one-time PROM instead of an internal mask ROM.

µ

PD17P203A and µPD17P204 are suitable for evaluating a program when developing µPD17203A and µPD17204

systems respectively because the program can be written by the user.

µ

When reading this document, also refer to the

FEATURES

• 17K architecture: General-purpose register format

• Pin-compatible (except for PROM programming function):µPD17P203A with µPD17203A

• Internal one-time PROM: 4096 x 16 bits (µPD17P203A)

7936 x 16 bits (µPD17P204)

µ

• Static RAM: 16 Kbits (

8 Kbits (µPD17P204)

• Power supply voltage: 2.9 to 5.5 V (at TA = –20 to +75°C, fX = 4MHz)

PD17P203A)

2.0 to 5.5 V (at T

PD17203A and µPD17204 Data Sheets.

µ

PD17P204 with µPD17204

A = –20 to +75°C, fXT = 32kHz)

The features of each product is shown in the following table:

µ

Item

Pull-up resistor of RESET pin

Pull-up resistor of P0A and P0B pins

Main clock oscillator circuit

Subclock oscillator circuit

µ

PD17P203A and µPD17P204 are different from µPD17203A and µPD17204 respectively in the power

supply voltage and the operating ambient temperature. Therefore, use µPD17P203A and µPD17P204

only for the system evaluation.

This document explains µPD17P204 as a typical product where no specification is made.

The information in this document is subject to change without notice.

PD17P203A-001

µ

PD17P204-001

Provided

µ

PD17P203A-002

µ

PD17P204-002

Not provided

Provided

Not provided

µ

PD17P203A-003

µ

PD17P204-003

Not provided

Provided

µ

PD17203A

µ

PD17204

On request

(mask option)

Document No. IC-2851A

(O. D. No. IC-8303B) Date Published June 1995 P Printed in Japan

The mark ★ shows major revised points.

©

1992

ORDERING INFORMATION

Part Number Package

µ

PD17P203AGC-001-3BH 52-pin plastic QFP (14 × 14 mm)

µ

PD17P203AGC-002-3BH 52-pin plastic QFP (14 × 14 mm)

µ

PD17P203AGC-003-3BH 52-pin plastic QFP (14 × 14 mm)

µ

PD17P204GC-001-3BH 52-pin plastic QFP (14 × 14 mm)

µ

PD17P204GC-002-3BH 52-pin plastic QFP (14 × 14 mm)

µ

PD17P204GC-003-3BH 52-pin plastic QFP (14 × 14 mm)

µ

PD17P203A, 17P204

2

PIN CONFIGURATION (TOP VIEW)

(1) Normal operation mode

P1C3

P1C2/SI

1/SO

P1C

0/SCK

P1C

2/TM1OUT

P1B3/TM2OUT

P1B

1/TM0OUT

0

P1B

µ

PD17P203A, 17P204

P1A3

P1A2

P1A1

P1A0

P0D3

LED

REM

VXRAM

VDD

XIN

XOUT

GND0

RESET

WDOUT

XTIN

XTOUT

VREG

GND5

52 51 50 49 48 47 46 45 44 43 42 41 40

1

2

3

µ

PD17P204GC-001-3BH

PD17P204GC-002-3BH

4

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24 25 26

2

GND1

GND

AMPIN–

PD17P204GC-003-3BH

REF

V

AMPOUT

CMPIN+

PD17P203AGC-001-3BH

PD17P203AGC-002-3BH

PD17P203AGC-003-3BH

3

INT

GND

TM0IN

CMPOUT

P0A0

P0A1

39

38

37

36

35

34

33

32

31

30

29

28

27

P0D

2

P0D1

P0D0

P0C3

P0C2

P0C1

GND4

P0C0

P0B3

P0B2

P0B1

P0B0

P0A3

P0A2

AMPIN– : Operational amplifier input

AMPOUT : Operational amplifier output

CMPIN+ : Comparator input

CMPOUT : Comparator output

0-GND5 : Ground

GND

INT : External interrupt input

LED : Remote controller transmission

output indicator

0-P0A3 : I/O port 0A

P0A

P0B0-P0B3 : I/O port 0B

P0C0-P0C3 : I/O port 0C

0-P0D3 : I/O port 0D

P0D

P1A0-P1A3 : I/O port 1A

P1B0-P1B3 : I/O port 1B

0-P1C3 : I/O port 1C

P1C

REM : Remote controller transmission

output

RESET : Reset input

SCK : Serial clock input/output

SI : Serial data input

SO : Serial data output

TM0IN : Timer 0 input

TM0OUT : Timer 0 output

TM1OUT : Timer 1 output

TM2OUT : Timer 2 output

DD : Power supply

V

VREG : Voltage regulator output

VREF : Reference voltage output

XRAM : Static RAM (XRAM) power supply

V

WDOUT : Overrun detection output

XIN, XOUT : Main clock oscillation use

IN, XTOUT : Subclock oscillation use

XT

3

(2) PROM programming mode

(L)

µ

PD17P203A, 17P204

D3

(Open)

GND

VDD

CLK

GND

(L)

52 51 50 49 48 47 46 45 44 43 42 41 40

1

2

3

µ

4

5

6

0

5

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24 25 26

2

(L)

GND1

GND

µ

PD17P204GC-002-3BH

PD17P204GC-003-3BH

(L)

(Open)

PD17P203AGC-002-3BH

PD17P203AGC-003-3BH

PD17P204GC-001-3BH

GND3

PD17P203AGC-001-3BH

PP

(L)

V

(Open)

39

38

37

36

35

34

33

32

31

30

29

28

27

(L)

D2

D1

D0

D7

D6

D5

GND4

D4

MD3

MD2

MD1

MD0

(L)

Caution Those enclosed in parentheses indicate the processing of the pins not used in PROM

programming mode.

L : Ground these pins through a resistor (470Ω).

Open: Do not connect anything to these pins.

CLK : PROM clock input

D0-D7 : PROM data I/O

GND, GND

0-GND5 : Ground

MD0-MD3 : PROM mode selection

VDD : Power supply

VPP : Program power supply

4

BLOCK DIAGRAM

P0A

0

P0A

1

P0A

2

P0A

3

P0B0/MD0 P0B1/MD1

2

/MD2

P0B

3

/MD3

P0B

0

/D4

P0C P0C

1

/D5

2

/D6

P0C

3

/D7

P0C

0

/D0

P0D

1

/D1

P0D

2

/D2

P0D

3

/D3

P0D

P1A

0

P1A

1

P1A

2

P1A

3

0

P1B1/TM0OUT P1B P1B

P1B

2

/TM1OUT

3

/TM2OUT

P0A

P0B

P0C

P0D

P1A

P1B

Timer0/

Counter

RF

RAM

336 × 4 bits

SYSTEM REG.

ALU

One Time

PROM

4096 × 16 bits ( PD17P203A)

µ

7936 × 16 bits ( PD17P204)

µ

Program Counter

Instruction Decoder

µ

PD17P203A, 17P204

V

REG

V

DD

V

XRAM

V

REF

Power Supply Circuit

GND

GND GND GND GND GND

TM0IN

CMPOUT

Remote Control Receiver

CMPIN +

AMPOUT

AMPIN –

Remote

REM

Control Transmitter

LED

0

1

2

3

4

5

P1C0/SCK

P1C

1

/SO

P1C2/SI

P1C

Timer1/ Counter

Timer2/ Counter

P1C

3

Stack

5 × 12 bits ( PD17P203A)

µ

7 × 13 bits ( PD17P204)

µ

XRAM

Interrupt Controller

INT/V

RESET

WDOUT

PP

4096 × 4 bits

µ

Serial

I/O

( PD17P203A) 2048 × 4 bits ( PD17P204)

µ

CPU Clock Clock Stop

XIN/CLK

Watch Timer Divider

Main clock

CPU Clock

Subclock

X

XT

OUT

IN

OUT

5

µ

PD17P203A, 17P204

CONTENTS

1. PIN FUNCTIONS ..................................................................................................................... 7

1.1 NORMAL OPERATION MODE ..................................................................................................... 7

1.2 PROM PROGRAMMING MODE ................................................................................................... 9

1.3 PIN I/O CIRCUITS .......................................................................................................................... 9

★ ★

1.4 PROCESSING OF UNUSED PINS ................................................................................................ 12

1.5 NOTES ON USING RESET AND INT PINS ................................................................................. 13

2. DIFFERENCES BETWEEN MASK ROM PRODUCTS AND ONE-TIME PROM

PRODUCTS .............................................................................................................................. 14

3. ONE-TIME PROM (PROGRAM MEMORY) WRITING, READING,

AND VERIFICATION ............................................................................................................... 15

3.1 OPERATION MODE FOR WRITING, READING,

AND VERIFICATION OF PROGRAM MEMORY .......................................................................... 15

3.2 PROGRAM MEMORY WRITE PROCEDURE................................................................................ 16

3.3 PROGRAM MEMORY READ PROCEDURE ................................................................................. 17

4. ELECTRICAL SPECIFICATIONS ............................................................................................. 18

5. PACKAGE DRAWINGS ........................................................................................................... 23

6. RECOMMENDED SOLDERING CONDITIONS...................................................................... 24

APPENDIX A. MICROCONTROLLERS FOR LEARNING REMOTE CONTROLLER ............. 25

APPENDIX B. DEVELOPMENT TOOLS ..................................................................................... 26

6

1. PIN FUNCTIONS

µ

PD17P203A, 17P204

1.1 NORMAL OPERATION MODE

Pin No. Symbol Function Output Format At Reset

Outputs NRZ signal in synchronization with

1

2

3

4

5 6

7

8

9

LED

REM

VXRAM

VDD

XIN

XOUT

GND0

RESET

WDOUT

infrared remote controller signal. Remains low while remote control carrier is output

Outputs active-high infrared remote control signal

Supplies power to XRAM

Positive power

Connect 4-MHz ceramic oscillator for main clock oscillation

Ground

Inputs low-active system reset signal. While this pin remains low level, oscillation of main clock stops. Pull-up resistor can also be connected by mask option

(µPD17P203A-001 and µPD17P204-001 only).

Outputs signal for detecting overrun. This pin outputs a low-level when an overflow in the watchdog timer or an overflow/underflow in the stack is detected. Connect this pin to the RESET pin.

CMOS push-pull

–

N-ch open drain

High-level output

Low-level output

(Oscillation stop)

High impedance

(1/2)

–

★

10 11

12

13

14

15

16

17

18

19

20

XTIN

XTOUT

VREG

GND5

GND1

AMPIN-

GND2

AMPOUT

VREF

CMPIN+

GND3

Remark GND

Keep all these pins at the same potential to stabilize the operation of the operational amplifier.

Connect 32-kHz crystal oscillator across these pins. When option not using subclock is selected, main clock is divided and is supplied to watch timer.

Outputs signal from voltage regulator for subclock oscillator circuit. Connect external 0.1-µF capacitor.

Ground

Ground of operation amplifier

Inverted input of operational amplifier

Ground of operational amplifier

Output of operational amplifier

Outputs reference voltage of 1/2VDD. Connect external 0.1-µF capacitor.

Non-inverted input of comparator. Output of this comparator can be obtained from CMPOUT.

Ground of operational amplifier

1-GND3 are the ground pins of the operational amplifier.

–

(Oscillation)

–

Input

–

Output

–

Input

–

7

µ

PD17P203A, 17P204

Pin No. Symbol Function Output Format At Reset

Comparator output. Externally connect CMPOUT

21

22

CMPOUT

TM0IN

and TM0IN when using microcontroller as teaching remote controller

Clock input to timer 0. Input clock is sampled by internal clock and then input to envelope signal generator circuit, as well as to timer 0. By using timer 0 with timer 1, frequency of clock input to this pin can be measured.

–

Output

Input

(2/2)

23

24 to 27

28 to 31

32 34 to 36

33

37 to 40

41 to 44

45 46

47

48

INT

P0A0

to

P0A3

P0B0

to

P0B3

P0C0 P0C1

to

P0C3

GND4

P0D0

to

P0D3

P1A0

to

P1A3

P1B0 P1B1/

TM0OUT

P1B2/

TM1OUT

P1B3/

TM2OUT

External interrupt signal input pin

Constitute 4-bit I/O port, which can be set in input or output mode in 4-bit units. Pull-up resistor can be connected by mask option (µPD17P203A-001, -002 and

µ

PD17P204-001, -002 only). When one or more of these pins goes low in standby mode standby mode is released.

Constitute 4-bit I/O port, which can be set in input or output mode in 4-bit units.

Ground

Constitute 4-bit I/O port, which can be set in input or output mode in 4-bit units.

Constitute 4-bit I/O port, which can be set in input or output mode in bitwise. Pull-up registor can be connected through program.

Port 1B or timer output

• P1B0-P1B3

- 4-bit I/O port

- Can be set in input/output mode in bitwise

- Pull-up resistor can be connected through program

• TM0OUT-TM2OUT

- Timer output

–

CMOS push-pull

N-ch open drain

–

N-ch open drain

Input

–

Input

(P1B0-P1B3)

Port 1C or serial interface I/O

• P1C0-P1C3

49 50 51 52

P1C0/SCK P1C1/SO P1C2/SI P1C3

- 4-bit I/O port

- Can be set in input/output mode in bitwise

• SCK, SO, SI

- SCK : serial clock I/O

- SO : serial clock data output

- SI : serial clock data input

CMOS push-pull

Input

(P1C0-P1C3)

Caution For “A” standard products, note that standby mode is released when one or more of P0C and

P0D pins goes high in standby mode.

8

µ

p

PD17P203A, 17P204

1.2 PROM PROGRAMMING MODE

Pin No. Symbol Function Output Format At Reset

3

7 13 14 16 20 33

GND GND0 GND5 GND1 GND2 GND3 GND4

Ground

–

4

5

23

28 to 31

32, 34

to 36

37 to 40

VDD

CLK

VPP

MD0 to MD3

D4 to D7

D0 to D3

Positive power

Address updating clock input

Supplies program voltage. Apply 12.5V to this pin

Selects PROM programming mode

8-bit data I/O

–

CMOS push-pull

1.3 PIN I/O CIRCUITS

This section shows the I/O circuits of the µPD17P204 pins in simplified schematic diagrams.

(1) P0A

0-P0A3, P0B0/MD0-P0B3/MD3

Data

Output

latch

V

DD

P-ch

V

DD

Pull-up resistor

–

Input

–

Input

Note

Output disable

In

NoteµPD17P203A-001, -002 and µPD17P204-001, -002 only.

N-ch

ut buffer

9