MSI MS-6750 Schematics
5
4
3
2
1
Title Page
MS-6750 VER:0A ATX
*AMD PGA 754 Processor
D D
*VIA K8T400M / VT8237 Chipset
(DDR 333 / AGP 8X / VLink 8X)
*Winbond 83697HF-VF LPC I/O
*LAN PHY VT6103 Ethernet 10 / 100
*AC97 AL650 Codec
*USB 2.0 support (integrated into VT8237)
*Jump Less support
*AGP SLOT * 1 ( 8X )
*PCI SLOT * 5
C C
*DDR DIMM * 2
*CNR * 1
Cover Sheet 1
Block Diagram
Clock Synthesizer 7
System Memory
DDR DIMM 1 & 2 8
DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8T400M(HT)
K8 Vcore power
AGP SLOT 8X
SB VT8237
PCI Connectors 1 & 2 & 3 & 4 & 5
1394a Controller
AC97 Codec
Audio Connector
ATA 66/100/133
2
3GPIO SPEC
4,5,6AMD K8 -> 754 PGA Socket
9
10
11,12,13
14
15
16,17,18
19,20,21
22
23
24
25
26VT6103-LAN PHY
CNR SLOT
27
28Front USB Port
Rear USB Port
LPC I/O W83697HF & Floppy
Hardware monitor
B B
Keyboard/Mouse Port/BIOS
LPT/COM Port
ACPI Power
PowerOK Circuit
Front Panel
BULK / Decoupling
Power Generation
Manual Parts
29
30
31
32
33
34
35,36
37
38
39
40
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
1
Cover Sheet
MS-6750
Last Revision Date:
Sheet
Rev
0A
Wednesday, January 29, 2003
140
of
5
Block Diagram
4
3
2
1
AMD K8
D D
A
C C
G
P
AGP 8X /Fast Write
P
Socket 754
HT
VIA
K8T400M
DDR
DDR * 2
R
O
VLINK
SATA1 SATA2
PCI Bus
B B
PCI 5
PCI 4
PCI 3
PCI 2
PCI 1
AC'97 Link
VIA
VT8237
Dual SATA
10/100 BaseT
Lan
1394a
LPC BUS
SUPER I/O
W83697HF
USB
Onboard AC'97
Codec
X BUS
A A
5
CNR SLOT
Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
==> Front-Port *4 ,
Back-Port *4
4
3
ROM Floopy Parallel Serial
Title
Document Number
2
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
Keyboard
Mouse
Micro Star Restricted Secret
Block Diagram
MS-6750
Last Revision Date:
Sheet
1
Rev
0A
Wednesday, January 29, 2003
40
2
of
PGNT#4LAN_PCLKPCI SLOT 2AD19
5
GPIO FUNCTION
VT8237 GPIO Function Define
D D
PIN NAME Function define
GPO0 (VSUS33)
GPO1 (VSUS33)
GPO2/SUSA#(VSUS33)
GPO3/SUSST1#(VSUS33)
GPO4/SUSCLK(VSUS33)
GPO5/CPUSTP#
GPO6/PCISTP#
GPO7/GNT5
GPO8/GPI8/VGATE
GPO9/GPI9/UDPWEREN
C C
GPO10/GPI10/INTE#
GPO11/GPI11/INTF#
GPO12/GPI12/INTG#
GPO13/GPI13/INTH#
GPO14/GPI14/APICD0
GPO15/GPI15/APICD1
GPO20/GPI20/ACSDIN2
GPO21/GPI21/ACSDIN3
GPO22/GPI22/GHI#
GPO23/GPI23/DPSLP
B B
GPO24/GPI24/GPIOA
GPO25/GPI25/GPIOB
GPO26/GPI26/SMBDT2
GPO27/GPI27/SMBCK2
GPO28/GPI28/VIDSEL
GPO29/GPI29/VRDSLP
GPO30/GPI30/GPIOC
GPO31/GPI31/GPIOD
A A
GPI1 (VSUS33)
GPI2/EXTSMI#
(VSUS33)
GPI3/RING# (VSUS33)
GPI4/LID# (VSUS33)
Default
Function
GPO0
GPO1
SUSA#
SUSST1#
SUSCLK
CPUSTP#
PCISTP#
GP07
GPI8
GPI9
GPI10
GPI11
GPI12
GPI13
GPI14
GPI15
SDIN2
SDIN3
GPI22
GPI23
GPIOA
GPIOB
SMBDT2
SMBCK2
GPI28 VIDSEL Pull down to GND
GPI29 VRDSLP Pull down to GND
GPIOC
GPIOD
GPI0
GPI1
EXTSMI#
RING#
LID#
5
SUSLED ( Power LED )
CTL_PLED1#
SUSA#
SUSST#
SUSCLK
CPUSTP#
PCISTP#
GNT5
VGATE
NA
NA
NA
PIRQE#
PIRQF#
PIRQG#
PIRQH#
APICD0#
APICD1#
AC_SDIN2
AC_SDIN3
NA
NA
NA
NA
NA
NA
NA
NA
GHI# NA
-LDTSTOP Pull up to VCC3
LDT Freq Strapping bit1
LDT Width (L=8 bit,H=8 bit)
SMBDATA2/Slave SMBUS
SMBCLK2/Slave SMBUS
NA
NA
LDT Freq Strapping bit0
Fast Command (0:disable)
GPI0 NA
ATADET0=>Detect IDE1 ATA100/66
EXTSMI#
RING#
ATADET1=>Detect IDE2 ATA100/66
4
Pull up / down
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC
Pull up to VCC
Pull up to VCC
Pull up to VCC
Pull up to VCC3
Pull up to VCC3
Pull down to GND
Pull down to GND
Pull up to VCC3
Pull down to GND
Pull down to GND
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull down to GND
Pull down to GND
Pull up to VBATGPI0 (VBAT)
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
4
3
PIN NAME
GPI5/BATLOW#
(VSUS33)
GPI6/AGPBZ
GPI7/REQ5
GPI16/INTRUDER#
(VBAT)
GPI17/CPUMISS
GPI18/AOLGP1/THRM#
8235(CE)/8237
Strapping
VT8237>>PDA0
VT8235(CE)>>SDA0
VT8237>>PDA1
VT8235(CE)>>SDA1 Low Pull down to GND
VT8237>>PDCS#3
VT8235(CE)>>SDCS#3
VT8237>>ACSDO
VT8235(CE)>>SXO
VT8237>>PDA2
VT8235(CE)>>SDA2
VT8237>>MII_EEDI
VT8235(CE)>>SDCS#1
VT8237>>PDCS#1
VT8237>>PDDACK#
VT8235/8237>>SPKR
VT8237>>ACSYNC
VT8235(CE)>>SXI
Default
BATLOW#
BATLOW#
AGPBZ AGPBZ# Pull up to VCC3NA
GPI7
INTRUDER#
CPUMISS
AOLGP1
APICCLK
Low
High
PREQ#5
INTRUDER
CPUMISS
THRM#
APICCLK
LDT Transmit timing control
1/0 : enable / disableLow Pull down to GND
External loop test mode
1/0 : enable / disable
Test mode
1/0 : enable / disableLow Pull down to GND
Auto reboot
0/1 : enable / disableLow Pull down to GND
Romsip Select
1/0 : enable / disableHigh Pull up to VCC3
Eliminate Lan
Eeprom
SATA master/slave mode
0/1 : enable / disableHigh Pull up to VCC3
External Sata Phy
0/1 : enable / disable Pull up to VCC3High
CPU Freq Strapping
0/1 : enable / disable Pull up to VCC3
LPC FWH Command
0/1 : enable / disableHigh Pull up to VCC3
LPC ROM
1/0 : enable / disableHigh Pull up to VCC3
2
NA
NA
NA
NA
NAGPI19/APICCLK
Function define Pull up / downState
1/0:enable/disable
0/1:enable/disableHigh
Pull up / downFunction defineFunction
Pull up to 3VDUAL
Pull up to VCC3
Pull up to VBAT
Pull up to 3VDUAL
Pull up to VCC3
Pull down to GND
Pull up to VCC3
PCI Routing
DEVICES
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
PCI SLOT 4
PCI SLOT 5
1394
3
INT#
INT#A
INT#B
INT#C
INT#D
INT#B
INT#C
INT#D
INT#A
INT#C
INT#D
INT#A
INT#B
INT#D
INT#A
INT#B
INT#C
INT#A
INT#B
INT#C
INT#D
IDSEL
AD16
AD17
AD18
AD19
AD21
INT#D AD25
REQ#/GNT#
PREQ#1
PGNT#1
PREQ#2
PGNT#2
PREQ#3
PGNT#3
PREQ#4
PGNT#4
PREQ#5
PGNT#5
PREQ#0
PGNT#0
2
CLOCK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
1394_PCLK
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
http://www.msi.com.tw
GPIO Spec.
MS-6750
1
Last Revision Date:
Wednesday, January 29, 2003
Sheet
340
1
Rev
0A
of
5
4
3
2
1
VDD_12_A
CADIN15
CADIN14
CADIN13
CADIN12
CADIN11
CADIN10
CADIN9
CADIN8
CADIN7
CADIN6
CADIN5
CADIN4
CADIN3
CADIN2
CADIN1
CADIN0
VDD_12_A
CADIP15
CADIP14
CADIP13
CADIP12
CADIP11
CADIP10
CADIP9
CADIP8
CADIP7
CADIP6
CADIP5
CADIP4
CADIP3
CADIP2
CADIP1
CADIP0
CTLIP1
CTLIN1
C474
0.22u/BOT
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
T27
T28
V29
U29
V27
V28
Y29
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
Y25
W25
Y27
Y28
R27
R26
T29
R29
C139
0.22u
U7A
N12-7540010-A10
VLDT0_A6
VLDT0_A5
VLDT0_A4
VLDT0_A3
VLDT0_A2
VLDT0_A1
VLDT0_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
2
C216
C141
X_0.22u
0.22u
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
HYPER TRANSPORT - LINK0
L0_CTLOUT_L0
C224
C190
0.22u
0.22u
AH29
VLDT0_B6
AH27
VLDT0_B5
AG28
VLDT0_B4
AG26
VLDT0_B3
AF29
VLDT0_B2
AE28
VLDT0_B1
AF25
VLDT0_B0
N26
CADON15
N27
L25
CADON14
M25
L26
CADON13
L27
J25
CADON12
K25
G25
CADON11
H25
G26
CADON10
G27
E25
CADON9
F25
E26
CADON8
E27
N29
CADON7
P29
M28
CADON6
M27
L29
CADON5
M29
K28
CADON4
K27
H28
CADON3
H27
G29
CADON2
H29
F28
CADON1
F27
E29
CADON0
F29
CLKOP1
J26
CLKON1
J27
CLKOP0
J29
CLKON0
K29
N25
P25
P28
P27
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
C140
0.22u
CADOP15
CADOP14
CADOP13
CADOP12
CADOP11
CADOP10
CADOP9
CADOP8
CADOP7
CADOP6
CADOP5
CADOP4
CADOP3
CADOP2
CADOP1
CADOP0
CTLOP0
CTLON0
K8 DDR & HT
MS-6750
VLDT0
VLDT0 5
C64
4.7U/0805
CADOP[0..15] 11
CADON[0..15] 11CADIN[0..15]11
CLKOP1 11
CLKON1 11
CLKOP0 11
CLKON0 11
CTLOP0 11
CTLON0 11
Last Revision Date:
Wednesday, January 29, 2003
Sheet
440
1
C53
0.22u
Rev
0A
of
VREF routed as 40~50 mils trace wide ,
Space>25 mils
C49
D D
DDR_VREF8
VDD_25_SUS
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
C C
B B
DDR_VREF
R91 30.1RST
R95 30.1RST
MD[63..0]10
MEMDM[7..0]10
A A
-MDQS[7..0]10
C41
102P
104P
MEMZN
MEMZP
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MEMDM7
MEMDM6
MEMDM5
MEMDM4
MEMDM3
MEMDM2
MEMDM1
MEMDM0
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
5
AE13
AG12
AG3
AE2
AH3
AH9
AG5
AH5
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
AA1
AG1
AH7
AH13
AB1
AJ13
D14
C14
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AJ4
AF1
AJ3
AJ5
AJ6
AJ7
AJ9
A13
A14
AJ2
AJ8
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
VTT_SENSE 34
VTT_SENSE
MEMVREF1
MEMZN
MEMZP
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
U7B
RSVD_MEMADDA15
RSVD_MEMADDA14
RSVD_MEMADDB15
RSVD_MEMADDB14
MEMORY INTERFACE
VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4
MEMRESET_L
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
4
D17
A18
B17
C17
AF16
AG16
AH16
AJ17
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
VTT_DDR_SUS
MCKE0
MCKE1
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
MCKE0 8,9
MCKE1 8,9
MEMCLK_H7 8,9
MEMCLK_L7 8,9
MEMCLK_H6 8,9
MEMCLK_L6 8,9
MEMCLK_H5 8,9
MEMCLK_L5 8,9
MEMCLK_H4 8,9
MEMCLK_L4 8,9
MEMCLK_H1 8,9
MEMCLK_L1 8,9
MEMCLK_H0 8,9
MEMCLK_L0 8,9
-MCS3 8,9
-MCS2 8,9
-MCS1 8,9
-MCS0 8,9
-MSRASA 8,9
-MSCASA 8,9
-MSWEA 8,9
MEMBANKA1 8,9
MEMBANKA0 8,9
MAA[13..0] 8,9
-MSRASB 8,9
-MSCASB 8,9
-MSWEB 8,9
MEMBANKB1 8,9
MEMBANKB0 8,9
MAB[13..0] 8,9
CADIP[0..15]11
CLKIP111
CLKIN111
CLKIP011
CLKIN011
CTLIP011
CTLIN011
3
VLDT0
R57 49.9RST
R51 49.9RST
5
4
3
VCCA_PLL trace length from the VR1 to the
PGA must be 0.75".
2
1
Place al filters close to the PGA.
Keep all power and signal trce away from
the VR1.
Place a cut in the GND plane around the
D D
LAYOUT: Route VDDA trace approx.
50 mils wide (use 2x25 mil traces to
exit ball field) and 500 mils long.
VDDA_25
FB1 180nH/1210
C28
0.22u
CPU_VDDA_25
C48
4.7u/0805
C63
3300p
1K
Q28
2N7002S
VCC2_5
+
EC11
22U/6.3V/S
-LDTSTOP
PS_ON#A36
PS_ON#A
R139
VCCA_PLL regulator circuit.
C56
0.22u
VCC2_5
R137
Near SB/VT8235
Q26
X_2N3904S
1K
R138
X_4.7K
VCC2_5
THRM# 17,30
AH25
C35
X_102P
CPU_GD36
R58 44.2RST
C C
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
B B
DBREQ_L
DBRDY
TMS
TCK
TRST_L
TDI
NC_AJ18
NC_AG17
NC_C19
NC_D18
A A
NC_D20
NC_B19
NC_C21
5
R44 330
R45 330
1 2
3 4
5 6
7 8
RN42 330X4
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R92 1K
VLDT0
VLDT04
R55 44.2RST
8/28 AMD CHANGE THE PULL-UP POWER
VCC2_5
C33
0.22u
RN5
8P4R-1K
8P4R-1K
RN52
4
C60
102P
VDD_25_SUS
102P
C61
-CPURST36
-LDTSTOP11,18
COREFB_H14
COREFB_L14
Differential , "10:10:5:10:10" .
VDDIO_SENSE34
CPUCLK0_H7
Near CPU in 0.5" .
CPUCLK0_L7
C57 3900P/X7R
C65 3900P/X7R
VTT_DDR_SUS
VCC2_5
3
L0_REF1
L0_REF0
R54
R53 820
R49 820
R93 1K
R89 1K
CPU_GD
VDDIO_SENSE
169RST
RN3
1 2
3 4
5 6
7 8
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
DBRDY
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
NC_AE23
NC_AF23
NC_AF22
NC_AF21
8P4R-1K
AJ25
AF20
AE18
AJ27
AF27
AE26
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
AG15
AH17
AJ28
AE23
AF23
AF22
AF21
AG2
AH1
AE21
AG4
AG6
AE9
AG9
A23
A24
B23
C16
C15
E20
E17
B21
A21
C18
A19
A28
AA2
B18
C20
C1
R3
D3
C6
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A5
VTT_B5
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
FREE29
J3
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40
U7C
THERMTRIP_L
THERMDA
THERMDC
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
G_FBCLKOUT_H
G_FBCLKOUT_L
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
NC_AF18
RSVD_SCL
RSVD_SDA
FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27
2
THERMTRIP_CPU_L
A20
THERMDA_CPU
A26
A27
VID4
AG13
VID3
AF14
VID2
AG14
VID1
AF15
VID0
AE15
AG18
AH18
NC_AG17
AG17
NC_AJ18
AJ18
FBCLKOUT_H
AH19
AJ19
AE19
D20
C21
D18
C19
B19
A22
AF18
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
R59
80.6RST
FBCLKOUT_L
Zdiff = 80 ohm
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
THERMDA_CPU 31
VID[4..0] 14
LAYOUT: Route
FBCLKOUT_H/L d if fe re n ti al ly
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )
8/28 AMD CHANGE THE PULL-UP POWER
VDD_25_SUS
R102 330
RN1
VID3
7 8
VID2
5 6
VID1
3 4
VID0
1 2
X_8P4R-4.7K
R7 X_4.7K
VID4
K8 HDT & MISC
MS-6750
Last Revision Date:
Wednesday, January 29, 2003
Sheet
1
VCC2_5
C2
104P
Rev
0A
540
of
5
4
3
2
1
U7E
B2
VSS1
AH20
VSS3
AB21
VSS4
W22
VSS5
M23
VSS6
L24
VSS7
AG25
VSS8
AG27
VSS9
D D
C C
B B
A A
AF2
AA8
AB9
AA10
AE16
G20
R20
U20
W20
AA20
AC20
AE20
AG20
AJ20
D21
H21
M21
AD21
AG21
G22
N22
R22
U22
AG29
AA22
AC22
AG22
AH22
AJ22
D23
H23
AB23
AD23
AG23
G24
N24
R24
U24
W24
AA24
AC24
AG24
AJ24
C25
D26
H26
M26
AD26
AF26
AH26
C27
D28
G28
H15
AB17
AD17
G18
AA18
AC18
D19
H19
AB19
AD19
AF19
N20
D2
VSS10
VSS11
W6
VSS12
Y7
VSS13
VSS14
VSS15
VSS16
J12
VSS17
B14
VSS18
Y15
VSS19
VSS20
J18
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
F21
VSS32
VSS33
K21
VSS34
VSS35
P21
VSS36
T21
VSS37
V21
VSS38
Y21
VSS39
VSS40
VSS41
B22
VSS42
E22
VSS43
VSS44
J22
VSS45
L22
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
F23
VSS57
VSS58
K23
VSS59
P23
VSS60
T23
VSS61
V23
VSS62
Y23
VSS63
VSS64
VSS65
VSS66
E24
VSS67
VSS68
J24
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
B25
VSS78
VSS79
B26
VSS80
VSS81
VSS82
VSS83
T26
VSS84
Y26
VSS85
VSS86
VSS87
VSS88
VSS89
B28
VSS90
VSS91
VSS92
F15
VSS187
VSS188
VSS206
VSS207
B16
VSS208
VSS209
VSS210
VSS211
VSS212
F19
VSS213
VSS214
K19
VSS215
Y19
VSS216
VSS217
VSS218
VSS219
J20
VSS220
L20
VSS221
VSS222
GROUND
5
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
EMI
VCORE
AC15
AB14
AA15
AB16
AA17
AC17
AE17
AB18
AD18
AG19
AC19
AA19
AB20
AD20
W21
AA21
AC21
M22
AB22
AD22
G23
W23
AA23
AC23
M24
AB24
AD24
AH24
AE25
GNDGND
H18
B20
E21
H22
H24
F26
V10
G13
K14
Y14
G15
H16
K16
Y16
G17
F18
K18
Y18
E19
G19
F20
H20
K20
M20
P20
T20
V20
Y20
G21
N21
R21
U21
F22
K22
P22
T22
V22
Y22
E23
N23
R23
U23
B24
D24
F24
K24
P24
T24
V24
Y24
K26
P26
V26
U7D
L7
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
J23
VDD7
VDD8
VDD9
N7
VDD10
L9
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
J15
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
J17
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD39
VDD38
J19
VDD37
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
J21
VDD51
L21
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
L23
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76
VDD77
VDD78
VDD79
VDD80
VDD81
VDD82
VDD83
VDD84
VDD85
VDD86
VDD87
VDD88
VDD89
VDD90
VDD91
VDD92
POWER
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50
VDDIO6
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD93
VDD94
VDD95
VDD_25_SUS
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
4
VCORE
LAYOUT: Place 6 EMI capsalong bottom right sid e of Clawhammer, 2 in middle
of HT link, and 12 along
VCORE
C464
C459
6.8pF/BOT
6.8pF/BOT
bottom left side of Claw-
C470
C461
C462
6.8pF/BOT
6.8pF/BOT
hammer.
C472
C460
6.8pF/BOT
6.8pF/BOT
C468
C469
6.8pF/BOT
C471
6.8pF/BOT
6.8pF/BOT
6.8pF/BOT
GND
LAYOUT: Place beside processor.
VDD_25_SUS
C74
0.22u
C151
C201
0.22u
0.22u
C228
VDD_25_SUS VDD_25_SUS
C47
4.7u/0805
C122
4.7u/0805
C156
4.7u/0805
GND
3
0.22u
C137
0.22u
C219
0.22uF
C142
GND
C100
GND
0.22u
0.22uF
2
LAYOUT: Place 1 capacitor every 1-1.5"
along VDD_CORE perimiter.
VCORE
C92
102P
C115
6.8pF
C110
102P
C106
102P
C101
GND
VCORE
C71
102P
102P
C175
GND
LAYOUT: Place 1000pF capacitors
between VRM & CPU.
LAYOUT: Place beside DDR slots.
VDD_25_SUS
C72
0.22uF
C127
GND
0.22uF
VDD_25_SUS
C114
4.7u/0805
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
102P
C174
4.7u/0805
GND
Micro Star Restricted Secret
K8 POWER & GND
MS-6750
Last Revision Date:
Wednesday, January 29, 2003
Sheet
640
1
of
Rev
0A
5
Clock Synthesizer
D D
C C
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
CLKVCC3
C307 104P
C301 104P
C318 104P
C315 104P
C325 104P
C322 104P
C312 104P
C309 104P
U21
46
VDD_46
47
VSS_47
2
VDD_2
5
VSS_5
32
VDDF
33
VSSF
9
VDD_9
10
VSS_10
16
VDD_16
15
VSS_15
19
VDD_19
20
VSS_20
29
VDD_29
30
VSS_30
27
VSS_27
38
VDD_38
39
VSS_39
35
VDD_35
34
VSS_34
43
VDDA
42
VSSA
PCI33_HT66SEL
CY28331
FS0/REF0
FS1/REF1
FS2/REF2
XOUT
48MHZ
PCI33_HT66_0
PCI33_HT66_1
PCI33_HT66_2
PCI33_7
PCI33_0
PCI33_1
PCI33_2
PCI33_3
PCI33_F
PCI33_4
PCI33_5
24_48MHZ/SEL
SDATA
SCLK
CPUT_0
CPUC_0
CPUT_1
CPUC_1
PCISTOP
SPREAD
4
VCC3
FB8 X_120S/0805
C333
104P
FS0
1
FS1
48
FS2
45
CLKX1
3
XIN
CLKX2
4
31
HT_66_0
7
HT_66_1
8
HT_66_2
11
12
13
14
17
18
FS3
23
21
22
SEL_24
28
SMBDATA1
26
SMBCLK1
25
41
40
R266 15RST
37
R267 15RST
36
SEL_66
6
24
SPREAD
44
CP14
X_COPPER
R236 22
R238 22
R250 22
R269 33
RN76
7 8
5 6
3 4
RN84
1 2
7 8
5 6
3 4
1 2
RN87 8P4R-22
7 8
5 6
3 4
1 2
R275 33
R284 10K
R253 10K
CLKVCC3
X1 14.318MHZ
SB_OSC14
AUD_CLK
APICCLK
C303 10P
C304 10P
8P4R-22
8P4R-22
CPUCLK0_H
CPUCLK0_L
CLKVCC3
C331
39P
USBCLK_SB48MHz
VCLK
GCLK_SLOT
GCLK_NB
LPC_PCLK
1394_PCLK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
SB_PCLK
SIO48M
SMBDATA1 8,17,27
SMBCLK1 8,17,27
CPUCLK0_H 5
CPUCLK0_L 5
C334
4.7u/0805
3
SB_OSC14 17
AUD_CLK 23
APICCLK 18
USBCLK_SB 16
VCLK 18
GCLK_SLOT 15
GCLK_NB 12
LPC_PCLK 30
1394_PCLK 22
PCICLK1 19
PCICLK2 19
PCICLK3 20
PCICLK4 20
PCICLK5 21
SB_PCLK 18
SIO48M 30
AUD_CLK
VCLK
GCLK_SLOT
GCLK_NB
USBCLK_SB
SIO48M
SB_OSC14
APICCLK
SB_PCLK
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
1394_PCLK
LPC_PCLK
CPUCLK0_H
CPUCLK0_L
SEL_24
FS3
FS0
FS2
FS1
HT_66_0
SEL_66
C305 X_10P
CN22
7 8
5 6
3 4
1 2
X_8P4C-10P
C320 X_10P
C326 X_10P
C302 X_10P
C308 X_10P
CN24
1 2
3 4
5 6
7 8
CN23
1 2
3 4
5 6
7 8
C313 X_5P
C316 X_5P
R280 10K
R288 10K
R239 X_10K
R245 X_10K
R235 X_10K
R243 10K
R244 10K
X_8P4C-10P
X_8P4C-10P
2
1
R240 10K
FS0
R241 10K
FS2
R237 10K
FS1
R279 X_10K
FS3
B B
A A
Input Configuration
FS0
FS1
FS2
1
1
1
1
1
1
0
0
1-
0
1
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X 24 or 48100,133.33,166.66,200
5
1
0
1
0
1
0
1
1
0
X
X
X
X
X
X
X
X
PCI_HT#
X
X
X
X
X
1
0
X
0
1
X
X
0
0
1
1
PCISTOP#
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
Clock Generator Output
24_48SEL#
X
X
X
X
CPU (MHz)
200
166.66
133.330
100
X
X
X
X
X
X
X
1
0
X
X
X
--
X1 input
X1 input
Hi-Z
100,133.33,166.66,200
100,133.33,166.66,200
100,133.33,166.66,200
100,133.33,166.66,200
100,133.33,166.66,200
100,133.33,166.66,200
100,133.33,166.66,200X
X
4
PCI33 (MHz)
33.33
33.33
33.33
33.33
-
ÂX1/6
X1/6
Hi-Z
33.33
33.33
33.33 24
33.33
0
33.33
0
33.33
PCI33_HT66 (MHz)
33.33 or 66.66
33.33 or 66.66
33.33 or 66.66
33.33 or 66.66
-
X1/6
X1/3
Hi-Z
66.66
33.33
33.33 or 66.66
33.33 or 66.66
66.66
66.66
0
33.33
24_48 (MHz)
24 or 48
24 or 48
24 or 48
24 or 48
-
Â0
0
Hi-Z
24 or 48
24 or 48
48
24 or 48
24 or 48
24 or 48
3
14.318 (MHz)
14.318
14.318
14.318
14.318
-X
Â0
0
Hi-Z
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
CLKVCC3
Comment
Normal Hammer operation
Reserved
Athlon compatible
Athlon compatible
Reserved
Reserved
Bypass mode
Bypass mode
Tri-state mode
33.33 vs. 66.66 MHz output select
33.33 vs. 66.66 MHz output select
24 vs. 48 MHz output select
24 vs. 48 MHz output select
PCISTOP vs. 33.33/66.66 MHz selects
PCISTOP vs. 33.33/66.66 MHz selects
PCISTOP vs. 33.33/66.66 MHz selects
PCISTOP vs. 33.33/66.66 MHz selects
2
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
Clock Synthesizer
MS-6750
Last Revision Date:
Wednesday, January 29, 2003
Sheet
1
740
Rev
0A
of
5
DR_MD[63..0]9,10
D D
C C
B B
DR_MD[63..0]
VDD_25_SUS
DDR_VREF
R143 4.7K
-MSWEA4,9
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP1
-MSWEA
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
Place 104p Cap. near the DIMM
VDD_25_SUS
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
SLAVE ADDRESS = 1010000B
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
3111826344250586674818993
4
SYSTEM MEMORY
104
112
128
136
143
156
164
172
1801582
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
184
PIN
DDR DIMM
SOCKET
NC(RESET#)
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
100
116
124
132
139
145
152
160
176
VDDID
VDDQ15
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VSS21
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
157
158
71
163
5
14
25
36
56
67
78
86
47
MAA13
167
MAA0
48
MAA1
43
MAA2
41
MAA3
130
MAA4
37
MAA5
32
MAA6
125
MAA7
29
MAA8
122
MAA9
27
MAA10
141
MAA11
118
MAA12
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
MEMCLK_H5
16
MEMCLK_L5
17
MEMCLK_H0
137
MEMCLK_L0
138
MEMCLK_H7
76
MEMCLK_L7
75
173
10
MCKE0
21
MCKE1
111
-MSCASA
65
-MSRASA
154
DR_MEMDM0
97
DR_MEMDM1
107
DR_MEMDM2
119
DR_MEMDM3
129
DR_MEMDM4
149
159
DR_MEMDM6
169
DR_MEMDM7
177
140
DDR1
DDRDIMM_184
-MCS0
-MCS1
-DR_MDQS0
-DR_MDQS1
-DR_MDQS2
-DR_MDQS3
-DR_MDQS4
-DR_MDQS5
-DR_MDQS6
-DR_MDQS7
SMBCLK1
SMBDATA1
-MCS0 4,9
-MCS1 4,9
-DR_MDQS0 9,10
-DR_MDQS1 9,10
-DR_MDQS2 9,10
-DR_MDQS3 9,10
-DR_MDQS4 9,10
-DR_MDQS5 9,10
-DR_MDQS6 9,10
-DR_MDQS7 9,10
MAA[13..0]
MAA[13..0] 4,9
MEMBANKA0 4,9
MEMBANKA1 4,9
SMBCLK1 7,17,27
SMBDATA1 7,17,27
MEMCLK_H5 4,9
MEMCLK_L5 4,9
MEMCLK_H0 4,9
MEMCLK_L0 4,9
MEMCLK_H7 4,9
MEMCLK_L7 4,9
MCKE0 4,9
MCKE1 4,9
-MSCASA 4,9
-MSRASA 4,9
DR_MEMDM[7..0]
3
VDD_25_SUS
Place 104p and 1000p
Cap. near the DIMM
DR_MEMDM[7..0] 9,10
R144 4.7K
-MSWEB4,9
C32
104P
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP2
-MSWEB
DDR_VREF
C25
1000P
2
VDD_25_SUS
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VDDQ2
VSS8
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
SLAVE ADDRESS = 1010001B
102
NC4
VSS0
VSS1
3111826344250586674818993
104
112
128
136
143
156
164
172
1801582
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
184
PIN
DDR DIMM
SOCKET
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC(RESET#)
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
100
116
124
132
139
145
152
160
176
VDDID
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
157
158
71
163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86
47
MAB13
167
MAB0
48
MAB1
43
MAB2
41
MAB3
130
MAB4
37
MAB5
32
MAB6
125
MAB7
29
MAB8
122
MAB9
27
MAB10
141
MAB11
118
MAB12
115
103
59
52
113
SMBCLK1
92
SMBDATA1
91
181
182
183
44
45
49
51
134
135
142
144
MEMCLK_H4
16
MEMCLK_L4
17
MEMCLK_H1
137
MEMCLK_L1
138
MEMCLK_H6
76
MEMCLK_L6
75
173
10
MCKE0
21
MCKE1
111
-MSCASB
65
-MSRASB
154
DR_MEMDM0
97
DR_MEMDM1
107
DR_MEMDM2
119
DR_MEMDM3
129
DR_MEMDM4
149
DR_MEMDM5DR_MEMDM5
159
DR_MEMDM6
169
DR_MEMDM7
177
140
DDR2
DDRDIMM_184
-MCS2
-MCS3
1
VDD_25_SUS
-MCS2 4,9
-MCS3 4,9
MAB[13..0] 4,9
MEMBANKB0 4,9
MEMBANKB1 4,9
MEMCLK_H4 4,9
MEMCLK_L4 4,9
MEMCLK_H1 4,9
MEMCLK_L1 4,9
MEMCLK_H6 4,9
MEMCLK_L6 4,9
-MSCASB 4,9
-MSRASB 4,9
VDD_25_SUS
A A
R43
1KST
R40
1KST
C38
104P
DDR_VREF
C26
104P
5
DDR_VREF 4
Micro Star Restricted Secret
Title
Document Number
4
3
2
System Memory : DDR DIMM 1
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
MS-6750
Last Revision Date:
Wednesday, January 29, 2003
Sheet
1
840
Rev
0A
of
5
4
3
2
1
RN48 47X4
7 8
5 6
3 4
1 2
RN46 47X4
7 8
5 6
3 4
1 2
RN44 47X4
7 8
5 6
3 4
1 2
RN41 47X4
7 8
5 6
3 4
1 2
RN39 47X4
7 8
5 6
3 4
1 2
RN37 47X4
7 8
5 6
3 4
1 2
RN35 47X4
7 8
5 6
3 4
1 2
RN32 47X4
7 8
5 6
3 4
1 2
RN29 47X4
7 8
5 6
3 4
1 2
RN27 47X4
7 8
5 6
3 4
1 2
RN25 47X4
7 8
5 6
3 4
1 2
VTT_DDR_SUS
MEMCLK_L6
VTT_DDR_SUSVTT_DDR_SUS
MAB7
MAB9
MAA9
MAA11
DR_MD23
MAB8
MAA7
DR_MD22
DR_MD18
MAA12
DR_MEMDM2
MAB11
DR_MD21
-DR_MDQS2
DR_MD17
MAB12
DR_MD16
DR_MD20
MCKE0
MCKE04,8
MCKE1
MCKE14,8
DR_MD11
DR_MD10
DR_MD15
DR_MD14
DR_MEMDM1
DR_MD13
-DR_MDQS1
DR_MD12
DR_MD9
DR_MD8
DR_MD3
DR_MD7
DR_MD6
DR_MD2
-DR_MDQS0
DR_MEMDM0
DR_MD1
DR_MD5
DR_MD4
DR_MD0
DR_MD[63..0]8,10
MAB[13..0]4,8
MAA[13..0]4,8
DR_MEMDM[7..0]8,10
-DR_MDQS[7..0]8,10
RN22 47X4
7 8
5 6
3 4
1 2
RN24 47X4
7 8
5 6
3 4
1 2
RN19 47X4
7 8
5 6
3 4
1 2
RN17 47X4
7 8
5 6
3 4
1 2
RN14 47X4
7 8
5 6
3 4
1 2
RN12 47X4
7 8
5 6
3 4
1 2
RN10 47X4
7 8
5 6
3 4
1 2
RN8 47X4
7 8
5 6
3 4
1 2
RN6 47X4
7 8
5 6
3 4
1 2
RN4 47X4
7 8
5 6
3 4
1 2
DR_MD[63..0]
MAB[13..0]
MAA[13..0]
DR_MEMDM[7..0]
-DR_MDQS[7..0]
MCKE1
MCKE0
MAB12
MAA12
MAB11
MAA11
MAA9
MAB9
MAB7
MAA7
MAB8
MAA8
MAA5
MAB5
MAB6
MAA6
MAB4
MAA4
MAB3
MAA3
MAB2
MAA2
MAB1
MAA1
MAA0
MAA10
MAB0
MAB10
MEMBANKB1
MEMBANKA1
MEMBANKB0
MEMBANKA0
-MSRASA
-MSRASB
-MSWEA
-MSWEB
-MCS0
-MSCASB
-MSCASA
-MCS1
-MCS3
-MCS2
MAB13
MAA13
CN3
8P4C-22P
CN4
8P4C-22P
CN5
8P4C-22P
CN7
8P4C-22P
CN8
8P4C-22P
CN10
8P4C-22P
CN12
8P4C-22P
CN13
8P4C-22P
CN15
8P4C-22P
CN17
8P4C-22P
CN19
8P4C-22P
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
DDR Terminations
DR_MD59
DR_MD63
D D
C C
B B
-MSCASA4,8
-MSCASB4,8
-MSRASB4,8
-MSRASA4,8
MEMCLK_H5
DR_MD58
DR_MD62
-DR_MDQS7
DR_MEMDM7
DR_MD57
DR_MD61
DR_MD56
DR_MD60
DR_MD51
DR_MD55
DR_MD50
DR_MD54
-DR_MDQS6
DR_MEMDM6
MAA13
MAB13
DR_MD53
DR_MD52
DR_MD49
DR_MD48
DR_MD47
DR_MD46
DR_MD43
DR_MD42
DR_MEMDM5
-DR_MDQS5
-MCS2
-MCS24,8
-MCS3
-MCS34,8
-MCS1
-MCS14,8
-MSCASA
DR_MD41
-MSWEB
-MSWEB4,8
-MSCASB
-MCS0
-MCS04,8
DR_MD45
-MSWEA4,8
-MSWEA
-MSRASB
-MSRASA
DR_MD44
R62 120RST
R147 47
RN73 47X4
7 8
5 6
3 4
1 2
RN70 47X4
7 8
5 6
3 4
1 2
RN67 47X4
7 8
5 6
3 4
1 2
RN64 47X4
7 8
5 6
3 4
1 2
RN61 47X4
7 8
5 6
3 4
1 2
RN58 47X4
7 8
5 6
3 4
1 2
RN55 47X4
7 8
5 6
3 4
1 2
RN54 47X4
7 8
5 6
3 4
1 2
RN51 47X4
7 8
5 6
3 4
1 2
RN49 47X4
7 8
5 6
3 4
1 2
MEMCLK_L5
MEMBANKA04,8
MEMBANKB04,8
MEMBANKA14,8
MEMBANKB14,8
MEMCLK_H6
DR_MD40
DR_MD39
DR_MD35
MEMBANKA0
MEMBANKB0
DR_MD38
DR_MD34
DR_MEMDM4
-DR_MDQS4
DR_MD37
DR_MD33
DR_MD36
DR_MD32
MEMBANKA1
MEMBANKB1
MAB10
MAB0
MAA10
MAA0
MAA1
MAB1
MAA2
MAB2
DR_MD31
DR_MD27
DR_MD30
DR_MD26
MAA3
MAB3
DR_MEMDM3
MAA4
-DR_MDQS3
DR_MD25
MAB4
MAA6
DR_MD29
DR_MD28
MAB6
MAB5
MAA5
MAA8
DR_MD24
DR_MD19
R133 120RST
A A
MEMCLK_H4
MEMCLK_H7
R63 120RST
R131 120RST
5
MEMCLK_L4
MEMCLK_L7
MEMCLK_H0
R88 120RST
R90 120RST
4
MEMCLK_L1MEMCLK_H1
MEMCLK_L0
3
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCLK_H7 4,8
MEMCLK_L7 4,8
MEMCLK_H6 4,8
MEMCLK_L6 4,8
MEMCLK_H5 4,8
MEMCLK_L5 4,8
MEMCLK_H4 4,8
MEMCLK_L4 4,8
MEMCLK_H1 4,8
MEMCLK_L1 4,8
MEMCLK_H0 4,8
MEMCLK_L0 4,8
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
DDR Terminations Ba nk 0
MS-6750
Last Revision Date:
Wednesday, January 29, 2003
Sheet
940
1
Rev
0A
of
5
4
3
2
1
LAYOUT: Place on backside,
DDR Terminations
D D
C C
B B
RN9 8P4R-10
MD0
1 2
MD4
3 4
MD5
5 6
MD1
7 8
RN11 8P4R-10
MEMDM0 DR_MEMDM0
1 2
-MDQS0
3 4
MD2
5 6
MD6
7 8
RN13 8P4R-10
MD7
1 2
MD3
3 4
MD8
5 6
MD9
7 8
RN15 8P4R-10
MD12
1 2
-MDQS1 -DR_MDQS1
3 4
MD13
5 6
MEMDM1
7 8
RN18 8P4R-10
MD14
1 2
MD15
3 4
MD10
5 6
MD11
7 8
RN23 8P4R-10
MD21 DR_MD21
1 2
MEMDM2 DR_MEMDM2
3 4
MD18 DR_MD18
5 6
MD22 DR_MD22
7 8
RN21 8P4R-10
MD20
1 2
MD16
3 4
-MDQS2
5 6
MD17
7 8
RN26 8P4R-10
MD23
1 2
MD19 DR_MD19
3 4
MD24
5 6
MD28 DR_MD28
7 8
RN30 8P4R-10
MD29
1 2
MD25
3 4
-MDQS3
5 6
MEMDM3 DR_MEMDM3
7 8
DR_MD0
DR_MD4
DR_MD5
DR_MD1
-DR_MDQS0
DR_MD2
DR_MD6
DR_MD7
DR_MD3
DR_MD8
DR_MD9
DR_MD12
DR_MD13
DR_MEMDM1
DR_MD14
DR_MD15
DR_MD10
DR_MD11
DR_MD20
DR_MD16
-DR_MDQS2
DR_MD17
DR_MD23
DR_MD24
DR_MD29
DR_MD25
-DR_MDQS3
RN34 8P4R-10
MD26
1 2
MD30
3 4
MD27
5 6
MD31
7 8
RN43 8P4R-10
MD32
1 2
MD36
3 4
MD33
5 6
MD37
7 8
RN45 8P4R-10
-MDQS4 -DR_MDQS4
1 2
MEMDM4 DR_MEMDM4
3 4
MD34 DR_MD34
5 6
MD38 DR_MD38
7 8
RN47 8P4R-10
MD35 DR_MD35
1 2
MD39
3 4
MD40
5 6
MD44
7 8
RN50 8P4R-10
MD45
1 2
MD41
3 4
-MDQS5 -DR_MDQS5
5 6
MEMDM5 DR_MEMDM5
7 8
RN53 8P4R-10
MD42 DR_MD42
1 2
MD43
3 4
MD46 DR_MD46
5 6
MD47
7 8
RN56 8P4R-10
MD48 DR_MD48
1 2
MD49
3 4
MD52 DR_MD52
5 6
MD53 DR_MD53
7 8
RN60 8P4R-10
MEMDM6
1 2
-MDQS6
3 4
MD54
5 6
MD50 DR_MD50
7 8
RN62 8P4R-10
MD55
1 2
MD51
3 4
MD60
5 6
MD56 DR_MD56
7 8
RN66 8P4R-10
MD61
1 2
MD57
3 4
MEMDM7 DR_MEMDM7
5 6
-MDQS7 -DR_MDQS7
7 8
RN69 8P4R-10
MD62 DR_MD62
1 2
MD58
3 4
MD63
5 6
MD59
7 8
DR_MD26
DR_MD30
DR_MD27
DR_MD31
DR_MD32
DR_MD36
DR_MD33
DR_MD37
DR_MD39
DR_MD40
DR_MD44
DR_MD45
DR_MD41
DR_MD43
DR_MD47
DR_MD49
DR_MEMDM6
-DR_MDQS6
DR_MD54
DR_MD55
DR_MD51
DR_MD60
DR_MD61
DR_MD57
DR_MD58
DR_MD63
DR_MD59
evenly spaced around VTT fill.
VDD_25_SUS
VTT_DDR_SUS
C43
X_0.22uF
C177
X_0.22uF
C226
X_0.22uF
C225
X_0.22uF
C37
X_0.22uF
VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS
C36
104P
C55
104P
C67
104P
C70
104P
C77
104P
C82
104P
VTT_DDR_SUS
C42
104P
104P
C31
VTT_DDR_SUS
104P
C155
104P
C150
C59
C158
104P
104P
C69
C162
104P
104P
C73
C165
104P
104P
C91
104P
C99
104P
C109
104P
C116
104P
C120
104P
C123
104P
C126
104P
C78
C169
104P
104P
LAYOUT: Locate close to Cla wham mer soc ket .
VTT_DDR_SUS
C54
4.7U/1206
GND
C85
C176
104P
104P
C93
C180
104P
104P
C103
C182
C129
104P
C136
104P
C143
104P
C148
104P
C152
104P
C157
104P
C161
104P
104P
104P
C113
C187
104P
104P
C118
C198
104P
104P
C121
C204
104P
104P
C164
104P
C168
104P
C171
104P
C178
104P
C181
104P
C185
104P
C193
104P
C125
C208
C40
0.22u
VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUS
C202
104P
C206
104P
C209
104P
C211
104P
C213
104P
C220
104P
104P
104P
104P
C128
C210
104P
C132
C212
104P
104P
C138
C217
104P
104P
C145
GND
C222
104P
104P
LAYOUT: Place alternating caps to GND and VDD_2.5_SUS
GND
in a single line along VTT island.
LAYOUT: Add 100pF and 1000pF on VTT fill near
Clawhammer and near DIMMs (both sides).
5
-MDQS[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MD[63..0]
MEMDM[7..0]
DR_MEMDM[7..0]
4
-MDQS[7..0]4
-DR_MDQS[7..0]8,9
A A
DR_MD[63..0]8,9
MD[63..0]4
MEMDM[7..0]4
DR_MEMDM[7..0]8,9
VTT_DDR_SUS
3
C144
4.7u/0805
C179
4.7u/0805
C205
4.7u/0805
C34
4.7u/0805
C242
4.7u/0805
GND
2
VTT_DDR_SUS
102P
C232
C231
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
VTT_DDR_SUS
C58
C50
102P
GND
102P
C147
GND
0.22u
100P
Micro Star Restricted Secret
DDR Terminations Ba nk 1
MS-6750
Last Revision Date:
Wednesday, January 29, 2003
Sheet
10 40
1
of
Rev
0A
A
B
C
D
E
PIN C22 FOR K8M400 (3.3V)
K8T400M HT Interface
VDD_12_A
A10
A24
A25
A26A9B10
T26
P24
P26
M24
K24
K26
H24
H26
R24
R22
N24
N22
L22
G24
M26
L24
F24
R26
P25
N26
M25
K25
H25
G26
R23
P22
N23
M22
K22
H22
G23
L26
L23
F25
B11
A12
D25
D26
C26
U24
U25
U26
V21
V22
V23
V24
V25
V26
C22
AVDD2
RCADP0
RCADP1
RCADP2
RCADP3
RCADP4
RCADP5
RCADP6
RCADP7
RCADP8
RCADP9
RCADP10
RCADP11
RCADP12
J24
RCADP13
J22
RCADP14
RCADP15
RCLKP0
RCLKP1
RCTLP
RCADN0
RCADN1
RCADN2
RCADN3
RCADN4
J26
RCADN5
RCADN6
RCADN7
RCADN8
RCADN9
RCADN10
RCADN11
RCADN12
J23
RCADN13
RCADN14
RCADN15
RCLKN0
RCLKN1
RCTLN
LDTRST
LDTSTP
RPCOMP
RNCOMP
RTCOMP
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
AGND2
VSS
C21
J18
From Claw Hammer
4 4
CADOP[0..15]4
CLKOP04
CLKOP14
CTLOP04
CADON[0..15]4
3 3
CLKON04
CLKON14
CTLON04
-LDTRST36
-LDTSTOP5,18
2 2
CADOP0
CADOP1
CADOP2
CADOP3
CADOP4
CADOP5
CADOP6
CADOP7
CADOP8
CADOP9
CADOP10
CADOP11
CADOP12
CADOP13
CADOP14
CADOP15
CLKOP0
CLKOP1
CTLOP0
CADON0
CADON1
CADON2
CADON3
CADON4
CADON5
CADON6
CADON7
CADON8
CADON9
CADON10
CADON11
CADON12
CADON13
CADON14
CADON15
CLKON0
CLKON1
CTLON0
-LDTRST
-LDTSTOP
RPCOMP
PNCOMP
RTCOMP
VDD_12_A
B23
B24
B25
B26B9C10
C11
C23
C24
C25C9D10
D11
D22
D23
D24D9E10
E11
E21
E22
E23
E24E9F10
F11
F15
F16
F19
F20
F21
F22
F23
G21
G22
H21
J11
J12
J13
J14
J15
J16
J10
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A8
B15
A23
B8
B13
B17
B19
VSS
B21
B22C8D8
VSS
VSS
VSS
VSS
VSS
D6
D18
D20
E5E6E8F7F8
D12
D14
D16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F18
F26
VSS
G25H1H23
VSS
J2
J3
VSS
F13
F14
F17
F12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K12
J21
J25
K4G1K10
K13
K14
K11
J17
K18
K21
L18
U14A
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
TCADP0
TCADP1
TCADP2
TCADP3
TCADP4
TCADP5
TCADP6
TCADP7
TCADP8
TCADP9
TCADP10
TCADP11
TCADP12
TCADP13
TCADP14
TCADP15
TCLKP0
TCLKP1
TCTLP
TCADN0
TCADN1
TCADN2
TCADN3
TCADN4
TCADN5
TCADN6
TCADN7
TCADN8
TCADN9
TCADN10
TCADN11
TCADN12
TCADN13
TCADN14
TCADN15
TCLKN0
TCLKN1
TCTLN
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VSS
VSS
VSS
VSS
VSS
K17
K23H2L10
VSS
VSS
VSS
VSS
L11
L13
L12
L14
L15
L16
VSS
K16
K15
B12
A13
B14
A15
A17
B18
A19
B20
E12
D13
E14
D15
D17
E18
D19
E20
B16
E16
A21
C12
A14
C14
A16
A18
C18
A20
C20
E13
C13
E15
C15
C17
E19
C19
D21
CLKIN0
C16
CLKIN1
E17
CTLIN0
A22
L21
M18
N18
N21
P18
P21
R18
T18
T21
T22
T23
T24
T25
U18
U21
U22
U23
VSS
K8M400/K8T400M
CADIP0
CADIP1
CADIP2
CADIP3
CADIP4
CADIP5
CADIP6
CADIP7
CADIP8
CADIP9
CADIP10
CADIP11
CADIP12
CADIP13
CADIP14
CADIP15
CLKIP0
CLKIP1
CTLIP0
CADIN0
CADIN1
CADIN2
CADIN3
CADIN4
CADIN5
CADIN6
CADIN7
CADIN8
CADIN9
CADIN10
CADIN11
CADIN12
CADIN13
CADIN14
CADIN15
VDD_12_A
To Claw Hammer
CADIP[0..15] 4
CLKIP0 4
CLKIP1 4
CTLIP0 4
CADIN[0..15] 4
CLKIN0 4
CLKIN1 4
CTLIN0 4
PNCOMP
RTCOMP
RPCOMP
VDD_12_A
C194 104P
C191 104P
Around NB
VDD_12_A
R121 49.9RST
R115 100RST
R120 49.9RST
1 1
Title
Size Document Number Rev
C
A
B
C
D
Date: Sheet
MICRO-STAR INT'L CO ., LTD.
NORTH BRIDGE K8T400M (HT)
MS-6750
0A
11 40Wednesday, January 29, 2003
E
of
A
B
K8T400M AGP 8X ,V-Link, Misc. Control
VDDQ
C
D
E
4 4
GAD[31..0]15
3 3
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC/BE#[3..0]15
AD_STBS015
AD_STBF015
AD_STBS115
AD_STBF115
GFRAME15
GIRDY15
GTRDY15
GDEVSEL15
GSTOP15
GPAR15
RBF15
WBF15
GREQ15
2 2
GGNT15
GSERR15
GCLK_NB7
SBA[7..0]15
1 1
SBA[7..0]
SB_STBS15
SB_STBF15
ST[2..0]
ST[2..0]15
AGPPCOMP
AGPNCOMP
AGPVREF_GC15
AGPVREF_GC
AGP8XDET#15
DBIL15
DBIH15
A
GC/BE#0GC/BE#[3..0]
GC/BE#1
GC/BE#2
GC/BE#3
AD_STBS0
AD_STBF0
AD_STBS1
AD_STBF1
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
SB_STBS
SB_STBF
ST0
ST1
ST2
DBIL
DBIH
AF18
GD0/DVOBHSYNC
AD18
GD1/DVOBVSYNC
AE18
GD2/DVOBD1
AF17
GD3/DVOBD0
AD17
GD4/DVOBD3
AD16
GD5/DVODB2
AE16
GD6/DVOBD5
AF16
GD7/DVOBD4
AF14
GD8/DVOBD6
AD14
GD9/DVOBD9
AD13
GD10/DVOBD8
AE13
GD11/DVOBD11
AF13
GD12/DVOBD10
AD12
GD13/DVOBCCLKINT
AF12
GD14/DVOBFLDSTL
AE12
GD15/MDDC_DATA
AD10
GD16/DVOCVSYNC
AE10
GD17/DVOCHSYNC
AF10
GD18/DVOCBLANK#
AD9
GD19/DVOCD0
AF9
GD20/DVOCD1
AF8
GD21/DVOCD2
AE9
GD22/DVOCD3
AD8
GD23/DVOCD4
AF6
GD24/DVOCD7
AD7
GD25/DVOCD6
AE6
GD26/DVOCD9
AD5
GD27/DVOCD8
AF5
GD28/DVOCD11
AF4
GD29/DVOCD10
AE4
GD30/DVOBCINTR#
AD4
GD31/DVOCFLDSTL
AD15
GBE0/DVOBD7
AF11
GBE1/DVOBBLANK#
AD11
GBE2
AC7
GBE3/DVOCD5
AF15
AD_STBS0/DVOBCLK#
AE15
AD_STBF0/DVOBCLK
AF7
AD_STBS1/DVOCCLK#
AE7
AD_STBF1/DVOCCLK
AC9
GFRAME/MDVI_DATA
AC10
GIRDY/MI2CCLK
AC14
GTRDY/MDVI_CLK
AC11
GDEVSEL/MI2CDATA
AC12
GSTOP/MDDC_CLK
AC16
GPAR
AD6
RBF
AC1
WBF
Y1
GREQ
AA3
GGNT
AC15
GSERR
A11
GCLK
AC2
SBA0/ADDID0
AC3
SBA1/ADDID1
AD1
SBA2/ADDID2
AD2
SBA3/ADDID3
AF2
SBA4/ADDID4
AD3
SBA5/ADDID5
AE3
SBA6/ADDID6
AF3
SBA7/ADDID7
AE1
SB_STBS
AF1
SB_STBF
AA2
ST0
AA1
ST1
AB1
ST2
V1
AGPPCOMP
W1
AGPNCOMP
AC13
AGPVREF0
AC6
AGPVREF1
Y2
AGP8XDET
AC4
DBIL
AC5
DBIH
U1
VCCQQ
M5K8M9L8N9P9R9
N5
L5K9L9
J9
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
G2G3G4G5H3H4H5J4J5
VCC3/NC
F6F2F5E1F4
VCC3/NC
VCC3/NC
F1K5E4E2E3
F3
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
SPCLK1/NC
SPCLK2/NC
DVID0/TVD0/NC
DVID1/TVD1/NC
DVID2/TVD2/NC
DVID3/TVD3/NC
DVID4/TVD4/NC
DVID5/TVD5/NC
DVID6/TVD6/NC
DVID7/TVD7/NC
DVID8/TVD8/NC
DVID9/TVD9/NC
DVID10/TVD10/NC
DVID11/TVD11/NC
DVIDET/TVCKI/NC
DVIDE/TVBL/NC
DVIHS/TVHS/NC
DVIVS/TVVS/NC
DVICLK/TVCLK/NC
VSSQQ
T1
R15
VSS
R14
VSS
R13
VSS
R12
VSS
R11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P23R1R2R3R4R5R10
VSS
VSS
VSS
VSS
VSS
VSS
P12
P13
P14
P15
P16
P17
B
VSS
VSS
VSS
VSS
VSS
VSS
N15
N16
N17
N25P5P10
P11
VSS
N14
VSS
N13
VSS
N12
VSS
N11
VSS
N10
VSS
VSS
M23
M21
VSS
M17
VSS
M16
VSS
M15
VSS
M14
VSS
VSS
M13
D1
VD0
VD1
VCC3/NC
VCC3/NC
VD2
VD3
VD4
VD5
VD6
VD7
VBE
VPAR
UPSTB
UPSTB
DNSTB
DNSTB
UPCMD
DNCMD
LVREF
LCOMPP
PWRGD
PCIRST
TESTIN
SUSTAT
DEBUG
AR/NC
AG/NC
AB/NC
RSET/NC
HSYNC/NC
VSYNC/NC
XIN/NC
INTA/NC
BISTIN/NC
SPD1/NC
SPD2/NC
GOP0/NC
GPOUT/NC
VSS
VSS
VSS
M10
M11
M12
U14B
K8M400/K8T400M
AD20
AD21
AF24
AE24
AE19
AF20
AD24
AF25
AE21
AF19
AE23
AF23
AF22
AD22
AF26
AD23
AF21
AD19
AE26
AD25
AC26
AD26
AC17
B3
A3
A2
C4
A1
B1
C6
E7
D3
P2
C2
P1
C1
J1
K2
K3
L4
K1
L2
L3
M4
L1
M2
M3
M1
P4
N1
N4
N3
P3
N2
D2
VSS
VSS
L17
L25
C
VLAD0
VLAD1
VLAD2
VLAD3
VLAD4
VLAD5
VLAD6
VLAD7
LVREF_NB
LCOMPP
TESTIN
DEBUG
VLAD[7..0] 18
VBE0# 18
VPAR 18
UPSTB 18
UPSTB# 18
DNSTB 18
DNSTB# 18
UPCMD 18
DNCMD 18
C241
X_102P
PWROK_NB# 17
PCIRST1# 16,30
SUSST# 17
R153 X_10K
R152 10K
VCC2_5
AGPVREF_GC
C491 1u_0805/BOT
C273 X_105P
LAYOUT: Place caps as close NB as possible
VCC2_5
TESTIN
AGPNCOMP
AGPPCOMP
LCOMPP
Title
NORTH BRIDGE K8T400M (AGP & VLINK)
Size Document Number Rev
C
D
Date: Sheet
R163 4.7K
VDDQ
R149 60.4RST
R146 60.4RST
R164 360RST
VCC2_5
R154
3KST
C234
104P
LVREF_NB
R167
1KST
C238
104P
MICRO-STAR INT'L CO ., LTD.
MS-6750
12 40Wednesday, January 29, 2003
E
0A
of
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