Motorola MC1496P1, MC1496BP, MC1496D, MC1496DR2, MC1496P Datasheet

 


These devices were designed for use where the output voltage is a
product of an input voltage (signal) and a switching function (carrier). Typical
applications include suppressed carrier and amplitude modulation,
synchronous detection, FM detection, phase detection, and chopper
applications. See Motorola Application Note AN531 for additional design
information.

• Excellent Carrier Suppression –65 dB typ @ 0.5 MHz

Excellent Carrier Suppression –50 dB typ @ 10 MHz

• Adjustable Gain and Signal Handling

• Balanced Inputs and Outputs

• High Common Mode Rejection –85 dB typical

This device contains 8 active transistors.

Order this document by MC1496/D

 

BALANCED

MODULATORS/DEMODULA T ORS

SEMICONDUCTOR

TECHNICAL DATA

D SUFFIX

PLASTIC PACKAGE

CASE 751A

14

1

P SUFFIX

PLASTIC PACKAGE

CASE 646

(SO–14)

14

1

0

20

Log Scale Id

40
60

IC = 500 kHz, IS = 1.0 kHz

499 kHz 500 kHz 501 kHz

IC = 500 kHz
IS = 1.0 kHz

Figure 1. Suppressed

Carrier Output

Waveform

Figure 2. Suppressed

Carrier Spectrum

PIN CONNECTIONS

Signal Input
Gain Adjust
Gain Adjust
Signal Input

Bias

Output

N/C

1
2
3
4
5
6
7

14

V

EE

13

N/C

12

Output

11

N/C

10

Carrier Input

9

N/C

8

Input Carrier

ORDERING INFORMATION

Operating

Device

MC1496D
MC1496P
MC1496BP Plastic DIPTA = –40°C to +125°C

Temperature Range

TA = 0°C to +70°C

Package

SO–14

Plastic DIP

Figure 4. Amplitude–Modulation Spectrum

10

8.0

IC = 500 kHz
IS = 1.0 kHz

IC = 500 kHz
IS = 1.0 kHz

MOTOROLA ANALOG IC DEVICE DATA

Figure 3. Amplitude

Modulation Output

Waveform

6.0

4.0

Linear Scale

2.0

0

 Motorola, Inc. 1996 Rev 4

499 kHz 500 kHz 501 kHz

1

MC1496, B

MAXIMUM RATINGS

Applied Voltage

(V6 – V8, V10 – V1, V12 – V8, V12 – V10, V8 – V4,

V8 – V1, V10 – V4, V6 – V10, V2 – V5, V3 – V5)

Differential Input Signal V8 – V10

Maximum Bias Current I
Thermal Resistance, Junction–to–Air

Plastic Dual In–Line Package
Operating Temperature Range T
Storage Temperature Range T

NOTE: ESD data available upon request.

ELECTRICAL CHARACTERISTICS (V

all input and output characteristics are single–ended, unless otherwise noted.)

Carrier Feedthrough

VC = 60 mVrms sine wave and

offset adjusted to zero

VC = 300 mVpp square wave:

offset adjusted to zero
offset not adjusted

Carrier Suppression

fS = 10 kHz, 300 mVrms

fC = 500 kHz, 60 mVrms sine wave
fC = 10 MHz, 60 mVrms sine wave

Transadmittance Bandwidth (Magnitude) (RL = 50 Ω)

Carrier Input Port, VC = 60 mVrms sine wave

fS = 1.0 kHz, 300 mVrms sine wave

Signal Input Port, VS = 300 mVrms sine wave

|VC| = 0.5 Vdc
Signal Gain (VS = 100 mVrms, f = 1.0 kHz; |VC|= 0.5 Vdc) 10 3 A
Single–Ended Input Impedance, Signal Port, f = 5.0 MHz

Parallel Input Resistance
Parallel Input Capacitance

Single–Ended Output Impedance, f = 10 MHz

Parallel Output Resistance
Parallel Output Capacitance

Input Bias Current

I1)I4

IbS+

Input Offset Current

I

Average Temperature Coefficient of Input Offset Current

(TA = –55°C to +125°C)
Output Offset Current (I6–I9) 7 – Ioo – 14 80 µA
Average Temperature Coefficient of Output Offset Current

(TA = –55°C to +125°C)
Common–Mode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV – 5.0 – Vpp
Common–Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 – ACM – –85 – dB
Common–Mode Quiescent Output V oltage (Pin 6 or Pin 9) 10 – V
Differential Output Voltage Swing Capability 10 – V
Power Supply Current I6 +I12

Power Supply Current I14

DC Power Dissipation 7 5 P

= I1–I4; I

ioS

2

(TA = 25°C, unless otherwise noted.)

Rating

Characteristic

;IbC+

ioC

I8)I10

2

= I8–I10

Symbol Value Unit

∆V 30 Vdc

V4 – V1

5

R

θJA

A

stg

= 12 Vdc, VEE = –8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 kΩ, Re = 1.0 kΩ, TA = T

CC

fC = 1.0 kHz
fC = 10 MHz

fC = 1.0 kHz
fC = 1.0 kHz

+5.0

±(5+I5Re)

10 mA

100 °C/W

0 to +70

–65 to +150

Fig. Note Symbol Min Typ Max Unit

5 1 V

5 2 V

8 8 BW

6 –

6 –

7 –

7 –

7 – TC

7 – TC

7 6 I

Vdc

°C
°C

I

I

CFT

CS

3dB

VS

r

ip

c

ip

r

op

c

oo

I

bS

I

bC

ioS

ioC

out
out

CC

I

EE

D



Iio

Ioo

–

40

–

140

–

0.04

–

20

40

2.5 3.5 – V/V



 – 2.0 – nA/°C

 – 90 – nA/°C

65

–

50

–

300

–

80

–

200

–

2.0

–

40

–

5.0

–

12

–

12

–

0.7

–

0.7

– 8.0 – Vpp
– 8.0 – Vpp
–

2.0

–

3.0

– 33 – mW

–
–

0.4

200

–
–

–

–

–
–

–
–

30
30

7.0

7.0

4.0

5.0

low

to T

mVrms

high

µVrms

dB

k

MHz

kΩ
pF

kΩ
pF

µA

µA

mAdc

,

2

MOTOROLA ANALOG IC DEVICE DATA

MC1496, B

GENERAL OPERATING INFORMATION

Carrier Feedthrough

Carrier feedthrough is defined as the output voltage at
carrier frequency with only the carrier applied (signal
voltage = 0).

Carrier null is achieved by balancing the currents in the
differential amplifier by means of a bias trim potentiometer
(R1 of Figure 5).

Carrier Suppression

Carrier suppression is defined as the ratio of each
sideband output to carrier output for the carrier and signal
voltage levels specified.

Carrier suppression is very dependent on carrier input
level, as shown in Figure 22. A low value of the carrier does
not fully switch the upper switching devices, and results in
lower signal gain, hence lower carrier suppression. A higher
than optimum carrier level results in unnecessary device and
circuit carrier feedthrough, which again degenerates the
suppression figure. The MC1496 has been characterized
with a 60 mVrms sinewave carrier input signal. This level
provides optimum carrier suppression at carrier frequencies
in the vicinity of 500 kHz, and is generally recommended for
balanced modulator applications.

Carrier feedthrough is independent of signal level, VS.
Thus carrier suppression can be maximized by operating
with large signal levels. However, a linear operating mode
must be maintained in the signal–input transistor pair – or
harmonics of the modulating signal will be generated and
appear in the device output as spurious sidebands of the
suppressed carrier. This requirement places an upper limit on
input–signal amplitude (see Figure 20). Note also that an
optimum carrier level is recommended in Figure 22 for good
carrier suppression and minimum spurious sideband
generation.

At higher frequencies circuit layout is very important in
order to minimize carrier feedthrough. Shielding may be
necessary in order to prevent capacitive coupling between
the carrier input leads and the output leads.

Signal Gain and Maximum Input Level

Signal gain (single–ended) at low frequencies is defined
as the voltage gain,

AVS+

A constant dc potential is applied to the carrier input terminals
to fully switch two of the upper transistors “on” and two
transistors “off” (VC = 0.5 Vdc). This in effect forms a cascode
differential amplifier.

Linear operation requires that the signal input be below a
critical value determined by RE and the bias current I5.

Note that in the test circuit of Figure 10, VS corresponds to a
maximum value of 1.0 V peak.

Common Mode Swing

The common–mode swing is the voltage which may be
applied to both bases of the signal differential amplifier,
without saturating the current sources or without saturating
the differential amplifier itself by swinging it into the upper

V
V

R

o
S

VS p I5 RE (Volts peak)

+

Re)

L

2r

e

where re+

26 mV
I5(mA)

switching devices. This swing is variable depending on the
particular circuit and biasing conditions chosen.

Power Dissipation

Power dissipation, PD, within the integrated circuit package
should be calculated as the summation of the voltage–current
products at each port, i.e. assuming V12 = V6, I5 = I6 = I12
and ignoring base current, PD = 2 I5 (V6 – V14) + I5)
V5 – V14 where subscripts refer to pin numbers.

Design Equations

The following is a partial list of design equations needed to
operate the circuit with other supply voltages and input
conditions.

A. Operating Current

The internal bias currents are set by the conditions at Pin 5.
Assume:

I5 = I6 = I12,
IBtt

IC for all transistors

then :

V

*

*

R5

+

The MC1496 has been characterized for the condition
I5 = 1.0 mA and is the generally recommended value.

B. Common–Mode Quiescent Output Voltage

Biasing

The MC1496 requires three dc bias voltage levels which
must be set externally. Guidelines for setting up these three
levels include maintaining at least 2.0 V collector–base bias
on all transistors while not exceeding the voltages given in
the absolute maximum rating table;

The foregoing conditions are based on the following
approximations:

Bias currents flowing into Pins 1, 4, 8 and 10 are transistor
base currents and can normally be neglected if external bias
dividers are designed to carry 1.0 mA or more.

Transadmittance Bandwidth

Carrier transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:

Signal transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:

f

*

500

I5

30 Vdc w [(V6, V12) – (V8, V10)] w2 Vdc
30 Vdc w [(V8, V10) – (V1, V4)] w2.7 Vdc
30 Vdc w [(V1, V4) – (V5)] w2.7 Vdc

V6 = V12, V8 = V10, V1 = V4

+

g

21C

io(signal)

+

g

21S

vs(signal)

where: R5 is the resistor between

W

where: Pin 5 and ground
where: φ = 0.75 at TA = +25°C

V6 = V12 = V+ – I5 R

io(each sideband)

vs(signal)

Vc+



L

Vo+



0.5 Vdc, Vo+

0

0

MOTOROLA ANALOG IC DEVICE DATA

3

MC1496, B

Coupling and Bypass Capacitors

Capacitors C1 and C2 (Figure 5) should be selected for a

reactance of less than 5.0 Ω at the carrier frequency.

Output Signal

The output signal is taken from Pins 6 and 12 either
balanced or single–ended. Figure 1 1 shows the output levels
of each of the two output sidebands resulting from variations
in both the carrier and modulating signal inputs with a
single–ended output connection.

Negative Supply

VEE should be dc only. The insertion of an RF choke in
series with VEE can enhance the stability of the internal
current sources.

TEST CIRCUITS

Figure 5. Carrier Rejection and Suppression

V

CC

Carrier

Input

V

C

V

S

Modulating

Signal Input

0.1

C

2

µ

10 k

1.0 k

F

R1

51

50 k

Carrier Null

0.1

C1

µ

1.0 k
R

e

F

515110 k

2

8

10

1
4

–8.0 Vdc

V

EE

1.0 k

MC1496

14 5

I5

I10

–

V

3.9 k

3

6.8 k

R

6

12

12 Vdc

L

R

3.9 k

I6

I9

Signal Port Stability

Under certain values of driving source impedance,
oscillation may occur. In this event, an RC suppression
network should be connected directly to each input using
short leads. This will reduce the Q of the source–tuned
circuits that cause the oscillation.

Signal Input

(Pins 1 and 4)

510

An alternate method for low–frequency applications is to
insert a 1.0 kΩ resistor in series with the input (Pins 1, 4). In
this case input current drift may cause serious degradation of
carrier suppression.

Figure 6. Input–Output Impedance

Re = 1.0 k

L

+V

–V

0.5 V

Z

o
o

in

NOTE: Shielding of input and output leads may be needed

to properly perform these tests.

2

8

–

+

10

MC1496

1

4

–8.0 Vdc

3

6
12

14 5

6.8 k

Z

+V

out
–V

10 pF

o
o

Figure 7. Bias and Offset Currents

V

CC

12 Vdc

Re = 1.0 k

2

8

10

MC1496

1
4

–8.0 Vdc

V

EE

14 5

I10

3

6
12

6.8 k

2.0 k

I6
I9

Carrier

Input

Modulating

Signal Input

1.0 k

1.0 k
I7

I8
I1
I4

4

Figure 8. Transconductance Bandwidth

1.0 k

51

µ

F

0.1

V

C

V

S

10 k

50 k

Carrier Null

0.1

51

µ

F

1.0 k
R

1.0 k

23

8

10

MC1496

1
4

14

5110 k

–

V

–8.0 Vdc

V

EE

MOTOROLA ANALOG IC DEVICE DATA

e

6

12

5

6.8 k

V

CC

12 Vdc

2.0 k

50 50

+V

0.01

–V

µ

F

o
o