Motorola MC14529BCL, MC14529BCP, MC14529BD Datasheet

MOTOROLA CMOS LOGIC DATA

1

MC14529B

  
 

The MC14529B analog data selector is a dual 4–channel or single
8–channel device depending on the input coding. The device is suitable for
digital as well as analog application, including various one–of–four and
one–of–eight data selector functions. Since the device has bidirectional
analog characteristics it can also be used as a dual binary to 1–of–4 or a
binary to 1–of–8 decoder.

• Data Paths Are Bidirectional

• 3–State Outputs

• Linear “On” Resistance

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load over the Rated Temperature Range.

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

Iin, I

out

Input or Output Current (DC or Transient),
per Pin

± 10

mA

P

D

Power Dissipation, per Package†

500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

TRUTH TABLE (X = Don’t Care)

ST

X

ST

Y

B A Z W

1 1 0 0 X0 Y0
1 1 0 1 X1 Y1
1 1 1 0 X2 Y2
1 1 1 1 X3 Y3

1 0 0 0 X0
1 0 0 1 X1
1 0 1 0 X2
1 0 1 1 X3

0 1 0 0 Y0
0 1 0 1 Y1
0 1 1 0 Y2
0 1 1 1 Y3

0 0 X X High

Impedance

This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

Dual 4–Channel Mode
2 Outputs

Single 8–Channel Mode
1 Output
(Z and W tied together)



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3
1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

BLOCK DIAGRAM

VDD = PIN 16

VSS = PIN 8

10

9

Z

W

A
B
X0
X1
X2

X3

Y0
Y1
Y2
Y3

6

STROBE X 1

STROBE Y 15

7
2
3
4
5

14
13
12
11

3–STATE OUTPUT ENABLE

MOTOROLA CMOS LOGIC DATAMC14529B

2

ELECTRICAL CHARACTERISTICS

– 55_C 25_C 125_C

Characteristic

Symbol

VDDTest Conditions

Min Max Min Typ # Max Min Max

Unit

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage

Range

V

DD

— VDD – 3.0 ≥ VSS ≥

V

EE

3.0 18 3.0 — 18 3.0 18 V

Quiescent Current Per

Package

I

DD

5.0
10
15

Control Inputs: Vin =

VSS or VDD,

Switch I/O: VSS

v

V

I/O

v VDD, and

∆V

switch

v 500 mV**

—
—
—

1.0

1.0

2.0

—
—
—

0.005

0.010

0.015

1.0

1.0

2.0

—
—
—

60
60

120

µA

Total Supply Current

(Dynamic Plus
Quiescent, Per Package

I

D(AV)

5.0
10
15

TA = 25_C only (The

channel component,
(Vin – V

out

)/Ron, is

not included.)

(0.07 µA/kHz) f + I

DD

Typical (0.20 µA/kHz) f + I

DD

(0.36 µA/kHz) f + I

DD

µA

CONTROL INPUTS — INHIBIT, A, B (Voltages Referenced to VSS)

Low–Level Input Voltage V

IL

5.0
10
15

Ron = per spec,
I

off

= per spec

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

V

High–Level Input Voltage V

IH

5.0
10
15

Ron = per spec,
I

off

= per spec

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

V

Input Leakage Current I

in

15 Vin = 0 or V

DD

— ± 0.1 — ±0.00001 ±0.1 — ±1.0 µA

Input Capacitance C

in

— — — — 5.0 7.5 — — pF

SWITCHES IN/OUT AND COMMONS OUT/IN — W, Z (Voltages Referenced to VEE)

Recommended Peak–to–

Peak Voltage Into or
Out of the Switch

V

I/O

— Channel On or Off 0 V

DD

0 — V

DD

0 V

DDVp–p

Recommended Static or

Dynamic Voltage
Across the Switch**
(Figure 5)

∆V

switch

— Channel On 0 600 0 — 600 0 300 mV

Output Offset Voltage V

OO

— Vin = 0 V, No Load — — — 10 — — — µV

ON Resistance R

on

1015∆V

switch

v 500 mV**,

Vin = VIL or V

IH

(Control), and Vin =
0 to VDD (Switch)

——400

240——

120

80

480
270——

560
350

Ω

∆ON Resistance Between

Any Two Channels
in the Same Package

∆R

on

10
15

—————

—

15
10

———

—

—
—

Ω

Off–Channel Leakage

Current (Figure 10)

I

off

15 Vin = VIL or V

IH

(Control) Channel to
Channel or Any One
Channel

± 100 — ± 0.05 ± 100 — ±1000 nA

Capacitance, Switch I/O C

I/O

— Inhibit = V

DD

— — — 8.0 — — — pF

Capacitance, Common O/I C

O/I

— Inhibit = V

DD

— — — 20 — — — pF

Capacitance, Feedthrough

(Channel Off)

C

I/O

——Pins Not Adjacent

Pins Adjacent

—————

—

0.15

0.47

———

—

—
—

pF

#Data labelled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.

** For voltage drops across the switch (∆V

switch

) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)

MOTOROLA CMOS LOGIC DATA

3

MC14529B

SWTCHING CHARACTERISTICS (T

A

= 25_C)

Characteristic

Figure Symbol V

SS

V

DD

Min Typ # Max Unit

Vin to V

out

Propagation Delay Time

(CL = 50 pF, RL = 1.0 kΩ)

7 t

PLH

, t

PHL

0.0 5.0
10
15

—
—
—

20
10

8.0

40
20
15

ns

Propagation Delay Time, Control to
Output, Vin = VDD or V

SS

(CL = 50 pF, RL = 1.0 kΩ)

8 t

PLZ

, t

PZL

,

t

PHZ

, t

PZH

0.0 5.0
10
15

—
—
—

140

70
50

400
160
120

ns

Crosstalk, Control to Output

(CL = 50 pF, RL = 1.0 kΩ
R

out

= 10 kΩ)

9 — 0.0 5.0

10
15

—
—
—

5.0

5.0

5.0

—

—

mV

Control Input Pulse Frequency

(CL = 50 pF, RL = 1.0 kΩ)

10 f

in

0.0 5.0
10
15

—
—
—

5.0
10
12

2.5

6.2

8.3

MHz

Noise Voltage

(f = 100 Hz)

11, 12 — 0.0 5.0

10
15

5.0
10
15

—
—
—

—
—
—

24
25
30

12
12
15

—
—
—

—
—
—

nV/

√cycle

Sine Wave Distortion

(Vin = 1.77 Vdc RMS
Centered @ 0.0 Vdc,
RL = 10 kΩ, f = 1.0 kHz)

— — – 5.0 5.0 — 0.36 — %

Off–Channel Leakage Current

(Vin = + 5.0 Vdc, V

out

= – 5.0 Vdc)

(Vin = – 5.0 Vdc, V

out

= + 5.0 Vdc)

(Vin = + 7.5 Vdc, V

out

= – 7.5 Vdc)

(Vin = – 7.5 Vdc, V

out

= + 7.5 Vdc)

— I

off

– 5.0
– 5.0
– 7.5
– 7.5

5.0

5.0

7.5

7.5

—
—
—
—

± 0.001

± 0.001
± 0.0015
± 0.0015

± 125
± 125
± 250
± 250

nA

Insertion Loss

(Vin = 1.77 Vdc
RMS centered @ 0.0 Vdc,
f = 1.0 MHz)
I

loss

= 20 Log10 (V

out/Vin

)

(RL = 1.0 kΩ)

(RL = 10 kΩ)
(RL = 100 kΩ)
(RL = 1.0 MΩ)

13 — – 5.0 5.0

—
—
—
—

2.0

0.8

0.25

0.01

—
—
—
—

dB

Bandwidth (– 3 dB)

(Vin = 1.77 Vdc
RMS centered @ 0.0 Vdc)

(RL = 1.0 kΩ)

(RL = 10 kΩ)
(RL = 100 kΩ)
(RL = 1.0 MΩ)

— BW – 5.0 5.0

—
—
—
—

35
28
27
26

—
—
—
—

MHz

Feedthrough and Crosstalk

20 Log10 (V

out/Vin

) = – 50 dB

(RL = 1.0 kΩ)

(RL = 10 kΩ)
(RL = 100 kΩ)
(RL = 1.0 MΩ)

— — – 5.0 5.0

—
—
—
—

850
100

12

1.5

—
—
—
—

MHz

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.