Motorola MC10103P, MC10103FN, MC10103L Datasheet
SEMICONDUCTOR TECHNICAL DATA
The MC10103 is a quad 2–input OR gate. The MC10103 provides one gate
with OR/NOR outputs.
PD= 25 mW typ/gate (No Load)
tpd= 2.0 ns typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
12
13
10
11
4
5
6
7
V
= PIN 1
CC1
V
= PIN 16
CC2
VEE= PIN 8
2
3
15
9
14
CERAMIC PACKAGE
PLASTIC PACKAGE
DIP
PIN ASSIGNMENT
V
A
OUT
B
OUT
CC1
A
IN
A
IN
B
IN
B
IN
V
EE
1
2
3
4
5
6
7
8
L SUFFIX
CASE 620–10
P SUFFIX
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
16
15
14
13
12
11
10
V
C
D
C
C
D
D
C
9
CC2
OUT
OUT
IN
IN
IN
IN
OUT
3/93
Motorola, Inc. 1996
3–11
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
REV 5
MC10103
Under
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Characteristic Symbol
Power Supply Drain Current I
Input Current I
Output Voltage Logic 1 V
Output Voltage Logic 0 V
Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
Switching Times (50Ω Load) ns
Propagation Delay t
Rise Time (20 to 80%) t
Fall Time (20 to 80%) t
* Individually test each input applying VIH or VIL to input under test.
E
inH
I
inL
OH
OL
OHA
OLA
4+2+
t
12+9–
2+
2–
Under
Test
8 29 21 26 29 mAdc
4* 390 245 245 µAdc
4* 0.5 0.5 0.3 µAdc
2
9
2
9
2
9
2
9
2
9
2 1.1 3.6 1.1 2.0 3.3 1.1 3.7
2 1.1 3.6 1.1 2.0 3.3 1.1 3.7
–30°C +25°C +85°C
Min Max Min Typ Max Min Max
–1.060
–1.060
–1.890
–1.890
–1.080
–1.080
1.0
1.0
–0.890
–0.890
–1.675
–1.675
–1.655
–1.655
3.1
3.1
–0.960
–0.960
–1.850
–1.850
–0.980
–0.980
1.0
1.0
2.0
2.0
–0.810
–0.810
–1.650
–1.650
–1.630
–1.630
2.9
2.9
–0.890
–0.890
–1.825
–1.825
–0.910
–0.910
1.0
1.0
–0.700
–0.700
–1.615
–1.615
–1.595
–1.595
3.3
3.3
Unit
Vdc
Vdc
Vdc
Vdc
MOTOROLA MECL Data
3–12
DL122 — Rev 6
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