Motorola Digital DNA MSC8101 Technical Data Manual

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Page 1

Technical Data Advance Information

MSC8101/D Rev. 6, 11/2002

Network ing Digital Signa l Processor

(mask set 2K42A)

Figure 1. MSC8101 Block Diagram

UTOPIA

Other

Peripherals

MII

TDMs

CPM

MCC / UART / HDLC / Transparent /

Ethernet / Fast Ethernet / ATM / SCC

PIT

System Protection

Reset Control Clock Control

SIU

8/16-bit Host

SC140

Power

Management

Clock/PLL

64-bit XA Data Bus

128-bit P-Bus

64-bit XB Data Bus

Extended Core

Interface

64-bit Local Bus

64-bit System Bus

Core

•

Serial Interface and TSA

3 × FCC

4 × SCC

SPI

I2C

2 × MCC

2 × SMC

Interrupt

Timers

Baud Rate

Parallel I/O

Generators

Controller

Dual Ported

RAM

Program

Sequencer

Address Register

File

Data ALU

File

Address

ALU

Data

ALU

64/32-bit System Bus

Interrupts

EOnCE™JTAG

2 × SDMA

RISC

Interface

DMA

Engine

Bridge

Q2PPC

Bridge

Boot

ROM

SRAM

512 KB

128-bit QBus

MEMC

L1 Interface

HDI16

MEMC

{

PIC

EFCOP

SIC_EXT

SIC

Interrupts

The Motorola MSC8101 16-bit Digital Signal Processor (DSP) is the first member of the family of DSPs based

on the StarCore™ SC140 DSP core. The MSC8101 is offered in three core speed levels: 250, 275, and 300 MHz.

The Motorola MSC8101 DSP is a very versatile device that in teg rates th e hi gh-perform ance SC140 four-ALU (Arithmetic Logic Unit) DSP core along with 512 KB of on-chip memory, a Communications Processor Module (CPM), a 64-bit bus, a very f lexible System Integrati on Unit (SIU), and a 16-channel DMA engin e on a single device. With its four-ALU core, the MSC8101 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8101 CPM is a 32-bit RISC-bas ed communications protocol engine tha t can net work to Time-Div ision Multiplexed (TDM) highways, Ethernet, and

Asynchronous Transfe r mod e (ATM) backbones. The MSC8101 60x-compatible bus interface facilitates its connection to multi-master sys tem architect ures. The very la rge on-chi p memory, 512 KB, reduces the need for off-chip program and data memories. The MSC8101 offers 1500 DSP MMACS (1200 core and 300 EFCOP) or 3600 RISC MIPS performance using an internal 300 MHz clock with a 1.6 V core and independent

3.3 V input/output (I/O). MSC8101 power dissipation is estimated at less than 0.6 W. Figure 1 shows a block diagram of the MSC8101 processor.

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Page 2

Table of Contents

MSC8101 Features............................................................................................................................................. iii

Target Applicatio ns ...... ... ........... ... ........... .. ... ........... ... ........... ... ........... ... ........... .. ........... .................... .. ........... .. iv

Product D oc u m e nt at io n................. .. ........... ... ........... ... ........... ... ........... ... .. ........... ... ........... ... ........ ... ... ........... .. .. iv

Chapter 1 Signal/ Connection Descriptions

1.1 Signal Groupings..............................................................................................................................................1-1

1.2 P owe r S ig n al s.... ... .. ............ .. ........... ... ........... ... ........... ... ........... .. ............ .. ........... ... ... ........ ........... ... ........... ... .. 1-4

1.3 C lo c k Sig na ls . ... ........... ... ........... ... .. ........... ... ........... ... ........... ... ........... ... ........... .. ......... .. ........... ... ........... ... ..... 1-5

1.4 Reset, Configuration, and EOnCE Event Signals ............................................................................................ 1-6

1.5 System Bus, HDI16, and Interrupt Signals ......................................................................................................1-8

1.6 Memory Controller Signals............................................................................................................................ 1-16

1.7 Communications Processor Module (CPM) Ports ......................................................................................... 1-18

1.8 JTAG Test Access Port Signals......................................................................................................................1-45

1.9 Reserved Signals ............................................................................................................................................1-46

Chapter 2 Specifications

2.1 Introduction...................................................................................................................................................... 2-1

2.2 Absolute Maximum Ratings ............................................................................................................................ 2-1

2.3 Recommended Operating Conditions.............................................................................................................. 2-2

2.4 Thermal Characteristics ...................................................................................................................................2-2

2.5 DC Electrical Characteristics........................................................................................................................... 2-3

2.6 C lo c k Con f ig ur at ion .. ... ........... ... ........... ... .. ........... ... ........... ... ........... ... ........... ... ........... .. . .......... ... ........... ... ..... 2-4

2.7 AC Timings...................................................................................................................................................... 2-7

Chapter 3 Packaging

3.1 Pin-Out and Package Information....................................................................................................................3-1

3.2 FC-PBGA Package Description....................................................................................................................... 3-1

3.3 FC-PBGA Package Mechanical Drawing...................................................................................................... 3-32

Chapter 4 Design Considerations

4.1 Thermal Design Considerations.......................................................................................................................4-1

4.2 Electrical Design Considerations ..................................................................................................................... 4-2

4.3 P owe r C o ns id e ra ti on s ... ........... ... ........... ... ........... .. ........... ... ........... ... ........... ... ........... ... ........ ... ........... .. ........... 4 -2

4.4 Layout Practices ............................................................................................................................................... 4-4

Index

Ordering Information, Disclaimer, and Contact Information.................................................................. Back Cover

Data Sheet Con vention s

OVERBAR Used to indicate a signa l th at i s active when pulled low (For example, the RESET pin i s active when

low.)

“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low “deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples: Signal/Symbol Logic State Signal State Voltage

True Asserted VIL/V

PIN False Deasserted VIH/V

PIN True Asserted VIH/V

PIN False Deasserted VIL/V

Note: Values for VIL, VOL, VIH, and VOH are defined by individual p roduct specifications.

Page 3

iii

MSC8101 Featur es

• SC140 Core — Architecture optimized for efficient C/C++ code compilation — Four 16-bit ALUs and two 32-bit AGUs — 1200 DSP MIPS, 1200 MMACS, 3000 RISC MIPS, running at 300 MHz — Very low power dissipati on—less than 0.25 W for the core running full s peed at 1.6 V — Variable-Length E xecution Set (VLES) executi on model — JTAG/Enhanced OnCE debug por t

• 150 MHz Communications Processor Module (CPM) — Programmable protocol machine using a 32-bit RISC engine — 155 Mbps ATM interface (including AAL 0/1/2/5) — 10/100 Mbit Ethernet interface — Up to four E1/T1 interfaces or one E3/T3 int erface and one E1/T1 interface — HDLC support up to T3 rates, or 256 channels

• 100 MHz 64- or 32-bit Wide Bus Interface — Support for bursts for high efficiency — Glueless interface to 60x-compatible bus systems — Multi-master support

• Enhanced Filter Coprocessor (EFCOP) — Independently and concurrently executes long filters (such as echo cancellation) — Runs at 300 MHz and provides 300 MMACS performance

• Programmable Memory Controller — Control for up to eight bank s of external memory — User-programmable mac hines (UPM) allowing glueles s in terface to various memory types

(SRAM, DRAM, EPROM, and Flash memory) and other user-definable peripherals

— Dedicated pipelined SDRAM memory interface

• Large On-Chip SRAM — 256K 16-bit words (512 KB) — Unified program and data space configurable by the application — Word and byte addressable

•DMA Controller — 16 DMA channels, FIFO based, with burs t capabilities — Sophisticated addressing capabi lities

• Small Foot Print Package — 17 mm × 17 mm plastic package

• Very Low Power Consumption — Estimated power consum ption of 570 mW for the entire device — Separate power supply for internal logic (1.6 V) and for I/O (3.3 V)

• Enhanced 16-bit Parallel Host Interface (HDI16) — Supports a variety of microcontroller, microprocessor, and DSP bus interfaces

• Phase-Lock Loops (PLLs) —System PLL — CPM DPLLs (SCC and SCM)

• Process Technology — Uses 0.13 micron copper interconnect process technology

Page 4

Target Appl icatio ns

The MSC8101 targe ts applications requiring very high performance , very large amounts of on-chip memory, and such networking capabilities as:

• Third-generation wideband wire less infrastructure systems

• Packet Telephony systems

• Multi-channel modem banks

• Multi-channel xDSL

Product Docume ntatio n

The documents listed in Table 1 are required for a complete description of the MSC8101 and are necessary to des ign properly with the part. Docum entation is available from the following sources (see back cover for detailed information):

• A local Motorola distributor

• A Motorola semiconductor sales office

• A Motorola Literature Distribution Center

• The World Wide Web (WWW)

Table 1. MSC8101 Documentation

Name Description Order Number

MSC8101 Techni cal Data

MSC810 1 fe at ure s l i st and ph ysi ca l, el ect ri cal , ti min g, and package specifications

MSC8101/D

MSC8101

User’s Guide

Detailed functional description of the MSC8101 memory configuration, operation, and register programming

MSC8101UG/D

MSC8101 Pocket Guide

Quick reference information for application deve lopment. MSC8101PG/D

MSC8101 Reference Manual

Detailed description of the MSC8101 processor core and instruction set

MSC810 1RM/D

SC140 DSP Core Reference Manual

Detailed description of the SC140 family processor core and instr uc t io n se t

MNSC140DSPCORERM/D

Application Notes

Documents describing specific applications or optimized device operation includi ng code examples

See the MSC8101 pr oduct website

Page 5

1-1

Chapter 1

Signal/ Connection Descriptions

1.1 Signal Groupings

The MSC8101 external s ignals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and Figure 1-2. Table 1- 1 lists the functional groups, the number of signal connections in each group, and referenc es the table that gives a detailed listing of mu ltiplexed signals within each g roup. Figure 1-1 shows MSC8101 external signals organized by func tion. Figure 1-2 indicates how the parallel input/output (I/O) ports signals are multiplexed. Because the parallel I/O design supported by the MSC8101 Communic ations Processor Module (CPM) is a subset of the parallel I/O signals supported by the MPC8260 device, port pins are not numbered sequentially.

Table 1- 1.

MSC8101 Functional Signal Groupings

Functional Group

Number of

Signal

Connections

Detailed Description

Power (VCC, VDD, and GND) 80 Table 1-1 on page 1-4

Clock 6 Table 1-2 on page 1-5

Reset, Configuration, and EOnCE 11 Table 1-3 on page 1-6

System Bus, HDI16, and Interrupts 133 Table 1-4 on page 1-8

Memory Controller 27 Table 1-2 on page 1-16

Communications Processor Module (CPM) Input/Output Parallel Ports

Port A 26 Table 1-3 on page 1-19

Port B 14 Table 1-4 on page 1-27

Port C 18 Table 1-5 on page 1-32

Port D 8 Table 1-6 on page 1-42

JTA G Te st Ac cess Port 5 Table 1-7 on page 1-45

Reserved (denotes connections that are always reserved) 5 Table 1-8 on page 1-46

Page 6

1-2

Signal Groupings

P O W

E R

6 0 x

B U S

↔ A[0–31]

VDD

→ 14 5

↔ TT[0–4]

VDDH

→ 25 4

↔ TSIZ[0–3]

VCCSYN

→ 1 1

↔ TBST

VCCSYN1

→ 1 1

↔ IRQ1 GBL

→ Reserved BADDR[29–31] IRQ[2–3, 5]

GND

→ 37 1

↔ BR

GNDSYN

→ 1 1

↔ BG

GNDSYN1

→ 1 1

↔ ABB IRQ2

↔ TS

C P M

I / O

P O R T S

↔ AACK

← ARTRY

For the signals multiplexed on

Ports A–D,

see Figure 1-2

Port A

1 ↔ DBG

PA[31–6]

↔ 26 1

↔ DBB IRQ3

↔ D[0–31]

Port B HDI16 Signals

PB[31–18]

↔ 14 16

↔ D[32–47] HD[0–15]

↔ D[48–51] HA[0–3]

Port C

↔ D52 HCS1

PC[31–22, 15–12, 7–4]

↔ 18

Single DS Double DS

↔ D53 HRW HRD/HRD

Port D

↔ D54 HDS/HDS HWR/HWR

PD[31–29, 19–16, 7]

↔ 8

Single HR Double HR

↔ D55 HREQ/HREQ HTRQ/HTRQ

J T A G

↔ D56 HACK/HACK HRRQ/HRRQ

TMS

→ 1 1

↔ D57 HDSP

TDI

→ 1 1

↔ D58 HDDS

TCK

→ 1 1

↔ D59 H8BIT

TRST

→ 1 1

↔ D60 HCS2

TDO ← 1 4 ↔ D[61–63] Reserved

← Reserved DP0 Reserved EXT_Br2

EOnCE Event

RESET

Configuration

1 ↔ IRQ1 DP1 IRQ1 EXT_BG2

EED

↔ 1 1

↔ IRQ2 DP2 Reserved EXT_DBG2

EE0 DBREQ

↔ 1 1

↔ IRQ3 DP3 Reserved EXT_BR3

EE1 HPE

↔ 1 1

↔ IRQ4 DP4 DREQ3 EXT_BG3

EE[2–3]

↔ 2 1

↔ IRQ5 DP5 DREQ4 EXT_DBG3

EE[4–5] BTM[0–1]

↔ 2 1

↔ IRQ6 DP6 DACK3 IRQ6

PORESET

→ 1 1

↔ IRQ7 DP7 DACK4 IRQ7

RSTCONF

→ 1 1

↔ TA

HRESET

↔ 1 1

↔ TEA

SRESET

↔ 1 1

← NMI

→ NMI_OUT

↔ PSDVAL

↔ IRQ7 INT_OUT

→ CS[0–7]

CLKIN

→ 1 1

→ BCTL1

BNKSEL[0–2] TC[0–2] MODCK[1–3]

→ 3 2

→ BADDR[27–28]

CLKOUT

← 1 1

→ ALE

DLLIN

→ 1 1

→ BCTL0

→ PWE[0–7] PSDDQM[0–7] PBS[0–7]

→ PSDA10 PGPL0

→ PSDWE PGPL1

→ POE PSDRAS PGPL2

TEST

→ 1 1

→ PSDCAS PGPL3

THERM[1–2]

↔ 2 1

↔ PGTA PUPMWAIT PPBS PGPL4

SPARE1, SPARE5

↔ 2 1

→ PSDAMUX PGPL5

Note: Refer to the

System Interface Unit (SIU)

chapter in the

MCS8101 Reference Manual

for details on how to configure these pins.

Figure 1-1. MSC8101 External Signals

Page 7

1-3

Signal Groupings

FCC1

ATM/UTOPIA

MPHY

Master mux poll or Slave

MPHY Master dir. poll

FCC1

Ethernet

MII

HDLC/

transp.

HDLC

Serial Nibble GPIO

TXENB

COL PA31

TXCLAV TXCLAV0 CRS

RTS

PA30 TXSOC TX_ER PA29 RXENB TX_EN PA28 RXSOC RX_DV PA27

RXCLAV RXCLAV0 RX_ER SDMA PA26

TXD0 MSNUM0 PA25 TXD1 MSNUM1 PA24 TXD2 PA23 TXD3 PA22 TXD4 TXD3 TXD3 PA21 TXD5 TXD2 TXD2 PA20 TXD6 TXD1 TXD1 PA19 TXD7 TXD0 TXD TXD0 PA18 RXD7 RXD0 RXD RXD0 PA17 RXD6 RXD1 RXD1 PA16 RXD5 RXD2 RXD2 PA15 RXD4 RXD3 RXD3 PA14 RXD3 MSNUM2 PA13 RXD2 SI1 MSNUM3 PA12 RXD1 TDMA1 MSNUM4 PA11 RXD0 SMC2 Serial Nibble MSNUM5 PA10

SMTXD L1TXD L1TXD0 PA9

FCC2 SMRXD L1RXD L1RXD0 PA8

Ethernet

MII

HDLC/

transp.

HDLC SMSYN L1TSYNC SI2 PA7

Serial Nibble SCC2 L1RSYNC TDMB2 PA6 TX_ER RXD L1TXD PB31 RX_DV TXD L1RXD PB30 TX_EN L1RSYNC PB29 RX_ER

RTS

RTS/TENA L1TSYNC PB28

COL

TDMC2

L1TXD

PB27

CRS L1RXD PB26 TXD3 TXD3 L1TXD3 L1TSYNC PB25 TXD2 TXD2 L1RXD3 L1RSYNC PB24

TXD1 TXD1 L1RXD2

TDMD2

L1TXD

PB23

TXD0 TXD TXD0 L1RXD1 L1RX D PB22 RXD0 RXD RXD0 L1TXD2 L1TSYNC PB21 RXD1 RXD1 L1TXD1 L1RSYNC

I2C

PB20 RXD2 RXD2 SDA PB19 RXD3 RXD3 SCL BRGs Clocks Timers PB18

Ext. Req. BRG1O CLK1 TGATE1 PC31

EXT1 BRG2O CLK2 TOUT1 PC30

SCC1

CTS/CLSN

BRG3O CLK3 TIN2 PC29

CTS/CLSN SIU Timer Input BRG4O CLK4

TIN1/

TOUT2

PC28

CLK5 BRG5O CLK5 TGATE2 PC27

TMCLK BRG6O CLK6 TOUT3 PC26

DMA

DACK2

BRG7O CLK7 TIN4 PC25

Ext. Req. DREQ2 BRG8O CLK8

TIN3/

TOUT4

PC24

EXT2 DACK1 CLK9 PC23

SCC1 LIST1 DREQ1 CLK10 PC22

TXADDR0

CTS/CLSN

SMTXD PC15 RXADDR0 CD/RENA LIST2 PC14 TXADDR1 CTS/CLSN LIST4 PC13 RXADDR1 FCC1 CD/RENA LIST3 PC12

TXADDR2

TXADDR2/

TXCLAV1

CTS LIST1 PC7

RXADDR2

RXADDR2/

RXCLAV1

CD LIST2 PC6

FCC2 SMC1

CTS

SMTXD LIST3 PC5

CD SMRXD LIST4 PC4

RXD DRA CK1/DONE1 PD31

TXD DRACK2/DONE2 PD30 RXADDR3 RXCLAV2 RTS/TENA SPI PD29 TXADDR4 TXCLAV3

SPISEL

BRG1O PD19

RXADDR4 RXCLAV3 SPICLK PD18

RXPRTY SPIMOSI BRG2O PD17 TXPRTY SPIMISO PD16

TXADDR3 TXCLAV2 SMSYN PD7

Figure 1-2. CPM Port A–D Pin Multiplexed Functionality

Page 8

1-4

Power Signals

1.2 Power S ignals

Table 1-1. Power and Ground Signal Inputs

Power Name Description

Internal Log ic Pow e r

dedicated for use with the device core. The voltage should be well-regulated and the

input should be provided with an extremely low impedance path to the V

power rail.

DDH

Input/Output Power

This so urce supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors.

CCSYN

System PLL Power

dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the V

power rail.

CCSYN1

SC140 PLL Power

dedicated for use with the SC140 core PLL. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the V

power rail.

GND System Ground

An isolated ground for the internal processing logic. This connection must be tied externally to all chip ground connections, except GND

SYN

and GND

SYN1

. The user must provide

adequate external decoupling capacitors.

GND

SYN

System PLL Ground

Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to ground.

GND

SYN1

SC140 PLL Ground 1

Ground dedicated for SC140 core PLL use. The connectio n should be provided with an extremely low-impedance path to ground.

Page 9

1-5

Clock Signals

1.3 Clock S ig nals

Table 1-2. Clock Signals

Signal

Name

Type Signal Description

CLKIN Input Clock In

Primary clock input to the MSC8101 PLL.

MODCK1

TC0

BNKSEL0

Input

Output

Clock Mode Input 1

Defines the operating mode of internal clock circuits.

Transfer Code 0

Supplies information that can be useful for debugging bus transactions initiated by the MSC8101.

Bank Select 0

Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.

MODCK2

TC1

BNKSEL1

Input

Output

Clock Mode Input 2

Defines the operating mode of internal clock circuits.

Transfer Code 1

Supplies information that can be useful for debugging bus transactions initiated by the MSC8101.

Bank Select 1

Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.

MODCK3

TC2

BNKSEL2

Input

Output

Clock Mode Input 3

Defines the operating mode of internal clock circuits.

Transfer Code 2

Supplies information that can be useful for debugging bus transactions initiated by the MSC8101.

Bank Select 2

Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.

CLKOUT Output Clock Out

The system bus clock.

DLLIN Input DLLIN

Synchro n iz es wit h an exte r na l de vi ce.

Page 10

1-6

Reset, Configuration, and EOnCE Event Signals

1.4 Rese t, Co nfi gurat ion , an d EO nCE Even t S ig nals

Table 1-3. Reset, Configuration, and EOnCE Event Signals

Signal Name Type Signal Description

DBREQ

EE0

Input

Output

Debug Request

Determines whether to go into SC140 Debug mode when PORESET

is deasserted.

Enhanced OnCE (EOnCE) Event 0

After PORESET

is deasserted, you can configure EE0 as a n input (default) or an output.

Debug request, enable Addr ess Event Detection Channel 0, or gener ate one of the EOnCE events.

Detection by Address Event Detection Channel 0. Used to trigger external debugging equipment.

HPE

EE1

Input

Output

Host Port Enable

When this pin is asserted during PORESET

, the Hos t p ort is en ab le d, th e sy st em da ta bu s

is 32 bits wide, an d the Host

must

program the reset configuration word.

EOnCE Event 1

After PORESET

is deasserted, you can configure EE1 as a n input (default) or an output.

Enable Address Event Detection Channel 1 or generate one of the EOnCE events.

Debug Acknowledge or detection by Address Event Detection Channel 1. Use d to trigger exter nal debugging equ ipment.

EE2

Input

Output

EOnCE Event 2

After PORESET

is deasserted, you can configure EE2 as a n input (default) or an output.

Enable Address Event Detection Channel 2 or generate one of the EOnCE events or enable the Event Counter.

Detection by Address Event Detection Channel 2. Used to trigger external debugging equipment.

EE3

Input

Output

EOnCE Event 3

After PORESET

is deasserted, you can configure EE3 as a n input (default) or an output.

See t he

Emulation and Debug

chapter in the

SC140 DSP Core Reference Manual

for

details on the ERC V Register.

Enable Address Event Detection Channel 3 or generate one of the EOnCE events.

EOnCE Receive Register (ERCV) was read by the DSP. Used to trigger external debugging equipment.

Page 11

1-7

Reset, Configuration, and EOnCE Event Signals

BTM[0–1]

EE4

EE5

Input

Output

Input

Output

Boot Mode 0–1

Determines the MSC8101 boot mode when PORESET

is deasserted. See the

Emulation

and Debug

chapter in the

SC140 DSP Core Reference Manual

for details on how to set

these pins.

EOnCE Event 4

After PORESET

is deasserted, you can configure EE4 as a n input (default) or an output.

See t he

Emulation and Debug

chapter in the

SC140 DSP Core Reference Manual

for

details on the ETRSMT Register.

Enable Address Event Detection Channel 4 or generate one of the EOnCE events

EOnCE Transmit Register (ETRSMT) was written by the DSP. Used to trigger external debugging equipment.

EOnCE Event 5

After PORESET

is deasserted, you can configure EE5 as a n input (default) or an output.

Enable Address Event Detection Channel 5.

Detection by Address Event Detection Channel 5. Used to trigger external debugging equipment.

EED

Input

Output

Enhanced OnCE (EOnCE) Event Detection

After PORESET

is deasserted, you can configure EED as an input (default) or output:

Enable the Data Event Detection Channel.

Detection by the Data Event Detection Channel. Used to trigger external debugging equipment.

PORESET

Input Power-On Reset

When asserted, t his line causes the MSC8101 to enter power-on res et state.

RSTCONF

Input Reset Configuration

Used during reset configuration sequence of the chip. A detailed explanation of its function

is pro v ided in the “Power-On R eset Flow” and “Hardware Reset Configuration” sections of the

MSC8101 Reference Manual

HRESET

Input Hard Reset

When as se rte d, this open-d rai n lin e causes the MSC8 101 to enter hard r es et stat e.

SRESET

Input Soft Reset

When asserted, this open -drain line causes the MSC8101 to enter soft reset state.

Note: See the

Emulation and Debug

chapter in the

SC140 DSP Core Reference Manual

for details on how to

configure these pins.

Table 1-3. Reset, Configuration, and EOnCE Event Signals (Continued)

Signal Name Type Signal Description

Page 12

1-8

System Bus, HDI16, and Interrupt Signals

1.5 System B us , HDI 16, and In terr upt Si gna ls

The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines . Individual assignment of a si gnal to a specific signal line is configured through registers in the System Interface Unit (SIU) and the Host Interface (HDI16). Table 1-4 describes the signals in this group.

Note: To boot from the host interface, the HDI16 must be enabled by pulling up the HPE signal line

during

PORESET. If the HPE signal is pulled up, the configuration word must then be loaded

from the host. The configuration word must set the Internal Space Port Size bit in the Bus Control Register (BCR[ISPS]) to change the system data bus width from 64 bits to 32 bits and reassign the upper 32 bits to their HDI16 functions. Never set the Host Port Enable (HEN) bit in the Host Port Control Register (HPCR) to enable the HDI16, unless the bus size is first changed from 64 bits to 32 bits by setting the BCR[ISPS] bit. Otherwise, unpredictable operation may occur.

Although there are eight interrupt request (IRQ) connections to the core processor, there are multiple external li nes th at can conne ct to t hese interna l signal l ine s. After re set, the defa ult con figur ation i ncl udes two IRQ 1

and two IRQ7 input lines. The designer must select one line for each required interrupt and

reconfigure the other external signal line or line s for alternate functions.

Table 1-4. System Bus, HDI16, and Interrupt Signals

Signal Data Flow Description

A[0–31] Input/Output Address Bus

When the MSC8101 is in external maste r bus mode, these pins function as the address bus. The MS C8101 drive s the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8101 is in Internal Master Bus mode, these pins are used as address lines connected to memory devices and are controlled by the MSC8101 memory controller.

TT[0–4] Input/Output Bus Transfer Type

The bus master drives these pins during the address tenure to spec ify the ty pe of transaction.

TSIZ[0–3] Input/Output Transf er Size

The bus master drives these pins with a value indicatin g the number of bytes transferred in the current transa ction.

TBST

Input/Output Bus Transfer Burst

The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers f our quad words).

IRQ1

GBL

Input

Input/Output

Interrupt Request 1

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Global

When a master within the chip initiates a bus transaction, it drives this pin. When an external master initiates a bus transaction, it should drive this pin. Assertion of this pin indicates that the transfer is global and it should be snooped by caches in the syste m.

Page 13

1-9

System Bus, HDI16, and Interrupt Signals

Reserved

BADDR29

IRQ2

Output

Input

The primary configuration is reserved.

Burst Address 29

One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8101 memory controller.

Interrupt Request 2

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Reserved

BADDR30

IRQ3

Output

Input

The primary configuration is reserved.

Burst Address 30

One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8101 memory controller.

Interrupt Request 3

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Reserved

BADDR31

IRQ5

Output

Input

The primary configuration is reserved.

Burst Address 31

One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8101 memory controller.

Interrupt Request 5

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Input/Output Output

Input

Bus Request

An output when an external arbiter is used. The MSC8101 asserts this pin to request ownership of the bus.

An input when an internal arbi ter is used. An external master should assert this pin to request bus ownership from the internal arbiter.

Input/Output Output

Input

Bus Grant

An output when an internal arbiter is used. T he MSC8101 asserts this pin to grant bus ownership to an external bus master .

An input when an external ar biter is used. The external arbiter should assert this pin to grant bus ownership to the MSC8101.

ABB

IRQ2

Input/Output Output

Input

Addres s Bu s B usy

The MSC 8101 as ser ts t h is pin f or th e d ura ti on of t he ad dre ss b us tenu r e. F ol lo win g an address acknowledge (AACK

) signal, which terminates the address bus tenure,

the MSC8101 deasserts ABB

for a fraction of a bus cycle and then stops driving

this pin.

The MSC8101 does not assume bus ownership as long as it senses that this pin is asserted by an external bus master.

Interrupt Request 2

One of the eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.

Table 1-4. System Bus , HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

Page 14

1-10

System Bus, HDI16, and Interrupt Signals

TS Input/Output Bus Transfer Start

Signals

the beg in nin g of a new addres s bu s ten u r e. Th e MSC 8 10 1 as s ert s thi s

signal when one of its internal bus masters (SC140 core or DMA) begins an address tenure. When the MSC8101 senses this pin being asserted by an external bus mast er, it responds to the addres s bus tenure as required (sno op if enabled, access internal MSC 8101 resources, memory controller support) .

AACK

Input/Output Address Acknowledge

A bus slave asserts this sign al to indi cate that it identified the address tenure. Assertion of this signal terminates the address tenure.

ARTRY

Input Address Retry

Assertion of this signal indicate s that the bus transaction should be retried by the bus master. The MSC8101 asserts this signal to enforce data coherency with its internal cache and to prevent deadlock situations.

DBG

Input/Output Output

Input

Data Bus Grant

An output when an internal arbiter is used. The MSC8101 asser ts this pin as an output to grant data bus ownership to an external bus master.

An input when an external ar biter is used. The external arbiter should assert this pin as an input to grant data bus ownership to t he MSC8101.

DBB

IRQ3

Input/Output Output

Input

Data Bus Busy

The MSC8101 asserts this pin as an output for the duration of the data bus tenure. Followin g a TA

, which terminates the data bus tenure, the MSC8101 deasserts

DBB

for a fra c tion of a bus cycle and t hen stops driving this pin.

The MSC8101 does not assume data bus ownership as long as it senses DBB

asserted by an external bus master.

Interrupt Request 3

One of the eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.

D[0–31] Input/Output Data Bus Most Significant Word

In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. In Host Por t Disabled mode, these 32 bits are part of the 64-bit data bus. In Host Port Enabled mode, these bits are used as the bus in 32-bit mode.

D[32–47]

HD[0–15]

Input/Output

Data Bus Bits 32–47

In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus.

Host Data

When the HDI16 interface is enabled, these signals are lines 0-15 of the bidirectional tri-sta te data bus.

D[48–51]

HA[0–3]

Input/Output

Input

Data Bus Bits 48–51

In write transactions the bus master drives the valid data on these pins. In read transactions the slave drives the valid data on these pins.

Host Address Line 0–3

When the HDI16 interface bus is enabled, these lines address intern al host registers.

Table 1-4. System Bus , HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

Page 15

1-11

System Bus, HDI16, and Interrupt Signals

D52

HCS1

Input/Output

Input

Data Bus Bit 52

In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin.

Host Chip Select

When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select is a logical OR of HCS1

and HCS2.

D53

HRW

HRD

/HRD

Input/Output

Input

Data Bus Bit 53

In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin.

Host Read Write Select

When th e HDI16 interface is enabl ed in Sing le Strobe mode, thi s is the read/wri te input (HRW).

Host Read Strobe

When the HDI16 is programm ed to interface with a double data strobe host bus , this pin is the read data strobe Schmitt trigger input (HRD

/HRD). The polarity of the

data strobe is programmable.

D54

HDS

/HDS

HWR

/HWR

Input/Output

Input

Data Bus Bit 54

In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin.

Host Data Strobe

When the HDI16 is programmed to interface with a single data strobe host bus, this pin is the data strobe Schmitt trigger input (HDS

/HDS). The polarity of the data

strobe is pr og r am m ab le .

Host Write Data Strobe

When the HDI16 is programm ed to interface with a double data strobe host bus , this pin is the write data strobe Schmitt trigger input (HWR

/HWR). The polarity of

the da ta strobe is programmable.

D55

HREQ

/HREQ

HTRQ

/HTRQ

Input/Output

Output

Data Bus Bit 55

In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin.

Host Request

When the HDI16 is programm ed to interface with a single host request host bus, this pin is the host request output (HREQ

/HREQ) . The polarity of t h e host request is pr ogrammabl e. The host request may be programmed as a driven or open-d rain output.

Transmit Host Request

When the HDI16 is programm ed to interface with a double host request host bus, this pin is the transmit host request output (HTRQ

/HTRQ). The sign al can be programmed as driven or open drain. The polarity of th e host request is programmable.

Table 1-4. System Bus , HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

Page 16

1-12

System Bus, HDI16, and Interrupt Signals

D56

HACK

/HACK

HRRQ

/HRRQ

Input/Output

Output

Data Bus Bit 56 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin.

Host Acknowledge

When the HDI16 is programm ed to interface with a single host request host bus, this pin is the host acknowledge Schmitt trigger input (HACK). The polarity of the host acknowledge is programmable.

Receive Host Request

When the HDI16 is programm ed to interface with a double host request host bus, this pin is the receive host request output (HRRQ

/HRRQ). The signal can be programmed as driven or open drain. The polarity of th e host request is programmable.

D57

HDSP

Input/Output

Input

Data Bus Bit 57

In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin.

Host Data Strobe Polarity

When the HDI16 interface is enabled, this pin is the host data strobe polarity (HDSP).

D58

HDDS

Input/Output

Input

Data Bus Bit 58

In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin.

Host Dual Data Strobe

When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS).

D59

H8BIT

Input/Output

Input

Data Bus Bit 59

In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin.

H8BIT

When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit or 16-bit mo de .

D60

HCS2

Input/Ou tpu t

Input

Data Bus Bit 60

In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin.

Host Chip Select

When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select is a logical OR of HCS1

and HCS2.

D[61–63]

Reserved

Input/Output Data Bus Bits 61–63

Used only in 60x-mode-only mode. In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus.

These dedicated signals are reserved when the HDI16 is enabled.

Table 1-4. System Bus , HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

Page 17

1-13

System Bus, HDI16, and Interrupt Signals

Reserved

DP0

EXT_BR2

Input

Input/Output

Input

The primary configuration is reserved.

Data Parity 0

The agent that drives the data bus also drives the data parity signals. The value driven on the da ta pa rity zero pin should give odd parit y (od d number of ones ) on

the group of signals that includes data parity 0 and D[0–7].

External Bus Request 2

1,2

An external master asserts this pin to request bus ownership from the internal arbiter.

IRQ1

DP1

EXT_BG2

Input

Input/Output

Output

Interrupt Request 1

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Data Parity 1

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity one pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and D[8–15].

External Bus Grant 2

1,2

The MSC8101 asserts this pin to grant bus ownership to an external bus master.

IRQ2

DP2

EXT_DBG2

Input

Input/Output

Output

Interrupt Request 2

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Data Parity 2

The agent that drives the data bus also drives the data parity signals. The value driven on the da ta pa r it y tw o pi n sho u ld gi ve odd parity (odd number of ones) on the group of signals that includes data parity 2 and D[16–23].

External Data Bus Grant 2

1,2

The MSC8101 asserts this pin to grant data bus ownership to an external bus master.

IRQ3

DP3

EXT_BR3

Input

Input/Output

Input

Interrupt Request 3

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Data Parity 3

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity three pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and D[24–31].

External Bus Request 3

1,2

An external master asserts this pin to request bus ownership from the internal arbiter.

Table 1-4. System Bus , HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

Page 18

1-14

System Bus, HDI16, and Interrupt Signals

IRQ4

DP4

DREQ3

EXT_BG3

Input

Input/Output

Input

Output

Interrupt Request 4

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Data Parity 4

The agent that drives the data bus also drives the data parity signals. The value driv en on the data parity four pin sh ould give odd parit y (odd numb er of ones) on

the group of signals that includes data parity 4 and D[32–39].

DMA Request 3

An ext ernal peripheral uses this pin to re quest DMA service.

External Bus Grant 3

1,2

The MSC8101 asserts this pin to grant bus ownership to an external bus master.

IRQ5

DP5

DREQ4

EXT_DBG3

Input

Input/Output

Input

Output

Interrupt Request 5

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Data Parity 5

The agent that drives the data bus also drives the data parity signals. The value driven on the da ta pa r it y fiv e pin sho uld give odd parity (odd numb er of ones ) on the group of signals that includes data parity 5 and D[40–47].

DMA Request 4

An ext ernal peripheral uses this pin to re quest DMA service.

External Data Bus Grant 3

1,2

The MSC8101 asserts this pin to grant data bus ownership to an external bus master.

IRQ6

DP6

DACK3

Input

Input/Output

Output

Interrupt Request 6

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Data Parity 6

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity six pin should give odd parity (odd number of ones) on the group of signal s that incl udes data parity 6 and D[48–5 5].

DMA Acknowledge 3

The DMA drives this output to acknowledge the DMA transaction on the bus.

IRQ7

DP7

DACK4

Input

Input/Output

Output

Interrupt Request 7

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Data Parity 7

The master or slave that drives the data bus also drives the data parity signals. The value driven on the data parity seven pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and D[56–63].

DMA Acknowledge

The DMA drives this output to acknowledge the DMA transaction on the bus.

Input/Output Transfer Acknowledge

Indicates that a data beat is vali d on the data bus. For single beat transf ers, assertion of TA

indicates the termination of the transfer. For burst transfers, TA is asserted four times to indicate the transfer of four data beats with the last assertion indicating the termination of the burst transfer.

Table 1-4. System Bus , HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

Page 19

1-15

System Bus, HDI16, and Interrupt Signals

TEA Input/Output Transfer Error Acknowledge

Indic ates a bus error. masters withi n the MSC8101 monitor the state of this pin. The MSC 8101 internal bus monitor can assert this pin if it identifies a bus transfer that is hung.

NMI

Input Non-Maskable Interrupt

When an external device asserts this line, the MSC8101 NMI input is asserted.

NMI_OUT

Output Non-Maskable Interrupt

Driven from the MSC8101 internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt, pending in the MSC8101 internal interrupt controller, is waiting to be handled by an external host.

PSDVAL

Input/Output Data Valid

Indicates that a data beat is vali d on the data bus. The di fference between the TA pin and PSDVAL

is that the TA pin is asserted to indicate data transfer terminations

while the PSDVAL

signal is asserted with each data beat movement. Thus, when

is asserted, PSDVAL is asserted, but when PSDVAL is asserted, TA is not necessarily asserted. For example when the SDMA initiates a double word (2x64 bits) transfer to a memory device that has a 32-bit port size, PSDVAL

is asserte d

three times without TA,

and finally both pins are asserted to terminat e the transfer.

IRQ7

INT_OUT

Input

Output

Interrupt Request 7

One of eight external line s that can request a service routine, via the internal interrupt controller, from the SC140 core.

Interrupt Output

Driven from the MSC8101 internal interrupt controller. Assertion of this output indicates that an unmask ed interrupt is pending in the MSC8101 internal interrupt controller.

Notes: 1. See the

System Interface Unit (SIU)

chapter in the

MCS8101 Reference Manual

for de tails on how to

configure these pins.

2. When used as the bus control arbiter for th e system bus, the MSC810 1 can support up to thre e external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signal s ( BR

/BG/DBG, EXT_BR2/EXT_BG2/EX T_D BG 2, and E XT_ BR 3 /EXT _BG3 /EX T_DBG 3). Each of these sig nal sets must be configured to indicate whether the external master is or is not a MSC810 1 master device. See the Bus Configuration Register (BCR) description in the

System

Interface Unit (SIU)

chapt er in th e

MCS8 10 1 Re f erence Manu al

for details on how to configure these pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR

/BG/DBG) have a dual functi on. When th e

MSC8101 is not the bus arbit er, these signals (BR

/BG/DBG) are used by the MSC8101 to obtain

master control of the bus.

3. See the

Host Interface (HDI16)

chapter in the

MCS8101 Reference Manual

for details on ho w to

configure these pins.

Table 1-4. System Bus , HDI16, and Interrupt Signals (Continued)

Signal Data Flow Description

Page 20

1-16

Memory Co ntrol l er Si gn al s

1.6 Memory Cont roll er Si gnal s

Refer to the Memory Controller chapter in the MSC8101 Reference Manual (MSC8101RM/D) for detailed in formation about configuring these signals.

Tabl e 1-2. Memory Controller Signals

Signal

Data Flow

Description

CS[0–7] Output Chip Select

Enable specific memory devices or peripherals connected to MSC8101 buses.

BCTL1

Output Buffer Control 1

Contr ols buffers on the data bus. Usua lly used with BCTL0

. The exact function of

this pin is defined by the value of SIUMCR[BCTLC]. See the

System Interface Unit

(SIU)

chapter in the

MS8101 Technica l Reference

manual for details.

BADDR[27–28] Output Burs t Add ress 27–28

Two of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8101 memory controller.

ALE Output Address Latch Enable

Contr ols the external address latch used in external master bus co nfiguration.

BCTL0

Output Buffer Control 0

Controls buffers on the data bus. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See the

System Interface Unit (SIU)

chapter in the

MS8101 Technical Reference

manual for details.

PWE[0–7]

PSDDQM[0–7]

PBS[0–7]

Output

Bus Wr ite Enable

Outputs of the bus General-Purpose Chip-select Machine (GPCM). These pins select byte lanes for write operations.

Bus SDRAM DQM

Outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM de vices.

Bus UPM Byte Select

Outputs of the User-Programmable Machine (UPM) in the memory controller. These pins select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device.

PSDA10

PGPL0

Output

Bus SDRAM A10

Output from the bus SDRAM controller. This pin is part of the address when a row address is driven. It is part of the command when a column address is driven.

Bus UPM General-Purpose Line 0

One of six general-purpose output lines of the UPM. The values and timing of this pin are programmed in the UPM.

PSDWE

PGPL1

Output

Bus SDRAM Write Enable

Output from the bu s SDRAM controller. This pin should connec t to the SDRAM WE input signal.

Bus UPM General-Purpose Line 1

One of six general -purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

Page 21

1-17

Memory Controller Signals

POE

PSDRAS

PGPL2

Output

Bus Output Enable

Output o f th e b us G PCM . Co nt rol s t h e o ut put bu ff e r of mem or y dev ic es duri n g rea d operat io ns .

Bus SDRAM RAS

Output from the bus SDRAM controller. This pin should connect to the SDRAM Row Address Strobe (RAS) input signal.

Bus UPM General-Purpose Line 2

One of six general -purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

PSDCAS

PGPL3

Output

Bus SDRAM CAS

Output from the bus SDRAM controller. This pin should connect to the SDRAM Column Address Strobe (CAS) input signal.

Bus UPM General-Purpose Line 3

One of six general -purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

PGTA

PUPMWAIT

PPBS

PGPL4

Input

Output

GPCM TA

Terminates transactions during GPCM operation. Requires an external pull up resistor for pr oper operation.

Bus UPM Wait

Input to the UPM. An external device can hold this pin high to force the UPM to wait until the device is ready for the operation to continue.

Bus Parity Byte Select

In systems in which data parity is stored in a separate chip, this output is the byte-select for that chip.

Bus UPM General-Purpose Line 4

One of six general -purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

PSDAMUX

PGPL5

Output

Bus SDRAM Address Multiplexer

Controls the SDRAM address multiplexer when the MSC8101 is in External Master mode.

Bus UPM General-Purpose Line 5

One of six general -purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

Table 1-2. Memory Controller Signals (Continued)

Signal

Data Flow

Description

Page 22

1-18

Communications Processor Module (CPM) Ports

1.7 Com muni cations Pr oc essor Mo dul e ( CPM ) Por ts

The MSC8101 CPM supports a su bset of signals included in the MPC8260. The following sections describe the func tionality of the signals in the MSC8101.

• The MSC8101 CPM includes the following set of communica tion controllers:

• Two full-duplex Fast Serial Communicatio ns Control lers (FCCs) that support: — Asynchronous Transfe r Mode (ATM) through a UTOPIA 8 interface (FCC1 only)—The

MSC8101 can operate as one of the following:

UTOPIA sl ave device

UTOPIA multi-PHY master device using direct polling for up to 4 PHY devices

UTOPIA multi-PHY master device using multiplex polling that can address up to 31 PHY

devices at addresses 0–30 (address 31 is reserved as a null port). — IEEE 802.3/Fast Ethernet through a Media-Independent Interface (MII) — High-Level Data Link Control (HDLC) Protocol:

Serial mode—Transfers data one bit at a time

Nibble mode—Transfers data four bits at a time — Transparent mode serial operation

• One FCC that operates wit h the T SA onl y

• Two Multi-Channel Controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64 Kbps each, mul tiplexed on up to four TDM interfaces

• Two full-duplex seria l communications contr ollers (SCCs) that support the following protocols: — IEEE 802.3/Fast Ethernet through a Media-Independent Interface (MII) — HDLC Protocol:

Serial mode—Transfers data one bit at a time

Nibble mode—Transfers data four bits at a time — Synchronous Data Link Control (SDLC) — LocalTalk (HDLC-based local area network protocol) — Universal Asynchronous Receiver/Transmitter (UART) — Synchronous UART (1x clock mode) — Binary Synchronous (BISYNC) communication — Transparent mode serial operation

• Two additional SCCs that operate with the TSA only

• Two full-duplex Serial Management Controllers (SMCs) that support the following protocols: — General Circuit Interface (GCI)/Integrated Services Digital Network (ISDN) monitor and C/I

channels (TSA only) — UART — Transparent mode serial operation

• Serial Peripheral Interface (SPI) support for master or slave ope ration

• Inter-Integrated Circuit (I

C) bus controller

• Time-Slot Assigner (T SA) that supports multiple xing from any of the SCCs, FCCs, SMCs, and two MCCs onto four time-division multiplexed (TDM) interfaces. The TSA uses two Serial Interface s (SI1 and SI2). SI1 uses TDMA1 which supports both serial and nibble mode. SI2 does not support nibble mode and includes TDMB2, TDMC2, and TDMD2 whic h operate only in serial mode.

The individual sets of externals signals associated with a sp ecific protocol an d data transfer mode are multiplex ed ac ros s any or all of the ports, as shown in Figure 1-2. The following sections provide detailed desc riptions of the signals s upported by Ports A–Port D.

Page 23

1-19

Communications Processor Module (CPM) Ports

1.7.1 Port A Signals

Table 1-3. Port A Signals

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated Signal

Protocol

PA31 FCC1: TXENB

UTOPIA master

FCC1: TXENB

UTOPIA slave

FCC1: COL

MII

Output

Input

FCC1: UTOPIA Master Transmit Enable

In the ATM UTOPIA interface supported by FCC1, TXENB is asserted by the MSC8101 (UTOPIA master PHY) when

there is valid transmit cell data (TXD[0–7]).

FCC1: UTOPIA Slave Transmit Enable

In the ATM UTOPIA interface supported by FCC1, TXENB is asserted by an external UTOPIA master PHY when there is valid trans m it cell data (TXD[0–7]).

FCC1: Medi a Inde pe nde nt Inte rfac e Coll is ion Dete ct

In the MII interface supported by FCC1, COL is asserted by an external fast Ethernet PHY.

PA30 FCC1: TXCLAV

UTOPIA slave

FCC1: TXCLAV

UTOPIA master

, or

FCC1: TXCLAV0

UTOPIA ma s ter , Mul ti- P H Y, direct polling

FCC1: RTS

HDLC, Serial and Nibble

FCC1: CRS

MII

Output

Input

Output

Input

FCC1: UTOPIA Slave Transmit Cell Available

In the ATM UTOPIA interface supported by FCC1, TXCLAV is asser ted by t he MSC 8101 (UT OP I A sla ve P HY) w h en th e MSC8101 c an accept one complete ATM cell.

FCC1: UTOPIA Master Transmit Cell Available

In the ATM UTOPIA interface supported by FCC1, TXCLAV is asserted by an external U TO PIA slave PHY to indicate that it can accept one complete ATM cell.

FCC1: UTOPIA Master Transmit Cell Available Multi-PHY Direct Polling

In the ATM UTOPIA interface supported by FCC1, TXCLAV0 is asserted by an external UTOPIA slave PHY using direct polling to indicate that it can accept one complete ATM cell.

FCC1: Request To Send

In the standard modem interface signals supported by FCC1 (RTS

, CTS, and CD). RTS is asynchronous with the

data. RTS

is typically used in conjunction with CD. The MSC8101 FCC1 tran smitter requests the receiver to send data by a sserting RTS

low. The request is accepted when

CTS

is returned low.

FCC1: Media Independent Interface Carrier Sense

In th e MII in terface supported by F CC1. CRS is asserted by an external fast Ethernet PHY. It in dicates activity on the cable.

Page 24

1-20

Communications Processor Module (CPM) Ports

PA29 FCC1: TXSOC

UTOPIA master

FCC1: TXSOC

UTOPIA slave

FCC1: TX_ER

MII

Output

Input

Output

FCC1: UTOPIA Transmit Start of Cell

In the ATM UTOPIA interface supported by FCC1. TXSOC is asserted by the MSC8101 (UTOPIA master PHY) when

TXD[0–7] contains the fir s t valid byte of the cell.

FCC1: UTOPIA Transmit Start of Cell

In the ATM UTOPIA interface supported by FCC1. TXSOC is asserted by the external UTOPIA master PHY when TXD[0–7] contains the fir s t valid byte of the cell.

FCC1: Media Independent Interface Transmit Error

In the MI I interface supported by FC C1. TX_E R is asser ted by the MSC8101 to force propagation of transmit errors.

PA28 FCC1: RXENB

UTOPIA master

FCC1: RXENB

UTOPIA slave

FCC1: TX_EN

MII

Output

Input

Output

FCC1: UTOPIA Master Receive Enable

In th e AT M UTOP IA in ter f ac e suppo r te d by F CC 1. (U TO PIA master) RXENB

is asserted by the MSC8101 (UTOPIA master PHY) to indicate that RXD[0–7] and RXSOC are to be sampled at the end of the next cycle. RX D[0–7] and RXSOC are enabled only in cycles foll owing those with RXENB

asserted.

FCC1: UTOPIA Master Receive Enable

In th e AT M UTOP IA in ter f ac e suppo r te d by F CC 1. (U TO PIA slave) RXENB

is an input asserted by an external PHY to indicate that RXD[0–7] and RXSOC is to be sampled at the end of the next cycl e. RXD[0–7] and RXSOC are enabled only in cycles following th ose with RXENB

asserted.

FCC1: Media Independent Interface Transmit Enable

In the MI I interface supported by FC C1. TX_E N is asser ted by the MSC8101 when transmitting data.

PA27 FCC1: RXSOC

UTOPIA master

FCC1: RXSOC

UTOPIA slave

FCC1: RX_DV

MII

Input

Output

Input

FCC1: UTOPIA Receive Start of Cell

Asserted by an external PHY when RXD[0–7] contains the first valid byte of the cell.

FCC1: UTOPIA Receive Start of Cell

Asserted by the MSC8101 (UTOPIA slave) for an exte rnal PHY when RXD[0–7] contains the first valid byte of the cell.

FCC1: Media Independent Interface Receive Data Valid

In the MII interface supported by FCC1. RX_DV is an input asserted by an external fast Ethernet PHY. RX_DV indicates that valid data is being sent. The presence of carrier sense but not RX_DV indicates reception of broken packet he ad er s , pro bably due to ba d wiring or a bad circui t.

Tabl e 1-3. Port A Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated Signal

Protocol

Page 25

1-21

Communications Processor Module (CPM) Ports

PA26 FCC1: RXCLAV

UTOPIA slave

FCC1: RXCLAV

UTOPIA ma s ter , or

RXCLAV0

UTOPIA ma s ter , Mul ti- P H Y, direct polling

FCC1: RX_ER

MII

Output

Input

FCC1: UTOPIA Slave Receive Cell Available

In the ATM UTOPIA interface supported by FCC1. RXCLAV is asserted by the MSC8101 (UTOPIA slave PHY) when one complete ATM cell is available for transfer.

FCC1: UTOPIA Master Receive Cell Available

In the ATM UTOPIA interface supported by FCC1. RXCLAV is asserted by an external PHY when one complete ATM cell is available for transfer.

FCC1: UTOPIA Master Receive Cell Available 0 Direct Polling

In the ATM UTOPIA interface supported by FCC1, RXCLAV0 is asserted by an external PHY when one complete ATM cell is available for transfer.

FCC1: Media Independent Interface Receive Error

In the MII interface and supported by FCC1. RX_ER is asserted by an external fast Ethernet PHY. This signal indicates a receive error, which often indicates bad wiring.

PA25 FCC1: TXD0

UTOPIA

SDMA: MSNUM0

Output

FCC1: UTOPIA Transmit Data Bit 0

In the ATM UTOPIA interface supported by FCC1. The MSC8101 outputs ATM cell octets (UTOPIA interface data)

on TXD[0–7]. TX D7 is the most significant bit. TXD0 is the least significant bit . Whe n no A TM dat a is av ai la bl e, id le cells are inserted. A cell is 53 bytes.

Module Serial Number Bit 0

MSNUM[0–4] of is the sub-block code of the current peripheral contr oller using SDMA. MSN UM5 indicates which section, transmit (0) or receive (1), is active during the transfer.

PA24 FCC1: TXD1

UTOPIA

SDMA: MSNUM1

Output

FCC1: UTOPIA Transmit Data Bit 1

In the ATM UTOPIA interface supported by FCC1. The MSC8101 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. TX D7 is the most significant bit. TXD0 is the least significant bit . Whe n no A TM dat a is av ai la bl e, id le cells are inserted. A cell is 53 bytes.

Module Serial Number Bit 1

MSNUM[0–4] of is the sub-block code of the current peripheral contr oller using SDMA. MSN UM5 indicates which section, transmit (0) or receive (1), is active during the transfer.

PA23 FCC1: TXD2

UTOPIA

Output FCC1: UTOPIA Transmit Data Bit 2

TXD[0– 7] i s par t o f th e ATM U TOP IA in ter f ac e s up po rte d b y FCC1. The MSC8101 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. TXD7 is the most significant bit. TXD 0 is the least sign ificant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes.

Tabl e 1-3. Port A Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated Signal

Protocol

Page 26

1-22

Communications Processor Module (CPM) Ports

PA22 FCC1: TXD3

UTOPIA

Output FCC1: UTOPIA Transmit Data Bit 3

PA21 FCC1: TXD4

UTOPIA

FCC1: TXD3

MII

and

HDLC nibb le

Output

FCC1: UTOPIA Transmit Data Bit 4

FCC1: MII and HDLC Nibble Transmit Data Bit 3

TXD[3–0] supports MII and HDLC nibble modes in FCC1. TXD3 is the most significant bit. TXD0 is the least significant bit.

PA20 FCC1: TXD5

UTOPIA

FCC1: TXD2

MII

and

HDLC nibb le

Output

FCC1: UTOPIA Transmit Data Bit 5

FCC1: MII and HDLC Nibble Transmit Data Bit 2

TXD[3–0] is supported by MII and HDLC nibble mo des in FCC1. TXD3 is the most significant bit. TXD0 is the least significant bit.

PA19 FCC1: TXD6

UTOPIA

FCC1: TXD1

MII

and

HDLC nibb le

Output

FCC1: UTOPIA Transmit Data Bit 6

FCC1: MII and HDLC Nibble Transmit Data Bit 1

TXD[3–0] is supported by MII and HDLC transparent nibble modes in FCC1. TXD3 is the most significant bit. TXD0 is the least significant bit.

Tabl e 1-3. Port A Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated Signal

Protocol

Page 27

1-23

Communications Processor Module (CPM) Ports

PA18 FCC1: TXD7

UTOPIA

FCC1: TXD0

MII

and

HDLC nibb le

FCC1: TXD

HDLC serial

and

transparent

Output

FCC1: UTOPIA Transmit Data Bit 7.

FCC1: MII and HDLC Nibble Transmit Data Bit 0

TXD[3–0] is supported by MII and HDLC nibble mo des in FCC1. TXD3 is the most significant bit. TXD0 is the least significant bit.

FCC1: HDLC Serial and Transparent Transmit Data Bit

The TXD serial bit is supported by HDLC serial and transparent modes in FCC1.

PA17 FCC1: RXD7

UTOPIA

FCC1: RXD0

MII

and

HDLC nibb le

FCC1: RXD

HDLC serial

and

transparent

Input

FCC1: UTOPIA Receive Data Bit 7.

RXD[0–7] is part of the ATM UTOPIA interface supported by FCC1. The MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri- stated, enabled only when RXENB

is asserted.

FCC1: MII and HDLC Nibble Receive Data Bit 0

RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD3 is the most significant bit. RXD0 is the least significant bit.

FCC1: HDLC Serial and Transparent Receive Data Bit

The RXD s erial bit is suppor ted by HDLC and transparent by FCC1.

PA16 FCC1: RXD6

UTOPIA

FCC1: RXD1

MII

and

HDLC nibb le

Input

FCC1: UTOPIA Receive Data Bit 6.

is asserted.

FCC1: MII and HDLC Nibble Receive Data Bit 1

RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD3 is the most significant bit. RXD0 is the least significant bit.

Tabl e 1-3. Port A Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated Signal

Protocol

Page 28

1-24

Communications Processor Module (CPM) Ports

PA15 FCC1: RXD5

UTOPIA

RXD2

MII

and

HDLC nibb le

Input

FCC1: UTOPIA Receive Data Bit 5

In the ATM UTOPIA interface supported by FCC1. The MSC8101 inputs ATM cell octets (UTOPIA interface data)

on RXD[0–7]. RXD7 is the most signifi c ant bit. RXD0 is the least significant bit . Whe n no A TM dat a is av ai la bl e, id le cells are inserted. A cell is 53 bytes. To support M ulti-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB

is asserted.

FCC1: MII and HDLC Nibble Receive Data Bit 2

RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD3 is the most significant bit. RXD0 is the least significant bit.

PA14 FCC1: RXD4

UTOPIA

FCC1: RXD3

MII

and

HDLC nibb le

Input

FCC1: UTOPIA Receive Data Bit 4.

In the ATM UTOPIA interface supported by FCC1. The MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most signifi c ant bit. RXD0 is the least significant bit . Whe n no A TM dat a is av ai la bl e, id le cells are inserted. A cell is 53 bytes. To support M ulti-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB

is asserted.

FCC1: MII and HDLC Nibble Receive Data Bit 3

RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD3 is the most significant bit. RXD0 is the least significant bit.

PA13 FCC1: RXD3

UTOPIA

SDMA: MSNUM2

Input

Output

FCC1: UTOPIA Receive Data Bit 3

In the ATM UTOPIA interface supported by FCC1. The MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most signifi c ant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB

is asserted.

Module Serial Number Bit 2

MSNUM[0– 4] is th e sub-bl ock cod e of the cur rent peri pheral controller using SDMA. MSNUM5 indicates which section, trans mit (0) or receive (1), is active during the transfer.

PA12 FCC1: RXD2

UTOPIA

SDMA: MSNUM3

Input

Output

FCC1: UTOPIA Receive Data Bit 2

In the ATM UTOPIA interface supported by FCC1. The MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most signifi c ant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB

is asserted.

Module Serial Number Bit 3

MSNUM[0-4] of is the sub-block code of the curren t peripheral contr oller using SDMA. MSN UM5 indicates which section, transmit (0) or receive (1), is active during the transfer.

Tabl e 1-3. Port A Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated Signal

Protocol

Page 29

1-25

Communications Processor Module (CPM) Ports

PA11 FCC1: RXD1

UTOPIA

SDMA: MSNUM4

Input

Output

FCC1: UTOPIA RX Receive Data Bit 1

In the ATM UTOPIA interface supported by FCC1. The MSC8101 inputs ATM cell octets (UTOPIA interface data)

on RXD[0–7]. RXD7 is the most signifi c ant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB

is asserted.

Module Serial Number Bit 4

MSNUM[0–4] of is the sub-block code of the current peripheral contr oller using SDMA. MSN UM5 indicates which section, transmit (0) or receive (1) is active during the transfer.

PA10 FCC1: RXD0

UTOPIA

SDMA: MSNUM5

Input

Output

FCC1: UTOPIA RX Receive Data Bit 0

In the ATM UTOPIA interface supported by FCC1. The MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most signifi c ant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB

is asserted.

Module Serial Number Bit 5

MSNUM[0–4] of is the sub-block code of the current peripheral contr oller using SDMA. MSN UM5 indicates which section, transmit (0) or receive (1), is active during the transfer.

PA9 SMC2: SMTXD

SI1 TDMA1: L1TXD0

TDM ni bb le

Output

SMC2: Serial Management Transm it Data

Supported by SMC2. The SMC interface consists of SMTXD, SMRXD, SMSYN

, and a clock. Not all signals a re used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). See also PC15.

Time-Division Multiplexing A1: Layer 1 Transmit Data Bit 0

In the T DMA1 interface supported by SI1. L1TXD3 is the most significant bit. L1TXD0 is the least significant bit in nibble mode. TDMA1 transmits nibble data out L1TX D[0–3].

Tabl e 1-3. Port A Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated Signal

Protocol

Page 30

1-26

Communications Processor Module (CPM) Ports

PA8 SMC2: SMRXD

SI1 TDMA1: L1RXD0

TDM ni bb le

SI1 TDMA1: L1RXD

TDM se r ia l

Input

SMC2: Serial Management Receive Data

Supported by SMC2. The SMC interface consists of SMTXD, SMRXD, SMSYN

, and a clock. Not all signals a re used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI).

Time-Division Multiplexing A1: Layer 1 Nibble Receive Data Bit 0

In the T DMA1 interface supported by SI1. L1RXD3 is the most significant bit. L1RXD0 is the least significant bit in nibble mode. TDMA1 receives nibble data from

L1RXD[0–3].

Time-Division Multiplexing A1: Layer 1 Serial Receive Data

In the TDMA1 interface supported by SI1. TDMA1 receives serial data from L1RXD.

PA7 SMC2: SMSYN

SI1 TDMA1: L1TSYNC

TDM ni bb le

and

TDM serial

Input

SMC2: Serial Management Synchronization

The SMC interface consists of SMTXD, SMRXD, SMSYN

, and a clock. Not all signals are used for al l applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or gener al-circuit interface (GCI).

Time-Division Multiplexing A1: Layer 1 Transmit Synchronization

In the T DMA1 interface supported by S I1, this is the synchronizing signal for the transmit channel. See the

Serial

Interface with Time-Slot Assigner

chapter in the

MSC8101

Techni cal Reference

manual .

PA6 SI1 TDMA1: L1RSYNC

TDM ni bb le

and

TDM serial

Input Time-Division Multiplexing A1: Layer 1 Receive

Synchronization.

In the T DMA1 interface supported by S I1, this is the synchronizing signal for the receive channel.

Tabl e 1-3. Port A Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated Signal

Protocol

Page 31

1-27

Communications Processor Module (CPM) Ports

1.7.2 Port B Signals

Table 1-4. Port B Signals

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated I/O

Protocol

PB31 FCC2: TX_ER

MII

SCC2: RXD

SI2 TDMB2: L1TXD

TDM se r ia l

Output

Input

Output

FCC2: Media Independent Interface Transmit Error

In the MII interface supported by FCC2. TX_ER is asserted by the MSC8101 to force propagation of transmit errors.

SCC2: Receive Data

Supported by SCC2. SCC2 receives serial da ta from RXD.

Time-Division Multiplexing B2: Layer 1 Transmit Data

In the T DMB2 interface supported by S I2. L1TXD supports serial mode. TDMB2 transmits serial data out of L1TXD.

PB30 SCC2: TXD

FCC2: RX_DV

MII

SI2 TDMB2: L1RXD

TDM se r ia l

Output

Input

SCC2: Transmit Data.

Supported by SC C2. SCC2 transmits serial data out of TXD.

FCC2: Media Independent Interface Receive Data Valid In the MII inte rface supported by FCC2, RX_DV is asserted by an external fast Ethernet PHY. RX_DV indicates that valid da ta is bein g sent. The presence of carrier sense, but not RX_DV, indicates reception of broken packet headers, probably due to bad wiring or a bad circuit.

Time-Division Multiplexing B2: Layer 1 Receive Data

In the T DMB2 interface supported by S I2. L1RXD supports serial mode. TDMB2 receives serial data from L1RXD.

PB29 FCC2: TX_EN

MII

SI2 TDMB2: L1RSYNC

TDM se r ia l

Output

Input

FCC2: Media Independent Interface Transmit Enable

In the MII inte rface supported by FCC2. TX_EN is asserted by the MSC8101 when transmitting data.

Time-Division Multiplexing B2: Layer 1 Receive Synchronization

In the T DMB2 interface supported by S I2, this is the synchronizing signal for the receive channel.

Page 32

1-28

Communications Processor Module (CPM) Ports

PB28 FCC2: RTS

HDLC serial, HDLC nibble

and

transparent

FCC2: RX_ER

MII

SCC2: RTS, TENA

SI2 TDMB2: L1TSYNC

TDM se r ia l

Output

Input

Output

Input

FCC2: Request to Send

One of the standard modem interface signals suppo rted by FCC2 (RTS

, CTS, and CD). RTS is asynchronous with the

data. RTS

is typically used in conjunction with CD. The MSC8101 FCC2 tran smitter requests the receiver to send data by a sserting RTS

low. The request is accepted when

CTS

is returned low.

FCC2: Media Independent Interface Receive Error

In the MII inte rface supported by FCC2, RX_ER is asserted by an external fast Ethernet PHY. This signal indicates a receive error, which often indicates bad wiri ng.

SCC2: Request to Send, Transmit Enable

Typically used in conjunction with CD

supported by SCC2. The MSC8101 SCC2 transmitter requests the receiver to send data by asserting RTS

low. The request is accepted

when CTS

is retu rned low. TENA is the signal used in

Ether ne t mode.

Time-Division Multiplexing B2: Layer 1 Transmit Synchronization

In the T DMB2 interface supported by S I2, this is the synchronizing signal for the transmit channel. See the

Serial

Interface with Time-Slot Assigner

chapter in the

MSC8101

Techni cal Reference

manual.

PB27 FCC2: COL

MII

SI2 TDMC2: L1TXD

TDM se r ia l

Input

Output

FCC2: Medi a Inde pe nde nt Inte rfac e Coll is ion Dete ct

In the MII inter face supported by FCC2. CO L is asserted by an external fast Ethernet PHY.

Time-Division Multiplexing C2: Layer 1 Transmit Data

In the T DMC2 interface supp orted by SI2. L1TXD supports serial mode. TDMC2 transmits serial data out of L1TXD.

PB26 FCC2: CRS

MII

SI2 TDMC2: L1RXD

TDM se r ia l

Input

FCC2: Media Independent Interface Carrier Sense Input

In the MI I interface, CRS is asserted by an exte rnal fast Ethernet PHY. This signal indicates activity on the cable.

Time-Division Multiplexing C2: Layer 1 Receive Data

In the T DMC2 interface supp orted by SI2. L1RXD supports serial mode. TDMC2 receives serial data from L1R XD.

Tabl e 1-4. Port B Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated I/O

Protocol

Page 33

1-29

Communications Processor Module (CPM) Ports

PB25 FCC2: TXD3

MII

and

HDLC nibb le

SI1 TDMA1: L1TXD3

TDM ni bb le

SI2 TDMC2: L1TSYNC

TDM se r ia l

Output

Input

FCC2: MII and HDLC Nibble Transmit Data Bit 3

Supported by MII and HDLC nibble mode in FCC2. TXD3 is the most signifi cant bit. TXD0 is the least sign ificant bit.

Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 3

TDMA1 transmits nibble data out of L1TXD[0–3]. L1TXD3 is the most signifi cant bit and L1TXD0 is the least significant bit in nibble mode.

Time-Division Multiplexing C2: Layer 1 Transmit Synchronization

In the T DMC2 interface supp orted by SI2, this is the synchronizing signal for the transmit channel. See the

Serial

Interface with Time-Slot Assigner

chapter in the

MSC8101

Techni cal Reference

manual .

PB24 FCC2: TXD2

MII

and

HDLC nibb le

SI1 TDMA1: L1RXD3

nibble

SI2 TDMC2: L1RSYNC

serial

Output

Input

FCC2: MII and HDLC Nibble: Transmit Data Bit 2

Supported by MII and HDLC nibble mode in FCC2. TXD3 is the most signifi cant bit. TXD0 is the least sign ificant bit.

Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 3

TDMA1 receives nibble data into L1RXD[0–3]. L1RXD3 is the most signifi c ant bit and L1RXD0 is the least significant bit in nibble mode.

Time-Division Multiplexing C2: Layer 1 Receive Synchronization

In the T DMC2 interface supp orted by SI2, this is the synchronizing signal for the receive channel.

PB23 FCC2: TXD1

MII

and

HDLC nibb le

SI1 TDMA1: L1RXD2

TDM ni bb le

SI2 TDMD2: L1TXD

TDM se r ia l

Output

Input

Output

FCC2: MII and HDLC Nibble: Transmit Data Bit 1

Supported by MII and HDLC nibble mode in FCC2. TXD3 is the most signifi cant bit. TXD0 is the least sign ificant bit.

Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 2

In the T DMA1 interface supported by S I1. TDMA1 s upports bit and nibble modes. L1RXD3 is the most significant bit. L1RXD0 is the least significant bit in nibble mode. TDMA1 receives nibble data from L1RXD[0–3].

Time-Division Multiplexing D2: Layer 1 Transmit Data

In the T DMD2 interface supp orted by SI2. L1TXD supports serial mode. TDMA1 transmits serial data out of L1TXD.

Tabl e 1-4. Port B Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated I/O

Protocol

Page 34

1-30

Communications Processor Module (CPM) Ports

PB22 FCC2: TXD0

MII

and

HDLC nibb le

FCC2: TXD

HDLC serial

and

transparent

SI1 TDMA1: L1RXD1

TDM ni bb le

SI2 TDMD2: L1RXD

TDM se r ia l

Output

Input

FCC2: MII and HDLC Nibble Transmit Data Bit 0

TXD[0–3] is sup ported by MII and HDLC nibble mode in FCC2. TXD3 is the most significant bit. TXD0 is the least significant bit.

FCC2: HD LC Serial and Transparent Transmit Data

TXD is supported by HDLC serial mode and transparent mode in FCC2.

Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 1

Time-Division Multiplexing D2: Layer 1 Receive Data

In the TD MD2 interface supported by SI2. TDMD2 supports serial mode. TDMD2 receives serial data from L1R XD.

PB21 FCC2: RXD0

MII

and

HDLC nibb le

FCC2: RXD

HDLC serial

and

transparent

SI1 TDMA1: L1TXD2

TDM ni bb le

SI2 TDMD2: L1TSYNC

TDM se r ia l

Input

Output

Input

FCC2: MII and HDLC Nibble Receive Data Bit 0

RXD[0–3] is supported by MII and HDLC nibble mode in FCC2. RXD3 is the most significant bit. RXD0 is the least significant bit.

FCC2: HDLC Serial and Transparent Receive Data

Supported by HDLC serial mode and transparent mode in FCC2.

Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 2

In the T DMA1 interface supported by S I1. TDMA1 s upports bit and nibble modes. L1TXD3 is the most significant bit. L1TXD0 is the least significant bit in nibble mode. TDMA1 transmits nibble data out of L1TXD[0–3].

Time-Division Multiplexing D2: Layer 1 Transmit Synchro niz e Data

In the T DMD2 interface supp orted by SI2, this is the synchronizing signal for the transmit channel. See the

Serial

Interface with Time-Slot Assigner

chapter in the

MSC8101

Techni cal Reference

manual.

Tabl e 1-4. Port B Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated I/O

Protocol

Page 35

1-31

Communications Processor Module (CPM) Ports

PB20 FCC2: RXD1

MII

and

HDLC nibb le

SI1 TDMA1: L1TXD1

TDM ni bb le

SI2 TDMD2: L1RSYNC

TDM se r ia l

Input

Output

Input

FCC2: MII and HDLC Nibble: Receive Data Bit 1

RXD[0–3] is supported by MII and HDLC nibble mode in FCC2. RXD3 is the most significant bit. RXD0 is the least significant bit.

Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 1

Time-Division Multiplexing D2: Layer 1 Receive Synchro niz e Data

In the T DMD2 interface supp orted by SI2, this is the synchronizing signal for the receive channel.

PB19 FCC2: RXD2

MII

and

HDLC nibb le

C: SDA

Input

Input/

Output

FCC2: MII and HDLC Nibble Receive Data Bit 2

RXD[0–3] is supported by MII and HDLC nibble mode in FCC2. RXD3 is the most significant bit. RXD0 is the least significant bit.

C: Inter-Integrated Circuit Serial Data

The I

C interface comprises two signals: serial data (SDA)

and serial clock (SDA). The I

C controller uses a synchronous, multi master bus t hat can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock.

PB18 FCC2: RXD3

MII

and

HDLC nibb le

C: SCL

Input

Input/

Output

FCC2: MII and HDLC Nibble Receive Data Bit 3

RXD[0–3] is supported by MII and HDLC nibble mode in FCC2. RXD3 is the most significant bit. RXD0 is the least significant bit.

C: Inter-Integrated Circuit Serial Clock

The I

C interface comprises two signals: serial data (SDA)

and serial clock (SDA). The I

C controller uses a synchronous, multi master bus t hat can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock.

Tabl e 1-4. Port B Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

1.7.3 Port C Signals

Table 1-5. Port C Signals

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Controller:

Dedicated I/O

Protocol

PC31 BRG1O

CLK1

TIMER1/2: TGATE1

Output

Input

Baud-Rate Generator 1 Output

The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. BRG1O can be the internal input to the SIU timers. When CLK5 is selected (see PC27 below), it is the source for BRG1O which is the default input for the SIU timers. See the

System Interface Unit (SIU)

chapter in the

MSC8101 Technical Reference

manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled.

Clock 1

The CPM supports up to 10 clock in put pins. The clocks are sent to the bank-of-clocks selection logic, where they ca n be routed to the controllers.

Timer 1/2: Timer Gate 1

The timers can be gated/restarted by an exter nal gate si gnal. There are t wo gate signals: TGATE1

controls timer 1 and/or 2

and TGATE 2

controls timer 3 and/or 4.

PC30 BRG2O

CLK2

Timer1: TOUT1

EXT1

Output

Input

Output

Input

Baud-Rate Generator 2 Output

The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.

Clock 2

The CPM supports up to 10 clock in put pins. The clocks are sent to the bank-of-clocks selection logic, where they ca n be routed to the controllers.

Timer 1: Timer O ut 1

The timers (Timer[1–4]) can output a signal on a timer output (TOUT

[1–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The out put can also connect internally to the input of another timer, resulting in a 32-bit timer.

External Request 1

External request input line 1 asserts an internal request to the CPM proc essor. The signal can be programmed as leve l- or edge-sensitive , and also has programmable priority. Refer to the RISC Controller Configuration Register (RCCR) description in the Chapter 17 of the MSC8101 Reference Manual for programming information. There are no current microc ode applications for this request l ine. It is reserved for future de ve lo pm ent.

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Communications Processor Module (CPM) Ports

PC29 BRG3O

CLK3

TIN2

SCC1: CTS

, CLSN

Output

Input

Baud-Rate Generator 3 Output

The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.

Clock 3

The CPM supports up to 10 clock in put pins. The clocks are sent to the bank-of-clocks selection logic, where they ca n be routed to the controllers.

Timer Input 2

A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges.

SCC1: Clear to Send, Collision

Typically used in conjunction with RTS

. The MSC8101 SCC1

trans mitter sends out a request to send data signal (RTS

The request is accepted when CTS

is returned low. CLSN is

the signal used in Ethernet mode. See also PC15.

PC28 BRG4O

CLK4

TIN1

Timer2: TOUT2

SCC2: CTS, CLSN

Output

Input

Output

Input

Baud-Rate Generator 4 Output

The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.

Clock 4

The CPM supports up to 10 clock in put pins. The clocks are sent to the bank-of-clocks selection logic, where they ca n be routed to the controllers.

Timer Input 1

Timer 2: Timer O utput 2

The timers (Timer[1–4]) can output a signal on a timer output (TOUT[

1–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also be connected internally to the input of another timer, resulting in a 32-bit timer.

SCC2: Clear to Send, Collision

Typically used in conjunction with RTS

. The MSC8101 SCC2

trans mitter sends out a request to send data signal (RTS

The request is accepted when CTS

is returned low. CLSN is

the signal used in Ethernet mode. See also PC13.

Table 1- 5. Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Controller:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

PC27 BRG5O

CLK5

TIMER3/4: TGATE2

Output

Input

Baud-Rate Generator 5 Output

The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.

Clock 5

When selected, CLK5 is a source for the SIU timers via BRG1O. See the

System Interface Unit (SIU)

chapter in the

MSC8101 Techni ca l R efe rence

manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enable d (see PC26 below), the BRG1O input to the SIU timers is disabled.

Timer 3/4: Timer Gate 2

The timers can be gated/restarted by an exter nal gate si gnal. There are t wo gate signals: TGATE1

controls timer 1 and/or 2

and TGATE 2

controls timer 3 and/or 4.

PC26 BRG6O

CLK6

Timer3: TOUT3

TMCLK

Output

Input

Output

Input

Baud-Rate Generator 6 Output

The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.

Clock 6

The CPM supports up to 10 clock in put pins. The clocks are sent to the bank-of-clocks selection logic, where they ca n be routed to the controllers.

Timer 3: Timer O ut 3

The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1

–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The out put can also connect internally to the input of another timer, resulting in a 32-bit timer.

Timer Clock

When selected, TMCLK is the designated input to the SIU timers . When TMCLK is configured as the input to the SIU timers, the BRG1O input is disabled. See the

System

Interface Unit (SIU)

chapter in the

MSC8101 Technical

Reference

manual for additional information.

Table 1- 5. Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Controller:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

PC25 BRG7O

CLK7

TIN4

DMA: DACK2

Output

Input

Output

Baud-Rate Generator 7 Output

The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.

Clock 7

The CPM supports up to 10 clock in put pins. The clocks are sent to the bank-of-clocks selection logic, where they ca n be routed to the controllers.

Timer Input 4

DMA: Data Acknowledge 2

DACK2

, DREQ2, DRACK2 and DONE2 belong to the SIU

DMA. DONE2

and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pin s associat ed with the PIO ports.

PC24 BRG8O

CLK8

TIN3

Timer4: TOUT4

DMA: DREQ2

Output

Input

Output

Input

Baud-Rate Generator 8 Output

The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins.

Clock 8

The CPM supports up to 10 clock in put pins. The clocks are sent to the bank-of-clocks selection logic, where they ca n be routed to the controllers.

Timer Input 3

A timer can have one of the following sources: another timer, system clock, system clock divided by 16, or a timer input. The CPM supports up to four timer inputs. The timer inputs can be captured on t he rising, falling, or both edges.

Timer 4: Timer O ut 4

The timers (Timer1–4]) can output a signal on a timer output (TOUT[1–4]

) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also be connected internally to the input of another timer, resulting in a 32-bit timer.

DMA: Data Request 2

DACK2

, DREQ2, DRACK2, and DONE2 belong to the SIU

DMA. DONE2

and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pin s associat ed with the PIO ports.

Table 1- 5. Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Controller:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

PC23 CLK9

DMA: DACK1

EXT2

Input

Output

Input

Clock 9

The CPM supports up to 10 clock in put pins. The clocks are sent to the bank-of-clocks selection logic, where they ca n be routed to the controllers.

DMA: Data Acknowledge 1

DACK1

, DREQ1, DRACK1, and DONE1 belong to the SIU

DMA. DONE1

and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pin s associat ed with the PIO ports.

External Request 2

External request input line 2 asserts an internal request to the CPM proc essor. The signal can be programmed as leve l- or edge-sensitive , and also has programmable priority. Refer to the RISC Controller Configuration Register (RCCR) description in the Chapter 17 of the MSC8101 Reference Manual for programming information. There are no current microc ode applications for this request l ine. It is reserved for future de ve lo pm ent.

PC22 SI1: L1ST1

CLK10

DMA: DREQ1

Output

Input

Input/

Output

Serial Interface 1: La yer 1 Strobe 1

In the t ime-slot assigner supported by SI1. The MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling thr ee-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control.

Clock 10

The CPM supports up to 10 clock in put pins. The clocks are sent to the bank-of-clocks selection logic, where they ca n be routed to the controllers.

DMA: Request 1

DACK1

, DREQ1, DRACK1, and DONE1 belong to the SIU

DMA. DONE1

and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pin s associat ed with the PIO ports.

Table 1- 5. Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Controller:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

PC15 SMC2: SMTXD

SCC1: CTS

/CLSN

FCC1: TXADDR0

UTOPIA master

FCC1: TXADDR0

UTOPIA slave

Output

Input

Output

Input

SMC2: Serial Management Transm it Data

Supported by SMC2. The SMC interface consists of SMTXD, SMRXD, SMSYN

, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that support three protocols or modes: UART, transparent, or general-circuit interface (GCI). See also PA9.

SCC1: Clear To Send, Collision

Typically used in conjunction with RTS

. The MSC8101 SCC1

trans mitter sends out a request to send data signal (RTS

The request is accepted when CTS

is returned low. CLSN is

the signal used in Ethernet mode. See also PC29.

FCC1: UTOPIA Master Transmit Address Bit 0

In the ATM UTOPIA master interface supported by FCC1, this is transmit address bit 0.

FCC1: UTOPIA Slave Transmit Address Bit 0

In the ATM UTOPIA slave interface supported by FCC1, this is transmit address bit 0.

PC14 SI1: L1ST2

SCC1: CD

, RENA

FCC1: RXADDR0

UTOPIA master

FCC1: RXADDR0

UTOPIA sl av e

Output

Input

Output

Input

Serial Interface 1: La yer 1 Strobe 2

In the time-slot assigner supported by SI1. The MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling thr ee-state I/O buffe rs in a multiple-transmitter architecture. These strobes can als o be gene rate output wave forms fo r such applications as step pe r- m oto r co ntr o l.

SCC1: Carrier Detect, Receive Enable

Typically used in conjunction with RTS

supported by SCC1. The MSC8101 SCC1 transmitter requests the receiver to send data by asserting RTS

low. The request is accepted

when CTS

is returned low.

FCC1: UTOPIA Multi-PHY Master Receive Address Bit 0

In the ATM UTOPIA master interface supported by FCC1, this is receive address bit 0.

FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 0

In the ATM UTOPIA slave interface supported by FCC1, this is receive address bit 0.

Table 1- 5. Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Controller:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

PC13 SI1: L1ST4

SCC2: CTS

,CLSN

FCC1:TXADDR1

UTOPIA master

FCC1: TXADDR1

UTOPIA slave

Output

Input

Output

Input

Serial Interface 1: La yer 1 Strobe 4

SCC2: Clear to Send, Collision

Typically used in conjunction with RTS

. The MSC8101 SCC2

trans mitter sends out a request to send data signal (RTS

The request is accepted when CTS

is returned low. CLSN is

the signal used in Ethernet mode. See also PC28.

FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 1

In the ATM UTOPIA master interface supported by FCC1, this is transmit address bit 1.

FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 1

In the ATM UTOPIA slave interface supported by FCC1, this is transmit address bit 1.

PC12 SI1: L1ST3

SCC2: CD

, RENA

FCC1: RXADDR1

UTOPIA master

FCC1: RXADDR1

UTOPIA sl av e

Output

Input

Output

Input

Serial Interface 1: La yer 1 Strobe 3

SCC2: Carrier Detect, Request Enable

Typically used in conjunction with RTS

supported by SCC2. The MSC8101 SCC2 transmitter requests to the receiver that it sends data by asserting RTS

low. The request is accept ed

when CTS

is returned low.

FCC1: UTOPIA Multi-PHY Master Receive Address Bit 1

In the ATM UTOPIA master interface supported by FCC1, this is receive address bit 1.

FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 1

In the ATM UTOPIA slave interface supported by FCC1, this is receive address bit 1.

Table 1- 5. Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Controller:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

PC7 SI2: L1ST1

FCC1: CTS

HDLC serial, HDLC nibble

and

transparent

FCC1: TXADDR2

UTOPIA master

FCC1: TXADDR2

UTOPIA sl av e

FCC1: TXCLAV1

UTOPIA multi-PHY master, direct polling

Output

Input

Output

Input

Serial Interface 2: Strobe 1

In the time-slot assigner supported by SI2. The MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling thr ee-state I/O buffe rs in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control.

FCC1: Clear To Send

In the standard modem interface signals supported by FCC1 (RTS

, CTS, and CD). CTS is asy nchronous with the data.

FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 2 In the ATM UTOPIA master interface supported by FCC1, this is transmit address bit 2.

FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 2

In the ATM UTOPIA slave interface supported by FCC1 using multiplexed polling, this is transmit address bit 2.

FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 1 Direct Polling

In the ATM UTOPIA master interface supp orted by FCC1 using direct polling, TX CLAV1 is asserted by an external UTOPIA s lave PHY to indicate that it can accept one complete ATM cell.

Table 1- 5. Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Controller:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

PC6 SI2: L1ST2

FCC1: CD

HDLC serial, HDLC nibble

and

transparent

FCC1: RXADDR2

UTOPIA master

FCC1: RXADDR2

UTOPIA slave

FCC1: RXCLAV1

UTOPIA multi-PHY master, direct polling

Output

Input

Output

Input

Serial Interface 2: La yer 1 Strobe 2

In the t ime-slot assigner supported by SI2. The MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling thr ee-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control.

FCC1: Carrier Detect

In the standard modem interface signals supported by FCC1 (RTS

, CTS, and CD). CD is an input asynchronous with the

data.

FCC1: UTOPIA Multi-PHY Master Receive Address Bit 2

In the ATM UTOPIA master interface supported by FCC1, this is receive address bit 2.

FCC1: UTOPIA Slave Receive Address Bit 2

In the ATM UTOPIA slave interface supported by FCC1 using multiplexed polling, this is receive address bit 2.

FCC1: UTOPIA Multi-PHY Master Receive Cell Available 1 Direct Polling

In the ATM UTOPIA master interface supp orted by FCC1 using direct polling, RXCLAV1 is asserted by an external PHY when one com pl et e A TM cel l is avai lable for tran s fer.

PC5 SMC1: SMTXD

SI2: L1ST3

FCC2: CTS

HDLC serial, HDLC nibble

and

transparent

Output

Input

SMC1: Transmit Data

Supported by SMC1. The SMC interface consists of SMTXD, SMRXD, SMSYN

, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI).

Serial Interface 2: La yer 1 Strobe 3

In the t ime-slot assigner supported by SI2. The MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling thr ee-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control.

FCC2: Clear To Send

In the standard modem interface signals supported by FCC2 (RTS

, CTS, and CD). CTS is asy nchronous with the data.

Table 1- 5. Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Controller:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

PC4 SMC1: SMRXD

SI2: L1ST4

FCC2: CD

HDLC serial, HDLC nibble

and

transparent

Input

Output

Input

SMC1: Receive Data

Supported by SMC1. The SMC interface consists of SMTXD, SMRXD, SMSYN

, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI).

Serial Interface 2: La yer 1 Strobe 4

FCC2: Carrier Detect

In the standard modem interface signals supported by FCC2 (RTS

, CTS and CD). CD is asynchronous with the data.

Table 1- 5. Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Controller:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

1.7.4 Port D Signals

Table 1-6. Port D Signals

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated I/O

Protocol

PD31 SCC1: RXD

DMA: DRACK1

DMA: DONE1

Input

Output

Input/

Output

SCC1: Receive Data

Supported by SCC1. SCC1 receives serial da ta from RXD.

DMA: Data Request Acknowledge 1

DACK1

, DREQ1, DRACK1, and DONE1 belong to the SIU

DMA. DONE1

and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports.

DMA: Done 1

DACK1

, DREQ1, DRACK1, and DONE1 belong to the SIU

DMA. DONE1

and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports.

PD30 SCC1: TXD

DMA: DRACK2

DMA: DONE2

Output

Input/

Output

SCC1: Transmit Data

Supported by SCC1. SCC1 transmits serial data out of TXD.

DMA: Data Request Acknowledge 2

DACK2

, DREQ2, DRACK2, and DONE2 belong to the SIU

DMA. DONE2

and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports.

DMA: Done 2

DACK2

, DREQ2, DRACK2, and DONE2 belong to the SIU

DMA. DONE2

and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports.

PD29 SCC1: RTS

, TENA

FCC1: RXADDR3 UTOPIA master

FCC1: RXADDR3

UTOPIA slave

FCC1: RXCLAV2

UTOPIA multi-PHY master, direct polling

Output

Input

SCC1: Request to Send, Transmit Enable

Typically used in conjunction with CD

supported by SCC2. The MSC8101 SCC1 transmitter requests the receiver to send data by asserting RTS

low. The request is accepted

when CTS

is retu rned low. TENA is the signal used in

Ether ne t mode.

FCC1: UTOPIA Multi-PHY Master Receive Address Bit 3

In the ATM UTOPIA master interface supp orted by FCC1 using multiplexed polling, this is receive address bit 3.

FCC1: UTOPIA Slave Receive Address Bit 3

In the ATM UTOPIA slave interface supported by FCC1 using multiplexed polling, this is receive address bit 3.

FCC1: UTOPIA Multi-PHY Master Receive Cell Available 2 Direct Polling

In the ATM UTOPIA master interface supp orted by FCC1 using direct polling, RXCLAV2 is asserted by an external PHY when one complete ATM cell is available for transfer.

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Communications Processor Module (CPM) Ports

PD19 FCC1: TXADDR4

UTOPIA master

FCC1: TXADDR4

UTOPIA slave

FCC1: TXCLAV3

UTOPIA multi-PHY master, direct polling

BRG1O

SPI: SPIS

Output

Input

Output

Input

FCC1: Multi-PHY Master Transmit Address Bit 4 Multiplexed Polling

In the ATM UTOPIA master interface supp orted by FCC1 using multiplexed polling, this is transmit address bit 4.

FCC1: UTOPIA Slave Transmit Address Bit 4

In the ATM UTOPIA slave interface supported by FCC1 using multiplexed polling, this is transmit address bit 4.

FCC1: UTOPIA Multi-PHY master Transmit Cell Available 3 Direct Polling

In the ATM UTOPIA master interface supp orted by FCC1 using direct polling, TX CLAV3 is asserted by an external UTOPIA s lave PHY to indicate that it can accept one complete ATM cell.

Baud Rate Generator 1 Output

The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provid e an output to one of the 8 BRG pins. BRG1O can be the int e rnal in put to the SIU timers. When CL K5 is selected (see PC27 above), it is the source for BRG1O whic h is the default input for the SIU timers. See the

System Interface

Unit (SIU)

chapter in the

MSC8101 Technical Reference

manual f or additional informatio n. If CLK5 is not enab led, BRG1O uses an internal input. If TMCLK is enabled (see PC26 above), the BRG1O input to the SIU timers is disabled.

SPI: Select

The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL

). The SPI can be configured as a slave or ma st er in si ng le - or mul tip le-maste r environm en ts . S PIS E L

is the enable input to the SPI slave.

In a mult imaster environment, SPISEL

(always an input) detects an error when more than one master is opera ting. SPI mast ers mu st outp ut a sl a ve sel ect si gn al to en ab le SPI slave devices by using a separate general-purpose I/O signal. Assertion of an SPI SPISEL

while it is master causes

an error.

Table 1- 6. Port D Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated I/O

Protocol

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Communications Processor Module (CPM) Ports

PD18 FCC1: RXADDR4

UTOPIA master

FCC1: RXADDR4

UTOPIA slave

FCC1: RXCLAV3

UTOPIA multi-PHY master, direct polling

SPI: SPICLK

Output

Input

Input/

Output

FCC1: UTOPIA Master Receive Address Bit 4

In the ATM UTOPIA master interface supp orted by FCC1 using multiplexed polling, this is receive address bit 4.

FCC1: UTOPIA Slave Receive Address Bit 4

In the ATM UTOPIA slave interface supported by FCC1, this is the receive address bit 4.

FCC1: UTOPIA Multi-PHY Master Receive Cell Available 3 Direct Polling

In the ATM UTOPIA master interface supp orted by FCC1 using direct polling, RXCLAV3 is asserted by an external PHY when one complete ATM cell is available for transfer.

SPI: Clock

The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL). The SPI can be configured as a slave or ma st er in si ng le - or mul tip le-maste r environments. SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK phase and polarity can be configured. When the SPI is a master, SPICLK is the clock output signal that shifts received data in from SPIMISO and transmitted data out to SPIMOSI.

PD17 BRG2O

FCC1: RXPRTY

UTOPIA

SPI: SPIMOSI

Output

Input

Input/

Output

Baud Rate Generator 2 Output

The CPM supports up to 8 BRGs. The BRGs can be used internally to the MSC810 1 and/or provide an output to one of the 8 BRG pins.

FCC1: UTOPIA Receive Parity

In the ATM UTOPIA interface supported by FCC1, this is

the odd pa rit y bit for RXD[0–7].

SPI: Master Output Slave Input

The SPI interface comprises our signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL

). The SPI can be configured as a slave or master in single- or multiple-master environments. When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and transmitted data out through SPIMISO.

PD16 FCC1: TXPRTY

UTOPIA

SPI: SPIMISO

Output

Input/

Output

FCC1: UTOPIA Transmit Parity

In the ATM UTOPIA interface supported by FCC1, this is the odd parity bit for TXD[0–7].

SPI: Master Input Slave Output

The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK), and select (SPISEL

). The SPI can be configured as a slave or ma st er in si ng le - or mul tip le-maste r environments. When the SPI is a slave, SPICLK is the clock input t hat shifts received data in from SPIMOSI and transmitted data out through SPIMISO.

Table 1- 6. Port D Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated I/O

Protocol

Page 49

1-45

JTAG Test Access Port Signals

1.8 JTA G Test Acces s P ort S ign als

The MSC8101 supports the st andard set of T est Acc ess Port (TAP) signals defined by IEEE 1 149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-7.

PD7 SMC1: SMSYN

FCC1: TXADDR3

UTOPIA master

FCC1: TXADDR3

UTOPIA sl av e

FCC1: TXCLAV2

UTOPIA multi-PHY master, direct polling

Input

Output

Input

SMC1: Serial Management Synchronization

Supported by SMC1. SMSYN

is an input. The SMC

interface consists of SMTXD, SMRXD, SMSYN

and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent or general-circuit interface (GCI).

FCC1: UTOPIA Master Transmit Address Bit 3

In the ATM UTOPIA master interface supp orted by FCC1 using multiplexed polling, this is transmit address bit 3.

FCC1: UTOPIA Slave Transmit Cell Available 2

In the ATM UTOPIA slave interface supported by FCC1 using multiplexed polling, this is transmit address bit 3.

FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 2 Direct Polling

In the ATM UTOPIA master interface supp orted by FCC1 using direct polling, TX CLAV2 is asserted by an external UTOPIA s lave PHY to indicate that it can accept one complete ATM cell.

Tabl e 1-7. JTAG Test Access Port Signals

Signal

Name

Type Signal Description

TCK Input Test C loc k— A test clock signal for synchronizing JTAG test logic.

TDI Input Test Data Input—A test data serial signal for test instructions and data. TDI is sampled

on the rising edge of TCK and has an internal pull-up resistor.

TDO Output Test Data Output—A test data serial signal for test instructions and data. TDO can be

tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK.

TMS Input Test Mode Select—Sequences the test controller’s state machine, is sampled on the

rising edge of TCK, and has an internal pull-up resistor.

TRST

Input Test Reset—Asynchronously initializes the test controller, has an internal pull-up

resistor, and mus t be asserte d after power up.

Table 1- 6. Port D Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

GeneralPurpose

I/O

Peripheral Control ler:

Dedicated I/O

Protocol

Page 50

1-46

Reserved Signals

1.9 Rese rved S ign als

Table 1-8. Reserved Signals

Signal Name Type Signal Descr ipt ion

TEST Input Test

Used for manufacturing testing. You must connect this input to GND.

THERM[1–2] — Leave discon nected.

SPARE1, 5 — Spare Pins

Leave disconnected for backward compatibility with future revisions of this device.

Page 51

2-1

Chapter 2

Specifications

2.1 Introduction

This document contains detailed info rmation on power considerations, DC/AC electrical ch aracteristics, and AC timing specifications for the MSC8101 communications processor . For additional information, see the MSC8101 Reference Manual.

Note: The MSC8101 electrical specifications are preliminary and many are from design simulations.

These specifications may not be fully tested or guaranteed at this early s tage of the product life cycle. Finalized specifications will be published after thorough characteriza tion and device qualifications have been complet ed.

2.2 Absolute Maximu m Ratings

In calcula ting timing requirem ents, adding a maximum value of one specification to a minimum value of another specification does not yield a reas onable sum. A maximum specification is calculated us ing a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direc tion. Therefore, a

“maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist.

Table 2-1 describes the maximum electrical ratings for the MSC8101 .

CAUTION

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unuse d inputs are tied to an appropriate logic voltage level (for example, either GND or V

Table 2-1. Absolute Maximum Ratings

Rating Symbol Value Unit

Core su pply voltage

–0.2 to 1.7 V

PLL supply voltage

CCSYN

–0.2 to 1.7 V

I/O supply voltage

DDH

–0.2 to 3.6 V

Input voltage

(GND – 0. 2) to 3.6 V

Maximum operating temperature range

–40 to 120 °C

Storag e tem p era t u re r an ge T

STG

–55 to +150 °C

Page 52

2-2

Recommended Operating Conditions

2.3 Recommended Operating Con ditions

Table 2-2 lists recommended operating con dit ions. Proper devic e operati on outsi de of thes e conditi ons is not guaranteed.

2.4 Thermal Characteristi cs

Table 2-3 describes thermal ch aracteristics of the MSC8101.

Notes: 1. Functional operating conditions are given in T able 2-2.

2. Absolute maximum ratings are stress ratings only, and functi onal operation at the maximum is not

guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage.

3. The input vo ltage must not exceed the I/O s upply V

DDH

by more than 2.5 V at any time, including

during power-on reset. In turn, V

DDH

can exceed VDD/V

CCSYN

by more than 3.3 V during power-on

reset, but for no more than 100 ms. V

DDH

should not exceed VDD/V

CCSYN

by more than 2.1 V during

normal operation. V

DD/VCCSYN

must not exceed V

DDH

by more than 0.4 V at any time, including

during power-on reset. See Section 4.2,

Electri c al D es ig n Con si de r at io ns

, on page 4-2 for more

information.

4. Section 4.1,

Thermal Design Considerations

, on page 4-1 includes a formula for computing the c hip

junction temperature (T

Table 2-2. Recommended Operating Conditions

Rating Symbol Value Unit

SC140 Core supply voltage V

1.5 to 1.7 V

PLL supply voltage V

CCSYN

1.5 to 1.7 V

I/O supply voltage V

DDH

3.13 5 to 3.465 V

Input voltage V

–0.2 to V

DDH

+ 0.2 V

Operating temperature range T

–40 to 105 °C

Table 2-3. Therma l Character isti c s

Characterist ic Symbol

FC-PBGA

× 17mm

Unit

Junction-to-ambient

1, 2

θJA

or θ

52 °C/W

Junction-to-ambient, four-layer board

1, 3

θJA

or θ

25 °C/W

Junction-to-board (bottom)

θJB

or θ

22 °C/W

Junction-to-ca se (top)

θJC

or θ

0.3 °C/W

Junction-to-package (top)

0.3 °C/W

Notes: 1. Junction temperature is a function of on-chip powe r dissipation, package thermal resistance, mountin g

site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEM I G 38-87 and EIA/JESD 51-2 with the single layer (1s) board horizontal.

3. Per JESD51-6 with the boards horizontal.

4. Thermal resistance between the die and the printed circuit boa rd per JESD 51-8.

5. Indicates the average thermal resistance between the die and the case top surface as measured by the

cold pl ate method (MIL SPEC-883 Method 1012.1) wi th the cold plate temperature used for case temperature.

6. Thermal characterization parameter ind icating the temperature difference between package top and the junction temperature, per EIA/JESD51-2.

Table 2-1. Absolute Maximum Ratings2 (Continued)

Rating Symbol Value Unit

Page 53

2-3

DC Electrical Characteristics

See Section 4.1, Thermal Design Considerations, on page 4-1 for details on these characteristics.

2.5 DC E lectri cal Chara cter is tic s

This sect ion d es cribe s the DC e lec tr ical c ha rac ter ist ics f or th e MSC81 01. The m easu rement s in Table 2-4 assume the followi ng system conditions:

•T

= 0 – 100 °C

•

= 1.6 V ± 5% V

• V

DDH

= 3.3 V ± 5% V

• GND = 0 V

Note: The lea k ag e current is measured for nomin al V

DDH

and VDD or both V

DDH

and VDD must vary in

the same direction (for example, both

DDH

and VDD vary by ± 5 p e r cent).

Table 2-4. DC Electrical Characteristics

Characteristic Symb ol Min Max Unit

Input high voltage, all inputs except CLKIN V

2.0 3.465 V

Input low voltage V

GND 0.8 V

CLKIN input high voltage V

IHC

2.5 3.465 V

CLKIN input low voltage

ILC

GND 0.8 V

Input leakage cu rrent, V

= V

DDH

—10µA

Tri-st ate (hig h im pedance of f sta te) le ak ag e cu r ren t, V

= V

DDH

—10µA

Signal low input current, V

= 0.4 V I

—–4.0mA

Signal high input current, V

= 2.0 V I

—4.0mA

Output high voltage, I

= –2 mA, except open drain pins V

2.4 — V

Output low voltage, I

= 3.2 mA V

—0.4V

Notes: 1. The optimum CL KIN duty cy cle is obta ined when: V

ILC

= V

DDH

– V

IHC

Table 2-5. Typical Power Dissipation

Characterist ic Symbol Typical Unit

Core po wer dissipation at 30 0 MHz P

CORE

350 mW

CPM power dissipation at 150 MHz P

CPM

240 mW

SIU power dissipation at 100 MHz P

SIU

80 mW

Core leakage power P

LCO

3mW

Input/Output Ports leakage power P

LCP

6mW

SIU leak ag e po w er P

LSI

2mW

Page 54

2-4

Clock Configuration

2.6 Clock C on fig urati on

The following sections provide a general desc ription of clock configuration.

2.6.1 Valid Clock Modes

Table 2-6 shows the maximum frequency values for each rated core frequency (250, 275, or 300 MHz). The user must ensure that maximum frequency valu es are not exceeded.

Six bit values map the MSC8101 clocks to one of the val id configuration mode options. Each option determines the

CLKIN, SC140 core, system bus, SCC clock, CPM, and CLKOUT frequen cies. The six bit

values are derived from three dedicated input pins (

MODCK[1–3]) and three bi ts from the reset

configuration word (MODCK_H). To configure the SPLL pre-division factor, SPLL multiplication factor, and the frequencies for the SC140 core, SCC clocks, CPM parallel I/O ports, and system buses, the

MODCK[1–3] pins are samp led and combined with the MODCK_H values when the int ernal

power-on reset

(internal PORESET) is deasserted. Clock configuration changes only when the internal

PORESET signal is deasserted.

The following factor s ar e con f igured:

• SPLL pre-division factor (SPLL PDF)

• SPLL multiplication factor (SPLL MF)

• Bus post-division factor (Bus DF) The SCC division factor (SCC DF) is fixed at 4 and the CP M division factor (CPM DF) is fixed at 2. The

BRG division factor (BRG DF) is configured through the System Clock Control Register (SCCR) and can be 4, 16 (default after re set), 64, or 256.

Note: Refer to AN2288/D Clock Mode Selection for MSC8101 Mask Set 2K42A for details on clock

configuration.

2.6.2 Clocks Programming Model

This sectio n describes the clock registers in detail. The regist ers discussed are as follo ws:

• System Clock Control Register (SCCR)

• System Clock Mode Register (SCMR)

Table 2-6. Maximum Frequencies

Characteristi c Maximum Frequency in MHz

Core Frequency 250 275 300 CPM Frequency (CPM CLK) 125 137.5 150 Bus Frequency (BCLK) 50 68.75 75 Serial Communication Controller Clock Frequency (SCLK) 62.5 68.75 75 Baud Rate Generator Clock Frequency (BRGCLK) 62.5 68.75 75 External Clock Output Frequency (CLKOUT) 50 68.75 75

Page 55

2-5

Clock Configuration

2.6.2.1 System Clock Control Register

The SCCR is memory-mapped into the SIU register map of the MSC8101.

2.6.2.2 System Clock Mode Register

SCMR is a read-only register that is updated during power-on reset (PORESET ) and provides the mode control signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. For details of the availabl e s etting options, see AN2288.

Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

—

TYPE R/W

RESET —

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

—DFBRG

TYPE R/W

RESET —

Figure 2-1. System Clock Control Register (SCCR)—0x10C80

Table 2-7. SCCR Bit Descriptions

Name

Bit No.

Defaults

Description Settings

PORESET

Hard

Reset

—

0–29

——Reserved

DFBRG

30–31

01 Unaffected Division Factor for the BRG Clock

Defines the BRGCLK frequency. Changing this value does not result in a loss of lock condition.

00 Divide by 4 01 Divide by 16 (default value) 10 Divide by 64 11 Divide by 256

Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

— COREPDF COREMF BUSDF CPMDF

TYPE R

RESET —

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SPLLPDF SPLLMF — DLLDIS —

TYPE R

RESET —

Figure 2-2. System Clock Mode Register (SCMR)—0x10C88

Page 56

2-6

Clock Configuration

Table 2-8. SCMR Bit Descriptions

Name

Bit No.

Defaults

Description Settings

PORESET

Hard

Reset

—

0–1

——Reserved

COREPDF

2–3

Configuration

Pins

Unaffected Core PLL Pre-Division Factor 00 CPLL PDF= 1

01 CPLL PDF= 2 10 CPLL PDF= 3 11 CPLL PDF= 4

COREMF

4–7

Configuration

Pins

Unaffected Core Multiplication Factor 0101 MF = 10

0110 MF = 12 All other combinations not used.

BUSDF

8–11

Configuration

Pins

Unaffected 60x Bus Division Factor 0010 Bus DF = 3

0011 Bus DF = 4 0100 Bus DF = 5 All other combinations not used.

CPMDF

12–15

Configuration

Pins

Unaffected CPM Division Factor 0001 CPM DF = 2

All other combinations are not used.

SPLLPDF

16–19

Configuration

Pins

Unaffected SPLL Pre-Division Factor 0000 SPLL PDF = 1

0001 SPLL PDF = 2 0010 SPLL PDF = 3 0011 SPLL PDF = 4 All other combinations not used

SPLLMF

20–23

Configuration

Pins

Unaffected S PLL Mu ltip lic ati on Fa cto r 0110 SPLL MF = 12

0111 SPLL MF = 14 1000 SPLL MF = 16 1001 SPLL MF = 18 1010 SPLL MF = 20 1011 SPLL MF = 22 1100 SPLL MF = 24 1101 SPLL MF = 26 1110 SPLL MF = 28 1111 SPLL MF = 30 All other combinations not used

—

——Reserved

DLLDIS25Configuration

Pins

Unaffected DLL Disable 0 DLL operation is enabled

1 DLL is disabled

—

26–31

——Reserved

Page 57

2-7

AC Timings

2.7 AC Ti ming s

The following se ct ions i nclude illus trati ons an d ta bles of cl ock diagra ms, signa ls, a nd para llel I/ O out puts and inputs. AC ti mi ngs are based on a 50 pF load, except where noted otherwise, and 50 Ω transmission line.

2.7.1 Clocking and Timing Characteristics

Table 2-9. System Clock Para me te r s

Characteristic Minimum Maximum Unit

Phase Jitter between BCLK and DLLIN —0.5ns CLKIN frequency

1,2

18 75 MHz CLKIN slope — 5 ns DLLIN slope — 2 ns CLKOUT frequency jitter — (0.01 × CLKOUT) + CLKIN jitter ns Delay between CLKOUT and DLLIN — 5 ns Notes: 1. Low CLKIN f req ue nc y ca use s poor P LL pe rfo r man ce . Ch oose a CL KIN f r eque ncy hi gh enoug h t o ke ep

the frequency after the predivider (SPLLMFCLK) higher than 18 MHz.

2. CLKIN should have a 50% ±

5% duty cycle.

Table 2-10. Clock Ranges

Clock Symbol

Maximum Rated Core Frequency

All Max. Val ues for SC140 Clock Rating of:

Min 250 MHz 275 MHz 300 MHz

Input Clock

CLKIN 18 MHz 62.5 68.75 MHz 75 MHz SPLL MF Clock SPLLMFCLK 18 MHz 20.83 22.9 MHz 25 MHz Bus BCLK 18 MHz 62.5 MHz 68.75 MHz 75 MHz Output CLKOUT 43.2 MHz 62.5 MHz 68.75 MHz 75 MHz Serial C om m unicatio ns Co ntroller SCLK 18 MHz 62.5 MHz 68. 75 MH z 75 MHz Communications Processor

Module

CPMCLK 36 MHz 125 MHz 137.5 MHz 150 MHz

SC140 Core DSPCLK 72 MHz 250 MHz 275 MHz 300 MHz Baud Rate Generator

• For BRG DF = 4

• For BRG DF = 16 (default)

•For BRG DF = 64

• For BRG DF = 256

BRGCLK

36 MHz

9 MHz

2.25 MHz

562.5 KHz

62.5 MHz

15.63 MHz

3.91 MHz

976.6 KHz

68.75 MHz

17.19 MHz

4.30 MHz

1.07 MHz

75 MHz

18.75 MHz

4.69 MHz

1.17 MHz

Page 58

2-8

AC Timings

2.7.2 Reset Timing

The MSC8101 has several inputs to the reset logic:

• Power-on reset (

PORESET)

• External hard reset (

HRESET)

• External soft reset (

SRESET)

Asser ti n g an ex ternal

PORESET causes concurrent asse rtion of an internal PORESET signal, HRESET,

and

SRESET. When the external PORESET signal is deasserted, the MSC8101 samples several

configuration pins:

•

RSTCONF—determines whether the MSC8101 is a master (0) or s lave (1) device

•

DBREQ—determines whether to operate in normal mode (0) or invoke the SC140 debug mode (1)

•

HPE—disable (0) or enable (1) the host port (HDI16)

•

BTM[0–1]—boot from external memory (00) or the HDI16 (01)

All these reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status regist er ind icat es the last sources to ca use a rese t. Table 2-11 describes reset causes.

2.7.2.1 Reset Operation

The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard r eset. Soft reset initializes the inter n al logic while maintaining the system configuration. The MSC8101 has two mechanisms for reset configuration: host reset configura tion and hardware reset configuration.

2.7.2.2 Power-On Reset Flow

Asserting the PORESET external pin initiates the power-on rese t flow. PORESET should be asserted externally for at least 16 input clock cycles after externa l power to the MSC8101 reaches at le as t 2/3 V

. As Table 2-12 shows, the MSC8101 has five confi gurati on pi ns, fou r of whi ch are mult iplex ed wi th

the SC1 40 co re E ONCE E ve nt (

EE[0–1], EE[4–5]) pins a nd th e fifth o f whic h is t he RSTCONF pin. These

pins are sampled at the rising edge of

PORESET. In addition to these configuration pins, three

(

MODCK[1–3]) pins are sampled by the MSC8101. The signals on these pins and the MODCK_H value

in the Hard Reset Configuration W ord determine the PLL locking mode, by defining the ratio bet w ee n the DSP clock, the bus clo cks, and the CPM clock frequencie s .

Table 2-11. Reset Causes

Name Direction Description

Power-on reset (PORESET

)

Input PORESET

init iat es t h e pow er- o n re set f low tha t re sets al l th e M SC8 10 1s and

conf igures various attributes of the MSC8101, including its clock mode.

Hard reset (HRESET

)

Input/Output The MSC8101 can detect an external assertion of HRESET

only if it occurs

while the MSC8101 is not asserting reset. During HRESET

, SRESET is

asserted. HRESET

is an open-drain pin.

Soft reset (SRESET

)

Input/Output The MSC8101 can detect an external assertion of SRESET

only if it occurs

while the MSC8101 is not asserting reset. SRESET

is an open-drain pin.

Page 59

2-9

AC Timings

Table 2-12. External Configuration Signals

Pin Description Settings

RSTCONF Reset Configu ratio n

Input line sampled by the MSC8101 at the rising edge of PORESET

0 Reset Co nfiguration Master. 1 Reset Configuration Slave.

DBREQ/ EE0

EONCE Event Bit 0

Input line sampled after SC140 core PLL locks. Holding EE0 high when PORES ET

is deasserted

puts the SC140 core into Debug mode.

0 SC140 core starts the normal processing

mode after reset.

1 SC140 core enters Debug mode immediately

after reset.

HPE/EE1 Host Port Enable

Input line sampled at the rising edge of PORESET. If asserted, the Host port is enabled, the system data bus is 32-bit wide, and the Host

must

program the rese t configuration wo rd.

0 Host port disabled (hardware reset

configu ration enab le d).

1 Host por t enabled.

BTM[0–1]/ EE[4–5]

Boot Mode

Input lines samp led at the rising edge of PORESET, which

determine the MSC8101 Boot

mode.

00 MSC8101 boots from external memory. 01 MSC8101 boots from HDI16. 10 Reserved. 11 Reserved.

Table 2-13. Reset Timing

No. Characteristics Expression Min Max Unit

1 Required externa l PO RESET duration minimum

• CLKIN = 18 MHz

• CLKIN = 75 MHz

16 / CLKIN

888.8

213.3

— —

ns ns

2 Delay from deassertion of external PORESE T

deassertion of internal P OR ESET

• CLKIN = 18 MHz

• CLKIN = 75 MHz

1024 / CLKIN

56.89

13.65

µs µs

3 Delay from deasserti on of internal PO RESET

to SPLL lock

• SPLLMFCLK = 18 MHz

• SPLLMFCLK = 25 MHz

800 / SPLLMFCLK

44.4

32.0

µs µs

4 Delay from SPLL lo ck to DLL lock

• DLL enab le d — BCLK = 18 MHz — BCLK = 75 MHz

• DLL disa bl ed

3073 / BLCK

—

170.72

40.97

0.0

µs µs

5 Delay from SPLL lock to HRESET

deassertion

• DLL enab le d — BCLK = 18 MHz — BCLK = 75 MHz

• DLL disa bl ed — BCLK = 18 MHz — BCLK = 75 MHz

3585 / BLCK

512 / BLCK

199.17

47.5

28.4

6.83

µs µs

6 Delay from SPLL lock to SRESET

deassertion

• DLL enab le d — BCLK = 18 MHz — BCLK = 75 MHz

• DLL disa bl ed — BCLK = 18 MHz — BCLK = 75 MHz

3588 / BLCK

515 / BLCK

199.33

47.84

28.61

6.87

µs µs

Note: Value given for lowest possible CLKIN frequency 18 MHz to ensure proper initialization of reset sequence.

Page 60

2-10

AC Timings

2.7.2.3 Host Reset Configuration

Host reset configuration allows the host to program the reset configuration word via the Host port after

PORESET is deasserted, as descri bed in the MSC8101 Reference Manual. The MSC8101 sam ples the

signals described in Table 2-12 one the rising edge of

PORESET when the signal is deasserted.

If HPE is sampled high, the host port is enabled. In this mode th e

RSTCONF pin must be pulled up. The

device extends the internal

PORESET until the host programs the reset configuration word register. The

host must write four 8-bit half-words to the Host Reset Configuration Register address to program the reset configuration word, which is 32 bits wide. For more information, see the MSC8101 Reference Manual. The reset confi guration word is programmed before the internal PLL and DLL in the MSC8101 are locked. The host must program it after the risin g edge of the

PORESET input. In this mode, the host

must have its own cloc k that doe s not depend on the MSC810 1 clock. After the PL L and DLL are locke d,

HRESET remains asserted for another 512 bus clocks and is then released. The SRESET is released three

bus clocks later (see Figure 2-3).

2.7.2.4 Hardware Reset Configuration

Hardware re set c onfi gura tion is enab le d if HPE is s ample d lo w at the ris ing edge of PORESET. The value driven on

RSTCONF while PORESET changes from assertion to deassertion determines the MSC8101

configuratio n. If

RSTCONF is deasserted (driven high) while PORESET changes, the MSC8101 acts as a

configuration slave. If

RSTCONF is asserted (driven low) while PORESET changes, the MSC8101 acts

as a configuration master. Section 2.7.2.4, Hardware Reset Configur ation, explai ns the configuration

sequence and the terms “configuration master” and “configuration slave.” Direct ly af t er the de assertio n of

PORESET and choice of the reset operation mode as configuration

master or configuration slave, the MSC8101 starts the configuration process. The MSC8101 asserts

HRESET and SRESET throughout the power-on reset process, including configuration. Configuration

takes 1024

CLOCKIN cycles, after which MODCK[1–3] are sampled t o d etermine th e MSC8 101’s working

mode.

Figure 2-3. Host Reset Configuration Timin g

PORESET

Internal

HRESET

Input

Output (I/O)

SRESET

Output (I/O)

HRESET/SRESET are extended for 512/515 BUS clocks, respectively, from PLL and DLL lock

PLL locks after 800 SPLLMFCLKs and DLL locks 3073 BUS clocks after PLL is locked. When DLL is disabled, reset period is shortened by DLL lock time.

RSTCONF, HPE pins are sampled

HRM, BTM

Any time

Host programs

Word

MODCK_H bits

are ready for PLL.

MODCK[1–3] pins are sampled.

PORESET

Reset Configuration

asserted for

min 16

CLKIN.

PLL locked

DLL locked

Page 61

2-11

AC Timings

Next, the MSC8101 halts until the SPLL locks. The SPLL locks according to

MODCK[1–3], which are

sampled, and to MODCK_H take n fr om the Reset Configuration Word. SPLL locking time is 800 reference cloc ks, which is the clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8101 are enabled. If the DLLDIS bit in the reset configuration word is reset, the DLL starts the locking process after the SPLL is locked. During PLL and DLL locking,

HRESET and SRESET are ass erted. HRESET remains asserted for another 512 BUS clocks and is then released. The SRESET is released three bus clocks later. If the DLLDIS bit in the reset configuration word is set, the

DLL is bypassed and there is no locking process, thus sa ving the DLL locking time. Figure 2-4 shows the power-on rese t flow.

2.7.3 System Bus Access Timing

2.7.3.1 Core Da ta Transfers

Generally, all MSC8101 bus and system output signals are driven from the rising edge of the reference clock (REFCLK), which is

DLLIN or, if the DLL is disabled, CLKOUT. Memory controller signals,

however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal t icks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-14 shows.

Figure 2-4. Hardware Reset Configuration Timing

Table 2-14. Tick Spacing for Memory Controller Signals

PLL Clock Ratio

Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)

T2 T3 T4

1:2, 1:3, 1:4, 1:5, 1:6 1/4 REFCLK 1/2 REFCLK 3/4 REFCLK

1:2.5 3/10 REFCLK 1/2 REFCLK 8/10 REFCLK 1:3.5 4/14 REFCLK 1/2 REFCLK 11/14 REFCLK

PORESET

Internal

HRESET

Input

SRESET

RSTCONF

is sampled for

master/slave determination

MODCK[1–3] are sampled. MODCK_H bits are ready for PLL.

HRESET

/SRESET are extended for 512/515 bus clocks, respectively, from PLL and DLL Lock time.

In reset configuration mode: reset configuration sequence occurs in this period.

PLL locks after 800 SPLLMFCLKs. DLL locks 3073 bus clocks after PLL is locked. When DLL is disabled, reset period is shortened by 3073 bus clocks.

Output (I/O)

asserted for

min 16

CLKIN.

3 4

PLL locked

DLL locked

Page 62

2-12

AC Timings

Figure 2-5 is a graphical representation of Table 2-14.

Note: The UPM machine and GPCM mac h in e outputs change on the internal tick determine d b y th e

memory control ler progra mming; t he AC specifi ca tions are re lati ve to th e i nternal tick . SDRAM machine outp uts change only on the

REFCLK rising edge.

Figure 2-5. Internal Tick Spacing for Memory Controller Signals

Table 2-15. AC Characteristics for SIU Inputs

Number Characteristic Value Units

10 Hold time for all signals after REFCLK rising edge 0.5 ns 11 AACK

/ARTRY/TA/TEA/DBG/BG/BR setup time before REFCLK rising edge 5 ns

12 Data bus setup time before REFCLK rising edge

a. Normal mode b. ECC and parity mode

4.55 6

ns 14 DP setup time before REFCLK rising edge 6 ns 15 Setup time before REFCLK rising edge for all other signals 4 ns

Note: Input specifications are measured from the TTL signal level (0.8 or 2.0 V) relative to the REFCLK rising

edge.

Table 2-16. AC Characteristics for SIU Outputs

Number Characteristic Maximum Minimum Units

31 PSDVAL/TEA/TA delay from REFCLK rising edge 9 1.0 ns

32a Address bus/Address attributes/GBL

delay from REFCL K rising

edge

8.5 1.0 ns

32b BADDR delay from REFCLK rising edge 10 1.0 ns 33a Data bus delay from REFCLK rising edge 8.5 1.0 ns 33b DP delay from REFCLK r ising edge 10 1.0 ns

34 Memory controller signals/ALE delay from REFCLK rising edge 5.5 1.0 ns 35 All other signals delay from REFCLK rising edge 6 1.0 ns

Note: Output specifications are measured from the 1.4 V level of the REFCLK rising edge to the TTL signal level

(0.8 or 2.0 V).

REFCLK

T1 T2 T3 T4

REFCLK

T1 T2 T3 T4

for 1:2.5

for 1:3.5

REFCLK

T1 T2 T3 T4

for 1:2, 1:3, 1:4, 1:5, 1:6

Page 63

2-13

AC Timings

Figure 2-6. Bus Signals

REFCLK

AACK/AR TRY/TA/TEA/DBG/BG/BR

DATA bus

All other inputs

PSDVAL/TEA/TA

Address bus/Address attributes/GBL

Data bus

DP input

BADDR

32a

32b

DP output

33a

33b

Memory controller/ALE

All other outputs

Page 64

2-14

AC Timings

2.7.3.2 DMA Data Transfers

Table 2-17 describes the DMA signal timing.

The DREQ signal is synchronized with the falling edge o f REFCLK . DONE timing is relative to the rising

edge of

REFCLK. To achieve fast response, a sync hronized peripheral should ass ert DREQ ac co r d in g to

the timings in Table 2-17. Figure 2-7 shows synchronous peripheral interactio n.

2.7.4 HDI16 Signals

Table 2-17. DMA Signals

Number Characteristic Minimum Maximum Units

72 DREQ setup ti me before REFCLK falling edge 6 —ns 73 DREQ hold time after REFCLK falling edge 0.5 — ns 74 DONE

setup time before REFCLK rising edge 9 — ns

75 DONE

hold ti me after REFCLK rising edge 0.5 — ns

76 DACK

/DRACK/DONE delay aft er REFCLK rising edge 0.5 9 ns

Figure 2-7. DMA Signals

Table 2-18. Host Interface (HDI16) Timing

1, 2

Number Characteri sti cs

Expression Min Max Unit

44a Read data strob e assertion width

HACK read assertion width

+ 3.3 6.6 — ns

44b Read data strobe deassertion width

HACK read deassertion width

+ 3.3 6.6 — ns

44c Read data strobe deassertion width

after “Last Data

5,6

, or between two consecutive CVR, ICR,

or ISR reads

HACK deassertion width after “Last Data Register” reads

5,6

(2.5 × TC) + 3.3 11.6 — ns

45 Write data strobe assertion width

HACK write asse rtion width

+ 3.3 6.6 — ns

46 Write data strobe deassertion width

HACK write deassertion width after ICR, CVR and Data Register writes

(2.5 × TC) + 3.3 11.6 — ns

REFCLK

DREQ

DONE Input

DACK/DONE/DRACK Outputs

Page 65

2-15

AC Timings

Figure 2-8 and Figu re 2-9 show HDI16 read signal timing. Figure 2-10 and Figure 2-11 show HDI16 write s i gn al timin g.

47 Host data input setup time before write data strobe

deassertion

Host data input setup time before HACK write deassertion

—3.3—ns

48 Host data input hold time after write data strobe

deassertion

Host data input hold time after HACK write deassertion

—3.3—ns

49 Read data strobe assertion to output data active from high

impedance

HACK read assertion to output data active from high impedance

—3.3—ns

50 Read data strobe assertion to output data valid

HACK

read assertion to output data valid

(1.5 × T

) + 3.3 — 8.25 ns

51 Read data strobe deassertion to output data high

impedance

HACK

read deassertion to output data high impedance

——3.3ns

52 Output data hold time after read data strobe deassertion

Output data hold time after HACK

read deassertion — 3.3 — ns

53 HCS [1–2]

assertion to read data str obe assertion

—3.3—ns

54 HCS [1–2]

assertion to write data strobe assertion

—3.3—ns

55 HCS [1–2]

assertion to output data valid TC + 3.3 — 6.6 ns

56 HCS [1–2]

hold time after data strobe deassertion

—0.0—ns

57 HA[0–3], HRW setup time before data strobe assertion

•Read

•Write

—

3.3

— —

ns ns

58 HA[0–3], HRW hold time after data strobe deassertion

—3.3—ns

61 Delay from read data strobe deassertion to host request

deassertion for “Last Data Register” read

4, 5, 10

(2.5 × TC) + 3.3 — 11.6 ns

62 Delay from write data strobe deassertion to host request

deassertion for “Last Data Register” write

5,8,10

(2.5 × TC) + 3.3 — 11.6 ns

63 Delay from DMA HACK

(OAD=0) or Read/Write data

strobe(OAD=1) deassertion to HREQ

assertion. (2.5 × TC) + 3.3 11.6 ns

64 Delay from DMA HACK

(OAD=0) or Read/Write data

strobe(OAD=1) assertion to HREQ

deassertion (3.5 × TC) + 3.3 — 14.9 ns

Notes: 1. T

= 1/ DSPCLK. At 300 MHz, TC = 3.3 ns

2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

3. V

= 3.3 V ± 0.3 V; TJ = –40°C to +100 °C, CL = 50 pF

4. The read data strobe is HRD

/HRD in the dual data strobe mode and HDS/HDS in the single data

strobe mode.

5. In 64-bit mode, The “last data register” is the register at addr ess $7, wh ich is the last location to be read or written in data transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).

6. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ

/HREQ signal.

7. This timing is applicable only if two consecutive reads from one of these registers are executed.

8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.

9. The data strobe is host read (HRD

/HRD) or host write (HWR/HWR) in the dual data strobe mode and

host data strobe (HDS

/HDS) in the single data strobe mode.

10. The host request is HREQ

/HREQ in the single host request mode and HRRQ/HRRQ and

HTRQ

/HTRQ in the double host request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is

empty, HTRQ

/HTRQ is deasserted only if HORX fifo is full (treat as level Host Request).

Table 2-18. Host Interface (HDI16) Timing

1, 2

(Continued)

Number Characteristics

Expression Min Max Unit

Page 66

2-16

AC Timings

Figure 2-8. Read Timing Diagram, Single Data Strobe

Figure 2-9. Read Timing Diagram, Double Data Strobe

HDS

HA[0–3]

HCS[1–2]

HD[0–15]

44c

44b

44a

5857

HREQ (single host request)

HRW

HRRQ

(double host request)

HRD

HA[0–3]

HCS[1–2]

HD[0–15]

55 44a

44b

44a

5857

HREQ

(single host request)

HRRQ

(double host request)

Page 67

2-17

AC Timings

Figure 2-10. Write Timing Diagram, Single Data Strobe

Figure 2-11. Write Timing Diagram, Double Data Strobe

HDS

HA[0–3]

HCS[1–2]

HD[0–15]

5857

HRW

HREQ

(single host request)

HTRQ

(double host request)

HWR

HA[0–3]

HCS[1–2]

HD[0–15]

5857

HREQ

(single host request)

HTRQ

(double host request)

Page 68

2-18

AC Timings

Figure 2-12 shows Host DMA read timing.

Figure 2-13 shows Host DMA write timing.

Figure 2-12. Host DMA Read Timing Diagram

Figure 2-13. Host DMA Write Timing Diagram

RX[0–3]

Read

Data Valid

44a

44b

(Output)

HREQ

HACK or

HWR

, HDS,

HRD

(Input)

HD[0–15]

(Output)

TX[0–3]

Write

Data

Valid

(Output)

HREQ

HACK or

HWR

, HDS,

HRD

(Input)

HD[0–15]

(Output)

Page 69

2-19

AC Timings

2.7.5 CPM Timings

Table 2-19. CPM Input Characteristics

No. Characteristic Typical Unit

16 FCC input setup time before low-to-high clock transition

a. internal clock (BRGxO) b. external clock (serial clock input)

ns ns

17 FCC input hold time after low-to-high clock transition

a. internal clock (BRGxO) b. external clock (serial clock input)

0 3

ns ns

18 SCC/SMC/SPI/I

C input setup time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input)

ns ns

19 SCC/SMC/SPI/I

C input hold time after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input)

0 5

ns 20 TDM input setup time before low-to-high serial clock transition 20 ns 21 TD M in pu t hol d tim e aft er low - to-high seria l transition 20 ns 22 PIO/TIMER/DMA input setup time before low-to-high serial clock transition 10 ns 23 PIO/TIMER/DMA input hold time after low-to-high serial clock transition 3 ns

Note: FCC, SCC, SMC, SPI, I

C are Non-Multiplexed Ser ial Interf ace signals.

Table 2-20. CP M Output Characteristics

No. Characteristic Min Max Unit

36 FCC output delay after low-to-high clock transition

a. internal clock (BRGxO) b. external clock ( s erial input clock)

0 2

ns ns

38 SCC/SMC/SPI/I

C output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock ( s erial input clock)

0 0

20 30

ns 40 TDM outp ut delay after low-to-high serial clock transition 5 35 ns 42 PIO/TIMER/DMA output delay after low-to-high serial clock transition 1 14 ns

Note: FCC, SCC, SMC, SPI, I

C are Non-Multiplexed Serial Interface signals.

Figure 2-14. FCC Internal Clock Diagram

BRGxO

FCC inputs

FCC outputs

16a

17a

36a

Page 70

2-20

AC Timings

Figure 2-15. FCC External Clock Diagram

Figure 2-16. SCC/SMC/SPI /I2C Internal Clock Diagram

Figure 2-17. SC C/SMC/SPI/I

C External Clock Diagram

Figure 2-18. TDM Signal Diagram

Figure 2-19. PIO, Timer, and DMA Signal Diagram

Serial input clock

FCC inputs

FCC outputs

16b

17b

36b

BRGxO

SCC/SMC/SPI/I2C inputs

SCC/SMC/SPI/I2C outputs

18a

19a

38a

Serial input clock

SCC/SMC/SPI/I2C inputs

SCC/SMCSPI/I2C outputs

18b

19b

38b

Serial input clock

TDM inputs

TDM outputs

REFCLK

PIO/TIMER/DMA inputs

PIO/TIMER/DMA outputs

Page 71

2-21

AC Timings

Note: The timing values li sted are preliminary and ref er to m inimum system timing requirements.

Actual implem entation requires conforma nce to the specific protocol requirements. Refer to Chapter 1 to identify the speci f ic input and output signals associated with the referenced internal controllers and supported communication protocols. For example, FCC1 supports ATM/Utopia opera tion in slave mode, multi-PHY maste r direct polling mode, and multi-PHY master multi plexed polling mode and eac h of these modes supports its own set of signals; the direction (input or output) of some of the shared signal names depends on the selected mode.

2.7.6 EE Signals

Figure 2-20 shows the s ignal behavior of the EE pins.

2.7.7 JTAG Signals

Table 2-21. EE Pins Timing

Number Characteristics Type Minimum

65 EE pins as inputs Asynchronous 4 DSPCLKs 66 EE pins as outputs Synchronous to DSPCLK 1 DSPCLK

Notes: 1. DSPCLK is the SC140 core clock. The ratio between DSPCLK and CLKOUT is configured during

power-on-reset. See AN2288 for details.

2. Direction of the EE pins is conf igured in the EE_CTRL register of the EO nCE (See the

SC140 Core

Reference Manual

, MNSC140DSPCORERM/D).

3. Refer to Table 1-3 on page 1-6 for detai led information about EE pin functionality.

Figure 2-20. EE Pins Timing

Table 2-22. JTAG Timing

No. Characteristics

All frequencies

Unit

Min Max

500 TCK frequency of operation 0.0 40.0 MHz 501 TCK cycle ti me 25.0 —ns

502 TCK clock pulse width measured at 1.6 V 12.5 — ns 503 TCK rise and fall times 0.0 3.0 ns 508 TMS, TDI data set-u p tim e 6.0 — ns 509 TMS, TDI data hold time 3.0 — ns 510 TCK low to TDO data valid 0.0 5.0 ns 511 TCK low to TDO high impedance 0.0 5.0 ns 512 TRST

assert time 100.0 — ns

513 TRST

set-up time to TCK low 40.0 — ns

EEi, EED out

EEi, EED in

Page 72

2-22

AC Timings

Figure 2-21. Test Clock Input Timing Diagram

Figure 2-22. Test Access Port Timing Diagram

Figure 2-23. TRST

Timing Diagram

TCK

(Input)

501

502

503503

TCK

(Input)

TDI

(Input)

TDO

(Output)

TDO

(Output)

TDO

(Output)

Input Data Valid

Output Data Valid

TMS

508

509

510

511

510

TCK

(Input)

TRST

(Input)

513

512

Page 73

3-1

Chapter 3

Packaging

3.1 Pin-Out and P ackage In fo rma tio n

This sections provides information about the MSC8101 package, including diagrams of the package pinouts and tables showing how the signals discus sed in Chapter 1 are allocated. The MSC8101 is available in a 332-pin Flip Chip-Plasti c Ball Grid Array (FC-PBGA).

3.2 FC-PB GA Pac kage Descr iption

Figure 3-1 and Figu re 3-2 show top and bottom vie ws of the FC-PBGA package, including pinouts. Table 3-1 lists the MSC8101 signa ls al phabet icall y by sign al nam e. Conne ctions with mu lti ple name s are

listed individually by each name. Signals with programmable polarity are shown both as signals which are asserted low (default) and high (i. e., NAME

/NAME). Table 3-2 lists the signals numer ically by pin

number. Each pin number is listed once with the various signals that are multiplexed to it. Fo r simplicity, signals with progra mmable polarity are shown in this table only with their default name (asserted low).

Page 74

3-2

FC-PBGA Package Description

Figure 3-1. MSC8101 Flip Chip Plastic Ball Grid Array (FC-PBGA), Top View

1342567810 141312119

Top View

15 16

EE1

PA29

PA28

18 19

THERM

IRQ1

PA31

PB30

TDO

EE4

PA27

PB27

PC25

PC24

PC22

PB21

PB23

PA21

IRQ5

EE0

PD30

PD29

DP0

IRQ3

TMS

PD31

EED

EE3

PB28

PC26

PA25

PA24

SPARE

PB22

PD19

PA18

PB19

THERM

PC30

PC29

IRQ4

TRST

PC31

EE5

EE2

PC28

PB26

PB25

PB24

PA22

PA20

PC15

PA15

PD18

IRQ2

VDD

PB29

TCK

PB31

VDD

VDDH

VDD

VDDH

VDD

PA23

PB18

PA17

PC12

SRESET

PD16

IRQ6

GND

VDDH

GND

VDD

GND

PC23

PB20

PA19

PC13

NMI_

NMI

D17

D14

PA30

GND

D15

D16

D12

GND

D13

PC27

PA16

PD17

GND

VDDH

VCC

GND

VCC

GND

D11

GND

D10

GND

TDI

IRQ7

VDDH

GND

PA26

GND

VDDH

PC14

HRESET

TEST

RST

D22

D19

D20

D21

GND

D18

VDDH

CLKIN

DLL_IN

VDD

CLK

PA11

PA14

PA13

D62

PWE5

PSDA

PWE1

D61

PWE6

TEA

PWE7

PSDA

CS1

CS5

A28

A23

A19

A16

A11

D27

D24

D25

D26

D23

GND

VDD

GND

VDDH

PA12

PD7

PA9

PA10

D32

D29

D30

D31

GND

D28

VDDH

PC6

PC4

VDDH

PC7

PA7

PC5

PA8

D37

D34

D35

D36

D33

GND

VDDH

TSIZ3

GND

VDD

PA6

ABB

INT

SPARE

D42

D39

D40

D41

GND

D38

VDD

TT1

GND

VDDH

AACK

ARTRY

D46

D43

GND

D44

D45

PSD

BADDR

GND

VDDH

CS6

A21

TT0

GND

VDD

TBST

D51

D48

GND

PWE2

D49

D50

GND

BADDR

PSD

D47

GND

A26

GND

VDDH

TT3

TT4

TT2

D55

D52

VDDH

GND

D53

D54

VDDH

GND

VDDH

GND

VDDH

GND

VDDH

D60

D57

VDDH

D58

D59

VDDH

VDD

D56

VDD

CS0

VDDH

VDD

A15

A12

D63

GBL

PGTA

PWE0

DBB

DBG

MOD

ALE

MOD

CS3

CS7

A30

A27

A24

A20

A13

A10

A17

MOD

CK1

CK2

CK3

31 30

MUX

CS2

SYN1

OUT

CONF

SYN1

OUT SYN

RESET

SYN

VAL

BADDR

POE

PWE4

BCTL0

PSD

CAS

PWE3

BCTL1

CS4

A31

A29

A25

A22

A14

A18

1342567810 14131211915161819

_OUT

MSC8

TSIZ1

TSIZ2

TSIZ0

Note: Signal names in this figure are the default signa ls after reset, except for signals C2, C19, D1, D2, D18,

E1, F3, H13, H14, and W11 which show the second configuration signal name.

Page 75

3-3

FC-PBGA Package Description

Figure 3-2. MSC8101 Flip Chip Plastic Ball Grid Array (FC-PBGA), Bottom Vie

134256781014 13 12 11 9

Bottom View

1516

EE1

PA29

PA28

1819

THERM

IRQ1

PA31

PB30

TDO

EE4

PA27

PB27

PC25

PC24

PC22

PB21

PB23

PA21

IRQ5

EE0

PD30

PD29

DP0

IRQ3

TMS

PD31

EED

EE3

PB28

PC26

PA25

PA24

SPARE

PB22

PD19

PA18

PB19

THERM

PC30

PC29

IRQ4

TRST

PC31

EE5

EE2

PC28

PB26

PB25

PB24

PA22

PA20

PC15

PA15

PD18

IRQ2

VDD

PB29

TCK

PB31

VDD

VDDH

VDD

VDDH

VDD

PA23

PB18

PA17

PC12

SRESET

PD16

IRQ6

GND

VDDH

GND

VDD

GND

PC23

PB20

PA19

PC13

NMI_

NMI

D17

D14

PA30

GND

D15

D16

D12

GND

D13

PC27

PA16

PD17

GND

VDDH

VCC

GND

VCC

GND

D11

GND

D10

GND

TDI

IRQ7

VDDH

GND

PA26

GND

VDDH

PC14

HRESET

TEST

RST

D22

D19

D20

D21

GND

D18

VDDH

CLKIN

DLL_IN

VDD

CLK

PA11

PA14

PA13

D62

PWE5

PSDA

PWE1

D61

PWE6

TEA

PWE7

PSDA

CS1

CS5

A28

A23

A19

A16

A11

D27

D24

D25

D26

D23

GND

VDD

GND

VDDH

PA12

PD7

PA9

PA10

D32

D29

D30

D31

GND

D28

VDDH

PC6

PC4

VDDH

PC7

PA7

PC5

PA8

D37

D34

D35

D36

D33

GND

VDDH

GND

VDD

PA6

ABB

INT

SPARE

D42

D39

D40

D41

GND

D38

VDD

TT1

GND

VDDH

AACK

ARTRY

D46

D43

GND

D44

D45

PSD

BADDR

GND

VDDH

CS6

A21

TT0

GND

VDD

TBST

D51

D48

GND

PWE2

D49

D50

GND

BADDR

PSD

D47

GND

A26

GND

VDDH

TT3

TT4

TT2

D55

D52

VDDH

GND

D53

D54

VDDH

GND

VDDH

GND

VDDH

GND

VDDH

D60

D57

VDDH

D58

D59

VDDH

VDD

D56

VDD

CS0

VDDH

VDD

A15

A12

D63

GBL

PGTA

PWE0

DBB

DBG

MOD

ALE

MOD

CS3

CS7

A30

A27

A24

A20

A13

A10

A17

MOD

CK1

CK2

CK3

3130

MUX

CS2

SYN1

OUT

CONF

SYN1

OUT

SYN

RESET

SYN

VAL

BADDR

POE

PWE4

BCTL0

PSD

CAS

PWE3

BCTL1

CS4

A31

A29

A25

A22

A14

A18

134256781014 13 12 11 915161819

_OUT

MSC8

TSIZ1

TSIZ3

TSIZ0

TSIZ2

Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name.

Page 76

3-4

FC-PBGA Package Description

Table 3-1. MSC8101 Signal Listing By Name

Signal Name Number

A0 W15 A1 N14 A2 V15 A3 T14 A4 U15 A5 W16 A6 V16 A7 W17 A8 U16

A9 V17 A10 W18 A11 U17 A12 T16 A13 V18 A14 V19 A15 R16 A16 T17 A17 U18 A18 U19 A19 R17 A20 T18 A21 M 13 A22 T19 A23 P17 A24 R18 A25 R19 A26 M 14 A27 P18 A28 N17 A29 P19 A30 N18 A31 N19

AACK

T12

Page 77

3-5

FC-PBGA Package Description

ABB V11 ALE H18

ARTRY

U12 BADDR27 D19 BADDR28 B19 BADDR29 C19 BADDR30 H14 BADDR31 H13

BCTL0

F19

BCTL1

L19

BG V12 BNKSEL0 E18 BNKSEL1 F18 BNKSEL2 G18

H17 BRG1O H3 BRG1O V2 BRG2O J3 BRG2O N7 BRG3O K3 BRG4O L3 BRG5O L7 BRG6O M2 BRG7O N1 BRG8O P1

BTM0 E1 BTM1 F3

for FCC1 N10

for FCC2 P10

/RENA for SCC1 T6

/RENA for SCC2 V4

CLK1 H3 CLK2 J3

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 78

3-6

FC-PBGA Package Description

CLK3 K3 CLK4 L3 CLK5 L7 CLK6 M2 CLK7 N1 CLK8 P1

CLK9 N5 CLK10 R1 CLKIN N8

CLKOUT T8 COL for FCC1 G1 COL for FCC2 M1

CRS for FCC1 J7 CRS for FCC2 M3

CS0

M16

CS1

L17

CS2

K19

CS3

L18

CS4

M19

CS5

M17

CS6

L13

CS7

M18

CTS

for FCC1 T10

CTS

for FCC2 W10

CTS

/CLSN for SCC1 K3

CTS

/CLSN for SCC1 V3

CTS

/CLSN for SCC2 L3

CTS

/CLSN for SCC 2 T5

D0 B3 D1 A3 D2 C4 D3 B4 D4 A4

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 79

3-7

FC-PBGA Package Description

D5 C5 D6 B5 D7 A5 D8 D6

D9 C6 D10 B6 D11 A6 D12 G7 D13 E7 D14 D7 D15 C7 D16 B7 D17 A7 D18 F8 D19 D8 D20 C8 D21 B8 D22 A8 D23 G9 D24 D9 D25 C9 D26 B9 D27 A9 D28 F10 D29 D10 D30 C10 D31 B10 D32 A10 D33 G11 D34 D11 D35 C11 D36 B11 D37 A11

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 80

3-8

FC-PBGA Package Description

D38 F12 D39 D12 D40 C12 D41 B12 D42 A12 D43 D13 D44 C13 D45 B13 D46 A13 D47 E14 D48 D14 D49 C14 D50 B14 D51 A14 D52 D15 D53 C15 D54 B15 D55 A15 D56 E16 D57 D16 D58 C16 D59 B16 D60 A16 D61 C17 D62 A17 D63 A18

DACK1

DACK2

DACK3

DACK4

DBB

C18

DBG

B18

DBREQ D2

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 81

3-9

FC-PBGA Package Description

DLLIN P8

DP0 C2 DP1 B1 DP2 D4 DP3 B2 DP4 C3 DP5 A2 DP6 D5 DP7 F6

DRACK1

/DONE1 H2

DRACK2

/DONE2 J2 DREQ1 R1 DREQ2 P1 DREQ3 C3 DREQ4 A2

EE0 D2 EE1 D1 EE2 E3 EE3 E2 EE4 E1 EE5 F3 EED F2

EXT_BG2

EXT_BG3

EXT_BR2

EXT_BR3

EXT_DBG2

EXT_DBG3

A2 EXT1 H3 EXT2 N5

GBL

D18 GND F11 GND F13

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 82

3-10

FC-PBGA Package Description

GND F15 GND F5 GND F7 GND F9 GND G10 GND G12 GND G14 GND G6 GND G8 GND H15 GND H5 GND H7 GND J14 GND J5 GND J6 GND K13 GND K15 GND K6 GND K7 GND L14 GND L15 GND L5 GND L6 GND M15 GND M5 GND N6 GND N9 GND P11 GND P12 GND P13 GND P14 GND P15 GND P6

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 83

3-11

FC-PBGA Package Description

GND P7 GND P9

GND

SYN

GND

SYN1

H8BIT B16

HA0 D14 HA1 C14 HA2 B14 HA3 A14

HACK

/HACK E16

HCS1

/HCS1 D15

HCS2

/HCS2 A16 HD0 A10 HD1 G11 HD2 D11 HD3 C11 HD4 B11 HD5 A11 HD6 F12 HD7 D12 HD8 C12 HD9 B12

HD10 A12 HD11 D13 HD12 C13 HD13 B13 HD14 A13 HD15 E14

HDDS C16

HDS

/HDS B15

HDSP D16

HPE D1

HRD

/HRD C15

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 84

3-12

FC-PBGA Package Description

HREQ/HREQ A15

HRESET V6

HRRQ

/HRRQ E16

HRW C15

HTRQ

/HTRQ A15

HWR

/HWR B15

INT_OUT

W11

IRQ1

D18

IRQ2

C19

IRQ2

V11

IRQ3

C18

IRQ3

H14

IRQ4

IRQ5

H13

IRQ6

IRQ7

W11 L1RSYNC for SI1 TDMA1 T11 L1RSYNC for SI2 TDMB2 K4 L1RSYNC for SI2 TDMC2 P3 L1RSYNC for SI2 TDMD2 P5

L1RXD for SI1 TDMA1 Serial U10

L1RXD for SI2 TDMB2 H1 L1RXD for SI2 TDMC2 M3

L1RXD for SI2 TDMD2 T2 L1RXD0 for SI1 TDMA1 Nibble U10 L1RXD1 for SI1 TDMA1 Nibble T2 L1RXD2 for SI1 TDMA1 Nibble V1 L1RXD3 for SI1 TDMA1 Nibble P3

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 85

3-13

FC-PBGA Package Description

L1TSYNC for SI1 TDMA1 V10 L1TSYNC for SI2 TDMB2 L2 L1TSYNC for SI2 TDMC2 N3 L1TSYNC for SI2 TDMD2 T1

L1TXD for SI1 TDMA1 Serial W9

L1TXD for SI2 TDMB2 H4 L1TXD for SI2 TDMC2 M1 L1TXD for SI2 TDMD2 V1

L1TXD0 for SI1 TDMA1 Nibble W9 L1TXD1 for SI1 TDMA1 Nibble P5 L1TXD2 for SI1 TDMA1 Nibble T1 L1TXD3 for SI1 TDMA1 Nibble N3

LIST1 for SI1 R1 LIST1 for SI2 T10 LIST2 for SI1 T6 LIST2 for SI2 N10 LIST3 for SI1 V4 LIST3 for SI2 W10 LIST4 for SI1 T5 LIST4 for SI2 P10

MODCK1 E18 MODCK2 F18 MODCK3 G18 MSNUM0 N2 MSNUM1 P2 MSNUM2 U8 MSNUM3 T9 MSNUM4 V8 MSNUM5 U9

NMI

NMI_OUT

V5 PA6 T11 PA7 V10

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 86

3-14

FC-PBGA Package Description

PA8 U10

PA9 W9 PA10 U9 PA11 V8 PA12 T9 PA13 U8 PA14 W8 PA15 W3 PA16 M7 PA17 T4 PA18 W2 PA19 R5 PA20 T3 PA21 U1 PA22 R3 PA23 P4 PA24 P2 PA25 N2 PA26 M6 PA27 L1 PA28 K1 PA29 J1 PA30 J7 PA31 G1 PB18 R4 PB19 U2 PB20 P5 PB21 T1 PB22 T2 PB23 V1 PB24 P3 PB25 N3 PB26 M3

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 87

3-15

FC-PBGA Package Description

PB27 M1 PB28 L2 PB29 K4 PB30 H1 PB31 H4

PBS0

K18

PBS1

K17

PBS2

K14

PBS3

J19

PBS4

H19

PBS5

D17

PBS6

B17

PBS7

F17 PC4 P10 PC5 W10 PC6 N10 PC7 T10

PC12 V4 PC13 T5 PC14 T6 PC15 V3 PC22 R1 PC23 N5 PC24 P1 PC25 N1 PC26 M2 PC27 L7 PC28 L3 PC29 K3 PC30 J3 PC31 H3

PD7 V9

PD16 U4

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 88

3-16

FC-PBGA Package Description

PD17 N7 PD18 U3 PD19 V2 PD29 K2 PD30 J2

PD31 H2 PGPL0 E17 PGPL1 F14 PGPL2 G19 PGPL3 E19 PGPL4 J18 PGPL5 J17

PGTA

J18

POE

G19

PORESET

PPBS

J18

PSDA10 E17

PSDAMUX J17

PSDCAS

E19

PSDDQM0

K18

PSDDQM1

K17

PSDDQM2

K14

PSDDQM3

J19

PSDDQM4

H19

PSDDQM5

D17

PSDDQM6

B17

PSDDQM7

F17

PSDRAS

G19

PSDVAL

G13

PSDWE

F14

PUPMWAIT J18

PWE0

K18

PWE1

K17

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 89

3-17

FC-PBGA Package Description

PWE2 K14 PWE3

J19

PWE4

H19

PWE5

D17

PWE6

B17

PWE7

F17 Reserved A17 Reserved A18 Reserved C2 Reserved C17 Reserved C19 Reserved H14 Reserved H13

RSTCONF

RTS

for FCC1 J7

RTS

for FCC2 L2

RTS

/TENA for SCC1 K2

RTS

/TENA for SCC2 L2 RX_DV for FCC1 M1 RX_DV for FCC2 H1 RX_ER for FCC1 M3 RX_ER for FCC2 L2

RXADDR0 for FCC1 UTOPIA 8 T6 RXADDR1 for FCC1 UTOPIA 8 V4 RXADDR2 for FCC1 UTOPIA 8 N10

RXADDR2/RXCLAV1 for FCC1 UTOPIA 8 N10

RXADDR3 for FCC1 UTOPIA 8 K2 RXADDR4 for FCC1 UTOPIA 8 U3

RXCLAV for FCC1 UTOPIA 8 M3 RXCLAV0 for FCC1 UTOPIA 8 M3 RXCLAV2 for FCC1 UTOPIA 8 K2 RXCLAV3 for FCC1 UTOPIA 8 V4

RXD for FCC1 transparent/HDLC serial T4

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 90

3-18

FC-PBGA Package Description

RXD for FCC2 transparent/HDLC serial T1

RXD for SCC1 H2 RXD for SCC2 H4

RXD0 for FCC1 MII/HDLC nibble T4

RXD0 for FCC1 UTOPIA 8 U9 RXD0 for FCC2 MII/HDLC nibble T1 RXD1 for FCC1 MII/HDLC nibble M7

RXD1 for FCC1 UTOPIA 8 V8 RXD1 for FCC2 MII/HDLC nibble P5 RXD2 for FCC1 MII/HDLC nibble W3

RXD2 for FCC1 UTOPIA 8 T9 RXD2 for FCC2 MII/HDLC nibble U2 RXD3 for FCC1 MII/HDLC nibble W8

RXD3 for FCC1 UTOPIA 8 U8 RXD3 for FCC2 MII/HDLC nibble R4

RXD4 for FCC1 UTOPIA 8 W8

RXD5 for FCC1 UTOPIA 8 W3

RXD6 for FCC1 UTOPIA 8 M7

RXD7 for FCC1 UTOPIA 8 T4

RXENB

for FCC1 K1

RXPRTY for FCC1 UTOPIA 8 N7

RXSOC for FCC1 M1

SCL R4

SDA U2 SMRXD for SMC1 P10 SMRXD for SMC2 U10 SMSYN

for SMC1 V9

SMSYN

for SMC2 V10 SMTXD for SMC1 W10 SMTXD for SMC2 W9 SMTXD for SMC2 V3

SPARE1 R2 SPARE5 U11

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 91

3-19

FC-PBGA Package Description

SPICLK U3 SPIMISO U4 SPIMOSI N7

SPISEL

SRESET

J13

TBST

U13 TC0 E18 TC1 F18 TC2 G18 TCK G4

TDI H6

TDO F1

TEA

G17

TEST W6

TGATE1

TGATE2

L7 THERM1 C1 THERM2 D3

TIN1/TOUT2

TIN2 K3

TIN3/TOUT4

TIN4 N1

TMCLK M2

TMS G2

TOUT1

TOUT3

TRST

T13 TSIZ0 V13 TSIZ1 W13 TSIZ2 W12 TSIZ3 N11

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 92

3-20

FC-PBGA Package Description

TT0 N13 TT1 N12 TT2 U14 TT3 V14

TT4 W14 TX_EN for FCC1 MII K1 TX_EN for FCC2 MII K4 TX_ER for FCC1 MII J1 TX_ER for FCC2 MII H4

TXADDR0 for FCC1 UTOPIA 8 V3 TXADDR1 for FCC1 UTOPIA 8 T5 TXADDR2 for FCC1 UTOPIA 8 T10 TXADDR2 for FCC1 UTOPIA 8 T10 TXADDR3 for FCC1 UTOPIA 8 V9 TXADDR4 for FCC1 UTOPIA 8 V2

TXCLAV for FCC1 UTOPIA 8 J7 TXCLAV0 for FCC1 UTOPIA 8 J7 TXCLAV1 for FCC1 UTOPIA 8 T10 TXCLAV2 for FCC1 UTOPIA 8 V9 TXCLAV3 for FCC1 UTOPIA 8 V2

TXD for FCC1 transparent/HDLC serial W2 TXD for FCC2 transparent/HDLC serial T2

TXD for SCC1 J2 TXD for SCC2 H1

TXD0 for FCC1 MII/HDLC nibble W2

TXD0 for FCC1 UTOPIA 8 N2 TXD0 for FCC2 MII/HDLC nibble T2 TXD1 for FCC1 MII/HDLC nibble R5

TXD1 for FCC1 UTOPIA 8 P2 TXD1 for FCC2 MII/HDLC nibble V1 TXD2 for FCC1 MII/HDLC nibble T3

TXD2 for FCC1 UTOPIA 8 P4 TXD2 for FCC2 MII/HDLC nibble P3

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 93

3-21

FC-PBGA Package Description

TXD3 for FCC1 MII/HDLC nibble U1

TXD3 for FCC1 UTOPIA 8 R3

TXD3 for FCC2 MII/HDLC nibble N3

TXD4 for FCC1 UTOPIA 8 U1 TXD5 for FCC1 UTOPIA 8 T3 TXD6 for FCC1 UTOPIA 8 R5 TXD7 for FCC1 UTOPIA 8 W2

TXENB

for FCC1 G1

TXPRTY for FCC1 UTOPIA 8 U4

TXSOC for FCC1 J1

CCSYN

CCSYN1

E12

F16

H16

L16

P16

R11

R13

DDH

E10

DDH

E11

DDH

E13

DDH

E15

DDH

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 94

3-22

FC-PBGA Package Description

DDH

G15

DDH

G16

DDH

J15

DDH

J16

DDH

K16

DDH

N15

DDH

N16

DDH

R10

DDH

R12

DDH

R14

DDH

R15

DDH

T15

Table 3-2. MSC8101 Signal Listing by Pin Designator

Number Signal Name

A2 IRQ5 / DP5 / DREQ4 / EXT_DBG3 A3 D1 A4 D4 A5 D7 A6 D11 A7 D17 A8 D22

A9 D27 A10 D32 / HD0 A11 D37 / HD5 A12 D42 / HD10 A13 D46 / HD14 A14 D51 / HA3

Table 3-1. MSC8101 Signal Listing By Name (Continued)

Signal Name Number

Page 95

3-23

FC-PBGA Package Description

A15 D55 / HREQ / HTRQ A16 D60 / HCS2 A17 D62 / Reserved A18 D63 / Reserved

IRQ1

/ DP1 /

EXT_BG2

B2 IRQ3

/ DP3 /

EXT_BR 3 B3 D0 B4 D3 B5 D6 B6 D10 B7 D16 B8 D21 B9 D26

B10 D31 B11 D36 / HD4 B12 D41 / HD9 B13 D45 / HD13 B14 D50 / HA2 B15 D54 / HDS

/ HWR B16 D59 / H8BIT B17 PWE6

/ PSDDQM6 / PBS6 B18 DBG B19 BADDR28

C1 THERM1 C2 Reserved / DP0 / EXT_BR2 C3 IRQ4 / DP4 / DREQ3 / EXT_BG3 C4 D2 C5 D5 C6 D9 C7 D15 C8 D20

C9 D25 C10 D30 C11 D35 / HD3 C12 D40 / HD8 C13 D44 / HD12 C14 D49 / HA1 C15 D53 / HRW / HRD

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

Page 96

3-24

FC-PBGA Package Description

C16 D58 / HDDS C17 D61 C18

DBB

/ IRQ3

C19 BADDR29 / IRQ2

D1 HPE / EE1 D2 DBREQ / EE0 D3 THERM2 D4 IRQ2

/ DP2 /

EXT_DBG2

IRQ6

/ DP6 / DACK3 D6 D8 D7 D14 D8 D19 D9 D24

D10 D29 D11 D34 / HD2 D12 D39 / HD7 D13 D43 / HD11 D14 D48 / HA0 D15 D52 / HCS1 D16 D57 / HDSP D17

PWE5

PSDDQM5

/ PBS5

D18

IRQ1

GBL

D19 BADDR27

E1 BTM0 / EE4 E2 EE3 E3 EE2 E4 V

DDH

E5 V

E6 V

DDH

E7 D13 E8 V

DDH

E9 V

E10 V

DDH

E11 V

DDH

E12 V

E13 V

DDH

E14 D47 / HD15 E15 V

DDH

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

Page 97

3-25

FC-PBGA Package Description

E16 D56 / HACK / HRRQ E17 PSDA10 / PGPL0 E18 MODCK1 / TC0 / BNKSEL0 E19

PSDCAS

/ PGPL3 F1 TDO F2 EED F3 BTM1 / EE5 F4 V

F5 GND F6

IRQ7

/ DP7 / DACK4 F7 GND F8 D18 F9 GND

F10 D28 F11 GND F12 D38 / HD6 F13 GND F14

PSDWE

/ PGPL1 F15 GND F16 V

F17

PWE7

PSDDQM7

/ PBS7 F18 MODCK2 / TC1 / BNKSEL1 F19 BCTL0

G1 PA31 / FCC1:UTOPIA8:TXENB / FCC1:MII:COL G2 TMS G3 TRST G4 TCK G5 V

DDH

G6 GND G7 D12 G8 GND

G9 D23 G10 GND G11 D33 / HD1 G12 GND G13 PSDVAL G14 GND G15 V

DDH

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

Page 98

3-26

FC-PBGA Package Description

G16 V

DDH

G17 TEA G18 MODCK3 / TC2 / BNKSEL2 G19

POE

PSDRAS

/ PGPL2 H1 PB30 / FCC2:MII:RX_DV / SCC2:TXD / TDBM2:L1RXD H2 PD31 / SCC1:RXD / DRACK1

/ DONE1 H3 PC31 / BRG1O / CLK1 / TGA TE1 H4 PB31 / FCC2:MII:TX_ER / SCC2:RXD / TDMB2:L1TXD H5 GND H6 TDI H7 GND

H13 Reserved / BADDR31 / IRQ5 H14 Reserved / BADDR30 / IRQ3 H15 GND H16 V

H17 BR H18 ALE H19 PWE4

/ PSDDQM4 / PBS4 J1 PA29 / FCC1:UTOPIA8:TXSOC / FCC1:MII:TX_ER J2 PD30 / SCC1:TXD / DMA:DRACK2

/DONE2 J3 PC30 / EXT1 / BRG2O / CLK2 / TOUT1 J4 V

J5 GND J6 GND J7 PA30 / FCC1:UTOPIA8:TXCLAV / FCC1:UTOPIA8:TXCLAV0 / FCC1:MII:CRS /

FCC1:HDLC and transparent:RTS J13 TA J14 GND J15 V

DDH

J16 V

DDH

J17 PSDAMUX / PGPL5 J18 PGTA

/ PUPMWAIT / PPBS / PGPL4

J19 PWE3

PSDDQM3

/ PBS3 K1 PA28 / FCC1:UTOPIA8:RXENB / FCC1:MII:TX_EN K2 PD29 / FCC1:UTOPIA8:RXADDR3 / FCC1:UTOPIA8:RXCLAV2 /

SCC1:RTS

/TENA

K3 PC29 / SCC1:CTS

/ SCC1:CLSN / BRG3O / CLK3 / TIN2

K4 PB29 / FCC2:MII:TX_EN / TDMB2:L1RSYNC

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

Page 99

3-27

FC-PBGA Package Description

K5 V

DDH

K6 GND

K7 GND K13 GND K14 PWE2

PSDDQM2

/ PBS2 K15 GND K16 V

DDH

K17 PWE1 /

PSDDQM1

/ PBS1 K18 PWE0 /

PSDDQM0

/ PBS0 K19 CS2

L1 PA27 / FCC1:UTOPIA8:RXSOC / FCC1:MII:RX_DV L2 PB28 / FCC2:RX_ER / FCC2:HDLC:RTS

/ SCC2:RTS/TENA / TDMB2:L1TSYNC

L3 PC28 / SCC2:CTS

/CLSN / BRG4O / CLK4 / TIN1/TOUT2

L4 V

L5 GND L6 GND

L7 PC27 / CLK5 / BRG5O / TGATE2 L13 CS6 L14 GND L15 GND L16 V

L17 CS1 L18 CS3 L19 BCTL1

M1 PB27 / FCC2:MII:COL / TDMC2:L1TXD M2 PC26 / TMCLK / BRG6O / CLK6 / TOUT3 M3 PB26 / FCC2:MII:CRS / TDMC2:L1RXD M4 V

DDH

M5 GND M6 PA26 / FCC1:UTOPIA8:RXCLAV / FCC1:UTOPIA8:RXCLAV0 /

FCC1:MII:RX_ER

M7 PA16 / FCC1:UTOPIA8:RXD6 / FCC1:MII and HDLC nibble:RXD1 M13 A21 M14 A26 M15 GND M16 CS0 M17 CS5 M18 CS7

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

Page 100

3-28

FC-PBGA Package Description

M19 CS4

N1 PC25 / DMA:DACK2 / BRG7O / CLK7 / TIN4 N2 PA25 / FCC1:UTOPIA8:TXD0 / SDMA:MSNUM0 N3 PB25 / FCC2:MII and HDLC nibble:TXD3 / TDMA1:nibble:L1TXD3 /

TDMC2:L1TSYNC

N4 V

N5 PC23 / EXT2 / DMA:DACK1 / CLK9 N6 GND N7 PD17 / FCC1:UTOPIA8:RXPRTY / SPI:SPIMOSI / BRG2O N8 CLKIN N9 GND

N10 PC6 / FCC1:UTOPIA8:RXADDR2 / FCC1:UTOPIA8:RXADDR2/RXCLAV1 /

FCC1:CD

/ SI2:LIST2 N11 TSIZ3 N12 TT1 N13 TT0 N14 A1 N15 V

DDH

N16 V

DDH

N17 A28 N18 A30 N19 A31

P1 PC24 / DMA:DREQ2 / BRG8O / CLK8 / TIN3/TOUT4 P2 PA24 / FCC1:UTOPIA8:TXD1 / SDMA:MSNUM1 P3 PB24 / FCC2:MII and HDLC nibble:TXD3 / TDMA1:nibble:L1RXD3 /

TDMC2:L1RSYNC P4 PA23 / FCC1:UTOPIA8:TXD2 P5 PB20 / FCC2:MII and HDLC nibble:RXD1 / TDMA1:nibble:L1TXD1 /

TDMD2:L1RSYNC P6 GND P7 GND P8 DLLIN P9 GND

P10 PC4 / FCC2:CD

/ SMC1:SMRXD / SI2:LIST4 P11 GND P12 GND P13 GND P14 GND P15 GND

Table 3-2. MSC8101 Signal Listing by Pin Designator (Continued)

Number Signal Name

Motorola Digital DNA MSC8101 Technical Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual