Mitsubishi M2V56S40AKT-7, M2V56S40AKT-6, M2V56S40AKT-5, M2V56S20AKT-7, M2V56S20AKT-6 Datasheet

SDRAM (Rev.1.01)	MITSUBISHI LSIs
Single Data Rate	M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01	256M Synchronous DRAM

Some of contents are subject to change without notice.

DESCRIPTION

M2V56S20AKT is a 4-bank x 16777216-word x 4-bit,

M2V56S30AKT is a 4-bank x 8388608-word x 8-bit,

M2V56S40AKT is a 4-bank x 4194304-word x 16-bit,

synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6), 166MHz(-5) and are suitable for main memory or graphic memory in computer systems.

FEATURES

-Single 3.3v±0.3V power supply

-Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2>

-Fully Synchronous operation referenced to clock rising edge

-Single Data Rate

-4 bank operation controlled by BA0, BA1 (Bank Address)

-/CAS latency- 2/3 (programmable)

-Burst length- 1/2/4/8/full page (programmable)

-Burst typesequential / interleave (programmable)

-Random column access

-Auto precharge / All bank precharge controlled by A10

-8192 refresh cycles /64ms (4 banks concurrent refresh)

-Auto refresh and Self refresh

-Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)

-LVTTL Interface

-10.65mm width x 13.1mm length, 64-pin STSOP(II) with 0.4mm lead pitch

		Max. Frequency	Max. Frequency	Standard
		@CL2	@CL3
	M2V56S20/30/40 AKT -5	133 MHz	166 MHz	PC133 (CL2)
	M2V56S20/30/40 AKT -6	100MHz	133 MHz	PC133 (CL3)
	M2V56S20/30/40 AKT -7	100 MHz	100MHz	PC100 (CL2)

MITSUBISHI ELECTRIC

1

SDRAM (Rev.1.01)

MITSUBISHI LSIs

Single Data Rate

M2V56S20/ 30/ 40 AKT -5, -6, -7

July '01

256M Synchronous DRAM

x4

x8

x16

1

64

VSS

VSS

VSS

VDD

VDD

VDD

2

63

DQ15

DQ7

NC

NC

DQ0

DQ0

3

62

VSSQ

VSSQ

VSSQ

VDDQ

VDDQ

VDDQ

4

61

DQ14

NC

NC

NC

NC

DQ1

5

60

DQ13

DQ6

DQ3

DQ0

DQ1

DQ2

6

59

VDDQ

VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

7

58

DQ12

NC

NC

NC

NC

DQ3

8

57

DQ11

DQ5

NC

NC

DQ2

DQ4

9

56

VSSQ

VSSQ

VSSQ

VDDQ

VDDQ

VDDQ

10

55

DQ10

NC

NC

NC

NC

DQ5

11

54

DQ9

DQ4

DQ2

DQ1

DQ3

DQ6

12

53

VDDQ

VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

NC

NC

DQ7

13

52

DQ8

NC

NC

NC

NC

NC

14

51

NC

NC

NC

NC

NC

NC

15

50

NC

NC

NC

NC

NC

NC

16

49

NC

NC

NC

VDD

VDD

VDD

17

48

NC

NC

NC

NC

NC

NC

18

47

VSS

VSS

VSS

NC

NC

LDQM

19

46

UDQM

DQM

DQM

/WE

/WE

/WE

20

45

NC

NC

NC

/CAS

/CAS

/CAS

21

44

CLK

CLK

CLK

/RAS

/RAS

/RAS

22

43

CKE

CKE

CKE

/CS

/CS

/CS

23

42

NC

NC

NC

NC

NC

NC

24

41

A12

A12

A12

BA0

BA0

BA0

25

40

A11

A11

A11

BA1

BA1

BA1

26

39

A9

A9

A9

A10/AP

A10/AP

A10/AP

27

38

A8

A8

A8

A0

A0

A0

28

37

A7

A7

A7

A1

A1

A1

29

36

A6

A6

A6

A2

A2

A2

30

35

A5

A5

A5

A3

A3

A3

31

34

A4

A4

A4

VDD

VDD

VDD

32

TOP VIEW

33

VSS

VSS

VSS

CLK

: Master Clock

CKE

: Clock Enable

/CS

: Chip Select

/RAS

: Row Address Strobe

/CAS

: Column Address Strobe

/WE

: Write Enable

DQ0-15

: Data I/O

DQM, DQMU/L : Output Disable / Write Mask

A0-12

: Address Input

BA0,1

: Bank Address Input

Vdd

: Power Supply

VddQ

: Power Supply for Output

Vss

: Ground

VssQ

: Ground for Output

MITSUBISHI ELECTRIC

2

SDRAM (Rev.1.01)	MITSUBISHI LSIs
Single Data Rate	M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01	256M Synchronous DRAM

BLOCK DIAGRAM		DQ0-3 (x4), 0-7 (x8), 0 - 15 (x16)
		I/O Buffer
Memory		Memory		Memory	Memory
Array		Array		Array	Array
Bank #0		Bank #1		Bank #2	Bank #3
Mode Register
		Control Circuitry
Address Buffer				Control Signal Buffer
		Clock Buffer
A0-12	BA0,1	CLK	CKE	/CS /RAS /CAS /WE DQMU/L

Type Designation Code

This rule is applied to only Synchronous DRAM family.

M 2 V 56 S 4 0 A KT - 5

Speed Grade 5: 166MHz@CL3, 133MHz@CL2 6: 133MHz@CL3, 100MHz@CL2 7: 100MHz@CL2

Package Type KT: STSOP(II)

Process Generation A:2nd. gen.

Function Reserved for Future Use

Organization 2n 2: x4, 3: x8, 4: x16

SDRAM Data Rate Type S:Single Data Rate

Density 56: 256M bits

Interface V:LVTTL

Memory Style (DRAM)

Mitsubishi Main Designation

MITSUBISHI ELECTRIC

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	SDRAM (Rev.1.01)		MITSUBISHI LSIs
	Single Data Rate		M2V56S20/ 30/ 40 AKT -5, -6, -7
	July '01		256M Synchronous DRAM
	PIN FUNCTION
	CLK	Input	Master Clock: All other inputs are referenced to the rising edge of CLK.
			Clock Enable: CKE controls internal clock. When CKE is low, internal
	CKE	Input	clock for the following cycle is ceased. CKE is also used to select auto
			/ self refresh. After self refresh mode is started, CKE becomes
			asynchronous input. Self refresh is maintained as long as CKE is low.
	/CS	Input	Chip Select: When /CS is high, any command means No Operation
	/RAS, /CAS, /WE	Input	Combination of /RAS, /CAS, /WE defines basic commands.
			A0-12 specify the Row / Column Address in conjunction with BA0,1.
			The Row Address is specified by A0-12. The Column Address is
	A0-12	Input	specified by A0-9,11. A10 is also used to indicate precharge option.
			When A10 is high at a read / write command, an auto precharge is
			performed. When A10 is high at a precharge command, all banks are
			precharged.
			Bank Address: BA0,1 specifies one of four banks to which a command
	BA0,1	Input	is applied. BA0,1 must be set with ACT, PRE, READ, WRITE
			commands.
	DQ0-15	Input / Output	Data In and Data out are referenced to the rising edge of CLK.
	DQM		Din Mask / Output Disable: When DQMU/L is high in burst write, Din for
		Input	the current cycle is masked. When DQMU/L is high in burst read, Dout
	DQMU/L
			is disabled at the next but one cycle.
	Vdd, Vss	Power Supply	Power Supply for the memory array and peripheral circuitry.
	VddQ, VssQ	Power Supply	VddQ and VssQ are supplied to the Output Buffers only.

MITSUBISHI ELECTRIC

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SDRAM (Rev.1.01)	MITSUBISHI LSIs
Single Data Rate	M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01	256M Synchronous DRAM

BASIC FUNCTIONS

The M2V56S20/30/40AKT provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.

CLK

/CS				Chip Select : L=select, H=deselect
				Command
/RAS
				Command	define basic commands
/CAS
				Command
/WE
				Refresh Option @refresh command
CKE
				Precharge Option @precharge or read/write command
A10

Activate (ACT) [/RAS =L, /CAS =/WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read (READ) [/RAS =H, /CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge, READA)

Write (WRITE) [/RAS =H, /CAS =/WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA).

Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA).

Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]

REFA command starts auto-refresh cycle. Refresh address are generated internally. After this command, the banks are precharged automatically.

MITSUBISHI ELECTRIC

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MITSUBISHI LSIs

SDRAM (Rev.1.01)

Single Data Rate

M2V56S20/ 30/ 40 AKT -5, -6, -7

July '01

256M Synchronous DRAM

COMMAND TRUTH TABLE

COMMAND

MNEMONIC

CKE

CKE

/CS

/RAS

/CAS

/WE

BA0,1

A10

A0-9,

note

n-1

n

/AP

11-12

Deselect

DESEL

H

X

H

X

X

X

X

X

X

No Operation

NOP

H

X

L

H

H

H

X

X

X

Row Address Entry &

ACT

H

X

L

L

H

H

V

V

V

Bank Activate

Single Bank Precharge

PRE

H

X

L

L

H

L

V

L

X

Precharge All Banks

PREA

H

X

L

L

H

L

X

H

X

Column Address Entry

WRITE

H

X

L

H

L

L

V

L

V

& Write

Column Address Entry

& Write with

WRITEA

H

X

L

H

L

L

V

H

V

Auto-Precharge

Column Address Entry

READ

H

X

L

H

L

H

V

L

V

& Read

Column Address Entry

& Read with

READA

H

X

L

H

L

H

V

H

V

Auto-Precharge

Auto-Refresh

REFA

H

H

L

L

L

H

X

X

X

Self-Refresh Entry

REFS

H

L

L

L

L

H

X

X

X

Self-Refresh Exit

REFSX

L

H

H

X

X

X

X

X

X

L

H

L

H

H

H

X

X

X

Burst Terminate

TBST

H

X

L

H

H

L

X

X

X

Mode Register Set

MRS

H

X

L

L

L

L

L

L

V

1

H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number

NOTE:

1. A7-9,11-12=L, A0-A6

=Mode

Address

MITSUBISHI ELECTRIC

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SDRAM (Rev.1.01)							MITSUBISHI LSIs
Single Data Rate					M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01						256M Synchronous DRAM
FUNCTION TRUTH TABLE
Current State	/CS	/RAS	/CAS	/WE	Address	Command	Action
IDLE	H	X	X	X	X	DESEL	NOP
	L	H	H	H	X	NOP	NOP
	L	H	H	L	X	TBST	ILLEGAL*2
	L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL*2
	L	L	H	H	BA, RA	ACT	Bank Active, Latch RA
	L	L	H	L	BA, A10	PRE / PREA	NOP*4
	L	L	L	H	X	REFA	Auto-Refresh*5
	L	L	L	L	Op-Code,	MRS	Mode Register Set*5
					Mode-Add
ROW ACTIVE	H	X	X	X	X	DESEL	NOP
	L	H	H	H	X	NOP	NOP
	L	H	H	L	X	TBST	NOP
	L	H	L	H	BA, CA, A10	READ / READA	Begin Read, Latch CA,
							Determine Auto-Precharge
	L	H	L	L	BA, CA, A10	WRITE /	Begin Write, Latch CA,
						WRITEA	Determine Auto-Precharge
	L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
	L	L	H	L	BA, A10	PRE / PREA	Precharge / Precharge All
	L	L	L	H	X	REFA	ILLEGAL
	L	L	L	L	Op-Code,	MRS	ILLEGAL
					Mode-Add
READ	H	X	X	X	X	DESEL	NOP (Continue Burst to END)
	L	H	H	H	X	NOP	NOP (Continue Burst to END)
	L	H	H	L	X	TBST	Terminate Burst
							Terminate Burst, Latch CA,
	L	H	L	H	BA, CA, A10	READ / READA	Begin New Read, Determine
							Auto-Precharge*3
						WRITE /	Terminate Burst, Latch CA,
	L	H	L	L	BA, CA, A10		Begin Write, Determine Auto-
						WRITEA
							Precharge*3
	L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
	L	L	H	L	BA, A10	PRE / PREA	Terminate Burst, Precharge
	L	L	L	H	X	REFA	ILLEGAL
	L	L	L	L	Op-Code,	MRS	ILLEGAL
					Mode-Add

MITSUBISHI ELECTRIC

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SDRAM (Rev.1.01)							MITSUBISHI LSIs
Single Data Rate					M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01						256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State	/CS	/RAS	/CAS	/WE	Address	Command	Action
WRITE	H	X	X	X	X	DESEL	NOP (Continue Burst to END)
	L	H	H	H	X	NOP	NOP (Continue Burst to END)
	L	H	H	L	X	TBST	Terminate Burst
							Terminate Burst, Latch CA,
	L	H	L	H	BA, CA, A10	READ / READA	Begin Read, Determine Auto-
							Precharge*3
						WRITE /	Terminate Burst, Latch CA,
	L	H	L	L	BA, CA, A10		Begin Write, Determine Auto-
						WRITEA
							Precharge*3
	L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
	L	L	H	L	BA, A10	PRE / PREA	Terminate Burst, Precharge
	L	L	L	H	X	REFA	ILLEGAL
	L	L	L	L	Op-Code,	MRS	ILLEGAL
					Mode-Add
READ with	H	X	X	X	X	DESEL	NOP (Continue Burst to END)
AUTO	L	H	H	H	X	NOP	NOP (Continue Burst to END)
PRECHARGE	L	H	H	L	X	TBST	ILLEGAL
	L	H	L	H	BA, CA, A10	READ / READA	ILLEGAL
	L	H	L	L	BA, CA, A10	WRITE /	ILLEGAL
						WRITEA
	L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
	L	L	H	L	BA, A10	PRE / PREA	ILLEGAL*2
	L	L	L	H	X	REFA	ILLEGAL
	L	L	L	L	Op-Code,	MRS	ILLEGAL
					Mode-Add
WRITE with	H	X	X	X	X	DESEL	NOP (Continue Burst to END)
AUTO	L	H	H	H	X	NOP	NOP (Continue Burst to END)
PRECHARGE	L	H	H	L	X	TBST	ILLEGAL
	L	H	L	H	BA, CA, A10	READ / READA	ILLEGAL
	L	H	L	L	BA, CA, A10	WRITE /	ILLEGAL
						WRITEA
	L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
	L	L	H	L	BA, A10	PRE / PREA	ILLEGAL*2
	L	L	L	H	X	REFA	ILLEGAL
	L	L	L	L	Op-Code,	MRS	ILLEGAL
					Mode-Add

MITSUBISHI ELECTRIC

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	SDRAM (Rev.1.01)								MITSUBISHI LSIs
	Single Data Rate						M2V56S20/ 30/ 40 AKT -5, -6, -7
	July '01							256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
	Current State		/CS	/RAS	/CAS	/WE	Address	Command	Action
	PRE -		H	X	X	X	X	DESEL	NOP (Idle after tRP)
	CHARGING		L	H	H	H	X	NOP	NOP (Idle after tRP)
			L	H	H	L	X	TBST	ILLEGAL*2
			L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL*2
			L	L	H	H	BA, RA	ACT	ILLEGAL*2
			L	L	H	L	BA, A10	PRE / PREA	NOP*4 (Idle after tRP)
			L	L	L	H	X	REFA	ILLEGAL
			L	L	L	L	Op-Code,	MRS	ILLEGAL
							Mode-Add
	ROW		H	X	X	X	X	DESEL	NOP (Row Active after tRCD)
	ACTIVATING		L	H	H	H	X	NOP	NOP (Row Active after tRCD)
			L	H	H	L	X	TBST	ILLEGAL*2
			L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL*2
			L	L	H	H	BA, RA	ACT	ILLEGAL*2
			L	L	H	L	BA, A10	PRE / PREA	ILLEGAL*2
			L	L	L	H	X	REFA	ILLEGAL
			L	L	L	L	Op-Code,	MRS	ILLEGAL
							Mode-Add
	WRITE RE-		H	X	X	X	X	DESEL	NOP
	COVERING		L	H	H	H	X	NOP	NOP
			L	H	H	L	X	TBST	ILLEGAL*2
			L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL*2
			L	L	H	H	BA, RA	ACT	ILLEGAL*2
			L	L	H	L	BA, A10	PRE / PREA	ILLEGAL*2
			L	L	L	H	X	REFA	ILLEGAL
			L	L	L	L	Op-Code,	MRS	ILLEGAL
							Mode-Add

MITSUBISHI ELECTRIC

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SDRAM (Rev.1.01)								MITSUBISHI LSIs
Single Data Rate						M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01							256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State		/CS	/RAS	/CAS	/WE	Address	Command	Action
RE-		H	X	X	X	X	DESEL	NOP (Idle after tRC)
FRESHING		L	H	H	H	X	NOP	NOP (Idle after tRC)
		L	H	H	L	X	TBST	ILLEGAL
		L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL
		L	L	H	H	BA, RA	ACT	ILLEGAL
		L	L	H	L	BA, A10	PRE / PREA	ILLEGAL
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add
MODE		H	X	X	X	X	DESEL	NOP (Idle after tRSC)
REGISTER		L	H	H	H	X	NOP	NOP (Idle after tRSC)
SETTING		L	H	H	L	X	TBST	ILLEGAL
		L	H	L	X	BA, CA, A10	READ / WRITE	ILLEGAL
		L	L	H	H	BA, RA	ACT	ILLEGAL
		L	L	H	L	BA, A10	PRE / PREA	ILLEGAL
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration

NOTES:

1.All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

2.ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.

3.Must satisfy bus contention, bus turn around, write recovery requirements.

4.NOP to bank precharging or in idle state. May precharge bank indicated by BA.

5.ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

MITSUBISHI ELECTRIC

10

SDRAM (Rev.1.01)

MITSUBISHI LSIs

Single Data Rate

M2V56S20/ 30/ 40 AKT -5, -6, -7

July '01

256M Synchronous DRAM

FUNCTION TRUTH TABLE for CKE

Current State

CKE

CKE

/CS

/RAS

/CAS

/WE

Add

Action

n-1

n

SELF-

H

X

X

X

X

X

X

INVALID

REFRESH*1

L

H

H

X

X

X

X

Exit Self-Refresh (Idle after tRC)

L

H

L

H

H

H

X

Exit Self-Refresh (Idle after tRC)

L

H

L

H

H

L

X

ILLEGAL

L

H

L

H

L

X

X

ILLEGAL

L

H

L

L

X

X

X

ILLEGAL

L

L

X

X

X

X

X

NOP (Maintain Self-Refresh)

POWER

H

X

X

X

X

X

X

INVALID

DOWN

L

H

X

X

X

X

X

Exit Power Down to Idle

L

L

X

X

X

X

X

NOP (Maintain Power Down)

ALL BANKS

H

H

X

X

X

X

X

Refer to Function Truth Table

IDLE*2

H

L

L

L

L

H

X

Enter Self-Refresh

H

L

H

X

X

X

X

Enter Power Down

H

L

L

H

H

H

X

Enter Power Down

H

L

L

H

H

L

X

ILLEGAL

H

L

L

H

L

X

X

ILLEGAL

H

L

L

L

X

X

X

ILLEGAL

L

X

X

X

X

X

X

Refer to Current State =Power Down

ANY STATE

H

H

X

X

X

X

X

Refer to Function Truth Table

other than

H

L

X

X

X

X

X

Begin CLK Suspend at Next Cycle*3

listed above

L

H

X

X

X

X

X

Exit CLK Suspend at Next Cycle*3

L

L

X

X

X

X

X

Maintain CLK Suspend

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

NOTES:

1.CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT.

2.Self-Refresh can be entered only from the All Banks Idle State.

3.Must be legal command.

MITSUBISHI ELECTRIC

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SDRAM (Rev.1.01)	MITSUBISHI LSIs
Single Data Rate	M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01	256M Synchronous DRAM

SIMPLIFIED STATE DIAGRAM

							SELF
							REFRESH
				REFS
						REFSX
	MODE	MRS			REFA		AUTO
	REGISTER		IDLE
							REFRESH
	SET
						CKEL
	CLK			CKEH
	SUSPEND
			ACT
							POWER
			CKEL				DOWN
		CKEH
			ROW
		TBST	ACTIVE			TBST
		WRITE			READ
	CKEL		WRITEA	READA			CKEL	READ
WRITE			READ
	WRITE						READ	SUSPEND
			WRITE
SUSPEND
	CKEH						CKEH
	WRITEA						READA
		WRITEA		READA
	CKEL						CKEL
WRITEA			PRE					READA
	WRITEA					READA
SUSPEND CKEH			PRE	PRE			CKEH	SUSPEND
POWER
APPLIED	POWER	PRE	PRE
	ON		CHARGE
								Automatic Sequence
								Command Sequence

MITSUBISHI ELECTRIC

12

SDRAM (Rev.1.01)	MITSUBISHI LSIs
Single Data Rate	M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01	256M Synchronous DRAM

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent a

SDRAM from damaged or malfunctioning.

1.Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.

2.Maintain stable power, stable clock, and NOP input conditions for a minimum of 100µs.

3.Issue precharge commands for all banks. (PRE or PREA)

4.After all banks become idle state (after tRP), issue 2 or more auto-refresh commands.

5.Issue a mode register set command to initialize the mode register.

After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.

CLK

/CS

/RAS

/CAS

/WE

																					BA0,1 A12-A0					V
	BA0	BA1		A12	A11		A10	A9		A8	A7	A6		A5	A4		A3	A2		A1		A0
	0	0		0	0		0	SW		0	0		LTMODE				BT			BL
							SW	0		Burst Write
								1		Single Write												BL		BT=0		BT=1
																					0 0 0			1		1
																					0 0 1			2		2
				CL			/CAS LATENCY										BURST				0 1 0			4		4
			0 0 0					R													0 1 1			8		8
																	LENGTH
			0 0 1					R													1 0 0			R		R
LATENCY			0 1 0					2													1 0 1			R		R
			0 1 1					3													1 1 0			R		R
MODE
			1 0 0					R													1 1 1			Full Page		R
			1 0 1					R
			1 1 0					R									BURST				0			SEQUENTIAL
			1 1 1					R									TYPE				1			INTERLEAVED

R: Reserved for Future Use

MITSUBISHI ELECTRIC

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SDRAM (Rev.1.01)								MITSUBISHI LSIs
Single Data Rate			M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01						256M Synchronous DRAM
CLK
Command	Read					Write
Address	Y					Y
DQ		Q0	Q1	Q2	Q3	D0	D1	D2	D3
	/CAS Latency
	CL= 3
	BL= 4		Burst Length				Burst Length
					Burst Type

Initial Address			BL									Column Addressing
A2	A1	A0					Sequential											Interleaved
0	0	0		0	1	2	3	4			5	6	7	0	1		2		3	4			5	6	7
0	0	1		1	2	3	4	5			6	7	0	1	0		3		2	5			4	7	6
0	1	0		2	3	4	5	6			7	0	1	2	3		0		1	6			7	4	5
0	1	1		3	4	5	6	7			0	1	2	3	2		1		0	7			6	5	4
1	0	0	8	4	5	6	7	0			1	2	3	4	5		6		7	0			1	2	3
1	0	1		5	6	7	0	1			2	3	4	5	4		7		6	1			0	3	2
1	1	0		6	7	0	1	2			3	4	5	6	7		4		5	2			3	0	1
1	1	1		7	0	1	2	3			4	5	6	7	6		5		4	3			2	1	0
-	0	0		0	1	2	3							0	1		2		3
-	0	1		1	2	3	0							1	0		3		2
-	1	0	4	2	3	0	1							2	3		0		1
-	1	1		3	0	1	2							3	2		1		0
-	-	0		0	1									0	1
-	-	1	2	1	0									1	0

MITSUBISHI ELECTRIC

14

SDRAM (Rev.1.01)	MITSUBISHI LSIs
Single Data Rate	M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01	256M Synchronous DRAM

OPERATIONAL DESCRIPTION

BANK ACTIVATE

One of four banks is activated by an ACT command.

An bank is selected by BA0-1. A row is selected by A0-12.

Multiple banks can be active state concurrently by issuing multiple ACT commands. Minimum activation interval between one bank and another bank is tRRD.

PRECHARGE

An open bank is deactivated by a PRE command.

A bank to be deactivated is designated by BA0-1.

When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case.

Minimum delay time of an ACT command after a PRE command to the same bank is tRP.

Bank Activation and Precharge All (BL=4, CL=3)

CLK

Command

ACT

ACT

READ

PRE

ACT

tR

RD

tR

CD

tRP

A0-9,11-12

Xa

Xb

Yb

Xa

A10

Xa

Xb

0

1

Xa

BA0-1

00

01

01

00

DQ

Qb0

Qb1

Qb2

Qb3

Precharge All

READ

A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4), A0- 9 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.

MITSUBISHI ELECTRIC

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