Mitsubishi M2V28S30TP-8L, M2V28S30TP-8, M2V28S30TP-7L, M2V28S40TP-8L, M2V28S40TP-8 Datasheet

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

PRELIMINARY

Some of contents are described for general products and are subject to change without notice.

DESCRIPTION

M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.

M2V28S20TP,M2V28S30TP,M2V28S40TP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems.

FEATURES

	ITEM				M2V28S20/30/40TP
					-6		-7	-8
tCLK	Clock Cycle Time	(Min.)			7.5ns		10ns	10ns
tRAS	Active to Precharge Command Period		(Min.)		45ns		50ns	50ns
tRCD	Row to Column Delay		(Min.)		20ns		20ns	20ns
tAC	Access Time from CLK		(Max.) (CL=3)		5.4ns		6ns	6ns
tRC	Ref/Active Command Period		(Min.)		67.5ns		70ns	70ns
	Operation Current	(Max.)		V28S20	120mA		115mA	115mA
Icc1				V28S30	130mA		120mA	120mA
	(Single Bank)
				V28S40	-		135mA	135mA
Icc6	Self Refresh Current		(Max.)		2mA		2mA	2mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>

-PC133(-6) supports x4/x8 only. And does not support Low-Power (L) version.

-Fully synchronous operation referenced to clock rising edge

-4-bank operation controlled by BA0,BA1(Bank Address)

-/CAS latency- 2/3 (programmable)

-Burst length- 1/2/4/8/FP (programmable)

-Burst typeSequential and interleave burst (programmable)

-Byte ControlDQML and DQMU (M2V28S40TP)

-Random column access

-Auto precharge / All bank precharge controlled by A10

-Auto and self refresh

-4096 refresh cycles /64ms

-LVTTL Interface

-Package

M2V28S20TP/30TP/40TP

400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch

MITSUBISHI ELECTRIC

1

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

Revision History

Rev.	Description

1.0- Add PC133 Specification.

MITSUBISHI ELECTRIC

2

128M Synchronous DRAM

SDRAM (Rev. 1.0E)

M2V28S20TP-6,-7,-8

(4-BANK x 8,388,608-WORD x

4-BIT)

Jun. '99

M2V28S30TP-6,-7,-7L,-8,-8L

(4-BANK x 4,194,304-WORD x

8-BIT)

MITSUBISHI LSIs

M2V28S40TP-7,-7L,-8,-8L

(4-BANK x 2,097,152-WORD x 16-BIT)

PIN CONFIGURATION (TOP VIEW)

M2V28S20TP

M2V28S30TP

M2V28S40TP

PIN CONFIGURATION

(TOP VIEW)

Vdd

Vdd

Vdd

1

54

Vss

Vss

Vss

NC

DQ0

DQ0

2

53

DQ15

DQ7

NC

VddQ

VddQ

VddQ

VssQ

VssQ

VssQ

3

52

NC

NC

DQ1

DQ14

NC

NC

4

51

DQ0

DQ1

DQ2

DQ13

DQ6

DQ3

5

50

VssQ

VssQ

VssQ

VddQ

VddQ

VddQ

6

49

NC

NC

DQ3

DQ12

NC

NC

7

48

NC

DQ2

DQ4

DQ11

DQ5

NC

8

47

VddQ

VddQ

VddQ

VssQ

VssQ

VssQ

9

46

NC

NC

DQ5

DQ10

NC

NC

10

45

DQ1

DQ3

DQ6

DQ9

DQ4

DQ2

11

44

VssQ

VssQ

VssQ

VddQ

VddQ

VddQ

12

43

NC

NC

DQ7

DQ8

NC

NC

13

42

Vdd

Vdd

Vdd

14

41

Vss

Vss

Vss

NC

NC

DQML

NC

NC

NC

15

40

/WE

/WE

/WE

DQMU

DQM

DQM

16

39

/CAS

/CAS

/CAS

CLK

CLK

CLK

17

38

/RAS

/RAS

/RAS

CKE

CKE

CKE

18

37

/CS

/CS

/CS

NC

NC

NC

19

36

BA0(A13)

BA0(A13)

BA0(A13)

A11

A11

A11

20

35

BA1(A12)

BA1(A12)

BA1(A12)

A9

A9

A9

21

34

A10(AP)

A10(AP)

A10(AP)

A8

A8

A8

22

33

A0

A0

A0

A7

A7

A7

23

32

A1

A1

A1

A6

A6

A6

24

31

A2

A2

A2

A5

A5

A5

25

30

A3

A3

A3

26

29

A4

A4

A4

Vdd

Vdd

Vdd

Vss

Vss

Vss

27

28

	CLK	: Master Clock	DQM	: Output Disable/ Write Mask
	CKE	: Clock Enable	A0-11	: Address Input
	/CS	: Chip Select
			BA0,1	: Bank Address
	/RAS	: Row Address Strobe
			Vdd	: Power Supply
	/CAS	: Column Address Strobe
			VddQ	: Power Supply for Output
	/WE	: Write Enable
			Vss	: Ground
	DQ0-15	: Data I/O
			VssQ	: Ground for Output

MITSUBISHI ELECTRIC

3

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

BLOCK DIAGRAM

				DQ0-7
			I/O Buffer
Memory Array		Memory Array			Memory Array		Memory Array
4096 x1024 x8		4096 x1024 x8			4096 x1024 x8		4096 x1024 x8
Cell Array		Cell Array			Cell Array		Cell Array
Bank #0		Bank #1			Bank #2			Bank #3
Mode
Register
			Control Circuitry
Address Buffer					Control Signal Buffer
		Clock Buffer
A0-11	BA0,1	CLK	CKE	/CS	/RAS	/CAS	/WE	DQM

Note : This figure shows the M2V28S30TP.

The M2V28S20TP configration is 4096x2048x4 of cell array and DQ 0-3.

The M2V28S40TP configration is 4096x512x16 of cell array and DQ 0-15.

Type Designation Code

M2 V 28 S 3 0 TP -8

These rules are only applied to the Synchronous DRAM family.

Access Item	-6 : 7.5ns (PC133/3-3-3),
	-7 : 10ns(PC100/2-2-2),
	-8 : 10ns(PC100/3-2-2)
Package Type	TP : TSOP(II)
Process Generation	Blank : 1st gen.
Function	0 : Random Column
Organization	2: x4,	3: x8,	4: x16
Synchronous DRAM
Density	28 : 128Mbit
Interface	V : LVTTL
Mitsubishi DRAM

MITSUBISHI ELECTRIC

4

128M Synchronous DRAM

SDRAM (Rev. 1.0E)		M2V28S20TP-6,-7,-8		(4-BANK x 8,388,608-WORD x	4-BIT)
Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L		(4-BANK x 4,194,304-WORD x	8-BIT)
MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L				(4-BANK x 2,097,152-WORD x 16-BIT)
PIN FUNCTION
CLK		Input	Master Clock:
			All other inputs are referenced to the rising edge of CLK.
			Clock Enable:
			CKE controls internal clock. When CKE is low, internal clock for the
CKE		Input	following cycle is ceased. CKE is also used to select auto /
			selfrefresh. After self refresh mode is started, CKE becomes
			synchronous input. Self refresh is maintained as long as CKE is low.
/CS		Input	Chip Select:
			When /CS is high, any command means No Operation.
/RAS, /CAS, /WE		Input	Combination of /RAS, /CAS, /WE defines basic commands.
			A0-11 specify the Row / Column Address in conjunction with BA0,1.
			The Row Address is specified by A0-11. The Column Address is
A0-11		Input	specified by A0-9,11 (x4) / A0-9 (x8) / A0-8 (x16).
			A10 is also used to indicate precharge option. When A10 is high at a
			read / write command, an auto precharge is performed. When A10 is
			high at a precharge command, all banks are precharged.
			Bank Address:
BA0,1		Input	BA0,1 specifies one of four banks to which a command is applied.
			BA0,1 must be set with ACT, PRE, READ, WRITE commands.
DQ0-7	Input / Output		Data In and Data out are referenced to the rising edge of CLK.
			Din Mask / Output Disable:
DQM		Input	When DQM is high in burst write, Din for the current cycle is masked.
			When DQM is high in burst read,	Dout is disabled at the next but one
			cycle.
Vdd, Vss	Power Supply		Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ	Power Supply		VddQ and VssQ are supplied to the Output Buffers only.

MITSUBISHI ELECTRIC

5

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

BASIC FUNCTIONS

The M2V28S30TP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh.

Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively.

To know the detailed definition of commands, please see the command truth table.

CLK

/CS				Chip Select : L=select, H=deselect
/RAS				Command
/CAS				Command	define basic commands
/WE				Command
CKE				Refresh Option @ refresh command
A10				Precharge Option @ precharge or read/write command

Activate (ACT) [/RAS =L, /CAS =/WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read (READ) [/RAS =H, /CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA).

Write (WRITE) [/RAS =H, /CAS =/WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA).

Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, all banks are deactivated (precharge all,

PREA ).

Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]

REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.

MITSUBISHI ELECTRIC

6

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

COMMAND TRUTH TABLE

COMMAND

MNEMONIC

CKE

CKE

/CS

/RAS

/CAS

/WE

BA0,1

A11

A10

A0-9

n-1

n

Deselect

DESEL

H

X

H

X

X

X

X

X

X

X

No Operation

NOP

H

X

L

H

H

H

X

X

X

X

Row Address Entry &

ACT

H

X

L

L

H

H

V

V

V

V

Bank Activate

Single Bank Precharge

PRE

H

X

L

L

H

L

V

X

L

X

Precharge All Banks

PREA

H

X

L

L

H

L

X

X

H

X

Column Address Entry

WRITE

H

X

L

H

L

L

V

V

L

V

& Write

Column Address Entry &

WRITEA

H

X

L

H

L

L

V

V

H

V

Write with Auto-Precharge

Column Address Entry

READ

H

X

L

H

L

H

V

V

L

V

& Read

Column Address Entry &

READA

H

X

L

H

L

H

V

V

H

V

Read with Auto-Precharge

Auto-Refresh

REFA

H

H

L

L

L

H

X

X

X

X

Self-Refresh Entry

REFS

H

L

L

L

L

H

X

X

X

X

L

H

H

X

X

X

X

X

X

X

Self-Refresh Exit

REFSX

L

H

L

H

H

H

X

X

X

X

Mode Register Set

MRS

H

X

L

L

L

L

L

L

L

V*1

H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number

NOTE:

1. A7-A9 =0, A0-A6 =Mode Address

MITSUBISHI ELECTRIC

7

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH TABLE

Current State	/CS	/RAS	/CAS	/WE	Address	Command	Action
IDLE	H	X	X	X	X	DESEL	NOP
	L	H	H	H	X	NOP	NOP
	L	H	H	L	BA	TBST	ILLEGAL*2
	L	H	L	X	BA, CA, A10	READ /	ILLEGAL*2
						WRITE
	L	L	H	H	BA, RA	ACT	Bank Active, Latch RA
	L	L	H	L	BA, A10	PRE /	NOP*4
						PREA
	L	L	L	H	X	REFA	Auto-Refresh*5
	L	L	L	L	Op-Code,	MRS	Mode Register Set*5
					Mode-Add
ROW ACTIVE	H	X	X	X	X	DESEL	NOP
	L	H	H	H	X	NOP	NOP
	L	H	H	L	BA	TBST	NOP
	L	H	L	H	BA, CA, A10	READ /	Begin Read, Latch CA, Determine
						READA	Auto-Precharge
	L	H	L	L	BA, CA, A10	WRITE /	Begin Write, Latch CA, Determine
						WRITEA	Auto-Precharge
	L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
	L	L	H	L	BA, A10	PRE /	Precharge / Precharge All
						PREA
	L	L	L	H	X	REFA	ILLEGAL
	L	L	L	L	Op-Code,	MRS	ILLEGAL
					Mode-Add

MITSUBISHI ELECTRIC

8

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)			M2V28S20TP-6,-7,-8					(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
				M2V28S30TP-6,-7,-7L,-8,-8L					(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs
				M2V28S40TP-7,-7L,-8,-8L					(4-BANK x 2,097,152-WORD x 16-BIT)
	FUNCTION TRUTH TABLE (continued)
	Current State	/CS	/RAS	/CAS	/WE	Address	Command		Action
	READ	H	X	X	X	X	DESEL		NOP (Continue Burst to END)
		L	H	H	H	X	NOP		NOP (Continue Burst to END)
		L	H	H	L	BA	TBST		Terminate Burst
		L	H	L	H	BA, CA, A10	READ		Terminate Burst, Latch CA, Begin New
							/READA		Read, Determine Auto-Precharge*3
		L	H	L	L	BA, CA, A10	WRITE /		Terminate Burst, Latch CA, Begin
							WRITEA		Write, Determine Auto-Precharge*3
		L	L	H	H	BA, RA	ACT		Bank Active / ILLEGAL*2
		L	L	H	L	BA, A10	PRE /		Terminate Burst, Precharge
							PREA
		L	L	L	H	X	REFA		ILLEGAL
		L	L	L	L	Op-Code,	MRS		ILLEGAL
						Mode-Add
	WRITE	H	X	X	X	X	DESEL		NOP (Continue Burst to END)
		L	H	H	H	X	NOP		NOP (Continue Burst to END)
		L	H	H	L	BA	TBST		Terminate Burst
		L	H	L	H	BA, CA, A10	READ /		Terminate Burst, Latch CA, Begin
							READA		Read, Determine Auto-Precharge*3
		L	H	L	L	BA, CA, A10	WRITE /		Terminate Burst, Latch CA,Begin
							WRITEA		Write, Determine Auto-Precharge*3
		L	L	H	H	BA, RA	ACT		Bank Active / ILLEGAL*2
		L	L	H	L	BA, A10	PRE /		Terminate Burst, Precharge
							PREA
		L	L	L	H	X	REFA		ILLEGAL
		L	L	L	L	Op-Code,	MRS		ILLEGAL
						Mode-Add

MITSUBISHI ELECTRIC

9

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH TABLE (continued)

	Current State	/CS	/RAS	/CAS	/WE	Address	Command	Action
	READ with	H	X	X	X	X	DESEL	NOP (Continue Burst to END)
	AUTO
		L	H	H	H	X	NOP	NOP (Continue Burst to END)
	PRECHARGE
		L	H	H	L	BA	TBST	ILLEGAL
		L	H	L	H	BA, CA, A10	READ /	ILLEGAL
							READA
		L	H	L	L	BA, CA, A10	WRITE /	ILLEGAL
							WRITEA
		L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
		L	L	H	L	BA, A10	PRE /	ILLEGAL*2
							PREA
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add
	WRITE with	H	X	X	X	X	DESEL	NOP (Continue Burst to END)
	AUTO
		L	H	H	H	X	NOP	NOP (Continue Burst to END)
	PRECHARGE
		L	H	H	L	BA	TBST	ILLEGAL
		L	H	L	H	BA, CA, A10	READ /	ILLEGAL
							READA
		L	H	L	L	BA, CA, A10	WRITE /	ILLEGAL
							WRITEA
		L	L	H	H	BA, RA	ACT	Bank Active / ILLEGAL*2
		L	L	H	L	BA, A10	PRE /	ILLEGAL*2
							PREA
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add

MITSUBISHI ELECTRIC

10

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH TABLE (continued)

Current State		/CS	/RAS	/CAS	/WE	Address	Command	Action
PRE -		H	X	X	X	X	DESEL	NOP (Idle after tRP)
CHARGING
		L	H	H	H	X	NOP	NOP (Idle after tRP)
		L	H	H	L	BA	TBST	ILLEGAL*2
		L	H	L	X	BA, CA, A10	READ /	ILLEGAL*2
							WRITE
		L	L	H	H	BA, RA	ACT	ILLEGAL*2
		L	L	H	L	BA, A10	PRE /	NOP*4 (Idle after tRP)
							PREA
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add
ROW		H	X	X	X	X	DESEL	NOP (Row Active after tRCD)
ACTIVATING
		L	H	H	H	X	NOP	NOP (Row Active after tRCD)
		L	H	H	L	BA	TBST	ILLEGAL*2
		L	H	L	X	BA, CA, A10	READ /	ILLEGAL*2
							WRITE
		L	L	H	H	BA, RA	ACT	ILLEGAL*2
		L	L	H	L	BA, A10	PRE /	ILLEGAL*2
							PREA
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add

MITSUBISHI ELECTRIC

11

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH TABLE (continued)

Current State		/CS	/RAS	/CAS	/WE	Address	Command	Action
WRITE		H	X	X	X	X	DESEL	NOP
RECOVERING
		L	H	H	H	X	NOP	NOP
		L	H	H	L	BA	TBST	ILLEGAL*2
		L	H	L	X	BA, CA, A10	READ /	ILLEGAL*2
							WRITE
		L	L	H	H	BA, RA	ACT	ILLEGAL*2
		L	L	H	L	BA, A10	PRE /	ILLEGAL*2
							PREA
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add
REFRESHING		H	X	X	X	X	DESEL	NOP (Idle after tRC)
		L	H	H	H	X	NOP	NOP (Idle after tRC)
		L	H	H	L	BA	TBST	ILLEGAL
		L	H	L	X	BA, CA, A10	READ /	ILLEGAL
							WRITE
		L	L	H	H	BA, RA	ACT	ILLEGAL
		L	L	H	L	BA, A10	PRE /	ILLEGAL
							PREA
		L	L	L	H	X	REFA	ILLEGAL
		L	L	L	L	Op-Code,	MRS	ILLEGAL
						Mode-Add

MITSUBISHI ELECTRIC

12

128M Synchronous DRAM

SDRAM (Rev. 1.0E)

M2V28S20TP-6,-7,-8

(4-BANK x 8,388,608-WORD x

4-BIT)

Jun. '99

M2V28S30TP-6,-7,-7L,-8,-8L

(4-BANK x 4,194,304-WORD x

8-BIT)

MITSUBISHI LSIs

M2V28S40TP-7,-7L,-8,-8L

(4-BANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH TABLE (continued)

Current State

/CS

/RAS

/CAS

/WE

Address

Command

Action

MODE

H

X

X

X

X

DESEL

NOP (Idle after tRSC)

REGISTER

SETTING

L

H

H

H

X

NOP

NOP (Idle after tRSC)

L

H

H

L

BA

TBST

ILLEGAL

L

H

L

X

BA, CA, A10

READ /

ILLEGAL

WRITE

L

L

H

H

BA, RA

ACT

ILLEGAL

L

L

H

L

BA, A10

PRE /

ILLEGAL

PREA

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code,

MRS

ILLEGAL

Mode-Add

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration

NOTES:

1.All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

2.ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.

3.Must satisfy bus contention, bus turn around, write recovery requirements.

4.NOP to bank precharging or in idle state. May precharge bank indicated by BA.

5.ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

MITSUBISHI ELECTRIC

13

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

FUNCTION TRUTH TABLE for CKE

	Current State	CKE	CKE	/CS	/RAS	/CAS	/WE	Add	Action
		n-1	n
	SELF-	H	X	X	X	X	X	X	INVALID
	REFRESH*1	L	H	H	X	X	X	X	Exit Self-Refresh (Idle after tRC)
		L	H	L	H	H	H	X	Exit Self-Refresh (Idle after tRC)
		L	H	L	H	H	L	X	ILLEGAL
		L	H	L	H	L	X	X	ILLEGAL
		L	H	L	L	X	X	X	ILLEGAL
		L	L	X	X	X	X	X	NOP (Maintain Self-Refresh)
	POWER	H	X	X	X	X	X	X	INVALID
	DOWN	L	H	X	X	X	X	X	Exit Power Down to Idle
		L	L	X	X	X	X	X	NOP (Maintain Power Down)
	ALL BANKS	H	H	X	X	X	X	X	Refer to Function Truth Table
	IDLE*2	H	L	L	L	L	H	X	Enter Self-Refresh
		H	L	H	X	X	X	X	Enter Power Down
		H	L	L	H	H	H	X	Enter Power Down
		H	L	L	H	H	L	X	ILLEGAL
		H	L	L	H	L	X	X	ILLEGAL
		H	L	L	L	X	X	X	ILLEGAL
		L	X	X	X	X	X	X	Refer to Current State =Power Down
	ANY STATE	H	H	X	X	X	X	X	Refer to Function Truth Table
	other than	H	L	X	X	X	X	X	Begin CLK Suspend at Next Cycle*3
	listed above
		L	H	X	X	X	X	X	Exit CLK Suspend at Next Cycle*3
		L	L	X	X	X	X	X	Maintain CLK Suspend
	ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

NOTES:

1.CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.

2.Power-Down and Self-Refresh can be entered only from the All Banks Idle State.

3.Must be legal command.

MITSUBISHI ELECTRIC

14

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

	SIMPLIFIED STATE DIAGRAM
							SELF
							REFRESH
					REFS
						REFSX
		MODE	MRS		REFA		AUTO
		REGISTER
				IDLE			REFRESH
		SET
						CKEL
		CLK			CKEH
		SUSPEND
				ACT			POWER
				CKEL			DOWN
			CKEH
				ROW
				ACTIVE
			WRITE			READ
		CKEL		WRITEA	READA		CKEL
	WRITE				READ			READ
		WRITE					READ
	SUSPEND			WRITE				SUSPEND
		CKEH					CKEH
		WRITEA					READA
			WRITEA		READA
	WRITEA	CKEL					CKEL	READA
		WRITEA		PRE		READA
	SUSPEND							SUSPEND
		CKEH					CKEH
				PRE	PRE
	POWER
	APPLIED	POWER	PRE	PRE
		ON		CHARGE
								Automatic Sequence
								Command Sequence

MITSUBISHI ELECTRIC

15

128M Synchronous DRAM

	SDRAM (Rev. 1.0E)	M2V28S20TP-6,-7,-8	(4-BANK x 8,388,608-WORD x	4-BIT)
	Jun. '99
		M2V28S30TP-6,-7,-7L,-8,-8L	(4-BANK x 4,194,304-WORD x	8-BIT)
	MITSUBISHI LSIs M2V28S40TP-7,-7L,-8,-8L		(4-BANK x 2,097,152-WORD x 16-BIT)

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.

1.Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.

2.Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.

3.Issue precharge commands for all banks. (PRE or PREA)

4.After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.

5.Issue a mode register set command to initialize the mode register.

After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.

CLK /CS /RAS /CAS /WE

BA0,1 A11-A0

BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

V

0	0	0	0	0	0	0	LTMODE	BT	BL

					BL	BT= 0		BT= 1
					0 0 0	1		1
					0 0 1	2		2
	CL	/CAS LATENCY		BURST	0 1 0	4		4
	0 0 0	R			0 1 1	8		8
				LENGTH
	0 0 1	R			1 0 0	R		R
LATENCY	0 1 0	2			1 0 1	R		R
	0 1 1	3			1 1 0	R		R
MODE
	1 0 0	R			1 1 1	FP		R
	1 0 1	R
	1 1 0	R		BURST	0	SEQUENTIAL
	1 1 1	R		TYPE	1	INTERLEAVED

R: Reserved for Future Use

MITSUBISHI ELECTRIC

16