SDRAM (Rev. 1.0E) |
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128M Synchronous DRAM |
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M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
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Nov. '99 |
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
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PRELIMINARY |
Some of contents are described for general products and are |
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subject to change without notice. |
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DESCRIPTION
M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20ATP,M2V28S30ATP,M2V28S40ATP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems.
FEATURES
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M2V28S20/30/40ATP |
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ITEM |
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-6 |
-7 |
-8 |
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tCLK |
Clock Cycle Time |
(Min.) |
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7.5ns |
10ns |
10ns |
tRAS |
Active to Precharge Command Period |
(Min.) |
45ns |
50ns |
50ns |
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tRCD |
Row to Column Delay |
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(Min.) |
20ns |
20ns |
20ns |
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tAC |
Access Time from CLK |
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(Max.) (CL=3) |
5.4ns |
6ns |
6ns |
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tRC |
Ref/Active Command Period |
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(Min.) |
67.5ns |
70ns |
70ns |
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Operation Current |
(Max.) |
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V28S20 |
100mA |
95mA |
95mA |
Icc1 |
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V28S30 |
110mA |
100mA |
100mA |
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V28S40 |
130mA |
120mA |
120mA |
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Icc6 |
Self Refresh Current |
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(Max.) |
2mA |
2mA |
2mA |
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
-Fully synchronous operation referenced to clock rising edge
-4-bank operation controlled by BA0,BA1(Bank Address)
-/CAS latency- 2/3 (programmable)
-Burst length- 1/2/4/8/FP (programmable)
-Burst typeSequential and interleave burst (programmable)
-Byte ControlDQML and DQMU (M2V28S40ATP)
-Random column access
-Auto precharge / All bank precharge controlled by A10
-Auto and self refresh
-4096 refresh cycles /64ms
-LVTTL Interface
-Package
M2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC |
1 |
SDRAM (Rev. 1.0E) |
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128M Synchronous DRAM |
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M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
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Nov. '99 |
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M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
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(4-BANK x 4,194,304-WORD x |
8-BIT) |
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MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
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PIN CONFIGURATION (TOP VIEW) |
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M2V28S20ATP |
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M2V28S30ATP |
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M2V28S40ATP |
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PIN CONFIGURATION |
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(TOP VIEW) |
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Vdd |
Vdd |
Vdd |
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1 |
54 |
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Vss |
Vss |
Vss |
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NC |
DQ0 |
DQ0 |
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2 |
53 |
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DQ15 |
DQ7 |
NC |
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VddQ |
VddQ |
VddQ |
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VssQ |
VssQ |
VssQ |
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3 |
52 |
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NC |
NC |
DQ1 |
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DQ14 |
NC |
NC |
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4 |
51 |
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DQ0 |
DQ1 |
DQ2 |
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DQ13 |
DQ6 |
DQ3 |
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5 |
50 |
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VssQ |
VssQ |
VssQ |
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VddQ |
VddQ |
VddQ |
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49 |
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NC |
NC |
DQ3 |
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DQ12 |
NC |
NC |
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7 |
48 |
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NC |
DQ2 |
DQ4 |
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DQ11 |
DQ5 |
NC |
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47 |
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VddQ |
VddQ |
VddQ |
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VssQ |
VssQ |
VssQ |
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46 |
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NC |
NC |
DQ5 |
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DQ10 |
NC |
NC |
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10 |
45 |
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DQ1 |
DQ3 |
DQ6 |
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DQ9 |
DQ4 |
DQ2 |
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44 |
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VssQ |
VssQ |
VssQ |
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VddQ |
VddQ |
VddQ |
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43 |
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NC |
NC |
DQ7 |
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DQ8 |
NC |
NC |
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42 |
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Vdd |
Vdd |
Vdd |
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Vss |
Vss |
Vss |
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41 |
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NC |
NC |
DQML |
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NC |
NC |
NC |
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15 |
40 |
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/WE |
/WE |
/WE |
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DQMU |
DQM |
DQM |
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16 |
39 |
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/CAS |
/CAS |
/CAS |
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CLK |
CLK |
CLK |
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38 |
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/RAS |
/RAS |
/RAS |
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CKE |
CKE |
CKE |
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37 |
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/CS |
/CS |
/CS |
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NC |
NC |
NC |
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36 |
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BA0(A13) |
BA0(A13) |
BA0(A13) |
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A11 |
A11 |
A11 |
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20 |
35 |
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BA1(A12) |
BA1(A12) |
BA1(A12) |
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A9 |
A9 |
A9 |
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34 |
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A10(AP) |
A10(AP) |
A10(AP) |
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A8 |
A8 |
A8 |
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33 |
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A0 |
A0 |
A0 |
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A7 |
A7 |
A7 |
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A1 |
A1 |
A1 |
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A6 |
A6 |
A6 |
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24 |
31 |
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A2 |
A2 |
A2 |
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A5 |
A5 |
A5 |
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25 |
30 |
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A3 |
A3 |
A3 |
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A4 |
A4 |
A4 |
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26 |
29 |
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Vdd |
Vdd |
Vdd |
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Vss |
Vss |
Vss |
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28 |
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CLK |
: Master Clock |
DQM |
: Output Disable/ Write Mask |
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CKE |
: Clock Enable |
A0-11 |
: Address Input |
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/CS |
: Chip Select |
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BA0,1 |
: Bank Address |
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/RAS |
: Row Address Strobe |
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Vdd |
: Power Supply |
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/CAS |
: Column Address Strobe |
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VddQ |
: Power Supply for Output |
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/WE |
: Write Enable |
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Vss |
: Ground |
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DQ0-15 |
: Data I/O |
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VssQ |
: Ground for Output |
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MITSUBISHI ELECTRIC |
2 |
SDRAM (Rev. 1.0E) |
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128M Synchronous DRAM |
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M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
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Nov. '99 |
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
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BLOCK DIAGRAM
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DQ0-7 |
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I/O Buffer |
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Memory Array |
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Memory Array |
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Memory Array |
Memory Array |
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4096 x1024 x8 |
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4096 x1024 x8 |
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4096 x1024 x8 |
4096 x1024 x8 |
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Cell Array |
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Cell Array |
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Cell Array |
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Cell Array |
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Bank #0 |
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Bank #1 |
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Bank #2 |
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Bank #3 |
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Mode |
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Register |
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Control Circuitry |
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Address Buffer |
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Control Signal Buffer |
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Clock Buffer |
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A0-11 |
BA0,1 |
CLK |
CKE |
/CS |
/RAS |
/CAS |
/WE |
DQM |
Note : This figure shows the M2V28S30ATP.
The M2V28S20ATP configration is 4096x2048x4 of cell array and DQ 0-3.
The M2V28S40ATP configration is 4096x512x16 of cell array and DQ 0-15.
Type Designation Code
M2 V 28 S 3 0 A TP -8
These rules are only applied to the Synchronous DRAM family.
Access Item |
-6 |
: 7.5ns (PC133/3-3-3), |
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-7 |
: 10ns(PC100/2-2-2), |
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-8 |
: 10ns(PC100/3-2-2) |
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Package Type |
TP : TSOP(II) |
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Process Generation |
A : 2nd. gen. |
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Function |
0 |
: Random Column |
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Organization |
2: x4, |
3: x8, |
4: x16 |
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Synchronous DRAM |
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Density |
28 : 128Mbit |
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Interface |
V : LVTTL |
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Mitsubishi DRAM |
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MITSUBISHI ELECTRIC |
3 |
SDRAM (Rev. 1.0E) |
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128M Synchronous DRAM |
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M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
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Nov. '99 |
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
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MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
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PIN FUNCTION |
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CLK |
Input |
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Master Clock: |
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All other inputs are referenced to the rising edge of CLK. |
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Clock Enable: |
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CKE controls internal clock. When CKE is low, internal clock for the |
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CKE |
Input |
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following cycle is ceased. CKE is also used to select auto / |
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selfrefresh. After self refresh mode is started, CKE becomes |
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synchronous input. Self refresh is maintained as long as CKE is low. |
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/CS |
Input |
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Chip Select: |
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When /CS is high, any command means No Operation. |
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/RAS, /CAS, /WE |
Input |
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Combination of /RAS, /CAS, /WE defines basic commands. |
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A0-11 specify the Row / Column Address in conjunction with BA0,1. |
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The Row Address is specified by A0-11. The Column Address is |
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A0-11 |
Input |
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specified by A0-9,11 (x4) / A0-9 (x8) / A0-8 (x16). |
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A10 is also used to indicate precharge option. When A10 is high at a |
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read / write command, an auto precharge is performed. When A10 is |
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high at a precharge command, all banks are precharged. |
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Bank Address: |
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BA0,1 |
Input |
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BA0,1 specifies one of four banks to which a command is applied. |
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BA0,1 must be set with ACT, PRE, READ, WRITE commands. |
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DQ0-7 |
Input / Output |
Data In and Data out are referenced to the rising edge of CLK. |
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Din Mask / Output Disable: |
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DQM |
Input |
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When DQM is high in burst write, Din for the current cycle is masked. |
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When DQM is high in burst read, Dout is disabled at the next but one |
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cycle. |
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Vdd, Vss |
Power Supply |
Power Supply for the memory array and peripheral circuitry. |
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VddQ, VssQ |
Power Supply |
VddQ and VssQ are supplied to the Output Buffers only. |
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MITSUBISHI ELECTRIC |
4 |
SDRAM (Rev. 1.0E) |
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128M Synchronous DRAM |
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M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
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Nov. '99 |
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
BASIC FUNCTIONS
The M2V28S30ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively.
To know the detailed definition of commands, please see the command truth table.
CLK
/CS |
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Chip Select : L=select, H=deselect |
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/RAS |
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Command |
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/CAS |
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Command |
define basic commands |
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/WE |
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Command |
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CKE |
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Refresh Option @ refresh command |
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A10 |
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Precharge Option @ precharge or read/write command |
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Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, all banks are deactivated (precharge all,
PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC |
5 |
SDRAM (Rev. 1.0E) |
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128M Synchronous DRAM |
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M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
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Nov. '99 |
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
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MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
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COMMAND TRUTH TABLE |
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COMMAND |
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MNEMONIC |
CKE |
CKE |
/CS |
/RAS |
/CAS |
/WE |
BA0,1 |
A11 |
A10 |
A0-9 |
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n-1 |
n |
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|
|
Deselect |
|
DESEL |
H |
X |
H |
X |
|
X |
X |
X |
X |
X |
X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
No Operation |
|
NOP |
H |
X |
L |
H |
|
H |
H |
X |
X |
X |
X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Row Address Entry & |
|
ACT |
H |
X |
L |
L |
|
H |
H |
V |
V |
V |
V |
|
Bank Activate |
|
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Single Bank Precharge |
|
PRE |
H |
X |
L |
L |
|
H |
L |
V |
X |
L |
X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Precharge All Banks |
|
PREA |
H |
X |
L |
L |
|
H |
L |
X |
X |
H |
X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Column Address Entry |
|
WRITE |
H |
X |
L |
H |
|
L |
L |
V |
V |
L |
V |
|
& Write |
|
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Column Address Entry & |
|
WRITEA |
H |
X |
L |
H |
|
L |
L |
V |
V |
H |
V |
|
Write with Auto-Precharge |
|
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Column Address Entry |
|
READ |
H |
X |
L |
H |
|
L |
H |
V |
V |
L |
V |
|
& Read |
|
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Column Address Entry & |
|
READA |
H |
X |
L |
H |
|
L |
H |
V |
V |
H |
V |
|
Read with Auto-Precharge |
|
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Auto-Refresh |
|
REFA |
H |
H |
L |
L |
|
L |
H |
X |
X |
X |
X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Self-Refresh Entry |
|
REFS |
H |
L |
L |
L |
|
L |
H |
X |
X |
X |
X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
X |
|
X |
X |
X |
X |
X |
X |
|
Self-Refresh Exit |
|
REFSX |
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
H |
|
H |
H |
X |
X |
X |
X |
|
|||
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Mode Register Set |
|
MRS |
H |
X |
L |
L |
|
L |
L |
L |
L |
L |
V*1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number |
|
|
|
|
|
|
|
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC |
6 |
|
SDRAM (Rev. 1.0E) |
|
|
|
|
|
128M Synchronous DRAM |
|
|||
|
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
|
|||||||
|
Nov. '99 |
|
|
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
|
||||
|
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
FUNCTION TRUTH TABLE |
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Current State |
/CS |
/RAS |
/CAS |
/WE |
Address |
Command |
Action |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IDLE |
H |
X |
X |
X |
X |
DESEL |
NOP |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
BA |
TBST |
ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
X |
BA, CA, A10 |
READ / |
ILLEGAL*2 |
|
|
|
|
|
WRITE |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active, Latch RA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / |
NOP*4 |
|
|
|
|
|
PREA |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
X |
REFA |
Auto-Refresh*5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
Mode Register Set*5 |
|
|
|
|
|
Mode-Add |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
ROW ACTIVE |
H |
X |
X |
X |
X |
DESEL |
NOP |
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
BA |
TBST |
NOP |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
H |
BA, CA, A10 |
READ / |
Begin Read, Latch CA, Determine |
|
|
|
|
|
READA |
Auto-Precharge |
|
|
||||||
|
|
|
|
|
|
|
|
|
|||
|
|
L |
H |
L |
L |
BA, CA, A10 |
WRITE / |
Begin Write, Latch CA, Determine |
|
|
|
|
|
WRITEA |
Auto-Precharge |
|
|
||||||
|
|
|
|
|
|
|
|
|
|||
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active / ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / |
Precharge / Precharge All |
|
|
|
|
|
PREA |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
|
Mode-Add |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
MITSUBISHI ELECTRIC |
7 |
|
SDRAM (Rev. 1.0E) |
|
|
|
|
|
128M Synchronous DRAM |
|
|||
|
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
|
|||||||
|
Nov. '99 |
|
|
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
|
||||
|
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
FUNCTION TRUTH TABLE (continued) |
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Current State |
/CS |
/RAS |
/CAS |
/WE |
Address |
Command |
Action |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
READ |
H |
X |
X |
X |
X |
DESEL |
NOP (Continue Burst to END) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP (Continue Burst to END) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
BA |
TBST |
Terminate Burst |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
L |
H |
L |
H |
BA, CA, A10 |
READ |
Terminate Burst, Latch CA, Begin New |
|
||
|
|
/READA |
Read, Determine Auto-Precharge*3 |
|
|
||||||
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
L |
BA, CA, A10 |
WRITE / |
Terminate Burst, Latch CA, Begin |
|
|
|
|
|
WRITEA |
Write, Determine Auto-Precharge*3 |
|
|
||||||
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active / ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / |
Terminate Burst, Precharge |
|
|
|
|
|
PREA |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
|
Mode-Add |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
WRITE |
H |
X |
X |
X |
X |
DESEL |
NOP (Continue Burst to END) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP (Continue Burst to END) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
BA |
TBST |
Terminate Burst |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
H |
BA, CA, A10 |
READ / |
Terminate Burst, Latch CA, Begin |
|
|
|
|
|
READA |
Read, Determine Auto-Precharge*3 |
|
|
||||||
|
|
|
|
|
|
|
|
|
|||
|
|
L |
H |
L |
L |
BA, CA, A10 |
WRITE / |
Terminate Burst, Latch CA,Begin |
|
|
|
|
|
WRITEA |
Write, Determine Auto-Precharge*3 |
|
|
||||||
|
|
|
|
|
|
|
|
|
|||
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active / ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / |
Terminate Burst, Precharge |
|
|
|
|
|
PREA |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
|
Mode-Add |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
MITSUBISHI ELECTRIC |
8 |
|
SDRAM (Rev. 1.0E) |
|
|
|
|
|
128M Synchronous DRAM |
|
|||
|
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
|
|||||||
|
Nov. '99 |
|
|
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
|
||||
|
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
FUNCTION TRUTH TABLE (continued) |
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Current State |
/CS |
/RAS |
/CAS |
/WE |
Address |
Command |
Action |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
READ with |
H |
X |
X |
X |
X |
DESEL |
NOP (Continue Burst to END) |
|
|
|
|
AUTO |
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP (Continue Burst to END) |
|
|
||
|
PRECHARGE |
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
BA |
TBST |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
H |
BA, CA, A10 |
READ / |
ILLEGAL |
|
|
|
|
|
READA |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
L |
BA, CA, A10 |
WRITE / |
ILLEGAL |
|
|
|
|
|
WRITEA |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active / ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / |
ILLEGAL*2 |
|
|
|
|
|
PREA |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
|
Mode-Add |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
WRITE with |
H |
X |
X |
X |
X |
DESEL |
NOP (Continue Burst to END) |
|
|
|
|
AUTO |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PRECHARGE |
L |
H |
H |
H |
X |
NOP |
NOP (Continue Burst to END) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
BA |
TBST |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
H |
BA, CA, A10 |
READ / |
ILLEGAL |
|
|
|
|
|
READA |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
L |
BA, CA, A10 |
WRITE / |
ILLEGAL |
|
|
|
|
|
WRITEA |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
Bank Active / ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / |
ILLEGAL*2 |
|
|
|
|
|
PREA |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
|
Mode-Add |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
MITSUBISHI ELECTRIC |
9 |
|
SDRAM (Rev. 1.0E) |
|
|
|
|
|
128M Synchronous DRAM |
|
||||
|
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
|
||||||||
|
Nov. '99 |
|
|
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
|
|||||
|
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
FUNCTION TRUTH TABLE (continued) |
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Current State |
/CS |
/RAS |
/CAS |
/WE |
Address |
Command |
Action |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PRE - |
H |
X |
X |
X |
X |
DESEL |
NOP (Idle after tRP) |
|
|
||
|
CHARGING |
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP (Idle after tRP) |
|
|
||
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
BA |
TBST |
ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
X |
BA, CA, A10 |
READ / |
ILLEGAL*2 |
|
|
|
|
|
|
WRITE |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / |
NOP*4 (Idle after tRP) |
|
|
|
|
|
|
PREA |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
|
|
Mode-Add |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ROW |
H |
X |
X |
X |
X |
DESEL |
NOP (Row Active after tRCD) |
|
|
||
|
ACTIVATING |
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP (Row Active after tRCD) |
|
|
||||
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
BA |
TBST |
ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
X |
BA, CA, A10 |
READ / |
ILLEGAL*2 |
|
|
|
|
|
|
WRITE |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / |
ILLEGAL*2 |
|
|
|
|
|
|
PREA |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
|
|
Mode-Add |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MITSUBISHI ELECTRIC |
10 |
|
SDRAM (Rev. 1.0E) |
|
|
|
|
|
128M Synchronous DRAM |
|
||||
|
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
|
||||||||
|
Nov. '99 |
|
|
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
|
|||||
|
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
FUNCTION TRUTH TABLE (continued) |
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Current State |
/CS |
/RAS |
/CAS |
/WE |
Address |
Command |
Action |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
WRITE |
H |
X |
X |
X |
X |
DESEL |
NOP |
|
|
|
|
|
RECOVERING |
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP |
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
BA |
TBST |
ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
X |
BA, CA, A10 |
READ / |
ILLEGAL*2 |
|
|
|
|
|
|
WRITE |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
ILLEGAL*2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / |
ILLEGAL*2 |
|
|
|
|
|
|
PREA |
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
|
|
Mode-Add |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
REFRESHING |
H |
X |
X |
X |
X |
DESEL |
NOP (Idle after tRC) |
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
H |
X |
NOP |
NOP (Idle after tRC) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
BA |
TBST |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
X |
BA, CA, A10 |
READ / |
ILLEGAL |
|
|
|
|
|
|
WRITE |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
BA, RA |
ACT |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
BA, A10 |
PRE / |
ILLEGAL |
|
|
|
|
|
|
PREA |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
X |
REFA |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
|
|
Mode-Add |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MITSUBISHI ELECTRIC |
11 |
|
SDRAM (Rev. 1.0E) |
|
|
|
|
|
|
128M Synchronous DRAM |
|
|||
|
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
|
||||||||
|
Nov. '99 |
|
|
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
|
|||||
|
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
||
|
FUNCTION TRUTH TABLE (continued) |
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Current State |
/CS |
/RAS |
/CAS |
/WE |
|
Address |
Command |
Action |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MODE |
H |
X |
X |
X |
|
X |
DESEL |
NOP (Idle after tRSC) |
|
|
|
|
REGISTER |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SETTING |
L |
H |
H |
H |
|
X |
NOP |
NOP (Idle after tRSC) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
H |
L |
|
BA |
TBST |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
X |
|
BA, CA, A10 |
READ / |
ILLEGAL |
|
|
|
|
|
|
WRITE |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
H |
|
BA, RA |
ACT |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
H |
L |
|
BA, A10 |
PRE / |
ILLEGAL |
|
|
|
|
|
|
PREA |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
H |
|
X |
REFA |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
L |
L |
|
Op-Code, |
MRS |
ILLEGAL |
|
|
|
|
|
|
Mode-Add |
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ABBREVIATIONS: |
|
|
|
|
|
|
|
|
|
|
|
|
H=High Level, L=Low Level, X=Don't Care |
|
|
|
|
|
|
|||||
|
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration |
|
|
|
NOTES:
1.All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2.ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.
3.Must satisfy bus contention, bus turn around, write recovery requirements.
4.NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5.ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC |
12 |
SDRAM (Rev. 1.0E) |
|
|
|
|
|
|
|
|
|
128M Synchronous DRAM |
||||
|
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
|||||||||||
Nov. '99 |
|
|
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
|||||||||
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
FUNCTION TRUTH TABLE for CKE |
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Current State |
CKE |
CKE |
/CS |
/RAS |
/CAS |
|
/WE |
Add |
Action |
|
|
|
|
|
n-1 |
n |
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
SELF- |
H |
X |
|
X |
X |
X |
|
X |
X |
INVALID |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
REFRESH*1 |
L |
H |
|
H |
X |
X |
|
X |
X |
Exit Self-Refresh (Idle after tRC) |
|
|
|
|
|
L |
H |
|
L |
H |
H |
|
H |
X |
Exit Self-Refresh (Idle after tRC) |
|
|
|
|
|
L |
H |
|
L |
H |
H |
|
L |
X |
ILLEGAL |
|
|
|
|
|
L |
H |
|
L |
H |
L |
|
X |
X |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
|
L |
L |
X |
|
X |
X |
ILLEGAL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
L |
|
X |
X |
X |
|
X |
X |
NOP (Maintain Self-Refresh) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
POWER |
H |
X |
|
X |
X |
X |
|
X |
X |
INVALID |
|
|
|
|
DOWN |
L |
H |
|
X |
X |
X |
|
X |
X |
Exit Power Down to Idle |
|
|
|
|
|
|
|
|
|
|||||||||
|
|
L |
L |
|
X |
X |
X |
|
X |
X |
NOP (Maintain Power Down) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ALL BANKS |
H |
H |
|
X |
X |
X |
|
X |
X |
Refer to Function Truth Table |
|
|
|
|
IDLE*2 |
H |
L |
|
L |
L |
L |
|
H |
X |
Enter Self-Refresh |
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
L |
|
H |
X |
X |
|
X |
X |
Enter Power Down |
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H |
L |
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L |
H |
H |
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H |
X |
Enter Power Down |
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H |
L |
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L |
H |
H |
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L |
X |
ILLEGAL |
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H |
L |
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L |
H |
L |
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X |
X |
ILLEGAL |
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H |
L |
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L |
L |
X |
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X |
X |
ILLEGAL |
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L |
X |
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X |
X |
X |
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X |
X |
Refer to Current State =Power Down |
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ANY STATE |
H |
H |
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X |
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X |
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X |
X |
Refer to Function Truth Table |
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other than |
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H |
L |
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X |
X |
X |
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X |
X |
Begin CLK Suspend at Next Cycle*3 |
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listed above |
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L |
H |
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X |
X |
X |
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X |
X |
Exit CLK Suspend at Next Cycle*3 |
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L |
L |
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X |
X |
X |
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X |
X |
Maintain CLK Suspend |
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ABBREVIATIONS: |
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H=High Level, L=Low Level, X=Don't Care
NOTES:
1.CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.
2.Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3.Must be legal command.
MITSUBISHI ELECTRIC |
13 |
SDRAM (Rev. 1.0E) |
|
128M Synchronous DRAM |
|
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
|
Nov. '99 |
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
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SIMPLIFIED STATE DIAGRAM |
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SELF |
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REFRESH |
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REFS |
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REFSX |
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MODE |
MRS |
REFA |
AUTO |
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REGISTER |
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IDLE |
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REFRESH |
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SET |
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CKEL |
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CLK |
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CKEH |
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SUSPEND |
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ACT |
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POWER |
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CKEL |
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DOWN |
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CKEH |
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ROW |
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ACTIVE |
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WRITE |
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READ |
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CKEL |
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WRITEA |
READA |
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CKEL |
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WRITE |
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READ |
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READ |
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WRITE |
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READ |
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SUSPEND |
WRITE |
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SUSPEND |
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CKEH |
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CKEH |
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WRITEA |
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READA |
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WRITEA |
READA |
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WRITEA |
CKEL |
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CKEL |
READA |
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WRITEA |
PRE |
READA |
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SUSPEND |
SUSPEND |
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CKEH |
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CKEH |
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PRE |
PRE |
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POWER |
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APPLIED |
POWER |
PRE |
PRE |
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ON |
CHARGE |
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Automatic Sequence |
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Command Sequence |
MITSUBISHI ELECTRIC |
14 |
SDRAM (Rev. 1.0E) |
|
128M Synchronous DRAM |
|
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
|
Nov. '99 |
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
|
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POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.
1.Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.
2.Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.
3.Issue precharge commands for all banks. (PRE or PREA)
4.After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5.Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CLK /CS /RAS /CAS /WE
BA0,1 A11-A0
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
V
0 |
0 |
0 |
0 |
0 |
0 |
0 |
LTMODE |
BT |
BL |
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BL |
BT= 0 |
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BT= 1 |
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0 0 0 |
1 |
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1 |
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0 0 1 |
2 |
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2 |
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CL |
/CAS LATENCY |
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BURST |
0 1 0 |
4 |
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4 |
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0 0 0 |
R |
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0 1 1 |
8 |
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8 |
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LENGTH |
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0 0 1 |
R |
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1 0 0 |
R |
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R |
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LATENCY |
0 1 0 |
2 |
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1 0 1 |
R |
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R |
0 1 1 |
3 |
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1 1 0 |
R |
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R |
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MODE |
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1 0 0 |
R |
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1 1 1 |
FP |
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R |
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1 0 1 |
R |
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1 1 0 |
R |
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BURST |
0 |
SEQUENTIAL |
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1 1 1 |
R |
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TYPE |
1 |
INTERLEAVED |
R: Reserved for Future Use
MITSUBISHI ELECTRIC |
15 |
SDRAM (Rev. 1.0E) |
|
128M Synchronous DRAM |
|
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 8,388,608-WORD x |
4-BIT) |
|
Nov. '99 |
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 4,194,304-WORD x |
8-BIT) |
MITSUBISHI LSIs |
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L |
(4-BANK x 2,097,152-WORD x 16-BIT) |
|
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CLK
Command |
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Read |
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Write |
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Address |
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Y |
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Y |
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DQ |
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Q0 |
Q1 |
Q2 |
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Q3 |
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D0 |
D1 |
D2 |
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D3 |
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CL= 3 |
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/CAS Latency |
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Burst Length |
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Burst Length |
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BL= 4
Burst Type
Initial Address |
BL |
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Column Addressing |
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A2 |
A1 |
A0 |
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Sequential |
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Interleaved |
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0 |
0 |
0 |
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1 |
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7 |
0 |
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6 |
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0 |
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1 |
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0 |
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0 |
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6 |
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1 |
8 |
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0 |
1 |
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1 |
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4 |
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1 |
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1 |
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0 |
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- |
0 |
0 |
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4 |
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1 |
0 |
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1 |
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- |
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0 |
2 |
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1 |
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1 |
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- |
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1 |
1 |
0 |
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1 |
0 |
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MITSUBISHI ELECTRIC |
16 |