11. ELECTRICAL PARTS LIST.........................................................................................................49
Please use this service manual with referring to the user guide ( D.F.U. ) without fail.
R
SA-17S1
08AK855010 MIT
First Issue 2002.12
MARANTZ DESIGN AND SERVICE
Using superior design and selected high grade components,
Only original
MARANTZ
parts can insure that your
MARANTZ
MARANTZ
product will continue to perform to the specifi cations for which
company has created the ultimate in stereo sound.
it is famous.
Parts for your
MARANTZ
ORDERING PARTS :
equipment are generally available to our National Marantz Subsidiary or Agent.
Parts can be ordered either by mail or by Fax.. In both cases, the correct part number has to be specifi ed.
The following information must be supplied to eliminate delays in processing your order :
1. Complete address
2. Complete part numbers and quantities required
3. Description of parts
4. Model number for which part is required
5. Way of shipment
6. Signature : any order form or Fax. must be signed, otherwise such part order will be considered as null and void.
CAUTION : After servicing this appliance and prior to returning to customer, measure the resistance between either primary AC
cord connector pins ( with unit NOT connected to AC mains and its Power switch ON ), and the face or Front Panel of product
and controls and chassis bottom.
Any resistance measurement less than 1 Megohms should cause unit to be repaired or corrected before AC power is applied,
and verifi ed before it is return to the user/customer.
Ref. UL Standard No. 1492.
In case of diffi culties, do not hesitate to contact the Technical
Department at above mentioned address.
020816MIT
1. TECHNICAL SPECIFICATIONS
Super Audio CDCD
Audio Characteristics
Analog output
Channels6channels (Max.)2channels
Frequency range2Hz — 100kHz2Hz — 20kHz
Frequency characteristics2Hz — 50kHz (-3dB)2Hz — 20kHz
Dynamic range114dB100dB
THD (1kHz)0.0008%0.0020%
Wow & Flutter Precision of quartzPrecision of quartz
While pressing <OPEN/CLOSE>and<NEXT>plug in the Mains cord.
Press<
Press<
Press<
Press<
"SA-17S1" is displayed
>
Version of Backend(QF01) u-COM is displayed
"Ver : X.XX" is displayed
>
Version of Frontend(Q125) µ-COM is displayed
"DrvVer : XX.XX" is displayed
>
All parts of FTD is turned on
>
Each Segment is displayed one by one
Press<
Turn off Power to quit Service Mode.
2-2. Reset the unit to the default settings
While pressing <OPEN/CLOSE>and<NEXT>plug in the Mains cord.
Press <PHANTOM-C>
All the setting are restored to the default setting.
When key is depressed,key name is displayed
>
Check of key
"SA-17S1" is displayed
"EEPROM Clear" is displayed
2
3. TAKING THE DISC OUT OF EMERGENCY
1. Remove 8 screws on the top cover and remove the top cover.
2. Remove 6 screws on the side panel and remove the side panel.
3. Remove Power SW. Link.
4. Remove 4 screws pointed with the arrows.
5. Disconnect all the wires at the right.
6. Remove the Mecha. component.
7. Turn the gear to the direction shown with your fi nger and disc tray will opened.
3
4. CAUTION Optical pick up and Servo Board
When removing the fl at wire between Optical pick up and Servo Board (PV16),
Solder the four lands pointed by arrows to short the circuit.
Otherwise the LASER DIODE may be damaged by static electricity.
62 ASYEIAsymmetry circuit on/off (low = off, high = on).
63 MD2IDigital Out on/off control (low = off, high = on).
64 DOUTO1, 0Digital Out output.
65 LRCKO1, 0D/A interface. LR clock output. f = Fs
66 PCMDO1, 0D/A interface. Serial data output (two's complement, MSB fi rst).
67 BCKO1, 0D/A interface. Bit clock output. Outputs a high signal when the playback disc has emphasis, and a low
68 EMPHO1, 0Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis.
69 XTSLICrystal selection input. Low when the crystal is 16.9344MHz; high when it is 33.8688MHz.
70 DVSS2——Digital GND.
71 XTAIICrystal oscillation circuit input. When the master clock is input externally,
input it from this pin.
72 XTAOOCrystal oscillation circuit output.
73 SOUTO1, 0Serial data output in servo block.
74 SOCKO1, 0Serial data readout clock output in servo block.
75 XOLTO1, 0Serial data latch output in servo block.
76 SQSOO1, 0Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output.
77 SQCKISQSO readout clock input.
78 SCSYIGRSCOR resynchronization input.
79 SBSOO1, 0Sub-Q P to W serial output.
80 EXCKISBSO readout clock input.
Notes)
PCMD is a MSB fi rst, two’s complement output.
XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection.
XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point
coincide.
The GFS signal goes high when the frame sync and the insertion protection timing match.
C2PO represents the data error status.
2827
Q116 : CXD3068Q
XTAI
XTSL
XTAO
71 72
27
FSTO
C4M
RFAC
ASYI
ASYO
ASYE
BIAS
XPCK
FI LO
FI LI
PCO
CLTV
MDP
LOCK
PWMI
SENS
DATA
XLAT
CLOK
SCOR
SBSO
EXCK
SCSY
SQSO
SQCK
RFDC
IGEN
16
50
49
48
62
57
12
53
54
55
52
25
24
23
7
4
5
6
15
79
80
78
76
77
43
CE
42
TE
41
SE
40
FE
39
VC
38
46
Clock
Generator
Asymmetry
Corrector
Digital
PLL
Digital
CLV
CPU
Interface
OPAmp
Analog SW
V16M
6069
59
Converter
44
VPCO
A/D
DCK
FCK
W
EMPH
VCTL
58
GFS
XUGF
13
11
EFM
demodurator
Sub Code
Processor
Servo
Auto
Sequencer
68
10
SERVO
Interface
MIRR
DFCT
FOK
SERVO DSP
FOCUS SERVO
TRACKING
SERVO
SLED SERVO
Error
Corrector
32K
RAM
2PO
RCK
W
C
L
65 66
1417
D/A
Interface
Digital
Signal processor block
PWM GENERATOR
TRACKING PWM
CK
CMD
B
P
67
3
OUT
Servo block
FOCUS PWM
GENERAT OR
GENERAT OR
SLED PWM
GENERATOR
UTE
M
TES1
37
TEST
36
XRST
2
63
MD2
DOUT
64
73
SOUT
74
SOCK
XOLT
75
SCLK
8
COUT
19
SSTP
26
ATSK
9
MIRR
20
21
DFCT
22
FOK
33
FFDR
34
FRDR
TFDR
31
32
TRDR
29
SFDR
30
SRDR
ADIO
Q126 : TC74VHC157
InputsOutput
STB SEL A B
H X X X L
L L L X L
L L H X H
L H X L L
L H X H H
H : High
L : Low
X :
SEL
1A
1B
1Y
2A
2B
2Y
GND
V
1
2
3
4
5
6
7
AGS
B
A
YB
A
B
Y
A
YBY
8
16
15
14
13
12
11
10
CC
STB
4A
4B
4Y
3A
3B
9
3Y
29
Q101 : CXD1881R
Pin Description
Power Supply Pins
NameType Description
VPA—Power supply pin for the RF block and serial port
VPB— Power supply pin for the servo block
VNA—Ground pin for the RF block and serial port
VNB—Ground pin for the servo block
V33—Power supply pin for the output buffers
V25— Reference power supply for the servo output
Input Pins
NameType Description
DVDRFP, DVDRFNIRF SIGNAL INPUTS: Differential RF signal attenuator input pins.
RFSINIRF SIGNAL INPUT: Single-ended RF signal attenuator input pin.
AIP, AINIAGC AMPLIFIER INPUTS: Differential AGC amplifi er input pins.
DIP, DINIANALOG INPUTS FOR RF SINGLE BUFFER: Differential analog inputs to the RF single-end output buffer
and full wave rectifi er.
A, B, C, DIPHOTO DETECTOR INTERFACE INPUTS: Inputs from the main beam photo detector matrix outputs.
A2, B2, C2, D2IPHOTO DETECTOR INTERFACE INPUTS: AC coupled inputs for the DPD from the main beam photo
detector matrix outputs.
CD_A, B, C, DICD PHOTO DETECTOR INTERFACE INPUTS: CD_A, B, C, D come from the CD main beam photo detector
matrix outputs.
CD_E, FICD PHOTO DETECTOR INTERFACE INPUTS: CD side beam photo dector outputs and used for the CD
tracking detection.
MINIRF SIGNAL INPUT FOR MIRROR: AC coupled inputs for the mirror dection circuit from MEVO.
DVDPDIAPC INPUT: DVD APC input pin from the monitor photo diode.
CDPDIAPC INPUT: CD APC input pin from the monitor photo diode.
LDONIAPC OUTPUT ON/OFF: APC output control pin. A high level activates LD output. (open low)
LINKILINKING SIGNAL INPUT PIN: In the linking area, this pin goes high and the Mirror and TE outputs are
disabled, when the link signal is enabled. (open low)
Output Pins
NameType Description
ATOP, ATONODIFFERENTIAL ATTENUATOR OUTPUTS: Attenuator outputs.
FNP, FNNODIFFERENTIAL NORMAL OUTPUTS: Filter normal outputs.
RFACOSINGLE-ENDED NORMAL OUTPUT: Single-ended RF output.
RFDCORF SIGNAL OUTPUT: Single-ended RF summing output reference to VPB-2.4 (V).
FEOFOCUSING ERROR SIGNAL OUTPUT: Focus error output reference to V125.
TEOTRACKING ERROR SIGNAL OUTPUT: Tracking error output reference to V125.
CEOCENTER ERROR SIGNAL OUTPUT: Center error output reference to V125.
MEVOORFDDC BOTTOM ENVELOPE OUTPUT: Bottom envelope, PI or bottom clamped RF envelope signal output for
mirror detection.
DFTODEFECT OUTPUT: CMOS output (V33 or VPB). When the PI signal level is below the detection level or when
the RF signal level is below the detection level, the DFT output goes high. This output is selected by serial port.
MIRROMIRROR DETECT OUTPUT: Mirror detect comparator output. CMOS output (V33 or VPB).
PIOPULL-IN SIGNAL OUTPUT: The summing signal output of A, B, C, D, or CD_A, B, C, D. Reference to V25/3.
DVDLDOAPC OUTPUT: DVD APC output pin to control the laser power.
CDLDOAPC OUTPUT: CD APC output pin to control the laser power.
MNTROMONITOR OUTPUT: Monitor output signal is selected by PIOR bit7-5.
Serial Port Pins
NameType Description
SDENISERIAL DATA ENABLE: Serial enable CMOS input. A high level input enables the serial port. (not to be left open)
SDATAI/O SERIAL DATA: Serial data bidirectional CMOS pin(V33 or VPA). NRZ programming data for the internal registers is
applied to this input. (not to be left open)
SCLKISERIAL CLOCK: Serial clock CMOS input. The clock applied to this pin is synchronized with the data applied to SDATA.
(not to be left open)
30
Analog Pins
NameTypeDescription
BYP—The RF AGC integration capacitor CBYP, is connected between BYP and VPA.
CP—DIFFERENTIAL PHASE TRACKING LPF PIN: The external capacitance is connected between CN.
CN—DIFFERENTIAL PHASE TRACKING LPF PIN: The external capacitance is connected between CP.
LCP—LENS SHIFT OFFSET CANCEL LPF PIN: The external capacitance is connected between LCN.
LCN—LENS SHIFT OFFSET CANCEL LPF PIN: The external capacitance is connected between LCP.
MP—MIRR TOP HOLD PIN: The external capacitance is connected to VPB.
MB—MIRR BOTTOM HOLD PIN: The external capacitance is connected to VPB.
MEV—RFDC BOTTOM ENVELOPE PIN: The external capacitance is connected to VPA.
MLPF—MIRROR LPF PIN: An external capacitance is connected to VPB.
TPH—PI TOP HOLD PIN: An external capacitance is connected to VPB.
VC—REFERENCE VOLTAGE OUTPUT: This pin provides the DC bias reference voltage (VPB/2). Output impedance is less
than 50 Ω.
V125—REFERENCE VOLTAGE OUTPUT: DC bias voltage output and it is also used for servo output reference. (V25/2)
RX—REFERENCE RESISTOR INPUT: An external 12.0 k&, 1 % resistor is connected from this pin to ground to establish a
precise PTAT (proportional to absolute temperature) reference current for the fi lter.
Q101 : CXD1881R
1
DVDRFP
DVDRFN
RFS I N
CD_A
CD_B 15
CD_C 14
CD_D 13
CD_E
CD_ F 17
DVDPD
CDPD
A2
B2
C2
D2
A
B 11
C
D
2
63
12
16
10
9
18
3
4
5
6
23
24
MUX
INPUT
SEL
MUX
CD/DVD
12dB is added
@ h i g h g a i n mo d e
From S-port
LD H/ L
2
INPUT IMP
SEL
A
B
C
D
12dB is added
@ high gain mode
6dB is added
@ high gain mode
GCA
GCA
3
S-PORT
GCA
EQ
GCA
EQ
GCA
EQ
GCA
EQ
3
FROM
S-PORT
APC SEL
DVD/ CD
Dua l APC
26
LDON
62 61 60 59
ATT
4
ATT
W/LPF
GCA
W/LPF
GCA
W/LPF
GCA
W/LPF
GCA
12dB is added
@ high ga i n mode
GCA
GCA
GCA
GCA
3
S-PORT
FROM
VC
3
22
CDLD
FNP
ATOP
ATON
AIN
AIP
AGC
INPUT
BIAS
2
INPUT IMP
SEL
SSOUT
SIGDET
B+D
SUM
Amp .
A+C
A+D
B+C
FROM
4dB
GCASEL
4
FROM
S-PORT
Comp .
PHASE
DETECTOR
PHASE
DETECTOR
Sink current
From S-port
2
BOTTOM
ENVELOPE
50
MEV
Pl l
MUX
32
MEVO
AGCO
21
DVDLD
Clamp
& Env
2
TOPHOLD
TOPHOLD
+3dB
Input lmp
From S-port
2
INPUT
BUFF
31
MIN
PROGRAMMABLE
DIFFERENTIATOR
Leve l
DAC
4dB
GCA
Mi r r ga in
From S-port
2
53 52
EQUAL I ZER
FILTER
FROM
4
S-PORT
70kHz
LPF
6dB
Amp
CE - ATT
CEPOL
Disk det &
Mi r r LPF
From S-por t
30
MLPF
FNN
DIN
DIP
55 5457
FULL WAVE
RECT I F I ER
OUTPUT INHIBIT
FROM S-PORT
AGCO
70kHz6dB, 4b i t
LPFGCA
FROM
5
S-PORT
Of f set
cansel
BCA DET
FROM
S-PORT
- 6dB @ n o r ma l
Buf f
Of f set
cansel
4
FROM
S-PORT
LPF
3
ATT
Po l se l .
buf f(-12dB)
SUBMUX
LPFGCA
CEFDBCD/ DVDCP / CN
Low lmp
CONTROL
Signals
To each block
Comp
hys & off set
From S-por t
MIRR
COMP
PEAK /
BOTTOM
HOLD
28
MB29MP
Internal
FDCHG
LINKEN
FROM
S-PORT
5
Of f set
cansel
TOPHLD
DAC
2
GCA
6dB, 4b i t
PI
FE
TE
CE
V25
V125
V25 / 3
Of f set
cansel
6
FROM
S-PORT
for servo output ref.
VCI fo rservo input
LINK
RFAC
AGC HOL D
FAST A t t a c k o f f
AGC
CHARGE
PUMP
COMP
MNTR
Cn t r l
HLDEN
3
FROM
S-PORT
VC=VP B / 2
SERI A L PORT
REGI STER
27
58
VPA
MIRR
SEL
TE
RST
V25 /2
V33 f or
out pu t buf f
19
VPB
VNA51VNB
56
BYP
49
RX
40
FE
Pl l
38
PI
35
TPH
34
DFT
61
RFDC
41
CE
42
MNTR
44
LCP
43
LCN
7
CP
8
CN
39
TE
37
V25
36
V125
20
VC
48
SDEN
47
SDATA
46
SCLK
45
V33
2533
31
Q123 : CXD2752R
Pin SymbolI/O Description No.
1 VSC— Core GND.
2 XMSLATILatch input for microcomputer serial communication. The address and data are atched at the fall of this pin.
3 MSCKIShift clock input for microcomputer serial communication. The serial input data is loaded and shifted at the rise
of the clock input to this pin. During readout, the readout data changes at the fall of the clock input to this pin.
4 MSDATIIData input for microcomputer serial communication. The data and address are serially input from the
microcomputer.
5 VDC— Core power supply. Supply +2.5V.
6 MSDATOO Data output for microcomputer serial communication. Hi-Z other than during output.
7 MSREADYO Output ready fl ag for microcomputer serial communication. Low output when ready. Open drain.
8 XMSDOEO Output enable for microcomputer serial communication. When an external tri-state buffer is used, the buffer is
activated by this pin. Low during MSDATO output.
9 XRSTIReset. The entire IC is reset when low. However, the clock output from the EXCKO1, EXCKO2 and LRCK output
pins does not stop even when reset.
10 SMUTEI Soft mute. Audio output is soft muted when high; mute off when low.
11 MCKIIMaster clock input. Input a 768Fs (33.8688MHz) clock.
12 VSIO— I/O GND.
13 EXCKO1O External output clock 1. 768Fs/512Fs/256Fs/128Fs is output according to the setting.
14 EXCKO2O External output clock 2. 768Fs/512Fs/256Fs/128Fs is output according to the setting.
15 LRCKO 1Fs (44.1kHz) clock output.
16 FRAMEO Frame signal output.
17 VDIO— I/O power supply. Supply +3.3V.
18 MNT0O Monitor output. Outputs a part of internal operation according to the microcomputer setting.
19 MNT1O Monitor output. Outputs a part of internal operation according to the microcomputer setting.
20 MNT2O Monitor output. Outputs a part of internal operation according to the microcomputer setting.
21 MNT3O Monitor output. Outputs a part of internal operation according to the microcomputer setting.
22 TESTOO Test output. Leave open.
23 TESTOO Test output. Leave open.
24 TESTOO Test output. Leave open.
25 TESTOO Test output. Leave open.
26 TCKITest clock input. Fix to low.
27 TDIIpu Test input (pulled up). Leave open.
28 VSC— Core GND.
29 TDOO Test output. Leave open.
30 TMSIpu Test input (pulled up). Leave open.
31 TRSTIpu Test reset (pulled up). Input the power-on reset signal or fi x to low.
32 TEST1I Test input. Fix to low.
33 TEST2ITest input. Fix to low.
34 TEST3ITest input. Fix to low.
35 VDC— Core power supply. Supply +2.5V.
36 TESTOO Test output. Leave open.
37 XBITO DST related monitor. No connected. For detailed information, see the DST_X_Bit item in Part 3 of the SACD
Format Book.
38 SUPDT0O Supplementary data output. (LSB)
39 SUPDT1O Supplementary data output.
40 SUPDT2O Supplementary data output.
41 SUPDT3O Supplementary data output.
42 VSIO— I/O GND.
43 SUPDT4O Supplementary data output.
44 SUPDT5O Supplementary data output.
45 VDIO— I/O power supply. Supply +3.3V.
46 SUPDT6O Supplementary data output.
47 SUPDT7O Supplementary data output. (MSB)
48 XSUPAKO Supplementary data acknowledge output.
49 VSC— Core GND.
50 TESTOO Test output. Leave open.
51 TESTIITest input. Fix to low.
52 TESTIITest input. Fix to low.
53 TESTOO Test output. Leave open.
54 VDC— Core power supply. Supply +2.5V.
55 TESTOO Test output. Leave open.
56 TESTOO Test output. Leave open.
57 BCKASLI Bit clock input/output selection for DSD data output. Low = input (slave), high = output (master).
58 VSDSD— DSD data output GND.
59 BCKAII Bit clock input for DSD data output. Input the bit clock to this pin when BCKASL = low.
60 BCKAOO Bit clock output for DSD data output. The bit clock is output from this pin when BCKASL = high.
32
61 PHREFIIPhase reference signal input for DSD output phase modulation.
62 PHREFOO Phase reference signal output for DSD output phase modulation.
63 ZDFLO Lch zero data detection fl ag (when set by the microcomputer). Goes high when silent data continues for 300ms.
64 DSALO Lch DSD data output.
65 ZDFRO Rch zero data detection fl ag (when set by the microcomputer). Goes high when silent data continues for 300ms.
66 DSARO Rch DSD data output.
67 VDDSD— Power supply for DSD data output. Supply +3.3V separated from other digital power supplies.
68 ZDFCO Cch zero data detection fl ag (when set by the microcomputer). Goes high when silent data continues for 300ms.
69 DSACO Cch DSD data output.
70 ZDFLFEO LFEch zero data detection fl ag (when set by the microcomputer). Goes high when silent data continues for
300ms.
71 DSALFEO LFEch DSD data output.
72 VSDSD— GND for DSD data output.
73 ZDFLSO LSch zero data detection fl ag (when set by the microcomputer). Goes high when silent data continues for
300ms.
74 DSALSO LSch DSD data output.
75 ZDFRSO RSch zero data detection fl ag (when set by the microcomputer). Goes high when silent data continues for
300ms.
76 DSARSO RSch DSD data output.
77 VDDSD— Power supply for DSD data output. Supply +3.3V separated from other digital power supplies.
78 TESTOO Test output. Leave open.
79 TESTOO Test output. Leave open.
80 VSC— Core GND.
81 TESTOO Test output. Leave open.
82 TESTOO Test output. Leave open.
83 VDC— Core power supply. Supply +2.5V.
84 TESTOO Test output. Leave open.
85 TESTOO Test output. Leave open.
86 VSIO— I/O GND.
87 TESTOO Test output. Leave open.
88 TESTIITest input. Fix to low.
89 TESTIITest input. Fix to low.
90 VDIO— I/O power supply. Supply +3.3V.
91 TESTOO Test output. Leave open.
92 TESTOO Test output. Leave open.
93 TESTOO Test output. Leave open.
94 VSC— Core GND.
95 TESTIITest input. Fix to high.
96 TESTIITest input. Fix to low.
97 TESTIIpu Test input. Fix to high.
98 TESTOO Test output. Leave open.
99 VDC— Core power supply. Supply +2.5V.
100 TESTIITest input. Fix to low.
101 TESTIITest input. Fix to low.
102 TESTIITest input. Fix to low.
103 TESTIITest input. Fix to low.
104 TESTIITest input. Fix to low.
105 TESTIITest input. Fix to low.
106 VSIO— I/O GND.
107 TESTIITest input. Fix to low.
108 TESTIITest input. Fix to low.
109 TESTIITest input. Fix to low.
110 VDIO— /O power supply. Supply +3.3V.
111 WAD0IExternal A/D data input for PSP physical disc mark detection. (LSB) This is used only when not using the
internal A/D converter and connecting an external A/D converter.
112 WAD1IExternal A/D data input for PSP physical disc mark detection.
113 WAD2IExternal A/D data input for PSP physical disc mark detection.
114 WAD3IExternal A/D data input for PSP physical disc mark detection.
115 VSIO— I/O GND.
116 VSC— Core GND.
117 WAD4IExternal A/D data input for PSP physical disc mark detection.
118 WAD5IExternal A/D data input for PSP physical disc mark detection.
119 WAD6IExternal A/D data input for PSP physical disc mark detection.
120 WAD7IExternal A/D data input for PSP physical disc mark detection. (MSB)
121 VDC— Core power supply. Supply +2.5V.
122 TESTIITest input. Fix to low.
123 WCKIOperating clock for PSP physical disc mark detection. Input the PLL clock corresponding to 1T of RF.
124 WAVDD— A/D power supply for PSP physical disc mark detection. Input +2.5V separated from the digital block.
125 WAVDD— A/D power supply for PSP physical disc mark detection. Input +2.5V separatedfrom the digital block.
33
Q123 : CXD2752R
126 WARFIAi Analog RF signal input for PSP physical disc mark detection. The full scale is 0.0 to 2.5V. (typ.)
127 WAVRBAi A/D bottom reference for PSP physical disc mark detection. The voltage input to this pin is set to bottom level of
the A/D converter.
128 WAVSS— A/D GND for PSP physical disc mark detection.
129 WAVSS— A/D GND for PSP physical disc mark detection.
130 VSIO— I/O GND.
131 DQ7I/O SDRAM data I/O. (MSB)
132 DQ6I/O SDRAM data I/O.
133 DQ5I/O SDRAM data I/O.
134 DQ4I/O SDRAM data I/O.
135 VDIO— I/O power supply. Supply +3.3V.
136 DQ3I/O SDRAM data I/O.
137 DQ2I/O SDRAM data I/O.
138 DQ1I/O SDRAM data I/O.
139 DQ0I/O SDRAM data I/O. (LSB)
140 VSIO— I/O GND.
141 DCLKO SDRAM clock output.
142 DCKEO SDRAM clock enable output.
143 XWEO SDRAM write enable output. Connect to the XWE pin of the SDRAM.
144 XCASO SDRAM column address strobe output. Connect to the CAS pin of the SDRAM.
145 XRASO SDRAM row address strobe output. Connect to the RAS pin of the SDRAM.
146 VDIO— I/O power supply. Supply +3.3V.
147 TESTOO Test output. Leave open.
148 A11O SDRAM address output. (MSB)
149 A10O SDRAM address output.
150 VSC— Core GND.
151 A9O SDRAM address output.
152 A8O SDRAM address output.
153 VDC— Core power supply. Supply +2.5V.
154 A7O SDRAM address output.
155 A6O SDRAM address output.
156 A5O SDRAM address output.
157 A4O SDRAM address output.
158 VSIO— I/O GND.
159 A3O SDRAM address output.
160 A2O SDRAM address output.
161 A1O SDRAM address output.
162 A0O SDRAM address output. (LSB)
163 VDIO— I/O power supply. Supply +3.3V.
164 XSRQO Output for data request to front-end processor.
165 XSHDIInput for header fl ag output from front-end processor.
166 SDCKIInput for data transfer clock output from front-end processor.
167 XSAKIInput for data valid fl ag output from front-end processor.
168 SDEFIInput for error fl ag output from front-end processor.
169 SD0IInput for stream data from front-end processor. (LSB)
170 SD1IInput for stream data from front-end processor.
171 SD2IInput for stream data from front-end processor.
172 SD3IInput for stream data from front-end processor.
173 SD4IInput for stream data from front-end processor.
174 SD5IInput for stream data from front-end processor.
175 SD6IInput for stream data from front-end processor.
176 SD7IInput for stream data from front-end processor. (MSB)
Ipu: pulled-up input, Ipd: pulled-down input, Ai: analog input
34
Q123 : CXD2752R
WARF I
WAD[7:0]
WCK
DQ[ 7 : 0 ]
A[11:0]
DCLK
DCKE
XWE
XCAS
XRAS
SD[7:0]
XSHD
XSAK
SDEF
XSRQ
A/D
PSP Data Detection
DST Decoder
Stream Manager
Microcomputer InterfaceC l oc k
Fader
Audio Interface
Supplementary
Data Interface
DSARS
DSA LS
DSA LFE
DSAC
DSAR
DSA L
PHREFO
PHREF I
BCKAO
BCKA I
ZDF
XSUPAK
SUPDT [7 : 0 ]
MSCK
XMSLAT
MSDATI
MSDATO
MSREADY
MCK I
XMSDOE
EXCKO1
LRCK
FRAME
EXCKO2
SMUTE
35
Q124 : CXD1882R
Pin Description
The pin descriptions by function are given below.
1. Read Channel Block (22 pins)
1-1. PLL (8 pins)
(1) PDHVCC (VC input for PD Hi-Z output)
Midpoint potential input for RFPLL. If the HPDVC bit (bit 6) of
the RFPLL1 register (E0h) is set to “1”, the voltage input to
this pin is output from the PDO pin when the PDO pin output is
other than VCC or GND. This pin sharpens the PDO pin output
waveform in order to reduce phase deviation.
(2) PDO (phase detector output: output)
Phase comparator charge pump output.
(3) FDO (frequency detector output: output)
Frequency comparator charge pump output.
(4) LPF1 (PLL LPF1: input)
Inverted input of the operational amplifi er of the PLL loop fi lter.
(5) LPF2 (PLL LPF2: input)
When the LPFTGN bit (bit 0) of the LOOPFCTL register (EAh)
is set to “1”, this pin is connected to the inverted input of the
operational amplifi er of the PLL loop fi lter. It is used to switch
the PLL loop gain.
(6) LPF5 (PLL LPF5: output)
Output of the operational amplifi er of the PLL loop fi lter.
(7) VCOIN (VCO input: input)
VCO input. When using the built-in operational amplifi er, the
output of the second operational amplifi er of the loop fi lter is
connected to this pin.
(8) VCOR1 (VCO resistor: input)
Connects the VCO oscillation range setting resistor. The
setting resistor is connected between his pin and GND. When
R2 is increased, the minimum oscillation frequency is reduced.
1-2: RF binary setting (6 pins)
(1) RFDCC (RF DC cut control: input)
Input for adjusting the RF signal DC cut HPF. A resistor is
connected between this pin and the midpoint potential in order
to raise the HPF cut-off frequency in areas other than the
DRAM address outputs. When connected to a 4M-bit DRAM,
the MA[11:9] pins can be used as monitor pins.
(6) MDB[F:0] (DRAM data bus: input/output)
DRAM data bus.
4. Sub CPU Interface (22 pins)
(1) XWR (sub CPU write: input)
Strobe negative logic input signal for writing internal registers.
(2) XRD (sub CPU read: input)
Strobe negative logic input signal for reading internal register
status.
(3) D[7:0] (sub CPU data bus: input/output)
8-bit data bus.
(4) A[7:0] (sub CPU address: input)
Address input signals for selecting internal registers from the
sub CPU.
(5) XINT0, 1 (sub CPU interrupt: output)
Interrupt request negative logic output signals for the sub CPU.
Interrupt requests from the decoder block and authentication
block are output from the XINT0 pin. Interrupt requests from
the read channel block are output from the XINT1 pin. These
are open drain outputs.
(6) XCS (chip select: input)
Chip select negative logic signal from the sub CPU.
(7) XWAT (wait: output)
Negative logic output wait signal used by the sub CPU to
access the buffer memory.
36
5. Host Interface (31 pins)
Pin symbols are listed in the order of ATAPI mode, DMA mode
and AV mode. Pull up means that the pin should be pulled up by a
resistor, “0” means low level output, and nc means No Connect.
(1) HCS0 (HOST chip select: input)/nc/nc
This pin is pulled up by a resistor.
ATAPI: Chip select negative logic input signal from the host.
This is connected with the CS1FX pin of the ATAPI interface.
DMA/AV: This pin is not used.
(2) HCS1 (HOST chip select: input)/nc/nc
This pin is pulled up by a resistor.
ATAPI: Chip select negative logic input signal from the host.
This is connected with the CS3FX pin of the ATAPI interface.
DMA/AV: This pin is not used.
(3) HA[2:0] (HOST address: input)/pull up/pull up
ATAPI: Address input signal for selecting internal registers from
the host.
DMA/AV: This pin is not used, and should be pulled up by a
resistor.
ATAPI: Strobe negative logic input signal for reading data from
the host.
DMA: Strobe negative logic input signal for reading data to the
host.
AV: Negative logic output signal indicating the lead byte of the
sector.
ATAPI: Strobe negative logic input signal for writing data from
the host.
DMA: Strobe negative logic output signal for writing data to the
host.
AV: Clock output for data transfer.
This pin is pulled up by a resistor.
ATAPI: DMA acknowledge negative logic input signal from the
host.
DMA: DMA request input signal from the host.
AV: Data transfer request input signal.
(7) DASP (drive active/slave present: input/output)/pull up/pull up
ATAPI: Negative logic signal indicating that a slave drive is
present or a drive is active; open drain signal.
DMA/AV: This pin is not used, and should be pulled up by a
resistor.
(8) HDB[F:0] (HOST data bus: input/output)/HDB[F:0] (HOST data
bus: input/output)/7 “0”, XVFLAG,
DATA[7:0] (“0”, video error fl ag, data: output)
ATAPI/DMA: 16-bit host data bus.
AV: Low level is output from the upper 7 bits. The 8th bit from
the upper side is an error fl ag output signal corresponding to
the lower 8 bits. The lower 8 bits are video data output signals.
ATAPI: DMA data request positive logic output signal to the
host; tri-state signal.
DMA: DMA acknowledge negative logic output signal to the
host.
AV: Data transfer acknowledge negative logic output signal.
(10) HINT (HOST interrupt: output)/pull up/pull up
ATAPI: Interrupt request positive logic output signal to the host;
tri-state signal.
DMA/AV: This pin is not used, and should be pulled up by a
resistor.
(11) XS16 (16-bit data transfer: output)/pull up/pull up
ATAPI: Negative logic signal indicating that a 16-bit data port
has been selected; open drain
signal. This is connected with the IOCS16 pin of the ATAPI
interface.
DMA/AV: This pin is not used, and should be pulled up by a
resistor.
(12) REDY (I/O channel ready: output)/pull up/pull up
ATAPI: Positive logic signal which is negated when a drive is
not ready to respond to a data transfer request; open drain
signal. This is connected with the IORDY pin of the ATAPI
interface.
DMA/AV: This pin is not used, and should be pulled up by a
resistor.
(13) XPDI (passed diagnostics: input/output)/pull up/pull up
ATAPI: Negative logic signal indicating that diagnostics of the
slave drive have been completed; open drain signal. This is
connected with the PDIAG pin of the ATAPI interface.
DMA/AV: This pin is not used, and should be pulled up by a
resistor.
(14) XHRS (HOST reset: input)/nc/nc
ATAPI: Reset negative logic signal from the host; pulled up by
a resistor.
DMA/AV: This pin is not used
37
Q124 : CXD1882R
RFDCC
RFI N
PDO
PDHVCC
FDO
LPF1
LPF2
VC1
LPF5
VCOR1
VCOI N
MDPOUT
MDSOUT
CLVS
MDIN1
MDIN2
SPO
VC2
GFS
APEO
GSCOR
MDAT
BCL K
LRCK
C2PO
WFCK
SCOR
SBIN
EXCK
XRCI
DDAT
DLRC
DBCK
111 113 114 115
116
117
130
131
132
127
126
125
124
120
121
144
142
140
Spindle
138
Control
137
135
136
107
109
146
160
158
163
CD-
155
DSP
151
150
148
147
153
159
DAC
162
157
ASF1
DASYO
RF
Asymmet r y
PLL
VCO
I/F
I/F
DMA
FIFO
ATAP I
Registers
ATAP I
Pac k e t
FIFO
MDB[F:0]
HOST
I/F
ATAP I
or
DMA
or
Vi deo
Internal Cl ock
16171819 20 21
23
XHRS
57
XPD I
51
REDY
55
XS1 6
54
HINT
46
HDRQ
24, 26, 27,
29 to 32, 34,
35, 37,
39 to 41,
43 to 45
DASP
65
XHAC
53
56, 59, 60
48
49
63
62
164
169
170
HA[2:0]
XHWR
XHRD
HCS1
HCS0
XRST
XTL 2
XTL 1
HDB [ F : 0
MA[8:0]
ASF2
XMWR
DASY I
XCAS
767891 92 939495
(Priority resolve & Sequencer)
DVD
Main Data
ECC & EDC
SYNC Det e c t
EFM
Demodulator
Sec to r ID
Det ec t
CD-ROM
Main Data
ECC & EDC
Descramble
Deinterleave & ECC
SYNC Control
CD E SP
Aut hen t i c at i on
167
XRAS
XMOE
DMA Con t r o l l e r
+
Subcode
MA9 /mn t 0
MA10 /mn t 1
MA11 /mn t 2
79 , 80 ,
82 to 87, 89
66 to 69, 71, 73 to 75, 96, 97,
99, 101, 102, 104 to 106
CPU I /F, DMA Contro ller
5, 7, 9 to 141, 2, 4, 172 to 176
XRD
XTAL
XWR
D[7:0]
A[7:0]
XCS
XINT1
XINT0
XWA I T
38
Q125 : GXPQ7100(MASK)
Pin No. Pin NameI/O Description
1 FTMUTO Actuator driver mute signal for foc/track
2 SLMUTO Actuator driver mute signal for spin/sledg
3 AMUTOMuting on/off "L" : muting on for CXD3068Q
4 SMUTOMuting on/off signal output to the DSD decoder "H" : muting on
5 XRSTOSystem reset signal output (L= reset)
6 CD/XDVDO CD/DVD(SACD) mode selection signal output (L=CD, H=SACD)
7 LOCK IGFS is sampled by 460 Hz "H" input when GFS is. "H"
8 MBHLD-NC
9 AMPSDTI/O Serial data transfer DATA signal input,output
10 AMPSCKOSerial data transfer clock signal output
11 AMPSENOSerial data transfer enable signal (H=enable)
12 XDECSELO OPU block on/off for modulation circuit (L=on)
13 VSSO Ground terminal (digital system)
14 D0I/O Two-way data bus
15 D1I/O Two-way data bus
16 D2I/O Two-way data bus
17 D3I/O Two-way data bus
18 D4I/O Two-way data bus
19 D5I/O Two-way data bus
20 D6I/O Two-way data bus
21 D7I/O Two-way data bus
22 XDECINT0IInterrupt signal input from CXD1881R
23 XDECINT1IInterrupt signal input from CXD1881R
24 TZCITrack signal, OPU in case by traversal the disc track line
25 PE3-NC
26 PE3-NC
27 SEEKODisplay data ready signal output to the feature MPU ("H" : read)
28 REQSTOReqest signal CXD1882R
29 NC-Not used (open)
30 DECMNT1IRF signal monitor input from CXD1882R
31 FOKIFocus on signal
32 GFSDECIGuard frame sync signal input
33 DRVRXDIInput signal data from the feature MPU
34 DRVTXDOOutput signal data for the featur MPU
35 DRVCLKIInput signal clock from the featur MPU
36 XDRVRDYOOutput data signal readey for the featur MPU
37 DRVIRQOIutput data signal readey from the featur MPU
38 XRESETIPower on reset signal input (L=reset)
39 VSSGround terminal (digital system)
40 XTALISystem clock input terminal (20 MHz)
41 EXTALO System clock output terminal (20 MHz)
42 VDDPower supply terminal (+3.3V) (digital system)
43 DSPXLATO Serial data latch pulse signal output to the CXD3068Q
44 XMSLATO Serial data latch pulse signal output to the CXD2752R
45 MSCKO Serial data transfer clock signal output to CXD2752R
46 MSDTOOSerial data output to the DSD CXD2752R
47 MSDTIISerial data input from the CXD2752R
48 MSREADYIReady signal input from the CXD2752R "L" : ready
49 DSPDTOO Serial data output to the CXD3068Q
50 DSPSCKOSerial data clock input from the CXD3068Q
51 SENSIInternal status (SENSE) signal input from CXD3068Q
52 SQSOISubcode Q data input
53 SNSCKOSerial status data clock output to the CXD3068Q
54 SQCKOSubcode Q data reading clock signal output
55 VSSGround terminal (digital system)
56 JITINIJitter signal input terminal
57 AMPMNTIMonitor signal from the CXD1881R
58 -ATTI-12dB atteneation request signal input "L" : attenation on
59 P17-NC
60 PJ0-NC
61 SCSYO GRSCOR data sync request signal for CXD3068Q
62 GFSDSPIFrequency generator signal input
63 C2POIC2 pointer signal input from the CXD3068Q
64 MIRRIMirror signal input from CXD3068Q
65 DECMNT2IMonitor signal from the CXD1882R
39
Q125 : GXPQ7100(MASK)
66 FJUP_DO Focus jump DOWN signal output
67 FJUP_UO Focus jump UP signal output
68 AVSS0Ground terminal (for A/D converter)
69 AVREFIReference voltage input terminal (for A/D converter)
70 AVDDIpower supply terminal (+3.3V) (for A/D converter)
71 XFCMP_LILayer swicthing monitor signal at the down from refrenc level
72 XFCMP_HILayer swicthing monitor signal at the up from refrenc level
73 XLIMISledge position dedector sw (L=inner)
74 XTCLSITray loading inner switch input from the toray loader (L=inner)
75 XTOPNITray loading inner switch input from the toray loader (L=open)
76 EDCERR-Not used (open)
77 BUEEMPIMPR2="L", input case of install data for the MPU(FLASH ROM version)
78 EPDA-Not used (open)
79 EPCL -Not used (open)
80 PCRXDIInstall data input for MPU chip (internal FLASH ROM TYPE)
81 PCTXDO Install data output for MPU chip (internal FLASH ROM TYPE)
82 FSJPOStart of Layer chenge signal
83 SYNCERRIMPR3="H", input case of install data for the MPU (FLASH ROM version)
84 XDECWROwrite strobe signal output for CXD1882R
85 XDECRDORead strobe signal output for CXD1882R
86 MPR1IMPR1="H", input case of install data for the MPU (FLASH ROM version)
87 VDDPower supply terminal (+3.3V) (digital system)
88 VSSGround termina1(digital system)
89 A0O Address signal output
90 A1O Address signal output
91 A2O Address signal output
92 A3O Address signal output
93 A4O Address signal output
94 A5O Address signal output
95 A6O Address signal output
96 A7O Address signal output
97 XMODEONOCD/DVD(SACD) RF-bypass/DFT selection signal output (H=CD, L=SACD)
98 LDONO Laser diode on/off control signal output "L" : laser diode off, "H" : laser diode on
99 EJECT-O Tray loader pull-in signal
100 EJECT+OTray loader push-out signal
QD41/QD61/QD71 : CS4397
SCLK
LRCK
SDATA
MCLK
CLOCK
DIVIDER
M4
(AD0/CS)
M3M2
(AD1/CDIN) (SCL/CCLK)
SERIAL INTERFACE
AND FORMAT SELECT
INTERPOLATION
FILTER
INTERPOLATION
FILTER
HARDWARE MODE CONTROL
(CONTROL PORT)
M1
M0
(SDA/CDOUT)
SOFT MUTE
MULTI-BIT
∆Σ
MODULATOR
MULTI-BIT
∆Σ
MODULATOR
RESET MUTEC MUTE
DYNAMIC
ELEME NT
MATCHING
LOGIC
DYNAMIC
ELEME NT
MATCHING
LOGIC
DE-EMPHASIS
FILTER
SWITCHED
CAPACITOR-DAC
AND FILTER
SWITCHED
CAPACITOR-DAC
AND FILTER
VOLTAGE REFERENCE
VREFCMOUTFILT-
FILT+
AOUTL+
AOUTL-
AOUTR+
AOUTR-
40
QD41/QD61/QD71 : CS4397
Reset - RST
Pin 1, Input
Function:
The device enters a low power mode and all internal state
machines registers are reset when low. When
high, the device will be in a normal operation mode .
RST DESCRIPTION
0Enabled
1Normal operation mode
Digital Ground - DGND
Pins 6 and 9, Inputs
Function:
Digital ground reference.
Digital Power - VD
Pins 7 and 8, Input
Function:
Digital power supply. Typically 5.0 to 3.0 VDC.
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 256x, 384x, 512x or
768x the input sample rate in Single
Speed Mode; either 128x, 192x 256x or 384x the input sample
rate in Double Speed Mode; or 64x, 96x
128x or 192x the input sample rate in Quad Speed Mode. Tables
Table 6. Quad Speed (100 to 200 kHz sample rates) Common Clock
Frequencies
Serial Clock - SCLK
Pin 11, Input
Function:
Clocks individual bits of serial data into the SDATA pin. The
required relationship between the Left/Right
clock, serial clock and serial data is defi ned by either the Mode
Control Byte in Control Port Mode or the
M0 - M4 pins in Hardware Mode. The options are detailed in
Figures 29-33
Left/Right Clock - LRCK
Pin 12, Input
Function:
The Left/Right clock determines which channel is currently being
input on the serial audio data input,
SDATA. The frequency of the Left/Right clock must be at the input
sample rate. Audio samples in
Left/Right sample pairs will be simultaneously output from the
digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference. The
required relationship between the
Left/Right clock, serial clock and serial data is defi ned by the
Mode Control Byte and the options are de-
tailed in Figures 29-33
Serial Audio Data - SDATA
Pin 13, Input
Function:
Serial audio data is input on this pin. The selection of the Digital
Interface Format is determined by set-
tings of the Mode select as detailed in Figures 29-33. The data is
clocked into SDATA via the serial clock
and the channel is determined by the Left/Right clock. The
required relationship between the Left/Right
clock, serial clock and serial data is defi ned by the Mode Control
Byte and the options are detailed inin
Figures 29-33
Soft Mute - MUTE
Pin 15, Input
Function:
The analog outputs will ramp to a muted state when enabled. The
ramp requires 1152 left/right clock cy-
cles in Single Speed, 2304 cycles in Double Speed and 4608
cycles in Quad Speed mode. The bias volt-
age on the outputs will be retained and MUTEC will go active at
the completion of the ramp period.
The analog outputs will ramp to a normal state when this function
transitions from the enabled to disabled
state. The ramp requires 1152 left/right clock cycles in Single
Speed, 2304 cycles in Double Speed and
4608 cycles in Quad Speed mode. The MUTEC will release
immediately on setting MUTE = 1.
The converter analog outputs will mute when enabled. The bias
voltage on the outputs will be retained
and MUTEC will go active during the mute period.
MuteDESCRIPTION
0Enabled
1Normal operation mode
Control Port / Hardware Mode Select - C/H
Pin 16, Input
Function:
Determines if the device will operate in either the Hardware Mode
or Control Port Mode.
C/H DESCRIPTION
0Hardware Mode Enabled
1Control Port Mode Enabled
Mute Control - MUTEC
Pin 17, Output
Function:
The Mute Control pin goes low during power-up initialization,
reset, muting, master clock to left/right clock
frequency ratio is incorrect or power-down. This pin is intended to
be used as a control for an external mute
circuit to prevent the clicks and pops that can occur in any single
supply system. Use of Mute Control is not
mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops.
41
QD41/QD61/QD71 : CS4397
Analog Ground - AGND
Pins 18 and 21, Inputs
Function:
Analog ground reference.
Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- ,
AOUTL+
Pins 19, 20, 23 and 24, Outputs
Function:
The full scale differential analog output level is specifi ed in the
Analog Characteristics specifi cations table.
Analog Power - VA
Pin 22, Input
Function:
Power for the analog and reference circuits. Typically 5VDC.
Common Mode Voltage - CMOUT
Pin 25, Output Function:
Filter connection for internal bias voltage, typically 50% of VREF.
Capacitors must be connected from CMOUT to analog ground,
as shown in Figure 6. CMOUT has a typical source impedence
of 25 kΩ and any current drawn from this pin will alter device
performance
Reference Ground - FILT-
Pin 26, Input Function:
Ground reference for the internal sampling circuits. Must be
connected to analog ground.
required relationship between the Left/Right clock, serial clock
and serial data as detailed in Figures 29-33 Selection of the
standard 15 µs/50 µs digital de-emphasis fi lter response, Figure
28, which requires re-confi guration of the digital fi lter to maintain
the proper fi lter response for 32, 44.1 or 48 kHz sample rates.
Selection of the appropriate clocking mode to match the input
sample rates. Access to the Direct Stream Digital Mode Access
to the 8x Interpolation Input Mode
CONTROL PORT MODE
Address Bit 0 / Chip Select - AD0 / CS
Pin 2, Input Function:
2
C mode, AD0 is a chip address bit. CS is used to enable the
In I
control port interface in SPI mode. The device will enter the SPI
mode at anytime a high to low transition is detected on this pin.
Once the device has entered the SPI mode, it will remain until
either the part is reset or undergoes a power-down cycle.
Address Bit 1 / Control Data Input - AD1/CDIN
Pin 3, Input Function:
In I2C mode, AD1 is a chip address bit. CDIN is the control data
input line for the control port interface in SPI mode.
Serial Control Interface Clock - SCL/CCLK
Pin 4, Input Function:
In I2C mode, SCL clocks the serial control data into or from
SDA/CDOUT.
In SPI mode, CCLK clocks the serial data into AD1/CDIN and out
of SDA/CDOUT.
Reference Filter - FILT+
Pin 27, Output Function:
Positive reference for internal sampling circuits. External
capacitors are required from FILT+ to analog ground, as shown in
Figure 6. FILT+ is not intended to supply external current.
Voltage Reference Input- VREF
Pin 28, Input Function:
Analog voltage reference. Typically 5VDC.
HARDWARE MODE
Mode Select - M0, M1, M2, M3, M4
Pins 2, 3, 4, 5 and 14, Inputs Function:
The Mode Select pins determine the operational mode of the
device as detailed in Tables 9-14. The op-tions include;
Selection of the Digital Interface Format which determines the
Serial Control Data I/O - SDA/CDOUT
Pin 5, Input/Output Function:
In I2C mode, SDA is a data input/output. CDOUT is the control
data output for the control port interface in SPI mode.
M1 - Mode Select
Pin 14, Input Function:
This pin is not used in Control Port Mode and must be terminated
to ground.
42
QF01 : MB90F553A
Pin PortSignalI/O Function DescriptionActive
1 P20/A16M41ODAC select Front L/RActive H
2 P21/A17M42ODAC select Surround L/RActive H
3 P22/A18M43ODAC select center,LFEActive H
4 P23/A19
5 P24/A20MUTE1OMUTE Front L/RActive H
6 P25/A21MUTE2OMUTE Surr.L/R, Center, LFEActive H
7 P26/A22
8 P27/A23
9 P30/ALE
10 P31/RD
11 VssVssGND
12 P32/WRL
13 P33/WRH
14 P34/WRQ
15 P35/HAK
16 P36/RDYFCENODisplay driver selectAdrs= L : inst=H
17 P37/CLKFRESODisplay driver resetActive L
18 P40/SCKFCLKODisplay driver clockActive L
19 P41/SOTFDATODisplay driver dataPulse
20 P42/SIN
21 P43/SCK1DRVCLKOFront end clockActive L
22 P44/SOT1DRVRXOFront end data output
23 VccVDD5V
24 P45/SIN1DRVTXIFront end data input
25 P46/ADTGCDRSTODAC resetActive L
26 P47/SCK0CDCLKODAC clockActive L
27 CCap.0.1µF
28 P50/SDA0/SOT0CDINODAC data outputPulse
29 P51/SCL0/SIN0CDOUTIDAC data inputPulse
30 P52/SDA1
31 P53/SCL1
32 P54/SDA2
33 P55/SCL2
34 AvccAVDD5V
35 AVRHAVRef5V
36 AVRLGNDGND
37 AvssAGNDGND
38 P60/AN0ADkey0IKey input A/D
39 P61/AN1ADkey1IKey input A/D
40 P62/AN2ADkey2IKey input A/D
41 P63/AN3ADkey3IKey input A/D
42 VssVssGND
43 P64/AN4EEDATOEEROM data
44 P65/AN5EECLKOEEROM clock
45 P66/AN6
46 P67/AN7
47 P70/IRQ0
48 P71/IRQ1
49 MD0MODE1IMode selectNormal H
50 MD1MODE2Mode selectNormal H
Pin PortSignalI/O Function DescriptionActive
51 MD2MODE3Mode selectNorma L
52 HSTHWSTBYHardware standbyNormal H
53 P72/IRQ2SEEKISearch signalPLAY=L : SEEK or STOP=H
54 P73/IRQ3STBSWIStandby on/off key inputActive H
55 P74/IRQ4IRIStandby on/off remote inputActive H
56 P75/IRQ5DRV RESOFront end resetActive L
57 P76/IRQ6DRV RDYIFront end readyActive L
58 P77/IRQ7DRV RQIFront end requestactive L
59 P80/TIN0
60 P81/TIN1
61 P82/TOT0
62 P83/TOT1
63 P84/IN0RC-5RC-5 inputActive L
64 P85/IN1
65 P86/IN2
66 P86/IN3
67 P90/OUT0CDI/O LED CDActive L (Setup of in putfor SA17-S1)
68 P91/OUT12chI/O LED 2chActive L (Setup of in putfor SA17-S1)
69 P92/PPG0MultiPTMONOO LED Multi(SA8260)PTMON(SA-17S1)Active L(LED Multi) : Active H(PTMON)
70 P93/PPG1STBYI/O LED standbyActive L (LED output) : H=LED input
S.MODE/TIME/PHAN-C
024B 08AK270110 BUTTON FOR POWER SWITCH
025B 284T154240 KNOB FOR PHONES VOLUME
08AK270110
284T154240
001D 411K257110 TOP LID GOLD
005D 323S010020 SCREW FOR TOP LID GOLD
006D 269J249110 SIDE PANEL GOLD
010D 323S010020 SCREW FOR SIDE PANEL GOLD
004G 291K057010 LEG GOLD BLAST
012G 08AK121010 LINK FOR POWER SWITCHE
001M 01AK304010 MECHA LOADER ASSY
002M 01AK130030 DUMPER FRONT
003M 01AK130040 DUMPER REAR
004M 01AK010010 SCREW DUMPER + LOADER
005M 01AK063120 ESCUTCHEON FOR CD TRAY
2) On the occasion, be confirmed the common parts on
the parts list.
3) Refer to “Common Parts List” for the other common
parts (RI05, DD4, DK4).
➆
{
One-way type, Mylar ±10% 50V
Capacity value
NOTE ON SAFETY :
SymbolFire or electrical shock hazard. Only original
parts should be used to replaced any part marked with
symbol . Any other component substitution (other
than original type), may increase risk of fire or electrical
shock hazard.
010728MIT
49
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
PA16-POWER AUDIO
CIRCUIT BOARD
PA16-CAPACITORS
C401 /F/L/S FILM 1800pF TP 100V PP APSV OF15182540
C401 /N OF55182550 FILM 1800pF 100V OF55182550
C402 /F/L/S FILM 330pF TP 100V PP APSV OF15331540
C402 /N OF55331550 FILM 330pF 100V OF55331550
C404 /F/L/S FILM 120pF J 100V APSV OF151215 40
C404 /N OF55121550 FILM 120pF 100V OF 5512 1550
C405 nsp ELECT. 470µF M 16V ARA OA47701650
C406 nsp ELECT. 470µF M 16V ARA OA47701650
C409 /F/L/S FILM 1200pF TP 100V PP APSV OF15122540
C409 /N OF55122550 FILM 1200pF 100V OF55122550
C410 /F/L/S FILM 560pF TP 100V PP APSV OF15561540
C410 /N OF55561550 FILM 560pF 100V OF55561550
C412 /F/L/S FILM 680pF 100V DTG OF5 5681570
C412 /N OF55681550 FILM 680pF 100V OF55681550
C413 nsp ELECT. 470µF M 16V ARA OA47701650
C414 nsp ELECT. 470µF M 16V ARA OA47701650
C416 nsp ELECT. 100µF 25V ARS OA10702540
C451 /F/L/S FILM 1800pF TP 100V PP APSV OF15182540
C451 /N OF55182550 FILM 1800pF 100V OF55182550
C452 /F/L/S FILM 330pF TP 100V PP APSV OF15331540
C452 /N OF55331550 FILM 330pF 100V OF55331550
C454 /F/L/S FILM 120pF J 100V APSV OF151215 40
C454 /N OF55121550 FILM 120pF 100V OF 5512 1550
C459 /F/L/S FILM 1200pF TP 100V PP APSV OF15122540
C459 /N OF55122550 FILM 1200pF 100V OF55122550
C460 /F/L/S FILM 560pF TP 100V PP APSV OF15561540
C460 /N OF55561550 FILM 560pF 100V OF55561550
C462 /F/L/S FILM 680pF 100V DTG OF5 5681570
C462 /N OF55681550 FILM 680pF 100V OF55681550
C466 nsp ELECT. 100µF 25V ARS OA10702540
C601 /F/L/S FILM 1800pF TP 100V PP APSV OF15182540
C601 /N OF55182550 FILM 1800pF 100V OF55182550
C602 /F/L/S FILM 330pF TP 100V PP APSV OF15331540
C602 /N OF55331550 FILM 330pF 100V OF55331550
C604 /F/L/S FILM 120pF J 100V APSV OF151215 40
C604 /N OF55121550 FILM 120pF 100V OF 5512 1550
C605 nsp ELECT. 470µF M 16V ARA OA47701650
C606 nsp ELECT. 470µF M 16V ARA OA47701650
C609 /F/L/S FILM 1200pF TP 100V PP APSV OF15122540
C609 /N OF55122550 FILM 1200pF 100V OF55122550
C610 /F/L/S FILM 560pF TP 100V PP APSV OF15561540
C610 /N OF55561550 FILM 560pF 100V OF55561550
C612 /F/L/S FILM 680pF 100V DTG OF5 5681570
C612 /N OF55681550 FILM 680pF 100V OF55681550
C613 nsp ELECT. 470µF M 16V ARA OA47701650
C614 nsp ELECT. 470µF M 16V ARA OA47701650
C616 nsp ELECT. 100µF 25V ARS OA10702540
C651 /F/L/S FILM 1800pF TP 100V PP APSV OF15182540
C651 /N OF55182550 FILM 1800pF 100V OF55182550
C652 /F/L/S FILM 330pF TP 100V PP APSV OF15331540
C652 /N OF55331550 FILM 330pF 100V OF55331550
C654 /F/L/S FILM 120pF J 100V APSV OF151215 40
C654 /N OF55121550 FILM 120pF 100V OF 5512 1550
C659 /F/L/S FILM 1200pF TP 100V PP APSV OF15122540
C659 /N OF55122550 FILM 1200pF 100V OF55122550
C660 /F/L/S FILM 560pF TP 100V PP APSV OF15561540
C660 /N OF55561550 FILM 560pF 100V OF55561550
C662 /F/L/S FILM 680pF 100V DTG OF5 5681570
C662 /N OF55681550 FILM 680pF 100V OF55681550
C666 nsp ELECT. 100µF 25V ARS OA10702540
C701 /F/L/S FILM 1800pF TP 100V PP APSV OF15182540
C701 /N OF55182550 FILM 1800pF 100V OF55182550
C702 /F/L/S FILM 330pF TP 100V PP APSV OF15331540
C702 /N OF55331550 FILM 330pF 100V OF55331550
C704 /F/L/S FILM 120pF J 100V APSV OF151215 40
C704 /N OF55121550 FILM 120pF 100V OF55121550
C705 nsp ELECT. 470µF M 16V ARA OA47701650
C706 nsp ELECT. 470µF M 16V ARA OA47701650
C709 /F/L/S FILM 1200pF TP 100V PP APSV OF1512254 0
C709 /N OF55122550 FILM 1200pF 100V OF55122550
C710 /F/L/S FILM 560pF TP 100V PP APSV OF15561540
C710 /N OF55561550 FILM 560pF 100V OF5 556155 0
C712 /F/L/S FILM 680pF 100V DTG OF5568157 0
C712 /N OF55681550 FILM 680pF 100V OF5 568155 0
C713 nsp ELECT. 470µF M 16V ARA OA47701650
C714 nsp ELECT. 470µF M 16V ARA OA47701650
C716 nsp ELECT. 100µF 25V ARS OA10702540
C751 /F/L/S FILM 1800pF TP 100V PP APSV OF1518254 0
C751 /N OF55182550 FILM 1800pF 100V OF55182550
C752 /F/L/S FILM 330pF TP 100V PP APSV OF15331540
C752 /N OF55331550 FILM 330pF 100V OF55331550
C754 /F/L/S FILM 120pF J 100V APSV OF 1512 1540
C754 /N OF55121550 FILM 120pF 100V OF55121550
C759 /F/L/S FILM 1200pF TP 100V PP APSV OF1512254 0
C759 /N OF55122550 FILM 1200pF 100V OF55122550
C760 /F/L/S FILM 560pF TP 100V PP APSV OF15561540
C760 /N OF55561550 FILM 560pF 100V OF5 556155 0
C762 /F/L/S FILM 680pF 100V DTG OF5568157 0
C762 /N OF55681550 FILM 680pF 100V OF5 568155 0
C766 nsp ELECT. 100µF 25V ARS OA10702540
C801 nsp ELECT. 6800µF 16V ±20% RA-2 OA68801620
C802 nsp ELECT. 3300µF M 6.3V RA-2 OA33800620
C805 nsp ELECT. 6800µF 16V OA68801620
C806 nsp ELECT. 3300µF M 6.3V RA-2 OA33800620
C809 nsp ELECT. 3300µF M 6.3V RA-2 OA33800620
C810 OC47701620 ELECT. 470µF 16V 10X12.5 ARE2 OC47701620
C822 nsp ELECT. 4700µF 25V RA-2 OA47802520
C823 nsp ELECT. 470µF 16V M RA-2 OA47701620
CD21 nsp ELECT. 10µF 63V RA-2 OA10606320
CD22 nsp ELECT. 100µF M 10V RA-2 OA10701020
CD25 nsp ELECT. 47µF M 25V RA-2 OA47602520
CD26 nsp ELECT. 220µF M 25V RA-2 OA22702520
CD41 nsp ELECT. 100µF M 16V RA-2 OA10701620
CD44 nsp ELECT. 100µF M 16V RA-2 OA10701620
CD45 nsp ELECT. 10µF 25V ARA OA10602550
CD47 nsp ELECT. 100µF 10V ARA OA10701050
CD61 nsp ELECT. 100µF M 16V RA-2 OA10701620
CD64 nsp ELECT. 100µF M 16V RA-2 OA10701620
CD65 nsp ELECT. 10µF 25V ARA OA10602550
CD67 nsp ELECT. 100µF 10V ARA OA10701050
CD71 nsp ELECT. 100µF M 16V RA-2 OA10701620
CD74 nsp ELECT. 100µF M 16V RA-2 OA10701620
CD75 nsp ELECT. 10µF 25V ARA OA10602550
CD77 nsp ELECT. 100µF 10V ARA OA10701050
CT05 nsp ELECT. 100µF 25V ARS OA10702540
D824 SHOTTKY 11EQS10 1A 100V
Q401 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q403 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q404 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q405 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q406 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q407 HF201701H0 F.E.T. 2SK170 V RANK HF201701H0
Q408 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q409 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q411 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q412 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q413 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q414 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q415 HF201701H0 F.E.T. 2SK170 V RANK HF201701H0
Q416 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q417 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q418 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q419 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q420
HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q423
Q424 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q451 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q453 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q454 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q455 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q456 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q457 HF201701H0 F.E.T. 2SK170 V RANK HF201701H0
Q458 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q459 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q461 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q462 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q463 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q464 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q465 HF201701H0 F.E.T. 2SK170 V RANK HF201701 H0
Q466 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q467 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q468 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q469 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q470
HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q473 Q474 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q601 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q603 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q604 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q605 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q606 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q607 HF201701H0 F.E.T. 2SK170 V RANK HF201701 H0
Q608 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q609 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q611 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q612 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q613 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q614 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q615 HF201701H0 F.E.T. 2SK170 V RANK HF201701 H0
Q616 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q617 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q618 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q619 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q620
HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q623 Q624 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q651 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q653 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q654 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q655 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q656 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q657 HF201701H0 F.E.T. 2SK170 V RANK HF201701 H0
Q658 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q659 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q661 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q662 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q663 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q664 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q665 HF201701H0 F.E.T. 2SK170 V RANK HF201701 H0
Q666 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q667 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q668 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q669 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q670
HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q673 Q674 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q701 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q703 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q704 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q705 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q706 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q707 HF201701H0 F.E.T. 2SK170 V RANK HF201701 H0
Q708 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q709 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q711 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q712 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q713 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q714 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q715 HF201701H0 F.E.T. 2SK170 V RANK HF201701 H0
Q716 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q717 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q718 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
NOTE : "nsp" PART IS LISTED FOR REFERENCE ONLY, MARANTZ WILL NOT SUPPLY THESE PARTS.
51
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
Q719 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q720
HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q723
Q724 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q751 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q753 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q754 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q755 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q756 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q757 HF201701H0 F.E.T. 2SK170 V RANK HF20170 1H0
Q758 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q759 HF203892A0 F.E.T. 2SK389 GR OR BL HF203892A0
Q761 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q762 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q763 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q764 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q765 HF201701H0 F.E.T. 2SK170 V RANK HF20170 1H0
Q766 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q767 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q768 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q769 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q770
HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q773
Q774 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q801 HC3690521F IC BA05T 5V/1A TO220 HC36905 21F
Q802 HC3690521F IC BA05T 5V/1A TO220 HC36905 21F
Q803 HC3891532F IC PQ15RW11 3.0 15 VARI REG. HC3891 532F
Q821 HC3890809F IC NJM7808FA +8V 1A REG HC3890809F
QD21 BA20004000 DIG.TRS. DTC114TS UN4215 10k BA20004000
QD22 BA20004000 DIG.TRS. DTC114TS UN4215 10k BA20004000
QD23 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
QD24 HT328782A0 TRS. 2SC2878 A OR BRANK HT328782A0
QD25 HT324582B0 TRS. 2SC2458 Y OR GR HT324582B0
QD26 HT324582B0 TRS. 2SC2458 Y OR GR HT324582B0
QD27 HT324582B0 TRS. 2SC2458 Y OR GR HT324582B0
QD41 HC10008880 IC CS4397
HC10008880
DSD/PCD DAC 24BIT 192K
QD60 HC010605K0 IC TC74VHC86F SOP HC010605K0
QD61 HC10008880 IC CS4397
VGDS-40V PD0.4W
Q503 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q504 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q505 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q506 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q507 HF201701H0 F.E.T. 2SK170 V RANK HF201701 H0
Q508 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q551 HF203691B0 F.E.T. 2SK369 BL
HF203691B0
VGDS-40V PD0.4W
Q552 HF203691B0 F.E.T. 2SK369 BL
HF203691B0
VGDS-40V PD0.4W
Q553 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q554 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q555 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q556 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q557 HF201701H0 F.E.T. 2SK170 V RANK HF201701 H0
Q558 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
PO16-MISCELLANEOUL501 LY20120620 RELAY ED2-12NU NEC 12V LY20120620
PP16-POWER IN/MUTE/±12V
CIRCUIT BOARD
PP16-CAPACITORS
C831 nsp ELECT. 470µF M 35V RA-2 OA47703520
C832 nsp ELECT. 10µF 63V RA-2 OA10606320
C851 OB47803520 ELECT. CAP 4700µF M 35V
OB47803520
FOR HIFI
NOTE : "nsp" PART IS LISTED FOR REFERENCE ONLY, MARANTZ WILL NOT SUPPLY THESE PARTS.
52
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
C852 OB47803520 ELECT. CAP 4700µF M 35V
OB47803520
FOR HIFI
C855 nsp ELECT. 47µF M 16V ARS OA47601640
C856 nsp ELECT. 47µF M 16V ARS OA47601640
C857 /F/L/S ELECT. 470µF 16V M ARA OA47701650
C857 /N nsp ELECT. 470µF 16V ARS OA47701640
C858 /F/L/S ELECT. 470µF 16V M ARA OA47701650
C858 /N nsp ELECT. 470µF 16V ARS OA47701640
CN01 nsp ELECT. 100µF M 50V RA-2 OA10705020
CN02 nsp ELECT. 1µF100V RA-2OA10510020
CN03 nsp ELECT. 4.7µF M 50V RA-2 OA47505020
CN22 nsp ELECT. 2.2µF M 50V RA-2 OA22505020
CN32 nsp ELECT. 2.2µF M 50V RA-2 OA22505020
CY51 nsp ELECT. 220µF M 50V RA-2 OA22705020
CY52 nsp ELECT. 100µF M 50V RA-2 OA10705020