LG Display LC320WUE-SBR1 Specification

Global LCD Panel Exchange Center
www.panelook.com
LC320WUE
Engineering Specification
SPECIFICATION
FOR
APPROVAL
() Preliminary Specification
()Final Specification
Title 32.0” WUXGA TFT LCD
MODEL
APPROVED BY
/
/
SIGNATURE
DATE
SUPPLIER RAKEN
*MODEL LC320WUE
SUFFIX SBR1(ROHS Verified)
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY
/ Team Leader
REVIEWED BY
/ PM
SIGNATURE
DATE
PREPARED BY
/
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 0.1
/ Engineer
LCM R&D Dept.
RAKEN Technology Co., Ltd
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
1/39
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
LC320WUE
Engineering Specification
CONTENTS
CONTENTS
RECORD OF REVISIONS
GENERAL DESCRIPTION1
ABSOLUTE MAXIMUM RATINGS2
ELECTRICAL SPECIFICATIONS3
ELECTRICAL CHARACTERISTICS3-1
INTERFACE CONNECTIONS3-2
SIGNAL TIMING SPECIFICATIONS3-3
DATA MAPPING AND TIMING3-4
PANEL PIXEL STRUCTURE3-5
POWER SEQUENCE3-6
OPTICAL SPECIFICATIONS4
MECHANICAL CHARACTERISTICS5
ITEMNumber
Page
1COVER
2
3
4
5
6
6
10
12
13
14
15
16
20
Ver. 0.1
RELIABILITY6
INTERNATIONAL STANDARDS7
SAFETY7-1
EMC7-2
PACKING8
DESIGNATION OF LOT MARK8-1
PACKING FORM8-2
PRECAUTIONS9
MOUTING PRECAUTIONS9-1
OPERATING PRECAUTIONS9-2
ELECTROSTATIC DISCHARGE CONTROL9-3
PRECAUTION FOR STRONG LIGHT EXPOSURE9-4
STORAGE9-5
HANDING PRECAUTION FOR PROTECTION FILM9-6
23
24
24
24
25
25
25
26
26
26
27
27
27
27
2/39
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
LC320WUE
Engineering Specification
RECORD OF REVISIONS
DescriptionPageRevision DateRevision No.
Preliminary Specification-Aug, 03, 20090.1
Ver. 0.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
3/39
www.panelook.com
Global LCD Panel Exchange Center
1. General Description
The LC320WUE is a Color Active Matrix Liquid Crystal Display with an integral External Electrode Fluorescent Lamp (EEFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive display type which is operating in the normally black mode. It has a 31.55 inch diagonally measured active display area with WUXGA resolution progressive mode (1080 vertical by 1920 horizontal pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes. Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot. Therefore, it can present a palette of more than 1.06B(true) colors. It has been designed to apply the 10-bit 2-port LVDS interface. It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut, high color depth and fast response time are important.
www.panelook.com
LC320WUE
Engineering Specification
+12.0V
LVDS
2Port
Reverse
LVDS Select
Bit Select
OPC Enable
ExtVBR-B
VBR-B out
High Input
High Input
CN1
(51pin)
General Features
Power Consumption
EEPROM
SCL
SDA
Timing Controller
[LVDS Rx + OPC + ODC
integrated]
Power Circuit
Block
CN2, 3pin, 18 Lamps/@135 mA
CN3, 3pin, 18 Lamps/@135mA
31.55 inches(801.31mm) diagonalActive Screen Size
760 (H) x 450 (V) x 47.5 mm(D) (Typ.)Outline Dimension
0.36375 mm x 0.36375 mmPixel Pitch
1920 horiz. by 1080 vert. Pixels, RGB stripe arrangementPixel Format
10-bit(D), 1.06 B colors Color Depth
500 cd/m2(Center 1point ,Typ.)Luminance, White
Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))Viewing Angle (CR>10)
Total 116.2 W (Typ.) (Logic=6.2 W, Back Light=110W with Inverter ,Control PCB)
5.7Kg(TBD)Weight
Transmissive mode, Normally blackDisplay Mode
Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)Surface Treatment
Mini-LVDS(RGB)
G1
Gate Driver Circuit
G1080
Source Driver Circuit
S1 S1920
TFT - LCD Panel
(1920 Ý RGB Ý 1080 pixels)
Back light Assembly
Ver. 0.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
4/39
www.panelook.com
Global LCD Panel Exchange Center
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or damage to the LCD Panel.
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Remark
Symbol
www.panelook.com
LC320WUE
Engineering Specification
Value
Unit
MaxMin
Power Input Voltage
LCD circuit
Operating Voltage (one side)
V[ RMS]1100700VOPB/L Input voltage
C+500TOPOperating Temperature
C+60-20TSTStorage Temperature
%RH9010HOPOperating Ambient Humidity
%RH9010HSTStorage Humidity
Notes : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39 C and no condensation of water.
2. Gravity mura can be guaranteed below 40୅ condition.
90%
60
60%
40
50
40%
Humidity [(%)RH]
10%
Wet Bulb Temperature [
10
0
C]
30
20
GY\Gr YG¶jV [DC]+14.0-0.3VLCD
GY\Gr YG¶j
Burst Dimming Duty
100%
Note 1
Storage
Operation
10 20 30 40 50 60 70 800-20
Dry Bulb Temperature [
Ver. 0.1
C]
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
5/39
www.panelook.com
Global LCD Panel Exchange Center
3. Electrical Specifications
It requires two kind of power inputs. One is employed to power for the LCD circuit. The other Is used for the EEFL backlight circuit.
3-1. Electrical Characteristics
Table 2. DC ELECTRICAL CHARACTERISTICS
Parameter Symbol
www.panelook.com
LC320WUE
Engineering Specification
Value
NoteUnit
MaxTypMin
Circuit :
ILCDPower Input Current
Notes : 1. The specified current and power consumption are under the V
condition whereas mosaic pattern(8 x 6) is displayed and f
V
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
White : 1023Gray Black : 0Gray
VDC13.212.010.8VLCDPower Input Voltage
=12.0V, 25 r 2C, fV=60Hz
LCD
is the frame frequency.
1mA650500-
2mA900690-
1Watt8.16.2-PLCDPower Consumption
3A3.0--IRUSHRush current
Mosaic Pattern(8 x 6)
Ver. 0.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
6/39
www.panelook.com
Global LCD Panel Exchange Center
Table 3. ELECTRICAL CHARACTERISTICS for IPB& Lamp (Continue)
www.panelook.com
LC420WUE
Product Specification
Parameter Symbol
Values
NotesUnit
MaxTypMin
Backlight Assembly :
Operating Voltage
(one side,fBL=62KHz, I
Operating Current (one side)
Established Starting Voltage (one side)
BL= 135mArms))
Parameter Symbol
0ć
25ć
VS
Values
1100950800VBL
140135130IBL
1225--
1020--
RMS
RMS
RMS
1, 2V
1mA
1, 3V
4kHz474543fBLOperating Frequency
3sec2.0--S TIMEStriking Time
6Watt7467PBLPower Consumption
9%10020PWM dutyBurst Dimming Duty
9Hz182-981/TBurst Dimming Frequency
NotesUnit
MaxTypMin
Lamp : APPENDIX
2V
5Min3--TSDischarge Stabilization Time
3V
7Hrs50,000Life Time
Established Starting Voltage (one side)
10751035820VLAMPLamp Voltage (one side)
87.53ILAMPLamp Current (one side)
1225VS0ć
1020VS25ć
mA
KHz806540f LAMPLamp Frequency
RMS
RMS
eC130TLAMPLamp Temperature
RMS
Notes : The design of the inverter must have specifications for the lamp in LCD Assembly.
The electrical characteristics of inverter are based on High-High Driving type. The performance of the lamps in LCM, for example life time or brightness, is extremely influenced by
the characteristics of the DC-AC inverter. So, all the parameters of an inverter should be carefully
designed so as not to produce too much leakage current from high-voltage output of the inverter.
When you design or order the inverter, please make sure unwanted lighting caused by the mismatch
of the lamp and the inverter (no lighting, flicker, etc) has never been occurred. When you confirm it,
the LCD– Assembly should be operated in the same condition as installed in your instrument.
Do not attach a conductive tape to lamp connecting wire.
If you attach conductive tape to the lamp wire, not only luminance level can be lower than typical one but also inverter operate abnormally on account of leakage current which is generated between lamp wire and conductive tape.
1. Specified values are defined for a Backlight Assembly.( IBL : 18 lamp, 7.5mA/Lamp)
2. Operating voltage is measured at 25 r 2C(after 2hr.aging). The variance range for operating voltage is r 10%.
3. The established starting voltage [
VS ] should be applied to the lamps for more than Striking time (S TIME)
for start-up. Inverter open voltage must be more than established starting voltage. Otherwise, the lamps may not be turned on. The used lamp current is typical value.
Ver. 0.1
7/33
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
}T
www.panelook.com
LC320WUE
Engineering Specification
S TIME
Vs = (Vpk-pk) / [ 2*root(2)]
4. Lamp frequency may produce interference with horizontal synchronous frequency. As a result, the may cause beat on the display. Therefore, lamp frequency shall be away as much as possible from the horizontal synchronous frequency and its harmonics range in order to prevent interference.
5. The brightness of the lamp after lighted for 5minutes is defined as 100%.
is the time required for the brightness of the center of the lamp to be not less than 95% at typical current.
T
S
The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.
6. Maximum level of power consumption is measured at initial turn on. Typical level of power consumption is measured after 2hrs aging at 25 r 2C.
7. The life time is determined as the time at which brightness of the lamp is 50% compared to that of initial
value at the typical lamp current on condition of continuous operating at 25 r 2C, based on duty 100%.
8.The output of the inverter must have symmetrical(negative and positive) voltage and current waveform
(Unsymmetrical ratio is less than 10%). Please do not use the inverter which has not only unsymmetrical
voltage and current but also spike wave. Requirements for a system inverter design, which is intended to achieve better display performance,
power efficiency and more reliable lamp characteristics. It can help increase the lamp lifetime and reduce leakage current.
a. The asymmetry rate of the inverter waveform should be less than 10%. b. The distortion rate of the waveform should be within ˲2 ·10%.
* Inverter output waveform had better be more similar to ideal sine wave.
* Asymmetry rate:
I p
| I
–I –p| / Iopx 100%
p
* Distortion rate
I -p
I
(or I –p) / I
p
Ver. 0.1
op
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
8/39
www.panelook.com
Global LCD Panel Exchange Center
9. The reference method of burst dimming duty ratio. It is recommended to use synchronous V-sync frequency to prevent waterfall (Vsync x 2 =Burst Frequency)
PWM
www.panelook.com
LC320WUE
Engineering Specification
{
A
+3.3V TTL
I-out
Output of Inverter to Lamp
90%
PWM duty={ A/T } * 100
Point A : rising time 90% of Iout point . Point B : falling starting point . I out duty = { a/T } * 100 PWM Frequency = 1/T
We recommend not to be much different between PWM duty and Iout duty .Dimming current output rising and falling time may produce humming and inverter trans’ sound noise.Burst dimming duty should be 100% for more than 1second after turn on.Equipment
Oscilloscope :TDS3054B(Tektronix) Current Probe : P6022 AC (Tektronix) High Voltage Probe: P5100(Tektronix)
10. The Cable between the backlight connector and its inverter power supply should be connected directly with a minimized length. The longer cable between the backlight and the inverter may cause the lower luminance of lamp and may require more higher starting voltage ( Vs ).
Point A
a
Point B
11. The operating current must be measured as near as backlight assembly input.
12. The operating current unbalance between left and right must be under 10% of Typical current
Left(Master) current – Right(Slave) Currentର 10% of typical current
Ver. 0.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
9/39
www.panelook.com
Global LCD Panel Exchange Center
3-2. Interface Connections
This LCD module employs two kinds of interface connection, a 51-pin connector is used for the module electronics and two 3-pin Balance PCB connectors are used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): FI-R51S-HF(manufactured by JAE) or KN25-51P-0.5SH(manufactured by Hirose)
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION
www.panelook.com
LC320WUE
Engineering Specification
1
2
3
4
5
6
7
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25 26
GND
LVDS Select
GND
R1AN
P
R1A
R1BN R1BP
R1CN
R1CP
GND
R1CLKN
R1CLKP
GND
R1DN
R1DP
R1EN R1EP
Reserved
DescriptionSymbolNo
Ground
No ConnectionNC
No ConnectionNC
No ConnectionNC
No ConnectionNC
No ConnectionNC
‘H’ =JEIDA , ‘L’ or NC = VESA
Vbr Input (For OPC)VBR_EXT8
Vbr Output (For OPC)OPC_OUT9
H : OPC Enable / L : OPC DisableOPC Enable10 Ground
FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+) Ground
FIRST LVDS Receiver Clock Signal(-) FIRST LVDS Receiver Clock
Signal(+) Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
FIRST LVDS Receiver Signal (E-) FIRST LVDS Receiver Signal (E+)
No connection or GND
No
27
28
29
30
31
32
33
34
35
36
37
38
39 40
41
42
43
44
45
46
47
48
49
50 51
-
Symbol
Bit Select
R2AN
R2AP
R2BN
R2BP
R2CN
R2CP
GND
R2CLKN
R2CLKP
GND
R2DN
R2DP
R2EN
R2EP
Reserved
Reserved
GND
GND
GND
NC VLCD
VLCD
VLCD VLCD
-
Description
‘H’ or NC= 10bit(D) , ‘L’ = 8bit
SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+) Ground
SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+) Ground
SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
SECOND LVDS Receiver Signal (E-)
SECOND LVDS Receiver Signal (E+) No connection or GND
No connection or GND
Ground
Ground
Ground
No connection Power Supply +12.0V
Power Supply +12.0V
Power Supply +12.0V Power Supply +12.0V
-
Notes :
1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. All V
LCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. Specific pins(pin No. #2~#6) are used for internal data process of the LCD module. If not used, these pins are no connection.
5. LVDS pin (pin No. #24,25,40,41) are used for 10Bit(D) of the LCD module. If used for 8Bit(R), these pins are no connection.
6. Specific pin No. #44 is used for “No signal detection” of system signal interface. It should be GND for NSB(No Signal Black) during the system interface signal is not. If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
Ver. 0.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
10 /39
www.panelook.com
Global LCD Panel Exchange Center
3-2-2. Backlight Module
www.panelook.com
LC320WUE
Engineering Specification
[ Master ]
1) Balance Connector
: 65002WS-03 (manufactured by YEONHO)
2) Mating Connector
: 65002HS-03 (manufactured by YEONHO)
Table 5. BACKLIGHT CONNECTOR PIN CONFIGURATION(CN2,CN3)
SymbolNo
H_Input
H_Input
FB
Rear view of LCM
123
Master
Master
High_Input2
NC3
1
23
Slave
[ Slave ]
1) Balance Connector
: 65002WS-03 (manufactured by YEONHO)
2) Mating Connector
: 65002HS-03 (manufactured by YEONHO)
Slave
High_InputHigh_Input1
High_Input
NC
Note
Ver. 0.1
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
11 /39
www.panelook.com
Global LCD Panel Exchange Center
3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timing should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE for NTSC (DE Only Mode)
www.panelook.com
LC320WUE
Engineering Specification
Horizontal
Vertical
Frequency
Display Period
Blank
Total
DCLK
Horizontal
Vertical
Symbol
tHV
tHB
t
HP
VVDisplay Period
VBBlank
VPTotal
Symbol
fCLK
fH
f
V
tclk-960-
tclk240140100
Lines-1080-t
Lines694511t
Lines114911251091t
KHz7067.565
Hz636057
NoteUnitMaxTypMinITEM
2200/2tclk120011001060
NoteUnitMaxTypMinITEM
148.5/2MHz7774.2570
Table 7 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timing should be satisfied with the following specification for normal operation.
Table 7. TIMING TABLE for PAL (DE Only Mode)
Symbol
NoteUnitMaxTypMinITEM
tclk-960-
tclk240140100
2200/2tclk120011001060
Lines-1080-t
Lines300270228t
Lines138013501308t
NoteUnitMaxTypMinITEM
148.5/2MHz7774.2570
KHz7067.565
Hz535047
Horizontal
Vertical
Frequency
Display Period
Blank
Total
DCLK
Horizontal
Vertical
tHV
tHB
HP
t
VVDisplay Period
VBBlank
VPTotal
Symbol
fCLK
fH
f
V
Note : The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).
The performance of the electro-optical characteristics may be influenced by variance of the vertical refresh rate.
Ver. 0.1
12 /39
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Loading...
+ 27 hidden pages