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high color depth and fast response time are important
Pixel F
t
1366 hori
768
RGB stri
t
1. General Description
The LC320EXJ is a Color Active Matrix Liquid Crystal Display with an integral the Source PCB and Gate
implanted on Panel (GIP). The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 31.5 inch diagonally measured
active display area with WXGA resolution (768 vertical by 1366 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7M(6bit + A-FRC) colors.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
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LC320EXJ
Product Specification
.
Control
Signals
RGB
Source Driver Circuit
S1S1366
G1
TFT - LCD Panel
G768
LVDS Select
LVDS 1Port
+12.0V
#9
CN1
(30pin)
EEPROM
SCL
Timing Controller
[LVDS Rx]
SDA
Power Circuit
Block
Power Signals
General Features
Active Screen Size31.5 inches(800.4mm) diagonal
Outline Dimension715.0mm(H) x 411.0mm(V) x 1.4mm(D) (Typ.)
Source D-IC : 6-bit mini-LVDS, gamma reference voltage, and control signals
Gate D-IC : Gate In Panel
vert. pixels
pe arrangemen
(1366 Ý RGB Ý 768 pixels)
[Gate In Panel]
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g
StorageHumidity
HST1090%RH
10%
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or damage to the
LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
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LC320EXJ
Product Specification
ParameterSymbol
UnitRemark
MinMax
Value
Power Input voltageVLCD-0.3+14.0V [DC]
Panel Front TemperatureT
Operating TemperatureT
Storage TemperatureT
Operating Ambient HumidityH
Note:
1. Ambient temperature condition (Ta = 25 r 2 ¶C )
SUR-+68
OP0+50
ST-20+60
OP1090%RH
¶C
¶C
¶C
2. Temperature and relative humidity range are shown in the figure below. Wet bulb temperature
should be Max 39 ¶C and no condensation of water.
3. Gravity mura can be guaranteed below 40ć condition.
4. The maximum operating temperature is based on the test condition that the surface temperature
of display area is less than or equal to 68 ć with LCD module alone in a temperature controlled
chamber. Thermal management should be considered in final product design to prevent the surface
temperature of display area from being over 68 ć. The range of operating temperature may
degrade in case of improper thermal management in final product design.
90%
X
4
2,3
60
60%
40
50
40%
Humidity [(%)RH]
¶C]
Wet Bulb
Temperature [
0
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¶C]
30
20
10
10203040506070800-20
Dry Bulb Temperature [
Storage
Operation
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3-1. Electrical Ch
3. Electrical Specifications
aracteristics
It requires two power inputs. One is employed to power for the LCD circuit.
Table 2. ELECTRICAL CHARACTERISTICS
ParameterSymbol
Circuit :
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LC320EXJ
Product Specification
Value
UnitNote
MinTypMax
Power Input VoltageV
Power Input CurrentILCD
Power ConsumptionP
Rush currentIRUSH--3.0A3
Notes : 1. The specified current and power consumption are under the V
condition whereas mosaic pattern(8 x 6) is displayed and f
LCD10.812.013.2VDC
-
-
LCD-4.085.30Watt1
340445
430560
=12.0V, 25 r 2¶C, fV=60Hz
LCD
is the frame frequency.
V
mA1
mA2
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
4. Ripple voltage level is recommended under ·5% of typical voltage.
White : 255Gray
Black : 0Gray
Mosaic Pattern(8 x 6)
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uj
3-2. Interface Connections
3-2-1. LCD Module
- LCD Connector(CN1) : KDF71G-30S-1H(Hirose) or FI-X30SSL-HF(JAE)
- Mating Connector : : FI-X30C2L (Manufactured by JAE) or Equivalente
1. All GND (Ground) pins should be connected together to the LCD module’s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. These pins are used only for LGD (Do not connect)
5. Specific pin No. #30 is used for “No signal detection” of system signal interface.
It should be GND for NSB (No Signal Black) while the system interface signal is not.
If this pin is “H”, LCD Module displays AGP (Auto Generation Pattern).
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{G[UGG{ptpunG{hislGOklGvGtP
(126)
(180)
(295)
If
EMI
dditi
3-3. Signal Timing Specifications
Table 4 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
{
ITEMSymbolMinTypMaxUnitNote
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LC320EXJ
Product Specification
Horizontal
Vertical
Frequency
Display
Period
Blankt
Totalt
Display
Period
BlanktVB
TotaltVP
ITEMSymbolMinTypMaxUnitNote
DCLKf
Horizontalf
Verticalf
t
HV-1366-tclk
HB90162410tclk
HP145615281776tclk
VV-768-tHP
t
20
788
(894)
CLK63.072.480.0MHz
H4547.455KHz2
V
57
(47)
22
790
(948)
60
(50)
240
1008
(1063)
63
(53)
tHP1
t
HP
Hz
57~63Hz
(PAL : 47~53Hz)
2
NTSC :
Note: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).
you use spread spectrum of
, add some a
onal clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency
Ć Timing should be set based on clock frequency.
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3-4-1. LVDS I
t
VV
3-4. Signal Timing Waveforms
nput Signal Timing Diagram
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LC320EXJ
Product Specification
DCLK
1366
tCLK
DE(Data Enable)
0.5 Vcc
Invalid data
DE, Data
tHT
Valid data
1
0.7VDD
tHV
0.3VDD
1366
Invalid data
DE(Data Enable)
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768
1768
tVT
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1) DC S
ificati
# V
{(LVDS+)
(
LVDS-)}/
2
2) AC Specification
A
3-4-2. LVDS Input Signal Characteristics
pec
on
LVDS -
LVDS +
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LC320EXJ
Product Specification
V
CM
=
0V
CM
+
V
IN _MAXVIN _MIN
DescriptionSymbolMinMaxUnitNote
LVDS Common mode VoltageV
LVDS Input Voltage RangeV
CM
IN
1.01.5V-
0.71.8V-
Change in common mode VoltageVCM-250mV-
T
clk
LVDS Clock
A
LVDS Data
(F
= 1/T
)
clk
LVDS 1’st Clock
LVDS 2nd/ 3rd/ 4thClock
tSKEW
tSKEW
t
SKEW_mintSKEW_max
clk
T
clk
80%
20%
t
RF
DescriptionSymbolMinMaxUnitNote
LVDS Differential Voltage
High Threshold
Low Threshold
LVDS Clock to Data Skewt
LVDS Clock/DATA Rising/Falling timet
V
TH
V
TL
SKEW
RF
Effective time of LVDSt
LVDS Clock to Clock Skew (Even to Odd)t
Note
1. All Input levels of LVDS signals are based on the EIA 644 Standard.
2. If t
isn’t enough, t
RF
should be meet the range.
eff
SKEW_EO
3. LVDS Differential Voltage is defined within t
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100300mV
-300-100mV
-|(0.20*T
260|(0.3*T
|·360|
-|1/7* T
eff
)/7|ps-
clk
)/7|ps2
clk
-ps-
|ps-
clk
3
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V
clk
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LC320EXJ
Product Specification
360ps
V+
data
Vcm
-
data
V+
clk
Vcm
0.5tui
tui
VTH
VTL
360ps
teff
tui : Unit Interval
V-
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