JVC LT-19DB1BU/AX Schematic

SCHEMATIC DIAGRAMS

INTEGRATED DIGITAL TERRESTRIAL/SATELLITE LCD TELEVISION

LT-19DB1BU/AX

DVD-ROM No.SML2009Q1

COPYRIGHT © 2009 Victor Company of Japan, Limited.

No.YA697<Rev.001>

2009/5

LT-19DB1BU

/AX

STANDARD CIRCUIT DIAGRAM

NOTE ON USING CIRCUIT DIAGRAMS

1.SAFETY

The components identified by the symbol and shading are
critical for safety. For continued safety replace safety ciritical
components only with manufactures recommended parts.

2.SPECIFIED VOLTAGE AND WAVEFORM VALUES

The voltage and waveform values have been measured under the
following conditions.

(1)Input signal : Colour bar signal

(2)Setting positions of
each knob/button and
variable resistor

(3)Internal resistance of tester

(4)Oscilloscope sweeping time

(5)Voltage values

Since the voltage values of signal circuit vary to some extent
according to adjustments, use them as reference values.

: Original setting position
when shipped

: DC 20kΩ/V

: H

: V

: Othters

: All DC voltage values

20µs / div

5ms / div

Sweeping time is
specified

3.INDICATION OF PARTS SYMBOL [EXAMPLE]

In the PW board

: R1209

R209

Type

No indication

MM
PP
MPP

MF
TF
BP

TAN

(3)Coils

No unit

Others

(4)Power Supply

Respective voltage values are indicated

(5)Test point

: Test point

(6)Connecting method

: Ceramic capacitor
: Metalized mylar capacitor

: Polypropylene capacitor
: Metalized polypropylene capacitor
: Metalized film capacitor
: Thin film capacitor
: Bipolar electrolytic capacitor
: Tantalum capacitor

: [µH]

: As specified

: B1

: 9V

: Connector

: Receptacle

: Only test point display

: Wrapping or soldering

: B2 (12V

: 5V

)

4.INDICATIONS ON THE CIRCUIT DIAGRAM

(1)Resistors

Resistance value

No unit : [Ω]

K
M

Rated allowable power
No indication : 1/16 [W]

Others : As specified

Type

No indication

OMR

MFR

MPR

UNFR

FR

Composition resistor 1/2 [W] is specified as 1/2S or Comp.

(2)Capacitors

Capacitance value

1 or higher : [pF]

less than 1

Withstand voltage

No indication : DC50[V]

Others : DC withstand voltage [V]

AC indicated
Electrolytic Capacitors

47/50[Example]: Capacitance value [µF]/withstand voltage[V]

: [kΩ]

: [MΩ]

: Carbon resistor

: Oxide metal film resistor

: Metal film resistor

: Metal plate resistor

: Uninflammable resistor

: Fusible resistor

: [µF]

: AC withstand voltage [V]

(7)Ground symbol

: LIVE side ground

: ISOLATED(NEUTRAL) side ground

: EARTH ground

: DIGITAL ground

5.NOTE FOR REPAIRING SERVICE

This model's power circuit is partly different in the GND. The
difference of the GND is shown by the LIVE : ( ) side GND and the
ISOLATED(NEUTRAL) : ( ) side GND. Therefore, care must be
taken for the following points.

(1)Do not touch the LIVE side GND or the LIVE side GND and the
ISOLATED(NEUTRAL) side GND simultaneously. if the above
caution is not respected, an electric shock may be caused.
Therefore, make sure that the power cord is surely removed from
the receptacle when, for example, the chassis is pulled out.

(2)Do not short between the LIVE side GND and ISOLATED(NEUTRAL
side GND or never measure with a measuring apparatus measure
with a measuring apparatus ( oscilloscope, etc.) the LIVE side GND
and ISOLATED(NEUTRAL) side GND at the same time.
If the above precaution is not respected, a fuse or any parts will be broken.

Since the circuit diagram is a standard one, the circuit and
circuit constants may be subject to change for improvement
without any notice.

NOTE
Due improvement in performance, some part numbers show
in the circuit diagram may not agree with those indicated in
the part list.
When ordering parts, please use the numbers that appear
in the Parts List.

)

(No.YA697<Rev.001>)2-1

CONTENTS

SEMICONDUCTOR SHAPES ......................................................................2-2

WIRING DIAGRAM .......................................................................................2-3

BLOCK DIAGRAM ........................................................................................2-5

CIRCUIT DIAGRAMS ...................................................................................2-7

MAIN PWB CIRCUIT DIAGRAM ................................................................................................................. 2-7

IR PWB CIRCUIT DIAGRAM .................................................................................................................... 2-63

KEY PWB CIRCUIT DIAGRAM................................................................................................................. 2-65

PATTERN DIAGRAMS .............................................................................. 2-67

MAIN PWB P ATTERN .............................................................................................................................. 2-67

IR PWB P ATTERN.................................................................................................................................... 2-71

KEY PWB P ATTERN ................................................................................................................................ 2-71

USING P.W. BOARD

P.W.B ASS㵭Y name LT-19DB1BU/AX

MAIN P.W. BOARD

IR P.W. BOARD

KEY P.W. BOARD

HU-71100004

HU-72200001

HU-72200002

SEMICONDUCTOR SHAPES

TRANSISTOR

BOTTOM VIEW FRONT VIEW TOP VIEW

CHIP TR

E
C
B

ECB

IC

BOTTOM VIEW FRONT VIEW TOP VIEW

OUT

E

IN

IN OUTE

CHIP IC

B

(G)E(S)C(D)

TOP VIEW

1 N

1

ECB

ECB

1

1 N

C

BE

N

N

1

2-2(No.YA697<Rev.001>)

N

WIRING DIAGRAM

LCD PANEL UNIT

LCD PANEL UNIT

[LCD CONTROL PWB]

TOP

TOP

KEY PWB

TOP

CN200

24

1

1

JP451

24

JP1

1

51

DIGITAL TUNER
(SATELLITE)

JP2

1

TOP

IR PWB

5

F100

250V/4A

CN100

L

JP2

1

6

JP3

1

N

4

JP4

JP761

1

DIGITAL TUNER
(TERRESTRIAL)

MAIN PWB

POWER UNIT

6

POWER CORD

SPEAKER(R)SPEAKER(L)

JP1

1

6

BLUE LED MODULE

2-4(No.YA697<Rev.001>)(No.YA697<Rev.001>)2-3

BLOCK DIAGRAM

SERVICE PORT

PC

RS232

KEY PWB

&

IR PWB

POWER UNIT

TXD/RXD

4Pin Con.

U831

ILX232

KEY_ADC1

KEY_ADC2

LED_B

LED_R

MOD2_ID

MOD1_ID

SCART_MUTE

SMPS_ON

PWM_DIM

A_DIM

BKLT_EN FLI_I2C0

AC_DETECT

P_PWM_DIM

P_A_DIM

P_BKLT_EN

+24V

+5V8STB

+5V

+12V

TA_A/RA_A

PD6IR_IN

PA1

PA0

PA2

PA3

PA5

PA6

PD7

PB4

KIA7042AF

PD0,PD1

MICOM CTRL

TA_A/RA_A

U82

PB5,6,7,RESETn

LS

PC0,PC1

CLK IN/OUT

JTAG

Development Only

*

U321,U322

DDR2(333MHz/512Mbit)

U181

FLASH MEMORY

UART1_TXD/RXD

UART0_TXD/RXD

PC2

M_I2C FLI_I2C1

CEC_A

PB2

PA4

PA5

PC5

A_RESET

PC4

PC3

LPM_RST_N

JTAG

HeaderHeader

DDRA[0:12]
/DDRDQ[0:31]

HOST_A[1:2]/HOST_D[0:7]

Y961

XTAL

INT_OUT WM0P

LS

Y81

XTAL

U113

EEPROM

UART1

UART0

CLK IN/OUT

I2C1

I2C0

EJTAG

DDR MEM
CTL. BUS

ROM MEM
CTL. BUS

U112

SCALER

PWM3

DFSYNC_IN_OUT_GPIO8

VGA_R,VGA_G,VGA_B

PWM2

PPWR

LVTX_ODD

LVTX_EVN

RESET_N

USB2.0 HOST

USB_PWREN

USB_FLAG

DVI_ARX

HDMIA_I2C

HDMIA_HPD

AHS, AVS

S0_SCL/SDA

AUD_IN_L3/R3

VXO_D11

SCART_FB

LBADC_IN4

A1P,B1P,C1P/SV1P

AUD_IN_L1/R1

AUD_OUT1R/L

AUD_OUT2R/L

PWM_DIM

A_DIM

BKLT_EN

RESETn_MAIN

SCART_FB_SEL

SCART_FB

SCART1_RO/LO

SCART2_RO/LO

USF-T

USB SWITCH

VGA_HS/VS

PC_RI/LI

PANEL_PWR

LVDS_OUT

LPM_RST_N

USB_HOST

U104

TMDS_A

HDMI_SCL/SDA

FLI_I2C1

HPDA

PC_R/G/B

U381

VIDEO

SWITCH

SCART_ID1

SCART1_R/G/B/CVBS

SCART1_RI/LI

U662

OP AMP

+5V

+5V_USB

PC

AUDIO

74HC14

HS/VS

VGA_SDA/SCL

EEPROM

SCART2_FB

SCART1_FB

SC1_R/L_OUT_O

SCART1_CVBSO

PANEL

USB IN

U551

HDMI SWITCH

P_PWM_DIM

P_A_DIM

P_BKLT_EN

PC IN

SCART1

+24V

TMDS 1

HPD1

TMDS 2

HPD2

CEC

CEC

EXT1

HDMI

HDMI

EXT4

EXT5

T+C TUNER

LNB_OUT

U921

RF_CVBS

SIF

U1021

Analog Tuner

TUNER0_I2C

IF+/-

CH_TER_RESET

TUNER_I/O_P_N

TUNER1_I2C

LNB_OUT

U961

DEMOD

U1081

DEMOD

&

A8293

FLI_I2C0

FLI_I2C0

CH_RESET22K_TONE

TS0_D[0..7]

TS0_SYNC

TS0_VALID
TS0_CLK

TS1_CLK

TS1_SYNC

TS1_VALID

TS1_D[0..7]

TS0_SYNC
TS0_VALID
TS0_CLK

TS1_CLK
TS1_SYNC
TS1_VALID

JP221

CI SLOT

Buffer&SW

Buffer&SW

Buffer&SW

Buffer&SW

POD_CTL.

PPKT_CLK
PPKT__D[0..7]
PPKT__SYNC
PPKT_I_VAL

MOD_CLK
MOD_D[0..7]
MOD_SYNC
MOD_VAL

TS0_SEL

MUX_TSI_CLK

MUX_TSI_SYNC

MUX_TSI_VAL

TS0_SEL
TS1_SEL

MUX_TSI_D[0..7]

TS1_SEL

Buffer

Buffer

MUX_TSI_CLK

MUX_TSI_SYNC

MUX_TSI_VAL

MUX_TS_D0

STREAM_CLK
STREAM_D[0..7]
STREAM_SYNC
STREAM_VAL

TS_SEL

CH_TER_RESET

CH_RESET

TS_Parallel

Inputs
[POD]

VXO_D0

VXO_D1

VXO_D5

A3P,B3P,C3P

AUD_IN_L4/R4

AUD_IN_L5/R5

AUDIO_MUTE

AUD_MCLK1

AUDO_SPDIF_OUT

(No.YA697<Rev.001>)2-5 2-6(No.YA697<Rev.001>)

B4P,A4P

SV3P

SV4P

TNR_SIF

GPIO134

I2SA_BCLK

I2SA_WCLK

I2SA_DAT0

RF_CVBS

SIF

I2S_OUT

FLI_I2C1

A_RESET

YPbPr

Component_R/L

SVHS_Y/C

AV_CVBS

AL/AR_CVBS

HEADPHONE_ID

AUDO_MUTE

U761

Digital Audio

AMP

SPDIF

HP_L/R

AMP_R-

AMP_R+

AMP_L-

AMP_L+

OP AMP

SPEAKER(R)

SPEAKER(L)

DIGITAL AUDIO

HPO_L/R

EXT2

EXT3

HEADPHONE

CIRCUIT DIAGRAMS

MAIN PWB CIRCUIT DIAGRAM (1/28) [DVB-T+C TUNER]

1

U921
FQD1116AME/BH

A A

RF PIN IN/OUT(OPTION)

1

2

RF IN

RF IN

ANT_PWR2GND3NC4RF_AGC5GND6VP_TUN_+5v

GND9NC10AS11SCL12SDA13REF14IF-AGC15DIF116DIF217WIF OUT/NC

7VT8

3

+5V IF192nd IF SOUND/LOW DIG IF1

2nd IF SOUND/LOW DIG IF2

18

20

21NC22

GND
GND

GND
GND

AS_IF23CVBS

24

4

25
26

27
28

IIC AS : Tuner : 0xC0h

Analog Demod : 0x86h

5

6

+5VT_ANT

L923
BLM18PG300SN1D

C939

220uF/16V/MVK/S

+5VTA

L921
BLM18PG300SN1D

B B

+5VTA

C C

C927

220uF/16V/MVK/S

L922
BLM18PG300SN1D

C931

220uF/16V/MVK/S

C922

104p/16V/1005

C925
104p/16V/1005

C929
104p/16V/1005

C923
102p/50V/1005

C926

102p/50V/1005

C930
102p/50V/1005

C935

OPEN-330p/1005

R944
331/F/1005

R929
121/F/1005

R948 000/1005

R949 000/1005

R932 000/1005

R933 000/1005

R934 000/1005

C936
OPEN-330p/1005

R926 000/1005

C932
OPEN_3R3p/50V/005

R950

OPEN-331

R928 750/F/1005

R952

OPEN-330/F/1005

R944 and R929 are located near by U921

R951
OPEN-331

IF0_NARROW-

IF0_NARROW+

TUNER0_AGC

RF_CVBS

C937
OPEN-220p/50V/1005

MAIN PWB
(26/28)

MAIN PWB (12/28)

C933
OPEN-104p/16V/1005

R947

330/1005

+5VTA +3V3DT

R930

562/1005

R943

562/1005

SIF

C934
220p/50V/1005

1

Q925

32

32

FDV301N_NL

1

MAIN PWB (12/28)

Q924
FDV301N_NL

TUNER0_SDA

TUNER0_SCL

MAIN PWB (26/28)

Antenna Power Short Protection Circuit

Antenna Current Limiting Circuit (100mA Limiting)

ANT_PWR_EN

HIGH ON

LOW

MAIN PWB (7/28)

D D

ANT_PWR_EN
ANT_PWR_CHK

IF ANT_PWR_CTRL is L

--> ANT_PWR_EN L
Fault Flag (Output):
Active-low, open-drain output.
Indicates overcurrent or
thermal shutdown conditions

+5V_ANT

OFF

R922 330/1005
R923 101/1005

+3V3DT

R924
103/1005

U922

1

EN

2

FLG

3

GND
NC4ILIM

POWER SW MIC2544-1YMM

+5VTA +5VT_ANT

8

OUT

7

IN

6

OUT

Current limit threshold is determined by
ILIMIT = 230V / RSET,
where : 154 < RSET < 2.29k

R927 222/1005

5

MAIN PWB ASS'Y (1/28)
[DVB-T+C TUNER]

HU-71100004

All location are from 921 to 960

1

2

3

4

5

6

lt-19db1bu_0514_24/30_0.0

2-8(No.YA697<Rev.001>)(No.YA697<Rev.001>)2-7

MAIN PWB CIRCUIT DIAGRAM (2/28) [QPSK TUNER]

5

D D

C C

MAIN PWB (27/28)

TUNER_Q_P

MAIN PWB (28/28)

TUNER_Q_N

LNB_OUT

MAIN PWB (28/28)

C1021

150p/50V/1005

C1025

150p/50V/1005

12

TUNER_AGC

R1023 101/1005

R1025 101/1005

4

D1021

OPEN-LNBTVS6-221S

C1022

OPEN-150p/50V/1005

C1026

OPEN-150p/50V/1005

+3.3V_RF-AMP

U1021

2

LNB-A

1

LNB-B

3

+3.3V_RF-AMP

9

AGC

5

QP

6

QN

3

DNBU12111IS(V)

XTAL-OUT

+3.3V_TUNER

GND13GND14GND15GND16SGND17SGND18SGND19SGND

SCL

SDA

20

2

11

10

12

4

R1021 000/1005

R1022 000/1005

+3.3V_TUNER

TUNER1_SCL

TUNER1_SDA

MAIN PWB (28/28)

1

* To be routed pattern without VIA Hole *

8

IP

7

IN

C1023

OPEN-150p/50V/1005

C1027

OPEN-150p/50V/1005

R1024 101/1005

R1026 101/1005

TUNER_I_P

C1024

150p/50V/1005

MAIN PWB (28/28)

TUNER_I_N

C1028

150p/50V/1005

B B

+3.3V_TUNER

C1034
220uF/16V/BLA/S

3

C1029
104p/16V/1005

U1022
RT9164

VIN

1

ADJ

VO
VO

+3.3V_RF-AMP+5V

2
4

R1027

201/F/1005

R1028

331/F/1005

C1030
226p/6.3V/2012

C1031
106p/10V/2012

L1021
BLM18PG300SN1D

C1032
106p/10V/2012

C1033
OPEN-104p/16V/1005

MAIN PWB ASS'Y (2/28)

A A

[QPSK TUNER]

HU-71100004

All location are from 1021 to 1050

5

4

3

2

1

lt-19db1bu_0514_26/30_0.0

(No.YA697<Rev.001>)2-9 2-10(No.YA697<Rev.001>)

MAIN PWB CIRCUIT DIAGRAM (3/28) [Power & Interface Connectors]

5

JP1

SMW200-24C

1

D D

POWER UNIT

CN200

C C

KEY PWB

JP2

2
3
4
5
6
7
8

9
10
11

2mm

12
13
14
15
16
17
18
19
20
21
22
23
24

JP2
SMW250-05

2.5mm

5
4
3
2
1

R5 330/1005
R6 330/1005

R7 330/1005

SMPS_ON

KEY_ADC2

KEY_ADC1

AC_DETECT

BL_EN_O
ANA_DIM
PWM_DIM

MAIN PWB (5/28)

L1
BLM41PG600SN1L

L2
BLM41PG600SN1L

L3
BLM21PG600SN1D

MAIN PWB
(5/28),(19/28),(22/28)

MAIN PWB (13/28)

MAIN PWB (5/28)

IR

LEDR

+5VSTB

C8

104p/16V/1005

IR_IN

L4
BLM18PG300SN1D

JP3

SMW250-06

6

B B

IR PWB

JP1

5
4

2.5mm

3
2
1

4

C1

100uF/25V/BXE/S

C3

470uF/16V/MVK/S

100uF/25V/BXE/S

C6

PM_LED_Ctrl

MAIN PWB (5/28)

R18
Open_103/1005

Only SA1 Model

MAIN PWB (5/28)

C2
104p/50V

C4
104p/50V

C7
104p/50V

PM_LED

MAX.3A

+12V

MAX.3.5A

+5V

MAX.500mA

+5V4STB

Q6

1

Open_MMBT4401

23

LED_B

[+12V]
AMP : 1500mA
QPSK : 400mA
PANEL : 800mA

[+5V]
USB : 500mA
CAM : 500mA
PANEL : 1200mA(Option)

[+5.8V]
MICOM : 9mA
RS232 : 10mA
TUNER : 220mA

R17
Open_301/3216

L : ON
H : OFF

3

MAIN PWB (5/28)

MAIN PWB (5/28)

+5VSTB

R8
103/1005

1

+5VSTB

23

Q2
MMBT4403

R9
301/3216

LEDB

AM_LED_Ctrl

STBY_EN

R10
Open_103/1005

Only SA1 Model

Open_SMW200-12P

OPEN

+5VSTB

Power on : L
Power off : H

AM_LED

1

JP5

12
11

2mm

10

R1
472/1005

R3
103/1005

R15
Open_301/3216

Q4

Open_MMBT4401

23

9
8
7
6
5
4
3
2
1

2

+5VSTB

R2
102/1005

Q1

1

MMBT4401

23

MAIN PWB (5/28)

+5VSTB

Open_BLM18PG300SN1D

SMPS_ON

C5
OPEN-104p/16V/1005

Alarm_LED_Ctrl

C9

Open_104p/16V/1005

MAIN PWB

SPI_STR
SPI_CLK

AM_LED
PM_LED
Alarm_LED

CDS_OUT

IR
LEDB
LEDR

SMPS_ON

Only SA1 Model

+5VSTB

(5/28)

MAIN PWB (5/28)

Alarm_LED

R13
Open_103/1005

R19
Open_472/1005L5

SPI_DIO

1

MAIN PWB (25/28)

R16
Open_301/3216

Q5

1

Open_MMBT4401

23

MAIN PWB
(5/28)

Only SA1 Model

JP4
53014-0410

1

2mm

BLUE LED

MODULE

A A

2
3
4

FRONT BLUE LED

LEDB

LED_R

L : ON
H : OFF

R12
103/1005

23

Q3

1

MMBT4403

R14
301/3216

MAIN PWB ASS'Y (3/28)

All location are from 1 to 20

LEDR

[Power and Interface Connectors]

HU-71100004

5

4

3

2

1

lt-19db1bu_0514_1/30_0.0

2-12(No.YA697<Rev.001>)(No.YA697<Rev.001>)2-11

MAIN PWB CIRCUIT DIAGRAM (4/28) [Power Regulation]

1

NORMAL POWER

+5V

A A

B B

106p/10V/2012

106p/16V/2012

C C

C21

106p/16V/2012

+3V3

C41

+3V3

C52

OPEN-104p/16V/1005

C23

106p/16V/2012

C28

OPEN-106p/16V/2012

C42

106p/10V/2012

C53

104p/16V/1005

C58

R21

104/1005

C48

104p/16V/1005

+5V

R33
103/1005

105p/16V/1005

C29

104p/16V/1005

104/F/1005

C59

R29
104/F/1005

R30

TP25
PCB_TP10

1

TP23
PCB_TP10

TP21
PCB_TP10

U21
MP2307

7

EN

8

SS

4

GND

Max.3A

1

4

7

6

10

C50
OPEN-106p/2012

U24
RT9018B25PSP

3

VIN

2

EN

4

VDD

8

GND

9

TAP

Max.3A

1

2

IN

9

U23
MP2121DQ

IN

IN

POK

EN/SYNC

VOUT

PGOOD

2

C22
103p/50V/1005

R42
000/1005

1

BS

3

SW

5

FB

6

COMP

GND_P

OPEN-561p/50V/1005

GND

GND

9

2

TP26
PCB_TP10

6

R1

7

ADJ

5

NC

R2

1

TP22
PCB_TP10

4.7uH/SPC7040-4R7/3.5A

1

D21

OPEN-SX34

C30

5

BS

3

SW

8

SW

1

FB

GND-PAD

11

R2

L21

243/F/1005

C27
332p/50V/1005

R24

562/1005

R39
000/1005

R31
304/F/1005

R32
6043/F/1005

R22

R2

C43

103p/50V/1005

R1

3

R1

R23
912/F/1005

C24
106p/10V/2012

C25
104p/16V/1005

VOUT = 0.925V * (1 + R1/R2)

TP24
PCB_TP10

L22

1

SPC6025-1R0M

C44

226p/6.3V/2012

BLM31PG601SN1

BLM31PG601SN1

C26
100uF/25V/BXE/S

C61

226p/6.3V/2012

+3V3

L16

L16

[Douglas Core]

+1V2

+1.2V,
Max.1634mA

check 1V2 ripple noise

C62
100uF/25V/BXE/S

+3.36V, Max.2.790A

4

STAND-BY POWER

+5V4STB

C31

106p/16V/2012

Open_104p/16V/1005

3V3 Power Branch

+3V3

+3V3_D

BLM18PG300SN1D

C46

104p/16V/1005

BLM18PG300SN1D

Vout=0.8V(R1+R2)/R2

1V8 Power Branch

+1V8

[Douglas DDR]

1

R34
753/F/1005 C56

R36
593/F/1005

C54

106p/10V/2012

R37
104/F/1005

+1.816V,
Max.781mA

C55

104p/16V/1005

+1V8

L25
BLM18PG300SN1D

104p/16V/1005

C32

5

L23

L24

TP29
PCB_TP10

1

VDDR_MEM

U22 RT9167-50PB

1

VIN

3

EN

2

GND

+3V3_A

C45 104p/16V/1005

C47 100uF/16V/MVK/S

+3V3H

C49 104p/16V/1005

C51 100uF/16V/MVK/S

C57

100uF/25V/BXE/S

5

VOUT

4

BP

104p/16V/1005

R35
102/F/1005

R38
102/F/1005

TP30
PCB_TP10

1

C69

DDR_VRF

C60

104p/16V/1005

6

C33

105p/16V/1005

+5VSTB

MAX 29mA

C34
104p/16V/1005

Vout=0.8V(R1+R2)/R2

U25
LD29150PT/P-PAK 5P

5

MAX 1.5A

TP28
PCB_TP10

1

R40
1692/F/1005

R41
103/F/1005

C66
103p/50V/1005

+3V3_D

C67
106p/10V/2012

+5.03V
MAX 642mA

C68

104p/16V/1005

MAIN PWB ASS'Y (4/28)
[Power Regulation]

HU-71100004

/INH1VIN2GND3VOUT4ADJ

TP27

+5V

D D

C63
106p/16V/2012

PCB_TP10

1

C64
104p/16V/1005

C65

OPEN-105p/16V/1005

GND

6

DGND GND_A

All location are from 21 to 80

1

2

3

4

5

6

lt-19db1bu_0514_2/30_0.0

(No.YA697<Rev.001>)2-13 2-14(No.YA697<Rev.001>)

MAIN PWB CIRCUIT DIAGRAM (5/28) [MICRO CTRL]

5

+5VSTB +5VSTB

D D

C C

C81

104p/16V/1005

U81
KIA7042AF

VCC1GND2OUT3GND

4

12

34

S81

OPEN-JTP1127WEM

MAIN PWB (16/28), (18/28)

MAIN PWB (18/28)

MAIN PWB (3/28)

R81
103/1005

C82

104p/16V/1005

MAIN PWB (3/28)

MAIN PWB (23/28)

MAIN PWB (3/28)

MAIN PWB (19/28)

+5VSTB +5VSTB

B B

R104

R104
103/1005

103/1005

MOD1_ID MOD2_ID

R106

R106
OPEN-103/1005

OPEN-103/1005

System Reset

R82
101/1005

AM_LED_Ctrl

Alarm_LED_Ctrl

PM_LED_Ctrl

+5VSTB

RESETn

SPI_STR
SPI_CLK

CEC_A
CEC_O

STBY_EN

SPI_DIO

IR_IN

Scart_Mute

OPEN_103/1005

+5VSTB

R110

R110
OPEN-103/1005

OPEN-103/1005

RA

TA

R93

MOSI
MISO
SCK

MOD3_ID

R95 101/1005
R91 101/1005

4

+5VSTB

R83
OPEN_103/1005

R84 101/1005

+5VSTB

C87

OPEN-103p/50V/1005

3

C83

106p/16V/2012

+5VSTB +5VSTB

C84

104p/16V/1005

U82

5

VCC1

17

VCC2

38

VCC3

40

PB0 (XCK/T0)

41

PB1 (T1)

42

PB2 (AIN0/INT2)

43

PB3 (AIN1/OC0)

44

PB4 (SS)

1

PB5 (MOSI)

2

PB6 (MISO)

3

PB7 (SCK)

9

PD0 (RXD)

10

PD1 (TXD)

11

PD2 (INT0)

12

PD3 (INT1)

13

PD4 (OC1B)

14

PD5 (OC1A)

15

PD6 (ICP)

16

PD7 (OC2)

6

GND1

18

GND2

28

GND3

39

GND4

ATMEGA324P-20AU

C85

104p/16V/1005

(ADC0) PA0
(ADC1) PA1
(ADC2) PA2
(ADC3) PA3
(ADC4) PA4
(ADC5) PA5
(ADC6) PA6
(ADC7) PA7

(SCL) PC0
(SDA) PC1

(TCK) PC2
(TMS) PC3
(TDO) PC4

(TDI) PC5
(TOSC1) PC6
(TOSC2) PC7

RESETn

XTAL2
XTAL1

C86

104p/16V/1005

AVCC

AREF

27
37
36
35
34
33
32
31
30
29

19
20
21
22
23
24
25
26

4

7
8

Address:0xAA

MISO
SCK
RESETn

MOD3_ID
MOD2_ID
MOD1_ID

CDS_OUT

R89 330/1005
R90 330/1005

R94 101/1005
R92 000/1005

RESETn

R96 000/1005

16MHZ/20pF/SMD

C88
200p/50V/1005

12

JP81

HPH-DS06-02

12
34
56

KEY_ADC2
KEY_ADC1
LED_B
LED_R

MAIN PWB (3/28)

M_SCL
M_SDA
INT_OUT
M_RST_N

AC_DETECT
A_RESET

OPEN-160p/1005

C89
200p/50V/1005

2

+5VSTB +5VSTB

MOSI

MAIN PWB
(3/28)

MAIN PWB

M_SCL
M_SDA

(15/28)

MAIN PWB
(3/28),(19/28),(22/28)

MAIN PWB (22/28)

C92

1

223

Open_32.768kHz/12.5pF/SMD

+5VSTB

R87
272/1005

441

3

Y82

+3V3_A

R88
272/1005

32
32

INT_OUT

C93

OPEN-160p/1005

R97 162/1005R97 162/1005

R98 162/1005R98 162/1005

Q81

1

FDV301N_NL

Q82
FDV301N_NL

1

R102 103/1005Y81

+5VSTB

FLI_SCL1
FLI_SDA1

1

KEY_ADC2

KEY_ADC1

C90

104p/16V/1005

C91

104p/16V/1005

MAIN PWB (6/28),(16/28),(22/28)

FLI_INT

R103
183/F/1005

+3V3_A

MAIN PWB
(6/28)

R105

R105
OPEN-103/1005

OPEN-103/1005

A A

R107

R107
103/1005

103/1005

R129

R129
103/1005

103/1005

MAIN PWB ASS'Y (5/28)

M_RST_N

L : Normal
H : Reset

R99
103/1005

R101
102/1005

1

23

R100
103/1005

Q83
MMBT4401

LPM_RST_N

[MICRO CTRL]

HU-71100004

All location are from 81 to 110

5

4

3

2

1

lt-19db1bu_0514_3/30_0.0

2-16(No.YA697<Rev.001>)(No.YA697<Rev.001>)2-15

MAIN PWB CIRCUIT DIAGRAM (6/28) [Douglas_USB,I2C,JTAG]

5

4

3

2

1

UART0 : PC Display Debug message

UART1 : G-Probe application run at PC & Serial command

I2C0 : FLI_SDA1 , FLI_SCL1 (Micom,eeprom,HDMI switch, Audio Amp)

D D

C C

B B

A A

I2C1 : FLI_SDA0 , FLI_SCL0 (Demode IC , LNB IC)

+3V3_A

(26/28),(27/28),(28/28)

MAIN PWB

MAIN PWB

(5/28),(16/28),(22/28)

MAIN PWB (23/28)

MAIN PWB (13/28)

MAIN PWB (9/28)
MAIN PWB (5/28)

FLI_SDA0

FLI_SCL0

FLI_SDA1

FLI_SCL1

UART1_RX
UART1_TX

C117

104p/16V/1005

C125
5R0p/50V/1005

R133
OPEN-153/1005

P_DIM
A_DIM

CI_PWR

FLI_INT

R128
622/F/1005

R113 222/1005
R115 222/1005
R116 222/1005
R117 222/1005

FLI_SDA0
FLI_SCL0

FLI_SDA1
FLI_SCL1

UART0_RX
UART0_TX

UART1_RX
UART1_TX

+3V3_A

OPEN-153/1005

R137
103/1005

L111

BLM18PG300SN1D

C118

47uF/16V/MVK/S

R134

+5V

R138

103/1005

R120 330/1005
R118 330/1005

R119 330/1005
R121 330/1005

TP116

PCB_TP08

TP113

PCB_TP08

C119

105p/16V/1005

L113
ACM2012H-900

4

C126

5R0p/50V/1005

R139
000/1005

21

3

R5523N USB HIGH-SIDE POWER SWITCH

1
1

USB_D0+
USB_D0-

C120

104p/16V/1005

C121

104p/16V/1005

OPEN-AVRL161A1R1NTB

OPEN-AVRL161A1R1NTB

1

EN

OUT

3

GND

FLG

U104

RV111

RV112

IN

U112G
&MPEG2_ONECHIP FLI10610H

D21

2WIRE_M1_SDA_UART2_TX

D20

2WIRE_M1_SCL_UART2_RX

F20

2WIRE_M0_SDA

E20

2WIRE_M0_SCL

A19

UART0_RXD

B19

UART0_TXD

A20

UART1_RXD

B20

UART1_TXD

C20

UART1_RTS

C19

UART1_CTS

A13

PWM3

B13

PWM2_GPIO6

C13

PWM1_GPIO5_/INT5

D13

PWM0_GPIO4_/INT4

C29

USB_FLAG

C28

USB_PWREN

AJ20

USBPHY_PADP

AH20

USBPHY_PADM

AG20

USBPHY_VRES

AG19

USB_AVDD33

AH19

USB_AVDD33

AF20

USB_AVDD33

AF19

USB_GND

AJ19

USB_GND

AD20

USB_GND

+5V_USB

+5V

C127

106p/16V/2012

5
4
2

L114
BLM21PG600SN1D

OTP_VDD33

RESET_N

REF_CLK

XTAL_IN

CLKOUT

OBUFC_CLK

EJ_RST_N

EJ_DINT

DFSYNC_IN_OUT_GPIO8

TESTMODE0
TESTMODE1

USB_AVDD12

JP112
KJA-UB-4-0004

1

VBUS

SGND

1

2

D-

2

3

D+

3

4

GND

SGND

4

C128

104p/16V/1005

TRST

TDI
TDO
TMS

TCK

5

6

A26

D23

A22
A23

E12

F21

B26
B27
A27
A28
B28
A29
B29

E13

C27
C26

AE20

C123

104p/16V/1005

+5V_USB

C129

100uF/25V/BXE/S

TP112

PCB_TP08

1

TP111

1

PCB_TP08

NVRAM_WP

TRST#
TDI
TDO
TMS
TCK
EJTAG_RST#
DINT

C112

OPEN-680p/1005

R122 000/1005

TP114

1
1

TP115

+3V3_A

PWR_/RESET

19.6608MHZ/
20PF/SX-1/SMD

C113

C113

270p/50V/1005

270p/50V/1005

PCB_TP08

PCB_TP08

L112
BLM18PG300SN1D

C124

106p/10V/2012

R111
OPEN-104/1005

R114
OPEN-104/1005

MAIN PWB (8/28)

Y111

12

R124 OPEN-000

BLT_EN

+1V2

MAIN PWB ASS'Y (6/28)
[Douglas_USB,I2C,JTAG]

U111

OPEN-ASM811REUSF-T

1

GND

2

RESET

Reset Threshole
: +3.08V

R112 000/1005R112 000/1005

C114

C114

270p/50V/1005

270p/50V/1005

VCC

+3V3_A

+3V3_A

MAIN PWB (13/28)

+3V3_A

4

3

MR

R123 102/1005
PR111 103*4/1005

18
27
36
45

R126 102/1005
R127 103/1005
C115 200p/50V/1005

EEPROM

Address:0xA4/A5

12

34

U113
24LC256

1

A0

2

A1

3

A2

4

VSS

OPEN-JTP1127WEM

R125 200/1005

8

VCC

7

WP

6

SCL

5

SDA

S111

LPM_RST_N

JP111
OPEN-2110-DS14-G

1

2

3

4

5

6

7

8

9

10

11

12

13 14

MAIN PWB (5/28)

+3V3_A

EJTAG

+3V3_A +3V3_A

C122
104p/16V/1005

FLI_SCL1
FLI_SDA1

WP

Q111
MMBT4401

UART0 : Message

JP113

1

2mm

OPEN

2
3
4

OPEN-53014-0410

C116

104p/16V/1005

R131
103/1005

R132
103/1005

1

NVRAM_WP : H = Enable write

23

NVRAM_WP : L = Disable write

+5V

R135

472/1005

NVRAM_WP

R136

472/1005

UART0_TX
UART0_RX

All location are from 111 to 160

HU-71100004

5

4

3

2

1

lt-19db1bu_0514_4/30_0.0

(No.YA697<Rev.001>)2-17 2-18(No.YA697<Rev.001>)

MAIN PWB CIRCUIT DIAGRAM (7/28) [Douglas I2S and FLEX ROM CONNECTOR]

5

+3V3_A

D D

MAIN PWB

(19/28)

MAIN PWB

SCART1_ID
SCART2_ID

(20/28)

C C

B B

MAIN PWB

L161

BLM18PG300SN1D

C161

106p/10V/2012

SCART1_ID
SCART2_ID

TP166

LBADC_IN1
LBADC_IN2
LBADC_IN3
LBADC_IN6

SCART1_ID
SCART2_ID

C165

103p/50V/1005

(8/28)

POD_CI

C162
104p/16V/1005

LBADC_IN1
LBADC_IN2
LBADC_IN3

LBADC_IN6

PCB_TP08

1

R175 103/1005
R176 103/1005
R177 103/1005
R178 103/1005

C166

103p/50V/1005

Model1_ID
Model2_ID
Model3_ID
Model4_ID

U112D
&MPEG2_ONECHIP FLI10610H

D24

LBADC_33

E23

LBADC_GND

C25

LBADC_IN1

C24

LBADC_IN2

B25

LBADC_IN3

B24

LBADC_IN4

A25

LBADC_IN5

A24

LBADC_IN6

F22

LBADC_RETURN

C21

IRDATA

U112F
&MPEG2_ONECHIP FLI10610H

A18

VXI_CLK

C18

VXI_DE

B18

VXI_VS

D18

VXI_HS

E19

VXI_D0

A17

VXI_D1

B17

VXI_D2

C17

VXI_D3

D17

VXI_D4

F17

VXI_D5

A16

VXI_D6

B16

VXI_D7

C16

VXI_D8

D16

VXI_D9

D19

VXI_D10

E16

VXI_D11

A15

VXI_D12

B15

VXI_D13

C15

VXI_D14

D15

VXI_D15

E15

VXI_D16

A14

VXI_D17

B14

VXI_D18/TS_ERR

C14

VXI_D19/DREQ_I

D14

VXI_D20/TS_VALID_O

E14

VXI_D21/TS_SYNC_O

E17

VXI_D22/TS_D_O

E18

VXI_D23/TS_CLK_O

4

AUDIN_I2S_BCLK

AUDIN_I2S_WCLK

AUDIN_I2S_DAT

AUD_MCLK0
AUD_MCLK1

AUDO_I2SA_BCLK

AUDO_I2SA_WCLK

AUDO_I2SA_DAT0
AUDO_I2SB_DAT1
AUDO_I2SB_DAT2

AUDO_I2SB_BCLK

AUDO_I2SB_WCLK

AUDIN_SPDIF_IN

AUDO_SPDIF_OUT

VXO_D0
VXO_D1
VXO_D2
VXO_D3
VXO_D4
VXO_D5
VXO_D6
VXO_D7
VXO_D8

VXO_D9
VXO_D10
VXO_D11
VXO_D12
VXO_D13
VXO_D14
VXO_D15

VXO_HS

VXO_VS

VXO_CLK

VXO_DE

AF15
AH16
AJ16
AE15
AE16
AF16
AG16
AH17
AJ17
AE17
AF17
AG17
AH18
AJ18
AD15
AE18

AF18
AG18
AD19
AE19

AC2
AB3
AA4

AC1
AB5

AB4
AC5
AC4
AD2
AE2

AC3
AD3

AA5

AD1

HEADPHONE_ID

R166 000/1005

HEADPHONE_ID

R167 000/1005
R179 000/1005

R165 000/1005

I2S_OUT_MCLK

I2S_OUT_CLK
I2S_OUT_WS
I2S_OUT_DAT

SPDIF_OUT

R162 103/1005

TS_SEL
CH_TER_RESET
HEADPHONE_ID

CH_RESET
POD_TER#
ANT_PWR_EN
ANT_PWR_CHK

SC1_SEL
SC_FB_SEL
PD_RESET
VGA_SW

3

MAIN PWB (22/28)

MAIN PWB (15/28)

+3V3_A

MAIN PWB (24/28)

MAIN PWB (26/28)
MAIN PWB (22/28)

MAIN PWB (28/28)
MAIN PWB (8/28)

MAIN PWB (1/28)

MAIN PWB (12/28)

MAIN PWB (16/28)

MAIN PWB (15/28)

MAIN PWB (15/28)

HOST_A[24..0]

MAIN PWB (8/28)

HOST_A1
HOST_A2
HOST_A3
HOST_A4
HOST_A5
HOST_A6
HOST_A7
HOST_A8
HOST_A9
HOST_A10
HOST_A11
HOST_A12
HOST_A13
HOST_A14
HOST_A15
HOST_A16
HOST_A17
HOST_A18
HOST_A19
HOST_A20

HOST_A22
HOST_A23
HOST_A24

DG_PE1

HOST_CS#

HOST_A21

HOST_CS0#

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1

2

R1100
222/1005

OPEN-104p/16V/1005

C1100

TP1639 PCB_TP10
TP1643 PCB_TP10
TP1647 PCB_TP10
TP1651 PCB_TP10
TP1655 PCB_TP10
TP1659 PCB_TP10
TP1663 PCB_TP10
TP1667 PCB_TP10
TP1671 PCB_TP10
TP1675 PCB_TP10
TP1679 PCB_TP10
TP1683 PCB_TP10
TP1687 PCB_TP10
TP1691 PCB_TP10
TP1695 PCB_TP10
TP1699 PCB_TP10
TP1703 PCB_TP10
TP1707 PCB_TP10
TP1711 PCB_TP10
TP1715 PCB_TP10

TP1718 PCB_TP10
TP1720 PCB_TP10
TP1721 PCB_TP10

+5V +3V3_A

R1101
222/1005

Q1100

1

MMBT4401

23

To Bottum side

TP1640PCB_TP10
TP1644PCB_TP10
TP1648PCB_TP10
TP1652PCB_TP10
TP1656PCB_TP10
TP1660PCB_TP10
TP1664PCB_TP10
TP1668PCB_TP10
TP1672PCB_TP10
TP1676PCB_TP10
TP1680PCB_TP10
TP1684PCB_TP10
TP1688PCB_TP10
TP1692PCB_TP10
TP1696PCB_TP10
TP1700PCB_TP10
TP1704PCB_TP10
TP1708PCB_TP10
TP1712PCB_TP10
TP1716PCB_TP10

#CS_FLASH_DG

1

TP1631 PCB_TP10

1

TP1632 PCB_TP10

1

TP1633 PCB_TP10

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

#CS_FLASH_DG

HOST_D0
HOST_D1
HOST_D2
HOST_D3
HOST_D4
HOST_D5
HOST_D6
HOST_D7
HOST_D8
HOST_D9
HOST_D10
HOST_D11
HOST_D12
HOST_D13
HOST_D14

HOST_D15
#CS_FLASH_DG
DG_PE1

C1101

104p/16V/1005

C1102
106p/10V/2012

1

MAIN PWB (8/28)

MAIN PWB (8/28)

HOST_D[15..0]

+5V

+3V3_A

Model1_ID

R173 OPEN-103/1005
R170 OPEN-103/1005
R171 OPEN-103/1005
R172 OPEN-103/1005

A A

R163 103/1005
R164 103/1005

Model2_ID

R168 OPEN-103/1005

Model3_ID
Model4_ID

R169 OPEN-103/1005

MAIN PWB ASS'Y (7/28)

+3V3_A

POD_CI

All location are from 161 to 180

5

R174 103/1005R174 103/1005

[Douglas I2S and FLEX ROM CONNECTOR]

HU-71100004

4

3

2

1

lt-19db1bu_0514_5/30_29/30_0.0

2-20(No.YA697<Rev.001>)(No.YA697<Rev.001>)2-19

MAIN PWB CIRCUIT DIAGRAM (8/28) [Douglas Flash & CI Interface]

5

U112C
&MPEG2_ONECHIP FLI10610H

Flash_WP#

D D

POD_DET#
POD_DAT_DIR

POD_A4
POD_A5
POD_A6
POD_A7
POD_A8
POD_A9
POD_A14

STREAM_CLK
STREAM_VAL
STREAM_SYNC

STREAM_D7
STREAM_D6
STREAM_D5
STREAM_D4
STREAM_D3
STREAM_D2
STREAM_D1

C C

CI_WAIT_N

MAIN PWB

(9/28)

CI_CD1_N
CI_CD2_N
CI_CE1_N

CI_IRQ_N CI_IOWR_N

CI_RESET

STREAM_D0

CI_WAIT_N

CI_CD1_N
CI_CD2_N
CI_CE1_N

CI_IRQ_N
CI_RESET

Bootstrap Pin Name

BSTRAP_BOOT_MODE

B B

BSTRAP_EXT_OSC

BSTRAP_16BIT_FLASH

BSTRAP_NAND_FLASH_EN

BSTRAP_PAGESIZE

BSTRAP_NAND_FLASH_DWIDTH

A A

BSTRAP_NOR_FLASH_SEL

W1
W2
W3

AD4
AD5

AE3

AF3
AF2

AG2

AF1

AG1

W5

W6

Y5
Y4

AB1
AA1

Y1
AB2
AA2

Y2
AA3

Y3

V3

V5

V4
AE4

W4

V2

V1

POD_HOST_A0
POD_HOST_A1

POD_HOST_A2

POD_HOST_A3

POD_HOST_A4

POD_HOST_A5

POD_HOST_A6

POD_HOST_A7

OOB_CTX
OOB_CRX
OOB_DRX

POD_DETEC_N
POD_DIR_N

POD_A4_CTX
POD_A5_ITX
POD_A6_ETX
POD_A7_QTX
POD_A8_CRX
POD_A9_DRX
POD_A14_MCLKO

POD_VS2_MCLKO
POD_BVD2_MOVAL
POD_BVD1_MOSTRT

POD_D15_MDO7
POD_D14_MDO6
POD_D13_MDO5
POD_D12_MDO4
POD_D11_MDO3
POD_D10_MDO2
POD_D9_MDO1
POD_D8_MDO0

POD_WAIT_N

POD_CD1
POD_CD2
POD_CE_1
POD_CE_2

POD_READY_IRQ_N
POD_RESET

Description

Pins POD_HOST_A[1:0] indicate on chip
hardware the host interface configuration
to use after hard reset:
A1;A0 = 00 = Function test, vendor mode.
A1;A0 = 01 = Function test, vendor mode.
A1;A0 = 10 = Boot from FLASH
A1;A0 = 11 = Boot from IROM

Pin POD_HOST_A2 indicates:
0 = Internal osc
1 = External osc

Pin POD_HOST_A3 indicates type of
memory for external boot FLASH.
0 = 8-bit FLASH
1 = 16-bit FLASH

Pin PODREG_HOST_A4 indicates type of
memory for external boot FLASH.
0 = NOR FLASH
1 = NAND FLASH

Pin POD_IOWR_HOST_A5 indicates page
size for off chip NAND FLASH.
0 = Small page NAND FLASH
1 = Large page NAND FLASH

Pin POD_IORD_HOST_A6 indicates data
width for NAND FLASH (used by IROM
boot s/w only).
0 = 8-bit NAND FLASH
1 = 16-bit NAND FLASH

Pin HOST_A[7] selects whether parallel
NOR flash or SPI flash is used for boot
when BSTRAP_BOOT_MODE=10 (IROM
bypass). Ignored if
BSTRAP_BOOT_MODE != 10.
0 = boot from parallel NOR flash
1 = boot from SPI flash

POD_HOST_D0/SPI_SDI

POD_HOST_D1
POD_HOST_D2
POD_HOST_D3
POD_HOST_D4
POD_HOST_D5
POD_HOST_D6
POD_HOST_D7

HOST_D8

HOST_D9
HOST_D10
HOST_D11
HOST_D12
HOST_D13
HOST_D14
HOST_D15

POD_HOST_A0
POD_HOST_A1

POD_HOST_A2/SPI_SDO

POD_HOST_A3/SPI_CLK

POD_REG_HOST_A4

POD_IOWR_HOST_A5

POD_IORD_HOST_A6

POD_WE_HOST_WR

HOST_A7
HOST_A8

HOST_A9
POD_HOST_A10
POD_HOST_A11
POD_HOST_A12
POD_HOST_A13

HOST_A14
HOST_A15
HOST_A16
HOST_A17
HOST_A18
HOST_A19
HOST_A20
HOST_A21
HOST_A22
HOST_A23
HOST_A24

POD_OE_HOST_RD

HOST_ACK

HOST_DEV_CS2_N
HOST_DEV_CS1_N
HOST_DEV_CS0_N

HOST_BOOT_CS_N

HOST_READY

AG7
AJ8
AG8
AE7
AH9
AF9
AJ10
AG10
AF7
AH8
AE8
AJ9
AG9
AE9
AH10
AF10

AJ15
AH15
AG15
AE14
AF14
AG14
AH14
AJ14
AE13
AF12
AG12
AH12
AJ12
AE11
AF11
AG11
AH11
AE10
AF13
AG13
AE12
AD13
AH13
AJ11
AD9

AJ13
AF8

AG3

AE5
AF4
AJ4
AG6

AH5

All location are from 181 to 220

5

4

+1V8

L26

HOST_D0
HOST_D1
HOST_D2
HOST_D3
HOST_D4
HOST_D5
HOST_D6
HOST_D7
HOST_D8
HOST_D9
HOST_D10
HOST_D11
HOST_D12
HOST_D13
HOST_D14
HOST_D15

HOST_A0
HOST_A1
HOST_A2
HOST_A3
HOST_A4
HOST_A5
HOST_A6
HOST_A7
HOST_A8
HOST_A9
HOST_A10
HOST_A11
HOST_A12
HOST_A13
HOST_A14
HOST_A15
HOST_A16
HOST_A17
HOST_A18
HOST_A19
HOST_A20
HOST_A21
HOST_A22
HOST_A23
HOST_A24

HOST_WE#
HOST_OE#

HOST_ACK

HOST_CS0#

HOST_CS#

HOST_RD

POD_DET#
HOST_CS#
HOST_RD
HOST_ACK

NOTE.
64 MBit FLASH : R203, R204, L26 OPEN
128 MBit FLASH : R204, L26 OPEN
256 MBit FLASH : L27 OPEN(P30 Series)
L26 OPEN (P33 Series)

R184 OPEN-103/1005

R183 472/1005
R205 103/1005

OPEN-BLM18PG300SN1D

+3V3_A

L27

BLM18PG300SN1D

HOST_A23
HOST_A24

PCB_TP08

MAIN PWB (7/28)

HOST_CS0#
HOST_CS#

STREAM_CLK
STREAM_VAL
STREAM_SYNC

MAIN PWB (7/28)

+3V3_A

BOOT STRAP SETTING

R187 103/1005
R189 OPEN-103/1005
R191 103/1005
R193 OPEN-103/1005
R195 103/1005
R197 103/1005
R199 OPEN-103/1005
R201 103/1005

4

HOST_A0
HOST_A1
HOST_A2
HOST_A3
HOST_A4
HOST_A5
HOST_A6
HOST_A7

C193

104p/16V/1005

HOST_A1

HOST_A2
HOST_A3
HOST_A4
HOST_A5
HOST_A6
HOST_A7
HOST_A8
HOST_A9
HOST_A10
HOST_A11
HOST_A12
HOST_A13
HOST_A14
HOST_A15
HOST_A16
HOST_A17
HOST_A18
HOST_A19
HOST_A20
HOST_A21
HOST_A22

R203 000/1005
R204 000/1005

TP186

1

Flash_WP#

HOST_A[24..0]

STREAM_D0
STREAM_D1
STREAM_D2
STREAM_D3
STREAM_D4
STREAM_D5
STREAM_D6
STREAM_D7

+3V3_D

C185

104p/16V/1005

+3V3_D

C186

104p/16V/1005

R188 OPEN-103/1005
R190 103/1005
R192 OPEN-103/1005
R194 103/1005
R196 OPEN-103/1005
R198 OPEN-103/1005
R200 103/1005
R202 OPEN-103/1005

C194

104p/16V/1005

A1

A1

B1

A2

C1

A3

D1

A4

D2

A5

A2

A6

C2

A7

A3

A8

B3

A9

C3

A10

D3

A11

C4

A12

A5

A13

B5

A14

C5

A15

D7

A16

D8

A17

A7

A18

B7

A19

C7

A20

C8

A21

A8

A22

G1

A23

H8

A24

B6

NC(A25)

H1

RFU1

G2

RFU2

F1

RFU3

E8

RFU4

B8

RFU5

A4

VPP

R206
472/F/1005

U185
SN74LVC244APWR

18

1Y1

16

1Y2

14

1Y3

12

1Y4

9

2Y1

7

2Y2

5

2Y3

3

2Y4

20

VCC

10

DGND

U187
SN74LVC244APWR

18

1Y1

16

1Y2

14

1Y3

12

1Y4

9

2Y1

7

2Y2

5

2Y3

3

2Y4

20

VCC

10

DGND

+3V3_A

3

H3

VCCA6VCC

VCCQD5VCCQD6VCCQ

VSSB2VSSH2VSSH4VSS

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

1G
2G

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

1G
2G

STREAM_D0
STREAM_D1
STREAM_D2
STREAM_D3
STREAM_D4
STREAM_D5
STREAM_D6
STREAM_D7

+3V3_D

C195

104p/16V/1005

3

U181

G4

PC28F256P33B85

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

CE

OE
WE
WP

ADV
CLK

RST

WAIT

H6

2
4
6
8
11
13
15
17

1
19

PPKT_CLK

2

PPKT_VAL

4

PPKT_SYNC

6
8
11
13
15
17

1
19

F2
E2
G3
E4
E5
G5
G6
H7
E1
E3
F3
F4
F5
H5
G7
E7

B4
F8
G8
C6
F6
E6

D4

F7

PPKT_D0
PPKT_D1
PPKT_D2
PPKT_D3
PPKT_D4
PPKT_D5
PPKT_D6
PPKT_D7

POD_CI

C181

104p/16V/1005

HOST_D0
HOST_D1
HOST_D2
HOST_D3
HOST_D4
HOST_D5
HOST_D6
HOST_D7
HOST_D8
HOST_D9
HOST_D10
HOST_D11
HOST_D12
HOST_D13
HOST_D14
HOST_D15

#CS_FLASH_DG

HOST_OE#
HOST_WE#

R207

330/1005

POD_CI

PPKT_CLK

PPKT_VAL

PPKT_SYNC

MUX_TSI_CLK
MUX_TSI_VAL
MUX_TSI_SYNC

POD_CI
POD_TER#

U188
SN74LVC244APWR

18

1Y1

16

1Y2

14

1Y3

12

1Y4

9

2Y1

7

2Y2

5

2Y3

3

2Y4

20

VCC

10

DGND

2

+3V3_A

C187

104p/16V/1005

C182

106p/10V/2012

HOST_D[15..0]

MAIN PWB (7/28)

C183

104p/16V/1005

+3V3_A

MAIN PWB (7/28)

#CS_FLASH_DG

R185
103/1005

CI_CE1_N

MAIN PWB (6/28)

PWR_/RESET

HOST_WE#

HOST_OE#

PPKT_D[7..0]

NOTE.
FREE CH : POD_TER# L , POD_DET# H
CI : POD_TER# H , POD_DET# L

MAIN PWB
(9/28)

MAIN PWB
(7/28)

2

1A1

4

1A2

6

1A3

8

1A4

11

2A1

13

2A2

15

2A3

17

2A4

1

1G

19

2G

MAIN PWB (9/28)

MAIN PWB

(24/28)

MAIN PWB

MUX_TSI_D0
MUX_TSI_D1
MUX_TSI_D2
MUX_TSI_D3
MUX_TSI_D4
MUX_TSI_D5
MUX_TSI_D6
MUX_TSI_D7

MUX_TSI_SYNC

(24/28)

MUX_TSI_CLK
MUX_TSI_VAL

POD_TER#

R208 330/1005
R209 330/1005

MUX_TSI_D0
MUX_TSI_D1
MUX_TSI_D2
MUX_TSI_D3
MUX_TSI_D4
MUX_TSI_D5
MUX_TSI_D6
MUX_TSI_D7

MAIN PWB ASS'Y (8/28)
[Douglas Flash & CI Interface]

HU-71100004

MAIN PWB (7/28)

2

HOST_D0
HOST_D1
HOST_D2
HOST_D3
HOST_D4
HOST_D5
HOST_D6
HOST_D7

+3V3_D

POD_A4
POD_A5
POD_A6
POD_A7
POD_A8
POD_A9
POD_A14

R210 OPEN-000/1005

POD_DET#
Flash_WP#WP#

R186
OPEN-000/1005

HOST_A0
HOST_A1
HOST_A2
HOST_A3
HOST_A10
HOST_A11
HOST_A12
HOST_A13

HOST_A4
HOST_A5
HOST_A6
MUX_TSI_CLK
MUX_TSI_VAL
MUX_TSI_SYNC

POD_DET#

MUX_TSI_D0
MUX_TSI_D1
MUX_TSI_D2
MUX_TSI_D3
MUX_TSI_D4
MUX_TSI_D5
MUX_TSI_D6
MUX_TSI_D7

POD_DET#

U182
SN74LVC245APWR

18

B0

17

B1

16

B2

15

B3

14

B4

13

B5

12

B6

11

B7

20

VCC

10

GND

U183
SN74LVC244APWR

2

1A1

4

1A2

6

1A3

8

1A4

11

2A1

13

2A2

15

2A3

17

2A4

1

1G

19

2G

U184
SN74LVT16244B

47

1A1

46

1A2

44

1A3

43

1A4

41

2A1

40

2A2

38

2A3

37

2A4

36

3A1

35

3A2

33

3A3

32

3A4

30

4A1

29

4A2

27

4A3

26

4A4

1

1G

48

2G

25

3G

24

4G

45

GND

39

GND

34

GND

28

GND

U186
SN74LVC244APWR

2

1A1

4

1A2

6

1A3

8

1A4

11

2A1

13

2A2

15

2A3

17

2A4

1

1G

19

2G

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

+5V

DGND

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4

VCC
VCC
VCC
VCC

GND
GND
GND
GND

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

+5V

DGND

T/R

/OE

1

CI_D[7..0]

MAIN PWB (9/28)

CI_A[14..0]

CI_CE1_N#

MAIN PWB

(9/28)

MAIN PWB
(9/28)

C191

104p/16V/1005R182 103/1005

C190

MDO_D[7..0]

MAIN PWB (9/28)

POD_DAT_DIR
POD_DET#

CI_A4
CI_A5
CI_A6
CI_A7
CI_A8
CI_A9
CI_A14

+3V3_D

C184
104p/16V/1005

CI_A0
CI_A1
CI_A2
CI_A3
CI_A10
CI_A11
CI_A12
CI_A13

MDO_CLK
MDO_VAL
MDO_SYNC

104p/16V/1005

C188

104p/16V/1005

MDO_D0
MDO_D1
MDO_D2
MDO_D3
MDO_D4
MDO_D5
MDO_D6
MDO_D7

+3V3_D

CI_D0
CI_D1
CI_D2
CI_D3
CI_D4
CI_D5
CI_D6
CI_D7

CI_WE_N
CI_OE_N
CI_REG_N

CI_IORD_N
MDO_CLK
MDO_VAL
MDO_SYNC

C189

104p/16V/1005

C192
104p/16V/1005

1

2

A0

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

1
19

18
16
14
12
9
7
5
3

20
10

2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23

+3V3_D

7
18
31
42

4
10
15
21

18
16
14
12
9
7
5
3

20
10

(No.YA697<Rev.001>)2-21 2-22(No.YA697<Rev.001>)

lt-19db1bu_0514_6/30_0.0

MAIN PWB CIRCUIT DIAGRAM (9/28) [CI Slot]

5

VCC_CI

R221

103/1005

R130

R239
000/1005

+3V3_A

D D

CI_CE1_N#

Open_000/1005

CI_CE1_N

CI_OE_N

MAIN PWB

(8/28)

C C

B B

CI_WE_N

CI_IRQ_N

CI_D[7..0]

CI_A[14..0]

VCC_CI

R223
103/1005

CI_D0
CI_D1
CI_D2
CI_D3
CI_D4
CI_D5
CI_D6
CI_D7

CI_A0
CI_A1
CI_A2
CI_A3
CI_A4
CI_A5
CI_A6
CI_A7
CI_A8
CI_A9
CI_A10
CI_A11
CI_A12
CI_A13
CI_A14

R224
103/1005

R225
103/1005 R229

CI_OE_N

VCC_CI

R233 103/1005

CI_D3
CI_D4
CI_D5
CI_D6
CI_D7

CI_A10

CI_A11
CI_A9
CI_A8
CI_A13
CI_A14
CI_WE_N
CI_IRQ_N

CI_MIVAL
CI_MCLKI
CI_A12
CI_A7
CI_A6
CI_A5
CI_A4
CI_A3
CI_A2
CI_A1
CI_A0
CI_D0
CI_D1
CI_D2

4

C221

104p/16V/1005

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

R222
121/5025

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

696970

70

JP221

A01C5A0045P1P00/1-SLOT

C222
104p/16V/1005

CI_CD1_N
CI_MDO_3
CI_MDO_4
CI_MDO_5
CI_MDO_6
CI_MDO_7

R232 103/1005

CI_IORD_N
CI_IOWR_N
CI_MISTART
CI_MDI_0
CI_MDI_1
CI_MDI_2
CI_MDI_3

CI_MDI_4
CI_MDI_5
CI_MDI_6
CI_MDI_7
CI_MCLKO
CI_RESET
CI_WAIT_N

CI_REG_N
CI_MOVAL
CI_MOSTART
CI_MDO_0
CI_MDO_1
CI_MDO_2
CI_CD2_N

+3V3_A +3V3_AVCC_CI

R226

103/1005

R227

103/1005

VCC_CI

VCC_CI

R238
103/1005

3

R228

103/1005

104/1005

104p/16V/1005

R230

103/1005

C229

R231

103/1005

CI_CD1_N

C228

104p/16V/1005

CI_IORD_N
CI_IOWR_N

CI_RESET

CI_WAIT_N

CI_REG_N

CI_CD2_N

MAIN PWB (8/28)

CI_MCLKO

2

TS INPUT

CI_MDI_0
CI_MDI_1
CI_MDI_2
CI_MDI_3
CI_MDI_4
CI_MDI_5
CI_MDI_6
CI_MDI_7

CI_MISTART
CI_MIVAL

CI_MCLKI MDO_CLK

PR221

18

330*4/1005

27
36
45

PR222

18

330*4/1005

27
36
45

PR223

18

330*4/1005

27
36
45

MDO_D0
MDO_D1
MDO_D2
MDO_D3
MDO_D4
MDO_D5
MDO_D6
MDO_D7

MDO_SYNC
MDO_VAL

TS OUTPUT

CI_MDO_0
CI_MDO_1
CI_MDO_2
CI_MDO_3
CI_MDO_4
CI_MDO_5
CI_MDO_6
CI_MDO_7

CI_MOSTART
CI_MOVAL

M_CLK

PR224

18

330*4/1005

27
36
45

PR225

18

330*4/1005

27
36
45

PR226

18

330*4/1005

27
36
45

PPKT_D0
PPKT_D1
PPKT_D2
PPKT_D3
PPKT_D4
PPKT_D5
PPKT_D6
PPKT_D7

PPKT_SYNC
PPKT_VAL

PPKT_CLK

These all of components must be located near Douglas

U221

OPEN-74HC14

R234 000/1005

M_CLK

R108

Open_000/1005

1

A1

2

O1

3

A2

4

O2

5

A3

6

O3

7

DGND

+5V

14
13

A6

12

O6

11

A5

10

O5

9

A4

8

O4

+3V3_A

1

MDO_D[7..0]

MDO_SYNC
MDO_VAL

MDO_CLK

PPKT_D[7..0]

PPKT_SYNC
PPKT_VAL

PPKT_CLK

R109

Open_000/1005

MAIN PWB
(8/28)

MAIN PWB
(8/28)

M_CLK

+5V

C223

C224

1

23

C224
Open-475p/16V/3216

Open-475p/16V/3216

Q221

Q221

IRLML6402TRPBF

IRLML6402TRPBF

C226

C226

106p/10V/2012

106p/10V/2012

Q222

Q222
MMBT4401

MMBT4401

2

1

3

R235

R235

472/1005

472/1005

C225

+3V3_A

A A

R236

R236
752/1005

752/1005

R237

MAIN PWB (6/28)

CI_PWR

R237
332/1005

332/1005

C225

Open-682p/50V/1005

Open-682p/50V/1005

C223

104p/16V/1005

104p/16V/1005

VCC_CI

C227

C227
106p/10V/2012

106p/10V/2012

MAIN PWB ASS'Y (9/28)
[CI Slot]

HU-71100004

All location are from 221 to 250

5

4

3

2

1

lt-19db1bu_0514_7/30_0.0

2-24(No.YA697<Rev.001>)(No.YA697<Rev.001>)2-23

MAIN PWB CIRCUIT DIAGRAM (10/28) [Douglas DDR Interface]

5

VDDR_MEM

D D

F25

F27

F29

H24

H27

H29

K25

K27

K29

M29

AF25

D25

SDDR_D0
SDDR_D1
SDDR_D2
SDDR_D3
SDDR_D4
SDDR_D5
SDDR_D6
SDDR_D7
SDDR_DM0
SDDR_DQS0
SDDR_DQS0#

SDDR_D8
SDDR_D9
SDDR_D10
SDDR_D11
SDDR_D12
SDDR_D13
SDDR_D14
SDDR_D15

C C

B B

SDDR_DM1
SDDR_DQS1
SDDR_DQS1#

SDDR_D16
SDDR_D17
SDDR_D18
SDDR_D19
SDDR_D20
SDDR_D21
SDDR_D22
SDDR_D23
SDDR_DM2
SDDR_DQS2
SDDR_DQS2#

SDDR_D24
SDDR_D25
SDDR_D26
SDDR_D27
SDDR_D28
SDDR_D29
SDDR_D30
SDDR_D31
SDDR_DM3
SDDR_DQS3
SDDR_DQS3#

C267

104p/16V/1005

F24

DDR_D0

M24

DDR_D1

J25

DDR_D2

K26

DDR_D3

M26

DDR_D4

E25

DDR_D5

L25

DDR_D6

F26

DDR_D7

K24

DDR_DM0

H25

DDR_DQS0

H26

DDR_DQS0_N

E29

DDR_D8

L29

DDR_D9

H28

DDR_D10

J29

DDR_D11

L27

DDR_D12

E27

DDR_D13

K28

DDR_D14

F28

DDR_D15

J27

DDR_DM1

G28

DDR_DQS1

G29

DDR_DQS1_N

Y24

DDR_D16

AF28

DDR_D17

AC25

DDR_D18

AD26

DDR_D19

AF26

DDR_D20

W25

DDR_D21

AE25

DDR_D22

Y26

DDR_D23

AD24

DDR_DM2

AB25

DDR_DQS2

AB26

DDR_DQS2_N

W29

DDR_D24

AE29

DDR_D25

AB28

DDR_D26

AC29

DDR_D27

AE27

DDR_D28

W27

DDR_D29

AD28

DDR_D30

Y28

DDR_D31

AC27

DDR_DM3

AA28

DDR_DQS3

AA29

DDR_DQS3_N

C268

104p/16V/1005

DDR_VDD

DDR_VDD

DDR_VDD

DDR_VDD

DDR_VDD

CVSS

CVSS

CVSS

CVSS

E24

E26

E28

G24

C270

104p/16V/1005

DDR_VDD

CVSS

G26

DDR_VDD

CVSS

G27

DDR_VDD

CVSS

J24

J26

N24

M25

DDR_VDD

DDR_VDD

DDR_VDD

DDR_VDD

DDR_VDD

&MPEG2_ONECHIP FLI10610H

CVSS

CVSS

CVSS

CVSS

CVSS

J28

L24

L26

L28

N27

C272

104p/16V/1005

P28

DDR_VDD

DDR_VDD

U112A

CVSS

CVSS

N28

R25

DDR_VDD

CVSS

P26

U25

DDR_VDD

CVSS

T24

V27

DDR_VDD

CVSS

T26

Y25

DDR_VDD

CVSS

V29

Y27

DDR_VDD

CVSS

W24

Y29

AB24

AB27

AB29

DDR_VDD

DDR_VDD

DDR_VDD

DDR_VDD

CVSS

CVSS

CVSS

CVSS

W26

W28

AA24

AA26

C274

104p/16V/1005

AD25

DDR_VDD

CVSS

AA27

AD27

AD29

DDR_VDD

CVSS

AC24

AC26

AF27

DDR_VDD

DDR_VDD

CVSS

CVSS

AC28

4

AF29

DDR_VDD

CVSS

AE24

D27

DDR_VDD

CVSS

AE26

104p/16V/1005

R24

G25

D29

DDR_VDD

DDR_VRF_ 1

DDR_VRF_ 0

DDRPLL_AVDD12

DDRPLL_AVDD33

DDRPLL_AGND

CVSS

CVSS

CVSS

D26

D28

AE28

C276

104p/16V/1005

VDDR_MEM

C252

102p/50V/1005

AA25

DDR_VDDI
DDR_VDDI

DDR_VRF_ 2

DLL_VAA0
DLL_VAA1

DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9

DDR_A10

DDR_A11

DDR_A12

DDR_BA0
DDR_BA1

DDR_CAS_N
DDR_RAS_N

DDR_CS_N

DDR_WE_N

DDR_CK

DDR_CK_N

DDR_CKE

DDR_ODT

DDR_CAL

RPLL_AVDD12

RPLL_AGND

RPLL_AVDD33

RPLL_AGND

C251
104p/16V/1005

C253

F23
AD23

M28
V24

P27
U29
R26
U26
P25
T28
R27
V28
R29
T29
V25
R28
V26

U28
T27

P24
N26
N25
T25

P29
N29

U27

M27

U24

C23
D22

B22

B23
E22

E21
C22

104p/16V/1005

3

DDR_VRF

C254
105p/16V/1005

C255

226p/6.3V/2012

SDDR_A0
SDDR_A1
SDDR_A2
SDDR_A3
SDDR_A4
SDDR_A5
SDDR_A6
SDDR_A7
SDDR_A8
SDDR_A9
SDDR_A10
SDDR_A11
SDDR_A12

SDDR_BA0
SDDR_BA1

SDDR_CAS
SDDR_RAS
SDDR_CS
SDDR_WE

R262 100/F/1005 R255 100/1005
R263 100/F/1005

R276 103/F/1005
R265 103/1005

R268 2940/F/1005

C278

C256

103p/50V/1005

C280

104p/16V/1005

C257
103p/50V/1005

C260
103p/50V/1005

The CKE pull down is for power off
mode DDR self refresh

DDR_CKE

C263
103p/50V/1005

C265
103p/50V/1005

C282

104p/16V/1005

C258
226p/6.3V/2012

C261
103p/50V/1005

DDR_CLK
DDR_CLK_N

DDR_CKE

DDR_ODT

C264
103p/50V/1005

C266
103p/50V/1005

BLM18PG300SN1D

BLM18PG300SN1D

C284

104p/16V/1005

R251

+3V3_A

1R0/2012

C259

226p/6.3V/2012

R252
1R0/2012

C262
226p/6.3V/2012

MAIN PWB (11/28)

L251

L252

+1V2

+3V3_A

VDDR_MEM

SDDR_D2
SDDR_D0
SDDR_D7
SDDR_D5
SDDR_D4
SDDR_D1
SDDR_D3
SDDR_D6

SDDR_D15
SDDR_D8
SDDR_D13
SDDR_D10
SDDR_D11

SDDR_D12
SDDR_D9
SDDR_D14
SDDR_D18
SDDR_D16
SDDR_D23
SDDR_D21
SDDR_D17
SDDR_D22
SDDR_D20
SDDR_D19

SDDR_D31
SDDR_D29
SDDR_D24
SDDR_D26
SDDR_D27

SDDR_D28
SDDR_D25
SDDR_D30

SDDR_DM0
SDDR_DM1
SDDR_DM2

SDDR_DQS0
SDDR_DQS0#

SDDR_DQS1
SDDR_DQS1#

SDDR_DQS2
SDDR_DQS2#

SDDR_DQS3
SDDR_DQS3#

SDDR_A11
SDDR_A2
SDDR_A8
SDDR_A0
SDDR_A5
SDDR_A4
SDDR_A9
SDDR_A6
SDDR_A10
SDDR_A12
SDDR_A3
SDDR_A7
SDDR_A1

SDDR_BA0
SDDR_BA1

SDDR_RAS
SDDR_CAS
SDDR_CS

SDDR_WE

2

PR251 100*4/1005

PR252 100*4/1005

PR254 100*4/1005

R272 100/1005
R273 100/1005
PR257 100*4/1005

PR258 100*4/1005

PR260 100*4/1005

PR261 100*4/1005

R274 100/1005
R275 100/1005
PR262 100*4/1005

R253 100/1005
R257 100/1005
R264 100/1005
R269 100/1005

R254 100/1005

R259 100/1005
R261 100/1005

R266 100/1005
R267 100/1005

R270 100/1005
R271 100/1005

PR253 100*4/1005

PR255 100*4/1005

PR256 100*4/1005

R256 100/1005

R258 100/1005
R260 100/1005

PR259 100*4/1005

R277 100/1005

1

DDR_D[31:0]

45
36
27
18
45
36
27
18
18
27
36
45

18
27
36
45
45
36
27
18
45
36
27
18
18
27
36
45

18
27
36
45

18
27
36
45
18
27
36
45
18
27
36
45

45
36
27
18

DDR_D2
DDR_D0
DDR_D7
DDR_D5
DDR_D4
DDR_D1
DDR_D3
DDR_D6

DDR_D15
DDR_D8
DDR_D13
DDR_D10
DDR_D11

DDR_D12
DDR_D9
DDR_D14
DDR_D18
DDR_D16
DDR_D23
DDR_D21
DDR_D17
DDR_D22
DDR_D20
DDR_D19

DDR_D31
DDR_D29
DDR_D24
DDR_D26
DDR_D27

DDR_D28
DDR_D25
DDR_D30

DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3SDDR_DM3

DDR_DQS0
DDR_DQS0#

DDR_DQS1
DDR_DQS1#

DDR_DQS2
DDR_DQS2#

DDR_DQS3
DDR_DQS3#

DDR_A11
DDR_A2
DDR_A8
DDR_A0
DDR_A5
DDR_A4
DDR_A9
DDR_A6
DDR_A10
DDR_A12
DDR_A3
DDR_A7
DDR_A1

DDR_BA0
DDR_BA1

DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3

DDR_DQS0
DDR_DQS0#

DDR_DQS1
DDR_DQS1#

DDR_DQS2
DDR_DQS2#

DDR_DQS3
DDR_DQS3#

DDR_A[12:0]

DDR_BA0
DDR_BA1

DDR_RAS
DDR_CAS
DDR_CS

DDR_WE

DDR_D[31:0]

MAIN PWB (11/28)

DDR_A[12:0]

MAIN PWB (11/28)

MAIN PWB
(11/28)

MAIN PWB
(11/28)

C269

104p/16V/1005

A A

C285

102p/50V/1005

C286
102p/50V/1005

C287
102p/50V/1005

C271

104p/16V/1005

C288
102p/50V/1005

C273

104p/16V/1005

C289
102p/50V/1005

C275

104p/16V/1005

C290
102p/50V/1005

C277

104p/16V/1005

C291
102p/50V/1005

C292
102p/50V/1005

C279

104p/16V/1005

C293
102p/50V/1005

C281

104p/16V/1005

C294
102p/50V/1005

C283

104p/16V/1005

C295
102p/50V/1005

C296
102p/50V/1005

MAIN PWB ASS'Y (10/28)
[Douglas DDR Interface]

HU-71100004

2

1

lt-19db1bu_0514_8/30_0.0

All location are from 251 to 320

C297

105p/16V/1005

5

4

C298
105p/16V/1005

3

C299
226p/6.3V/2012

C300
226p/6.3V/2012

(No.YA697<Rev.001>)2-25 2-26(No.YA697<Rev.001>)

MAIN PWB CIRCUIT DIAGRAM (11/28) [DDR2 Memory]

5

DDR_A[12:0]

MAIN PWB

D D

C C

B B

(10/28)

MAIN PWB

(10/28)

DDR_D[31:0]

DDR_BA0
DDR_BA1

DDR_CLK

DDR_CLK_N

DDR_CKE

DDR_ODT

DDR_CS
DDR_RAS
DDR_CAS

DDR_WE

DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3

DDR_DQS0

DDR_DQS0#

DDR_DQS1

DDR_DQS1#

DDR_DQS2

DDR_DQS2#

DDR_DQS3#

DDR_DQS3

226p/6.3V/2012

VDDR_MEM

C331

DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12

DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31

DDR_BA0
DDR_BA1

DDR_CLK
DDR_CLK_N
DDR_CKE

DDR_ODT
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE

DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3

DDR_DQS0
DDR_DQS0#

DDR_DQS1
DDR_DQS1#

DDR_DQS2
DDR_DQS2#

DDR_DQS3#
DDR_DQS3

226p/6.3V/2012

C333

VDDR_MEM

L321

BLM18PG300SN1D

C335

105p/16V/1005

4

C327

105p/16V/1005

3

VDDR_MEM

C321

104p/16V/1005

C323

U321

H5PS5162FFR-Y5

DDR_D0
DDR_D3
DDR_D7
DDR_D4
DDR_D1
DDR_D5
DDR_D6
DDR_D2
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15

VDDR_MEM VDDR_MEM

C328
104p/16V/1005

C337

104p/16V/1005

G8

DQ0

G2

DQ1

H7

DQ2

H3

DQ3

H1

DQ4

H9

DQ5

F1

DQ6

F9

DQ7

C8

DQ8

C2

DQ9

D7

DQ10

D3

DQ11

D1

DQ12

D9

DQ13

B1

DQ14

B9

DQ15

A1

VDD

E1

VDD

J9

VDD

M9

VDD

R1

VDD

A9

VDDQ

C1

VDDQ

C3

VDDQ

C7

VDDQ

C9

VDDQ

E9

VDDQ

G1

VDDQ

G3

VDDQ

G7

VDDQ

G9

VDDQ

A3

VSS

E3

VSS

J3

VSS

N1

VSS

P9

VSS

B2

VSSQ

B8

VSSQ

A7

VSSQ

D2

VSSQ

D8

VSSQ

E7

VSSQ

F2

VSSQ

F8

VSSQ

H2

VSSQ

H8

VSSQ

J1

VDDL

J7

VSSDL

104p/16V/1005

C339

LDQS#/NU

UDQS#/NU

VREF

A10
A11
A12

BA0
BA1

CK#

CKE

ODT

CS#
RAS#
CAS#

WE#

LDQS

UDQS

LDM
UDM

RFU
RFU
RFU

NC
NC
NC

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

CK

J2

DDR_A0

M8

DDR_A1

M3

DDR_A2

M7

DDR_A3

N2

DDR_A4

N8

DDR_A5

N3

DDR_A6

N7

DDR_A7

P2

DDR_A8

P8

DDR_A9

P3

DDR_A10

M2

DDR_A11

P7

DDR_A12

R2

DDR_BA0

L2

DDR_BA1

L3

DDR_CLK

J8

DDR_CLK_N

K8

DDR_CKE

K2

DDR_ODT

K9

DDR_CS

L8

DDR_RAS

K7

DDR_CAS

L7

DDR_WE

K3

DDR_DQS0

F7

DDR_DQS1

B7

DDR_DM0

F3

DDR_DM1

B3

DDR_DQS0# DDR_DQS2#

E8

DDR_DQS1#

A8

L1
R3
R7

A2
E2
R8

C341

103p/50V/1005

102p/50V/1005

DDR_VRF

DDR_CLK

R321
201/1005

DDR_CLK_N

C343

473p/16V/1005

C324
226p/6.3V/2012

DDR_VRF

C325
226p/6.3V/2012

DDR_CLK

R322
201/1005

DDR_CLK_N

C345
473p/16V/1005

VDDR_MEM

C326
102p/50V/1005

2

C322
104p/16V/1005

DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12

DDR_BA0
DDR_BA1

DDR_CLK
DDR_CLK_N
DDR_CKE

DDR_ODT
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE

DDR_DQS2
DDR_DQS3

DDR_DM2
DDR_DM3

DDR_DQS3#

U322

J2

VREF

M8

A0

M3

A1

M7

A2

N2

A3

N8

A4

N3

A5

N7

A6

P2

A7

P8

A8

P3

A9

M2

A10

P7

A11

R2

A12

L2

BA0

L3

BA1

J8

CK

K8

CK#

K2

CKE

K9

ODT

L8

CS#

K7

RAS#

L7

CAS#

K3

WE#

F7

LDQS

B7

UDQS

F3

LDM

B3

UDM

E8

LDQS#/NU

A8

UDQS#/NU

L1

RFU

R3

RFU

R7

RFU

A2

NC

E2

NC

R8

NC

H5PS5162FFR-Y5

333MHz/512Mbit(32Mx16)333MHz/512Mbit(32Mx16)

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD

VDD

VDD

VDD

VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS

VSS

VSS

VSS

VSS

VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDDL

VSSDL

G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9

A1
E1
J9
M9
R1

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A3
E3
J3
N1
P9

B2
B8
A7
D2
D8
E7
F2
F8
H2
H8

J1

J7

DDR_D16
DDR_D20
DDR_D23
DDR_D17
DDR_D22
DDR_D21
DDR_D19
DDR_D18
DDR_D29
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D24
DDR_D30
DDR_D31

C329
104p/16V/1005

1

BLM18PG300SN1D

C330
105p/16V/1005

L322

VDDR_MEM

A A

VDDR_MEM

C346

226p/6.3V/2012

All location are from 321 to 380

5

C332

226p/6.3V/2012

226p/6.3V/2012

C347

226p/6.3V/2012

C348

C334

105p/16V/1005

C349

105p/16V/1005

C350

105p/16V/1005

C336

105p/16V/1005

C351

105p/16V/1005

4

C352

104p/16V/1005

C338

104p/16V/1005

C353

104p/16V/1005

C354

104p/16V/1005

C340

103p/50V/1005

C355

103p/50V/1005

C356

103p/50V/1005

C342

103p/50V/1005

C357

103p/50V/1005

3

C358

473p/16V/1005

C344

473p/16V/1005

C359

473p/16V/1005

C360
473p/16V/1005

MAIN PWB ASS'Y (11/28)
[DDR2 Memory]

HU-71100004

2

1

lt-19db1bu_0514_9/30_0.0

2-28(No.YA697<Rev.001>)(No.YA697<Rev.001>)2-27