IS61VPD51232
IS61VPD51236 ISSI®
IS61VPD10018
512K x 32, 512K x 36, 1024K x 18 SYNCHRONOUS PIPELINED,
DOUBLE CYCLE DESELECT STATIC RAM
ADVANCE INFORMATION
MAY 2001
FEATURES
•Internal self-timed write cycle
•Individual Byte Write Control and Global Write
•Clock controlled, registered address, data and control
•Linear burst sequence control using MODE input
•Three chip enable option for simple depth expansion and address pipelining
•Common data inputs and data outputs
•JEDEC 100-Pin TQFP and 119-pin PBGA package
•Single +2.5V, ±5% operation
•Auto Power-down during deselect
•Double cycle deselect
•Snooze MODE for reduced-power standby
•JTAG Boundary Scan for PBGA package
FAST ACCESS TIME
DESCRIPTION
The ISSI IS61VPD51232, IS61VPD51236, and IS61VPD10018 are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61VPD51232 is organized as 524,288 words by 32 bits and the IS61VPD51236 is organized as 524,288 words by 36 bits. The IS61VPD10018 is organized as 1,048,576 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge- triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
Symbol |
Parameter |
-200 |
-166 |
Units |
tKQ |
Clock Access Time |
3.1 |
3.5 |
ns |
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tKC |
Cycle Time |
5 |
6 |
ns |
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Frequency |
200 |
166 |
MHz |
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This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
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ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPD51232
IS61VPD51236 ISSI®
IS61VPD10018
BLOCK DIAGRAM
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Q0 |
A0' |
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CLK |
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A0 |
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BINARY |
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COUNTER |
A1' |
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ADV |
CE |
Q1 |
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A1 |
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ADSC |
CLR |
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512Kx32; 512Kx36; |
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1024Kx18 |
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ADSP |
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MEMORY ARRAY |
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A19-A0 |
19/20 |
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17/18 |
19/20 |
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A18-A0 |
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REGISTER |
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CE |
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CLK |
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32, 36, |
32, 36, |
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or 18 |
or 18 |
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GW |
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DQd |
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BWE |
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BYTE WRITE |
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BWd |
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DQc |
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BWc |
BYTE WRITE |
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DQb |
Q |
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BWb |
BYTE WRITE |
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CLK |
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DQa |
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BWa |
BYTE WRITE |
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CE2 |
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INPUT |
OUTPUT |
or 18 |
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CE2 |
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ENABLE |
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REGISTERS |
REGISTERS |
DQa - DQd |
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OE |
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ENABLE |
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DELAY |
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Integrated Silicon Solution, Inc. — 1-800-379-4774 |
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ADVANCE INFORMATION |
Rev. 00A |
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05/31/01 |
IS61VPD51232
IS61VPD51236 ISSI®
IS61VPD10018
PIN CONFIGURATION
100-Pin TQFP
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A6 |
A7 CE |
CE2 |
BWd BWc BWb BWa |
CE2 VCC |
GND CLK GW BWE OE |
ADSC ADSP ADV |
A8 |
A9 |
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100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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NC |
1 |
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80 |
NC |
DQc1 |
2 |
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79 |
DQb8 |
DQc2 |
3 |
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78 |
DQb7 |
VCCQ |
4 |
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77 |
VCCQ |
GND |
5 |
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76 |
GND |
DQc3 |
6 |
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75 |
DQb6 |
DQc4 |
7 |
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74 |
DQb5 |
DQc5 |
8 |
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73 |
DQb4 |
DQc6 |
9 |
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72 |
DQb3 |
GND |
10 |
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71 |
GND |
VCCQ |
11 |
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70 |
VCCQ |
DQc7 |
12 |
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69 |
DQb2 |
DQc8 |
13 |
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68 |
DQb1 |
NC |
14 |
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67 |
GND |
VCC |
15 |
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66 |
NC |
NC |
16 |
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65 |
VCC |
GND |
17 |
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64 |
ZZ |
DQd1 |
18 |
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DQa8 |
DQd2 |
19 |
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62 |
DQa7 |
VCCQ |
20 |
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61 |
VCCQ |
GND |
21 |
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60 |
GND |
DQd3 |
22 |
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59 |
DQa6 |
DQd4 |
23 |
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DQa5 |
DQd5 |
24 |
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57 |
DQa4 |
DQd6 |
25 |
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56 |
DQa3 |
GND |
26 |
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55 |
GND |
VCCQ |
27 |
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54 |
VCCQ |
DQd7 |
28 |
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53 |
DQa2 |
DQd8 |
29 |
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52 |
DQa1 |
NC |
30 |
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51 |
NC |
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31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
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MODE |
A5 A4 |
A3 |
A2 A1 A0 NC |
NC GND |
VCC A18 A17 A10 A11 |
A12 A13 A14 |
A15 |
A16 |
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512K x 32
PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
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pins must tied to the two LSBs of the |
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address bus. |
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A2-A18 |
Synchronous Address Inputs |
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ADSC |
SynchronousControllerAddressStatus |
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ADSP |
SynchronousProcessorAddressStatus |
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ADV |
Synchronous Burst Address Advance |
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BWa-BWd |
Synchronous Byte Write Enable |
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BWE |
Synchronous Byte Write Enable |
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CE, CE2, CE2 |
Synchronous Chip Enable |
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CLK |
Synchronous Clock |
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DQa-DQd |
Synchronous Data Input/Output |
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GND |
Ground |
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GW |
Synchronous Global Write Enable |
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MODE |
Burst Sequence Mode Selection |
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OE |
Output Enable |
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VCC |
+2.5V Power Supply |
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VCCQ |
Isolated Output Buffer Supply: |
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+2.5V |
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ZZ |
Snooze Enable |
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Integrated Silicon Solution, Inc. — 1-800-379-4774 |
3 |
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPD51232
IS61VPD51236 ISSI®
IS61VPD10018
PIN CONFIGURATION
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119-pin PBGA (Top View) |
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100-Pin TQFP |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
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A6 |
A7 CE |
CE2 |
BWd |
BWc |
BWb BWa |
CE2 VCC |
GND CLK GW BWE OE |
ADSC ADSP ADV A8 |
A9 |
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A |
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100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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VCCQ |
A6 |
A4 |
ADSP |
A8 |
A16 |
VCCQ |
DQPc |
1 |
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80 |
DQPb |
B |
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A18 |
A3 |
ADSC |
A9 |
A17 |
NC |
DQc1 |
2 |
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79 |
DQb8 |
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NC |
DQc2 |
3 |
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78 |
DQb7 |
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C |
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A7 |
A2 |
VCC |
A12 |
A15 |
NC |
VCCQ |
4 |
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77 |
VCCQ |
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NC |
GND |
5 |
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76 |
GND |
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D |
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DQPc |
GND |
NC |
GND |
DQPb |
DQb8 |
DQc3 |
6 |
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75 |
DQb6 |
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DQc1 |
DQc4 |
7 |
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74 |
DQb5 |
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E |
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DQc5 |
8 |
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73 |
DQb4 |
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DQc2 |
DQc3 |
GND |
CE |
GND |
DQb6 |
DQb7 |
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DQc6 |
9 |
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72 |
DQb3 |
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F |
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GND |
10 |
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71 |
GND |
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VCCQ |
DQc4 |
GND |
OE |
GND |
DQb5 |
VCCQ |
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VCCQ |
11 |
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70 |
VCCQ |
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G |
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DQc7 |
12 |
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69 |
DQb2 |
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DQc5 |
DQc6 |
BWc |
ADV |
BWb |
DQb4 |
DQb3 |
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DQc8 |
13 |
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68 |
DQb1 |
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H |
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NC |
14 |
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67 |
GND |
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DQc7 |
DQc8 |
GND |
GW |
GND |
DQb2 |
DQb1 |
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VCC |
15 |
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66 |
NC |
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J |
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NC |
16 |
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65 |
VCC |
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VCCQ |
VCC |
NC |
VCC |
NC |
VCC |
VCCQ |
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GND |
17 |
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64 |
ZZ |
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K |
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DQd1 |
18 |
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63 |
DQa8 |
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DQd1 |
DQd2 |
GND |
CLK |
GND |
DQa7 |
DQa8 |
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DQd2 |
19 |
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62 |
DQa7 |
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L |
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VCCQ |
20 |
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61 |
VCCQ |
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DQd4 |
DQd3 |
BWd |
NC |
BWa |
DQa5 |
DQa6 |
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GND |
21 |
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60 |
GND |
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M |
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DQd3 |
22 |
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59 |
DQa6 |
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VCCQ |
DQd5 |
GND |
BWE |
GND |
DQa4 |
VCCQ |
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DQd4 |
23 |
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58 |
DQa5 |
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N |
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DQd5 |
24 |
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57 |
DQa4 |
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DQd6 |
DQd7 |
GND |
A1 |
GND |
DQa3 |
DQa2 |
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P |
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DQd6 |
25 |
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56 |
DQa3 |
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GND |
26 |
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55 |
GND |
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DQd8 |
DQPd |
GND |
A0 |
GND |
DQPa |
DQa1 |
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R |
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VCCQ |
27 |
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54 |
VCCQ |
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DQd7 |
28 |
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53 |
DQa2 |
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NC |
A5 |
MODE |
VCC |
NC |
A13 |
NC |
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T |
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DQd8 |
29 |
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52 |
DQa1 |
NC |
NC |
A10 |
A11 |
A14 |
NC |
ZZ |
DQPd |
30 |
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51 |
DQPa |
U |
|
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|
|
31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 |
46 47 48 49 50 |
|
||||||
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|
VCCQ |
TMS |
TDI |
TCK |
TDO |
NC |
VCCQ |
|
|
|
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|
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|
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|
|
MODE |
A5 A4 |
A3 |
A2 |
A1 |
A0 NC |
NC GND |
VCC A18 A17 A10 A11 |
A12 A13 A14 A15 |
A16 |
|
|
|
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|
|
512K x 36 |
|
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|
|
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|
|
PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
|
pins must tied to the two LSBs of the |
|
address bus. |
|
|
A2-A18 |
Synchronous Address Inputs |
|
|
ADSC |
SynchronousControllerAddressStatus |
|
|
ADSP |
SynchronousProcessorAddressStatus |
|
|
ADV |
SynchronousBurstAddressAdvance |
|
|
BWa-BWd |
Synchronous Byte Write Enable |
|
|
BWE |
Synchronous Byte Write Enable |
|
|
CE, CE2, CE2 |
Synchronous Chip Enable |
|
|
CLK |
Synchronous Clock |
|
|
DQa-DQd |
Synchronous Data Input/Output |
|
|
DQPa-DQPd |
Parity Data Input/Output |
|
|
GND |
Ground |
|
|
GW |
Synchronous Global Write Enable |
|
|
MODE |
Burst Sequence Mode Selection |
|
|
OE |
Output Enable |
|
|
TMS, TDI, |
JTAG Boundary Scan Pins |
TCK, TDO |
|
|
|
VCC |
+2.5V Power Supply |
|
|
VCCQ |
Isolated Output Buffer Supply: |
|
+2.5V |
|
|
ZZ |
Snooze Enable |
|
|
4 Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPD51232
IS61VPD51236 ISSI®
IS61VPD10018
PIN CONFIGURATION
|
119-pin PBGA (Top View) |
|
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100-Pin TQFP |
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||||||
1 |
2 |
3 |
4 |
5 |
6 |
7 |
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A |
A6 |
A4 |
ADSP |
A8 |
A16 |
VCCQ |
|
A6 |
A7 CE |
CE2 |
NC NC BWb BWa |
CE2 VCC |
GND CLK GW BWE OE |
ADSC ADSP |
ADV |
A8 |
A9 |
|
VCCQ |
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||||||
B |
A19 |
A3 |
|
A9 |
A18 |
NC |
|
100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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||||||
NC |
ADSC |
NC |
1 |
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80 |
A17 |
|||||
C |
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NC |
2 |
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79 |
NC |
NC |
A7 |
A2 |
VCC |
A12 |
A15 |
NC |
NC |
3 |
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78 |
NC |
D |
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VCCQ |
4 |
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77 |
VCCQ |
DQb1 |
NC |
GND |
NC |
GND |
DQPa |
NC |
GND |
5 |
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76 |
GND |
E |
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NC |
6 |
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75 |
NC |
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NC |
7 |
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74 |
DQPa |
|
NC |
DQb2 |
GND |
CE |
GND |
NC |
DQa8 |
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||||
DQb1 |
8 |
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73 |
DQa8 |
|||||||
F |
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DQb2 |
9 |
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72 |
DQa7 |
|
VCCQ |
NC |
GND |
OE |
GND |
DQa7 |
VCCQ |
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||||
GND |
10 |
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71 |
GND |
|||||||
G |
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VCCQ |
11 |
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70 |
VCCQ |
|
NC |
DQb3 |
BWb |
ADV |
GND |
NC |
DQa6 |
DQb3 |
12 |
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69 |
DQa6 |
H |
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DQb4 |
13 |
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68 |
DQa5 |
DQb4 |
NC |
GND |
GW |
GND |
DQa5 |
NC |
NC |
14 |
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67 |
GND |
J |
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VCC |
15 |
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66 |
NC |
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NC |
16 |
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65 |
VCC |
|
VCCQ |
VCC |
NC |
VCC |
NC |
VCC |
VCCQ |
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||||
K |
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GND |
17 |
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64 |
ZZ |
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DQb5 |
18 |
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63 |
DQa4 |
|
NC |
DQb5 |
GND |
CLK |
GND |
NC |
DQa4 |
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||||
DQb6 |
19 |
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62 |
DQa3 |
|||||||
L |
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VCCQ |
20 |
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61 |
VCCQ |
|
DQb6 |
NC |
GND |
NC |
BWa |
DQa3 |
NC |
GND |
21 |
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60 |
GND |
M |
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DQb7 |
22 |
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59 |
DQa2 |
VCCQ |
DQb7 |
GND |
BWE |
GND |
NC |
VCCQ |
DQb8 |
23 |
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58 |
DQa1 |
N |
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DQPb |
24 |
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|
57 |
NC |
DQb8 |
NC |
GND |
A1 |
GND |
DQa2 |
NC |
NC |
25 |
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56 |
NC |
P |
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GND |
26 |
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55 |
GND |
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VCCQ |
27 |
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54 |
VCCQ |
|
NC |
DQPb |
GND |
A0 |
GND |
NC |
DQa1 |
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||||
NC |
28 |
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53 |
NC |
|||||||
R |
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NC |
29 |
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52 |
NC |
|
NC |
A5 |
MODE |
VCC |
NC |
A13 |
NC |
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||||
NC |
30 |
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51 |
NC |
|||||||
T |
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||||
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31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
|
||||||||
NC |
A11 |
A10 |
NC |
A14 |
A17 |
ZZ |
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U |
|
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MODE |
A5 A4 |
A3 |
A2 A1 A0 NC |
NC GND |
VCC A19 A18 A10 A11 |
A12 A13 |
A14 |
A15 |
A16 |
|
VCCQ |
TMS |
TDI |
TCK |
TDO |
NC |
VCCQ |
|
|
||||||||||
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||||||||||
|
|
|
|
|
|
|
1024K x 18 |
|
|
|
|
|
|
|
|
|
|
|
PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
|
pins must tied to the two LSBs of the |
|
address bus. |
|
|
A2-A19 |
Synchronous Address Inputs |
|
|
ADSC |
SynchronousControllerAddressStatus |
|
|
ADSP |
SynchronousProcessorAddressStatus |
|
|
ADV |
SynchronousBurstAddressAdvance |
|
|
BWa-BWd |
Synchronous Byte Write Enable |
|
|
BWE |
Synchronous Byte Write Enable |
|
|
CE, CE2, CE2 |
Synchronous Chip Enable |
|
|
CLK |
Synchronous Clock |
|
|
DQa-DQd |
Synchronous Data Input/Output |
|
|
DQPa-DQPb |
Parity Data I/O; DQPa is parity for |
|
DQa1-8; DQPb is parity for DQb1-8 |
|
|
GND |
Ground |
|
|
GW |
Synchronous Global Write Enable |
|
|
MODE |
Burst Sequence Mode Selection |
|
|
OE |
Output Enable |
|
|
TMS, TDI, |
JTAG Boundary Scan Pins |
TCK, TDO |
|
|
|
VCC |
+2.5V Power Supply |
|
|
VCCQ |
Isolated Output Buffer Supply: |
|
+2.5V |
|
|
ZZ |
Snooze Enable |
|
|
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
5 |
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPD51232
IS61VPD51236 ISSI®
IS61VPD10018
TRUTH TABLE(1-8) (3CE option)
OPERATION |
ADDRESS |
CE |
CE2 |
CE2 |
ZZ |
ADSP |
ADSC |
ADV |
WRITE |
OE |
CLK |
DQ |
|
|
|
|
|
|
|
|
|
|
|
|
|
Deselect Cycle, Power-Down |
None |
H |
X |
X |
L |
X |
L |
X |
X |
X |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Deselect Cycle, Power-Down |
None |
L |
X |
L |
L |
L |
X |
X |
X |
X |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Deselect Cycle, Power-Down |
None |
L |
H |
X |
L |
L |
X |
X |
X |
X |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Deselect Cycle, Power-Down |
None |
L |
X |
L |
L |
H |
L |
X |
X |
X |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Deselect Cycle, Power-Down |
None |
L |
H |
X |
L |
H |
L |
X |
X |
X |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Snooze Mode, Power-Down |
None |
X |
X |
X |
H |
X |
X |
X |
X |
X |
X |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Begin Burst |
External |
L |
L |
H |
L |
L |
X |
X |
X |
L |
L-H |
Q |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Begin Burst |
External |
L |
L |
H |
L |
L |
X |
X |
X |
H |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Write Cycle, Begin Burst |
External |
L |
L |
H |
L |
H |
L |
X |
L |
X |
L-H |
D |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Begin Burst |
External |
L |
L |
H |
L |
H |
L |
X |
H |
L |
L-H |
Q |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Begin Burst |
External |
L |
L |
H |
L |
H |
L |
X |
H |
H |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Continue Burst |
Next |
X |
X |
X |
L |
H |
H |
L |
H |
L |
L-H |
Q |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Continue Burst |
Next |
X |
X |
X |
L |
H |
H |
L |
H |
H |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Continue Burst |
Next |
H |
X |
X |
L |
X |
H |
L |
H |
L |
L-H |
Q |
|
|
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|
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|
|
Read Cycle, Continue Burst |
Next |
H |
X |
X |
L |
X |
H |
L |
H |
H |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Write Cycle, Continue Burst |
Next |
X |
X |
X |
L |
H |
H |
L |
L |
X |
L-H |
D |
|
|
|
|
|
|
|
|
|
|
|
|
|
Write Cycle, Continue Burst |
Next |
H |
X |
X |
L |
X |
H |
L |
L |
X |
L-H |
D |
|
|
|
|
|
|
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|
|
|
|
|
|
Read Cycle, Suspend Burst |
Current |
X |
X |
X |
L |
H |
H |
H |
H |
L |
L-H |
Q |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Suspend Burst |
Current |
X |
X |
X |
L |
H |
H |
H |
H |
H |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Suspend Burst |
Current |
H |
X |
X |
L |
X |
H |
H |
H |
L |
L-H |
Q |
|
|
|
|
|
|
|
|
|
|
|
|
|
Read Cycle, Suspend Burst |
Current |
H |
X |
X |
L |
X |
H |
H |
H |
H |
L-H |
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
Write Cycle, Suspend Burst |
Current |
X |
X |
X |
L |
H |
H |
H |
L |
X |
L-H |
D |
|
|
|
|
|
|
|
|
|
|
|
|
|
Write Cycle, Suspend Burst |
Current |
H |
X |
X |
L |
X |
H |
H |
L |
X |
L-H |
D |
|
|
|
|
|
|
|
|
|
|
|
|
|
NOTE:
1.X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2.For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH.
3.BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version.
4.All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5.Wait states are inserted by suspending burst.
6.For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time.
7.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
05/31/01
IS61VPD51232 |
ISSI |
|
IS61VPD51236 |
® |
|
IS61VPD10018 |
|
TRUTH TABLE(1-8) (1CE option)
NEXT CYCLE |
ADDRESS |
CE |
ADSP |
ADSC |
ADV |
WRITE |
OE |
DQ |
|
|
|
|
|
|
|
|
|
Deselected |
None |
H |
X |
L |
X |
X |
X |
High-Z |
|
|
|
|
|
|
|
|
|
Read, Begin |
External |
L |
L |
X |
X |
X |
L |
Q |
|
|
|
|
|
|
|
|
|
Read, Begin |
External |
L |
L |
X |
X |
X |
H |
High-Z |
|
|
|
|
|
|
|
|
|
Write, Begin |
Current |
L |
H |
L |
X |
Write |
X |
D |
|
|
|
|
|
|
|
|
|
Read, Begin |
External |
L |
H |
L |
X |
Read |
L |
Q |
|
|
|
|
|
|
|
|
|
Read, Begin |
External |
L |
H |
L |
X |
Read |
H |
High-Z |
|
|
|
|
|
|
|
|
|
Read, Burst |
Next |
X |
H |
H |
L |
Read |
L |
Q |
|
|
|
|
|
|
|
|
|
Read, Burst |
Next |
X |
H |
H |
L |
Read |
H |
High-Z |
|
|
|
|
|
|
|
|
|
Read, Burst |
Next |
H |
X |
H |
L |
Read |
L |
Q |
|
|
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Read, Burst |
Next |
H |
X |
H |
L |
Read |
H |
High-Z |
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Write, Burst |
Next |
X |
H |
H |
L |
Write |
X |
D |
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Write, Burst |
Next |
H |
X |
H |
L |
Write |
X |
D |
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Read, Suspend |
Current |
X |
H |
H |
H |
Read |
L |
Q |
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Read, Suspend |
Current |
X |
H |
H |
H |
Read |
H |
High-Z |
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Read, Suspend |
Current |
H |
X |
H |
H |
Read |
L |
Q |
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Read, Suspend |
Current |
H |
X |
H |
H |
Read |
H |
High-Z |
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Write, Suspend |
Current |
X |
H |
H |
H |
Write |
X |
D |
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Write, Suspend |
Current |
H |
X |
H |
H |
Write |
X |
D |
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NOTE:
1.X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2.For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH.
3.BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version.
4.All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5.Wait states are inserted by suspending burst.
6.For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time.
7.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
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Function |
GW |
BWE |
BWa |
BWb |
BWc |
BWd |
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Read |
H |
H |
X |
X |
X |
X |
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Read |
H |
L |
H |
H |
H |
H |
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Write Byte 1 |
H |
L |
L |
H |
H |
H |
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Write All Bytes |
H |
L |
L |
L |
L |
L |
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Write All Bytes |
L |
X |
X |
X |
X |
X |
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Integrated Silicon Solution, Inc. — 1-800-379-4774 |
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7 |
||||||
ADVANCE INFORMATION |
Rev. 00A |
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05/31/01 |
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IS61VPD51232
IS61VPD51236 ISSI®
IS61VPD10018
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address |
1st Burst Address |
2nd Burst Address |
3rd Burst Address |
A1 A0 |
A1 A0 |
A1 A0 |
A1 A0 |
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00 |
01 |
10 |
11 |
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01 |
00 |
11 |
10 |
10 |
11 |
00 |
01 |
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11 |
10 |
01 |
00 |
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LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1 |
0,1 |
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameter |
Value |
Unit |
TBIAS |
Temperature Under Bias |
–40 to +85 |
°C |
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TSTG |
Storage Temperature |
–55 to +150 |
°C |
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PD |
Power Dissipation |
1.6 |
W |
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IOUT |
Output Current (per I/O) |
100 |
mA |
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VIN, VOUT |
Voltage Relative to GND for I/O Pins |
–0.5 to VCCQ + 0.5 |
V |
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VIN |
Voltage Relative to GND for |
–0.5 to VCC + 0.5 |
V |
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for Address and Control Inputs |
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VCC |
Voltage on Vcc Supply Relatiive to GND |
–0.5 to 3.2 |
V |
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Notes:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3.This device contains circuitry that will ensure the output devices are in High-Z at power up.
8 Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
05/31/01