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IS61NW6432 |
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ISSI |
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IS61NW6432 |
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64K x 32 SYNCHRONOUS STATIC RAM |
ADVANCE INFORMATION |
WITH NO-WAIT STATE BUS FEATURE
JULY 1998
FEATURES
•Fast access time:
–5 ns-100 MHz; 6 ns-83 MHz;
–7 ns-75 MHz; 8 ns-66 MHz
•No wait cycles between Read and Write
•Internal self-timed write cycle
•Individual Byte Write Control
•Clock controlled, registered address, data and control
•Pentium™ or linear burst sequence control using MODE input
•Three chip enables for simple depth expansion and address pipelining
•Common data inputs and data outputs
•JEDEC 100-pin TQFP and PQFP package
•Single +3.3V power supply
•Optional data strobe pin (#80) for latching data (See page 12 for detailed timing)
DESCRIPTION
The IS61NW6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, 'no-wait' bus, secondary cache for the Pentium, 680X0, and Power PC microprocessors. It is organized as 65,536 words by 32 bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no-wait' bus, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled by a positive-edge-triggered clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CEN is HIGH. In this state the internal device will hold their previous values.
When the ADV/LD is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV/LD is LOW.
Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when RD/WE is LOW. Separate byte enables allow individual bytes to be written. BW1controls I/O1-I/O8; BW2controls I/O9-I/O16; BW3controls I/O17-I/O24; BW4 controls I/O25-I/O32. All Bytes are written when BW1, BW2, BW3, and BW4 are LOW.
MODE pin upon power up is in interleave burst mode. It can be connected to GNDQ or VCCQ to alter power up state.
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. |
1 |
ADVANCE INFORMATION SR050-0B 07/15/98
IS61NW6432
BLOCK DIAGRAM
MODE |
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A0-A15 |
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CE1, CE2, CE3 |
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REGISTER |
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R/W |
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CEN |
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ADV/LD |
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INPUT |
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BW1 |
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BW2 |
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BW3 |
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BW4 |
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OE |
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CLOCK
64K x 32 BIT MEMORY ARRAY
ADDRESS
CONTROL
DIN DOUT
CONTROL LOGIC
MUX
SEL
I
OUTPUT
REGISTER
O
GATE |
OE |
DATA DS
I/O1-I/O32 (Optional)
2 Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR050-0B 07/15/98
IS61NW6432
PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)
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A6 |
A7 |
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CE1 |
CE2 |
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BW4 |
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BW3 |
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BW2 |
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BW1 |
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CE3 VCC |
GND CLK |
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R/W |
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CEN |
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OE |
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ADV/LD |
NC |
NC |
A8 |
A9 |
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100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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NC |
1 |
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80 |
NC |
I/O17 |
2 |
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79 |
I/O16 |
I/O18 |
3 |
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78 |
I/O15 |
VCCQ |
4 |
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77 |
VCCQ |
GNDQ |
5 |
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76 |
GNDQ |
I/O19 |
6 |
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75 |
I/O14 |
I/O20 |
7 |
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74 |
I/O13 |
I/O21 |
8 |
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73 |
I/O12 |
I/O22 |
9 |
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72 |
I/O11 |
GNDQ |
10 |
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71 |
GNDQ |
VCCQ |
11 |
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70 |
VCCQ |
I/O23 |
12 |
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69 |
I/O10 |
I/O24 |
13 |
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68 |
I/O9 |
VCC |
14 |
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67 |
GND |
VCC |
15 |
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66 |
VCC |
VCC |
16 |
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65 |
VCC |
GND |
17 |
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64 |
GND |
I/O25 |
18 |
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63 |
I/O8 |
I/O26 |
19 |
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62 |
I/O7 |
VCCQ |
20 |
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61 |
VCCQ |
GNDQ |
21 |
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60 |
GNDQ |
I/O27 |
22 |
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59 |
I/O6 |
I/O28 |
23 |
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58 |
I/O5 |
I/O29 |
24 |
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57 |
I/O4 |
I/O30 |
25 |
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56 |
I/O3 |
GNDQ |
26 |
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55 |
GNDQ |
VCCQ |
27 |
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54 |
VCCQ |
I/O31 |
28 |
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53 |
I/O2 |
I/O32 |
29 |
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52 |
I/O1 |
NC |
30 |
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51 |
NC |
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31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
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MODE |
A5 A4 |
A3 |
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A2 A1 A0 NC |
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NC GND |
VCC NC NC A10 A11 |
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A12 |
A13 |
A14 |
A15 |
NC |
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PIN DESCRIPTIONS
A0-A15 |
Address Inputs |
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CLK |
Clock |
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CEN |
Clock Enable |
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ADV/CD |
Advance Load |
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BW1-BW4 |
Synchronous Byte Write Enable |
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R/W |
Read/Write |
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CE1, CE2, CE3 Synchronous Chip Enable |
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OE |
Output Enable |
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Note:
1. Optional, NC or DS.
DS(1) |
Data Strobe |
I/O1-I/O32 |
Data Input/Output |
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MODE |
Burst Sequence Mode |
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VCC |
+3.3V Power Supply |
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GND |
Ground |
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VCCQ |
Isolated Output Buffer Supply: +3.3V |
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GNDQ |
Isolated Output Buffer Ground |
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NC |
No Connect |
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Integrated Silicon Solution, Inc. |
3 |
ADVANCE INFORMATION SR050-0B 07/15/98
IS61NW6432
TRUTH TABLE(1)
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Address |
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Operation |
Used |
R/W |
CEx |
ADV/LD |
CEN |
BWx |
CLK |
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Begin New Write Cycle |
External |
L |
L |
L |
L |
Valid |
L-H |
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Begin New Read Cycle |
External |
H |
L |
L |
L |
X |
L-H |
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Advance Burst Counter(2) |
Internal |
X |
X |
H |
L |
Valid |
L-H |
(Burst Write) |
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Advance Burst Counter |
Internal |
X |
X |
H |
L |
X |
L-H |
(Burst Read) |
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Deselect (2 Cycle)(3) |
X |
X |
H |
L |
L |
X |
L-H |
Hold/NOOP(4) |
X |
X |
X |
X |
H |
X |
L-H |
Notes: |
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1."X" Means don't care.
2.When ADV/LD signal is sampled HIGH, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore, the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3.Deselect cycle is initiated when CEx is sampled HIGH and ADV/LD sampled LOW at rising edge of clock. The data bus will tri-state two cycles after deselect is initiated.
4.When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers remains unchanged.
PARTIAL TRUTH TABLE (Non-burst)
Function |
R/W |
BW1 |
BW2 |
BW3 |
BW4 |
CEx |
ADV/LD |
Read |
H |
X |
X |
X |
X |
L |
L |
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Write Byte 1 |
L |
L |
H |
H |
H |
L |
L |
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Write Byte 2 |
L |
H |
L |
H |
H |
L |
L |
Write Byte 3 |
L |
H |
H |
L |
H |
L |
L |
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Write Byte 4 |
L |
H |
H |
H |
L |
L |
L |
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Write All Bytes |
L |
L |
L |
L |
L |
L |
L |
FUNCTIONAL TIMING DIAGRAM
CYCLE |
n+29 |
n+30 |
n+31 |
n+32 |
n+33 |
n+34 |
n+35 |
n+36 |
n+37 |
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CLOCK |
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ADDRESS |
A29 |
A30 |
A31 |
A32 |
A33 |
A34 |
A35 |
A36 |
A37 |
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(A0-A15) |
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CONTROL |
C29 |
C30 |
C31 |
C32 |
C33 |
C34 |
C35 |
C36 |
C37 |
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(BWx, R/W, ADV/LD) |
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DATA |
D27 |
D28 |
D29 |
D30 |
D31 |
D32 |
D33 |
D34 |
D35 |
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(I/O1-I/O32) |
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4 |
Integrated Silicon Solution, Inc. |
ADVANCE INFORMATION SR050-0B 07/15/98