IS61SPS25632T/D IS61LPS25632T/D IS61SPS25636T/D IS61LPS25636T/D ISSI®
IS61SPS51218T/D IS61LPS51218T/D
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, SINGLE-CYCLE DESELECT STATIC RAM
PRELIMINARY INFORMATION
MAY 2001
FEATURES
•Internal self-timed write cycle
•Individual Byte Write Control and Global Write
•Clock controlled, registered address, data and control
•Linear burst sequence control using MODE input
•Three chip enable option for simple depth expansion and address pipelining
•Common data inputs and data outputs
•JEDEC 100-Pin TQFP and 119-pin PBGA package
•Single +3.3V, +10%, –5% power supply
•Power-down snooze mode
•3.3V I/O For SPS
•2.5V I/O For LPS
•Single cycle deselect
•Snooze MODE for reduced-power standby
•T version (three chip selects)
•D version (two chip selects)
FAST ACCESS TIME
Symbol |
Parameter |
-150 |
-133 |
Units |
tKQ |
Clock Access Time |
3.8 |
4 |
ns |
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tKC |
Cycle Time |
6.7 |
7.5 |
ns |
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Frequency |
150 |
133 |
MHz |
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DESCRIPTION
The ISSI IS61SPS25632,IS61SPS25636,IS61SPS51218, IS61LPS25632, IS61LPS25636, and IS61LPS51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance memory for communication and networking applications. The IS61SPS25632 and IS61LPS25632 are organized as 262,144 words by 32 bits and the IS61SPS25636 and IS61LPS25636 are organized as 262,144 words by 36 bits. The IS61SPS51218 and IS61LPS51218 are organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive- edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
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PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D |
IS61LPS25632T/D |
ISSI |
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IS61SPS25636T/D |
IS61LPS25636T/D |
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IS61SPS51218T/D |
IS61LPS51218T/D |
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BLOCK DIAGRAM
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MODE |
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Q0 |
A0' |
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CLK |
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CLK |
A0 |
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BINARY |
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COUNTER |
A1' |
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ADV |
CE |
Q1 |
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A1 |
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ADSC |
CLR |
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256Kx32; 256Kx36; |
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512Kx18 |
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ADSP |
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A18-A0 |
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MEMORY ARRAY |
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(61SPS51218, |
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61LPS51218) |
18/19 |
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16/17 |
18/19 |
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Q |
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A17-A0 |
D |
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(61SPS25632/36, |
ADDRESS |
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61LPS25632/36) |
REGISTER |
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CE |
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CLK |
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32, 36, |
32, 36, |
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or 18 |
or 18 |
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GW |
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DQd |
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BWE |
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BYTE WRITE |
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BWd |
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CLK |
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DQc |
Q |
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BWc |
BYTE WRITE |
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(x32/x36) |
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CLK |
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DQb |
Q |
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BWb |
BYTE WRITE |
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(x32/x36/x18) |
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CLK |
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DQa |
Q |
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BWa |
BYTE WRITE |
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REGISTERS |
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(x32/x36/x18) |
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CLK |
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(T, D) CE |
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4 |
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32, 36, |
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(T, D) CE2 |
D |
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Q |
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INPUT |
OUTPUT |
or 18 |
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(T) CE2 |
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ENABLE |
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REGISTERS |
REGISTERS |
DQa - DQd |
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OE |
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REGISTER |
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CLK |
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CE |
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CLK |
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D |
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Q |
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ENABLE |
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DELAY |
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REGISTER |
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CLK |
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OE |
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Integrated Silicon Solution, Inc. — 1-800-379-4774 |
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PRELIMINARY INFORMATION |
Rev. 00B |
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05/09/01 |
IS61SPS25632T/D |
IS61LPS25632T/D |
ISSI |
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IS61SPS25636T/D |
IS61LPS25636T/D |
® |
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IS61SPS51218T/D |
IS61LPS51218T/D |
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PIN CONFIGURATION
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119-pin PBGA (Top View) |
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100-Pin TQFP (D Version) |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
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A6 |
A7 |
CE |
CE2 |
BWd BWc BWb BWa |
A17 VCC |
GND CLK GW BWE OE |
ADSC ADSP ADV A8 |
A9 |
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A |
A6 |
A4 |
ADSP |
A8 |
A16 |
VCCQ |
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100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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VCCQ |
NC |
1 |
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80 |
NC |
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B |
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DQc1 |
2 |
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79 |
DQb8 |
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NC |
CE2 |
A3 |
ADSC |
A9 |
A17 |
NC |
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DQc2 |
3 |
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78 |
DQb7 |
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C |
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A7 |
A2 |
VCC |
A12 |
A15 |
NC |
VCCQ |
4 |
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77 |
VCCQ |
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NC |
GND |
5 |
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76 |
GND |
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D |
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NC |
GND |
NC |
GND |
NC |
DQb8 |
DQc3 |
6 |
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75 |
DQb6 |
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DQc1 |
DQc4 |
7 |
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74 |
DQb5 |
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E |
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DQc3 |
GND |
CE |
GND |
DQb6 |
DQb7 |
DQc5 |
8 |
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73 |
DQb4 |
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DQc2 |
DQc6 |
9 |
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72 |
DQb3 |
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F |
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DQc4 |
GND |
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GND |
DQb5 |
VCCQ |
GND |
10 |
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71 |
GND |
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VCCQ |
OE |
VCCQ |
11 |
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70 |
VCCQ |
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G |
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DQc7 |
12 |
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69 |
DQb2 |
DQc5 |
DQc6 |
BWc |
ADV |
BWb |
DQb4 |
DQb3 |
DQc8 |
13 |
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68 |
DQb1 |
H |
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NC |
14 |
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67 |
GND |
DQc7 |
DQc8 |
GND |
GW |
GND |
DQb2 |
DQb1 |
VCC |
15 |
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66 |
NC |
J |
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NC |
16 |
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65 |
VCC |
VCCQ |
VCC |
NC |
VCC |
NC |
VCC |
VCCQ |
GND |
17 |
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64 |
ZZ |
K |
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DQd1 |
18 |
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63 |
DQa8 |
DQd1 |
DQd2 |
GND |
CLK |
GND |
DQa7 |
DQa8 |
DQd2 |
19 |
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62 |
DQa7 |
L |
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VCCQ |
20 |
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61 |
VCCQ |
DQd4 |
DQd3 |
BWd |
NC |
BWa |
DQa5 |
DQa6 |
GND |
21 |
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60 |
GND |
M |
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DQd3 |
22 |
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59 |
DQa6 |
VCCQ |
DQd5 |
GND |
BWE |
GND |
DQa4 |
VCCQ |
DQd4 |
23 |
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58 |
DQa5 |
N |
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DQd5 |
24 |
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57 |
DQa4 |
DQd6 |
DQd7 |
GND |
A1 |
GND |
DQa3 |
DQa2 |
DQd6 |
25 |
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56 |
DQa3 |
P |
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GND |
26 |
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55 |
GND |
DQd8 |
NC |
GND |
A0 |
GND |
NC |
DQa1 |
VCCQ |
27 |
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54 |
VCCQ |
R |
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DQd7 |
28 |
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53 |
DQa2 |
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DQd8 |
29 |
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52 |
DQa1 |
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NC |
A5 |
MODE |
VCC |
NC |
A13 |
NC |
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T |
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NC |
30 |
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51 |
NC |
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31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
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NC |
NC |
A10 |
A11 |
A14 |
NC |
ZZ |
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U |
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MODE |
A5 |
A4 |
A3 |
A2 A1 A0 NC |
NC GND |
VCC NC NC A10 A11 |
A12 A13 A14 A15 |
A16 |
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VCCQ |
NC |
NC |
NC |
NC |
NC |
VCCQ |
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256K x 32 |
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PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
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pins must tied to the two LSBs of the |
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address bus. |
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A2-A17 |
Synchronous Address Inputs |
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CLK |
Synchronous Clock |
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ADSP |
Synchronous Processor Address |
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Status |
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ADSC |
Synchronous Controller Address |
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Status |
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ADV |
Synchronous Burst Address Advance |
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BWa-BWd |
Synchronous Byte Write Enable |
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BWE |
Synchronous Byte Write Enable |
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GW |
Synchronous Global Write Enable |
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CE, CE2 |
Synchronous Chip Enable |
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OE |
Output Enable |
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DQa-DQd |
Synchronous Data Input/Output |
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MODE |
Burst Sequence Mode Selection |
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VCC |
+3.3V Power Supply |
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GND |
Ground |
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VCCQ |
Isolated Output Buffer Supply: |
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+3.3V or 2.5V |
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ZZ |
Snooze Enable |
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GNDQ |
Isolated Output Buffer Ground |
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Integrated Silicon Solution, Inc. — 1-800-379-4774 |
3 |
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D |
IS61LPS25632T/D |
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ISSI |
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|||||
IS61SPS25636T/D |
IS61LPS25636T/D |
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® |
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IS61SPS51218T/D |
IS61LPS51218T/D |
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PIN CONFIGURATION |
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100-Pin TQFP (T Version) |
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A6 |
A7 CE |
CE2 |
BWd BWc BWb BWa |
CE2 |
VCC |
GND CLK GW BWE OE |
ADSC ADSP ADV A8 |
A9 |
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100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
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NC |
1 |
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80 |
NC |
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DQc1 |
2 |
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79 |
DQb8 |
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DQc2 |
3 |
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78 |
DQb7 |
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VCCQ |
4 |
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77 |
VCCQ |
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GND |
5 |
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76 |
GND |
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DQc3 |
6 |
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75 |
DQb6 |
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DQc4 |
7 |
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74 |
DQb5 |
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DQc5 |
8 |
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73 |
DQb4 |
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DQc6 |
9 |
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72 |
DQb3 |
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GND |
10 |
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71 |
GND |
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VCCQ |
11 |
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70 |
VCCQ |
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DQc7 |
12 |
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69 |
DQb2 |
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DQc8 |
13 |
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68 |
DQb1 |
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NC |
14 |
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67 |
GND |
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VCC |
15 |
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66 |
NC |
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NC |
16 |
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65 |
VCC |
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GND |
17 |
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64 |
ZZ |
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DQd1 |
18 |
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63 |
DQa8 |
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DQd2 |
19 |
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62 |
DQa7 |
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VCCQ |
20 |
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61 |
VCCQ |
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GND |
21 |
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60 |
GND |
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DQd3 |
22 |
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59 |
DQa6 |
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DQd4 |
23 |
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58 |
DQa5 |
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DQd5 |
24 |
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57 |
DQa4 |
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DQd6 |
25 |
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56 |
DQa3 |
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GND |
26 |
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55 |
GND |
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VCCQ |
27 |
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|
|
|
54 |
VCCQ |
|
|
DQd7 |
28 |
|
|
|
|
|
|
|
53 |
DQa2 |
|
|
DQd8 |
29 |
|
|
|
|
|
|
|
52 |
DQa1 |
|
|
NC |
30 |
|
|
|
|
|
|
|
51 |
NC |
|
|
|
31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
|
|
||||||
|
|
MODE |
A5 A4 |
A3 |
A2 A1 A0 NC |
NC |
GND |
VCC NC A17 A10 A11 |
A12 A13 A14 A15 |
A16 |
|
|
256K x 32
PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
|
pins must tied to the two LSBs of the |
|
address bus. |
|
|
A2-A17 |
Synchronous Address Inputs |
|
|
CLK |
Synchronous Clock |
|
|
ADSP |
Synchronous Processor Address |
|
Status |
|
|
ADSC |
Synchronous Controller Address |
|
Status |
|
|
ADV |
Synchronous Burst Address Advance |
|
|
BWa-BWd |
Synchronous Byte Write Enable |
|
|
BWE |
Synchronous Byte Write Enable |
|
|
GW |
Synchronous Global Write Enable |
|
|
CE, CE2, CE2 Synchronous Chip Enable |
|
|
|
OE |
Output Enable |
|
|
DQa-DQd |
Synchronous Data Input/Output |
|
|
MODE |
Burst Sequence Mode Selection |
|
|
VCC |
+3.3V Power Supply |
|
|
GND |
Ground |
|
|
VCCQ |
Isolated Output Buffer Supply: |
|
+3.3V or 2.5V |
|
|
ZZ |
Snooze Enable |
|
|
GNDQ |
Isolated Output Buffer Ground |
|
|
4 Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D |
IS61LPS25632T/D |
ISSI |
|
IS61SPS25636T/D |
IS61LPS25636T/D |
® |
|
IS61SPS51218T/D |
IS61LPS51218T/D |
|
PIN CONFIGURATION
|
119-pin PBGA (Top View) |
|
|
|
|
100-Pin TQFP (D Version) |
|
|
|
|||||||||
1 |
2 |
3 |
4 |
5 |
6 |
7 |
|
A6 |
A7 |
CE |
CE2 BWd BWc BWb BWa |
A17 VCC |
GND CLK GW BWE OE |
ADSC ADSP ADV |
A8 |
A9 |
|
|
A |
|
|
|
|
|
|
|
100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
|
||||||
VCCQ |
A6 |
A4 |
ADSP |
A8 |
A16 |
VCCQ |
DQPc |
1 |
|
|
|
|
|
|
|
|
80 |
DQPb |
B |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
CE2 |
A3 |
ADSC |
A9 |
A17 |
NC |
DQc1 |
2 |
|
|
|
|
|
|
|
|
79 |
DQb8 |
|
NC |
DQc2 |
3 |
|
|
|
|
|
|
|
|
78 |
DQb7 |
||||||
C |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
A7 |
A2 |
VCC |
A12 |
A15 |
NC |
VCCQ |
4 |
|
|
|
|
|
|
|
|
77 |
VCCQ |
|
NC |
GND |
5 |
|
|
|
|
|
|
|
|
76 |
GND |
||||||
D |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
DQPc |
GND |
NC |
GND |
DQPb |
DQb8 |
DQc3 |
6 |
|
|
|
|
|
|
|
|
75 |
DQb6 |
|
DQc1 |
DQc4 |
7 |
|
|
|
|
|
|
|
|
74 |
DQb5 |
||||||
E |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
DQc5 |
8 |
|
|
|
|
|
|
|
|
73 |
DQb4 |
|
DQc2 |
DQc3 |
GND |
CE |
GND |
DQb6 |
DQb7 |
|
|
|
|
|
|
|
|
||||
DQc6 |
9 |
|
|
|
|
|
|
|
|
72 |
DQb3 |
|||||||
F |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
GND |
10 |
|
|
|
|
|
|
|
|
71 |
GND |
|
VCCQ |
DQc4 |
GND |
OE |
GND |
DQb5 |
VCCQ |
|
|
|
|
|
|
|
|
||||
VCCQ |
11 |
|
|
|
|
|
|
|
|
70 |
VCCQ |
|||||||
G |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
DQc7 |
12 |
|
|
|
|
|
|
|
|
69 |
DQb2 |
|
DQc5 |
DQc6 |
BWc |
ADV |
BWb |
DQb4 |
DQb3 |
|
|
|
|
|
|
|
|
||||
DQc8 |
13 |
|
|
|
|
|
|
|
|
68 |
DQb1 |
|||||||
H |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
NC |
14 |
|
|
|
|
|
|
|
|
67 |
GND |
|
DQc7 |
DQc8 |
GND |
GW |
GND |
DQb2 |
DQb1 |
|
|
|
|
|
|
|
|
||||
VCC |
15 |
|
|
|
|
|
|
|
|
66 |
NC |
|||||||
J |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
NC |
16 |
|
|
|
|
|
|
|
|
65 |
VCC |
|
VCCQ |
VCC |
NC |
VCC |
NC |
VCC |
VCCQ |
|
|
|
|
|
|
|
|
||||
GND |
17 |
|
|
|
|
|
|
|
|
64 |
ZZ |
|||||||
K |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
DQd1 |
18 |
|
|
|
|
|
|
|
|
63 |
DQa8 |
|
DQd1 |
DQd2 |
GND |
CLK |
GND |
DQa7 |
DQa8 |
|
|
|
|
|
|
|
|
||||
DQd2 |
19 |
|
|
|
|
|
|
|
|
62 |
DQa7 |
|||||||
L |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
VCCQ |
20 |
|
|
|
|
|
|
|
|
61 |
VCCQ |
|
DQd4 |
DQd3 |
BWd |
NC |
BWa |
DQa5 |
DQa6 |
|
|
|
|
|
|
|
|
||||
GND |
21 |
|
|
|
|
|
|
|
|
60 |
GND |
|||||||
M |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
DQd3 |
22 |
|
|
|
|
|
|
|
|
59 |
DQa6 |
|
VCCQ |
DQd5 |
GND |
BWE |
GND |
DQa4 |
VCCQ |
|
|
|
|
|
|
|
|
||||
N |
|
|
|
|
|
|
DQd4 |
23 |
|
|
|
|
|
|
|
|
58 |
DQa5 |
|
|
|
|
|
|
DQd5 |
24 |
|
|
|
|
|
|
|
|
57 |
DQa4 |
|
DQd6 |
DQd7 |
GND |
A1 |
GND |
DQa3 |
DQa2 |
|
|
|
|
|
|
|
|
||||
P |
|
|
|
|
|
|
DQd6 |
25 |
|
|
|
|
|
|
|
|
56 |
DQa3 |
|
|
|
|
|
|
GND |
26 |
|
|
|
|
|
|
|
|
55 |
GND |
|
DQd8 |
DQPd |
GND |
A0 |
GND |
DQPa |
DQa1 |
|
|
|
|
|
|
|
|
||||
R |
|
|
|
|
|
|
VCCQ |
27 |
|
|
|
|
|
|
|
|
54 |
VCCQ |
NC |
A5 |
MODE |
VCC |
NC |
A13 |
NC |
DQd7 |
28 |
|
|
|
|
|
|
|
|
53 |
DQa2 |
T |
|
|
|
|
|
|
DQd8 |
29 |
|
|
|
|
|
|
|
|
52 |
DQa1 |
NC |
NC |
A10 |
A11 |
A14 |
NC |
ZZ |
DQPd |
30 |
|
|
|
|
|
|
|
|
51 |
DQPa |
U |
|
|
|
|
|
|
|
31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCCQ |
NC |
NC |
NC |
NC |
NC |
VCCQ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MODE |
A5 |
A4 |
A3 |
A2 A1 A0 NC |
NC GND |
VCC NC NC A10 A11 |
A12 A13 A14 |
A15 |
A16 |
|
|
|
|
|
|
|
|
256K x 36 |
|
|
|
|
|
|
|
|
|
|
|
PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
|
pins must tied to the two LSBs of the |
|
address bus. |
|
|
A2-A17 |
Synchronous Address Inputs |
CLK |
Synchronous Clock |
|
|
ADSP |
Synchronous Processor Address |
|
Status |
|
|
ADSC |
Synchronous Controller Address |
|
Status |
|
|
ADV |
Synchronous Burst Address Advance |
BWa-BWd |
Individual Byte Write Enable |
|
|
BWE |
Synchronous Byte Write Enable |
|
|
GW |
Synchronous Global Write Enable |
|
|
CE, CE2 |
Synchronous Chip Enable |
OE |
Output Enable |
|
|
DQa-DQd |
Synchronous Data Input/Output |
|
|
MODE |
Burst Sequence Mode Selection |
|
|
VCC |
+3.3V Power Supply |
|
|
GND |
Ground |
|
|
VCCQ |
Isolated Output Buffer Supply: |
|
+3.3V or 2.5V |
|
|
ZZ |
Snooze Enable |
|
|
DQPa-DQPd |
Parity Data I/O |
|
|
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
5 |
PRELIMINARY INFORMATION Rev. 00B
05/09/01
IS61SPS25632T/D |
IS61LPS25632T/D |
ISSI |
|
IS61SPS25636T/D |
IS61LPS25636T/D |
® |
|
IS61SPS51218T/D |
IS61LPS51218T/D |
|
PIN CONFIGURATION
100-Pin TQFP (T Version)
|
A6 |
A7 CE |
CE2 |
BWd BWc BWb BWa |
CE2 VCC |
GND CLK GW BWE OE |
ADSC ADSP ADV A8 |
A9 |
|
|
100 99 98 97 |
96 95 94 93 |
92 91 90 89 88 87 86 |
85 84 83 82 81 |
|
||||
DQPc |
1 |
|
|
|
|
|
|
80 |
DQPb |
DQc1 |
2 |
|
|
|
|
|
|
79 |
DQb8 |
DQc2 |
3 |
|
|
|
|
|
|
78 |
DQb7 |
VCCQ |
4 |
|
|
|
|
|
|
77 |
VCCQ |
GND |
5 |
|
|
|
|
|
|
76 |
GND |
DQc3 |
6 |
|
|
|
|
|
|
75 |
DQb6 |
DQc4 |
7 |
|
|
|
|
|
|
74 |
DQb5 |
DQc5 |
8 |
|
|
|
|
|
|
73 |
DQb4 |
DQc6 |
9 |
|
|
|
|
|
|
72 |
DQb3 |
GND |
10 |
|
|
|
|
|
|
71 |
GND |
VCCQ |
11 |
|
|
|
|
|
|
70 |
VCCQ |
DQc7 |
12 |
|
|
|
|
|
|
69 |
DQb2 |
DQc8 |
13 |
|
|
|
|
|
|
68 |
DQb1 |
NC |
14 |
|
|
|
|
|
|
67 |
GND |
VCC |
15 |
|
|
|
|
|
|
66 |
NC |
NC |
16 |
|
|
|
|
|
|
65 |
VCC |
GND |
17 |
|
|
|
|
|
|
64 |
ZZ |
DQd1 |
18 |
|
|
|
|
|
|
63 |
DQa8 |
DQd2 |
19 |
|
|
|
|
|
|
62 |
DQa7 |
VCCQ |
20 |
|
|
|
|
|
|
61 |
VCCQ |
GND |
21 |
|
|
|
|
|
|
60 |
GND |
DQd3 |
22 |
|
|
|
|
|
|
59 |
DQa6 |
DQd4 |
23 |
|
|
|
|
|
|
58 |
DQa5 |
DQd5 |
24 |
|
|
|
|
|
|
57 |
DQa4 |
DQd6 |
25 |
|
|
|
|
|
|
56 |
DQa3 |
GND |
26 |
|
|
|
|
|
|
55 |
GND |
VCCQ |
27 |
|
|
|
|
|
|
54 |
VCCQ |
DQd7 |
28 |
|
|
|
|
|
|
53 |
DQa2 |
DQd8 |
29 |
|
|
|
|
|
|
52 |
DQa1 |
DQPd |
30 |
|
|
|
|
|
|
51 |
DQPa |
|
31 32 33 |
34 35 36 37 38 39 40 |
41 42 43 44 45 46 47 48 49 50 |
|
|||||
|
MODE |
A5 A4 |
A3 |
A2 A1 A0 NC |
NC GND |
VCC NC A17 A10 A11 |
A12 A13 A14 A15 |
A16 |
|
256K x 36
PIN DESCRIPTIONS
A0, A1 |
Synchronous Address Inputs. These |
|
pins must tied to the two LSBs of the |
|
address bus. |
A2-A17 |
Synchronous Address Inputs |
|
|
CLK |
Synchronous Clock |
|
|
ADSP |
Synchronous Processor Address |
|
Status |
|
|
ADSC |
Synchronous Controller Address |
|
Status |
ADV |
Synchronous Burst Address Advance |
|
|
BWa-BWd |
Individual Byte Write Enable |
|
|
BWE |
Synchronous Byte Write Enable |
|
|
GW |
Synchronous Global Write Enable |
CE, CE2, CE2 Synchronous Chip Enable |
|
|
|
OE |
Output Enable |
|
|
DQa-DQd |
Synchronous Data Input/Output |
MODE |
Burst Sequence Mode Selection |
|
|
VCC |
+3.3V Power Supply |
GND |
Ground |
|
|
VCCQ |
Isolated Output Buffer Supply: |
|
+3.3V or 2.5V |
|
|
ZZ |
Snooze Enable |
DQPa-DQPd |
Parity Data I/O |
|
|
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
05/09/01