MCS4
Microcomputer
Kit
MCS4
KIT
A
MCS~4
IDEAL FOR
- INTEL'S LOWEST COST MICROCOMPUTER.
PROTOTYPE OR LOW VOLUME
PRODUCTION.
The MCS-4 is a microprogrammable
computer set designed
as
such
terminals,
test systems, peripherals,
billing machines, measuring
systems, numeric and process
The 4004
CPU,
4003
are standard building blocks.
The
4008 and
4009
face devices which expand the capabilities of
Intel's MCS-4 microcomputer
set. Now standard
and RAMs may
be
gram memory of the MCS-4.
MCS-4 systems interface easily with
switches, keyboards, displays, teletypewriters, printers, readers, A-D converters and other popular peripherals.
A system built with the
computer set can have up to
bit
ROM
words, 1280 x 4
characters and 128
for
applications
control.
SR,
and 4002
are a pair
of
RAM
inter-
Intel PROMs, ROMs
used
for
the pro-
MCS-4 micro-
4K
x 8
bit
RAM
I/O
lines without
requiring any interface logic. By adding
a few simple gates the
have
up
to
48
RAM and
in
any combination, and 192
MCS-4 has a very powerful in-
The
MCS-4 can
ROM
packages
I/O
lines.
struction set that allows both binary
and decimal arithmetic.
It includes
conditional branching, jump to sub-
routine, and provides
use
of
ROM
look-up tables by indirect
for
the efficient
fetching.
The
Intel MCS-4 microcomputer set
(4002/3/4/8/9
and 4702A) are fabri-
cated with Silicon Gate Technology.
This low threshold technology allows
the design and production of higher
performance
MaS
circuits and provides
a higher functional density on a monolithic chip than conventional
MaS
technologies.
• Programmable General
Purpose Microcomputer
• 4-Bit Parallel CPU with 46
Instructions
• Instruction Set includes
Conditional Branching,
Jump to Subroutine and
Indirect Fetching
• Binary and Decimal
Arithmetic Modes
• Program Storage
in
4702A
Reprogrammable PROM
Simulates
2-Phase Dynamic Operation
•
4001
ROM
• 10.8 Microsecond
Instruction Cycle
CPU Directly Compatible
•
MCS-4 ROMs and
with
RAMs Using
Standard Memory
1/0
Interface Set
• Easy
Expansion-One
can
Directly Drive up to
32,768 Bits of
5120 Bits of RAM
to
4008/4009
ana
CPU
ROM and up
4004 CPU
16
I
CM·RAM,
MEMORY
BUS
I/O
0,
~"f
0,
GNO
5 12
Vss
6
p~~g~~}<p,
p~~~m<p,
Ou;~~nSYNC
·THIS
PIN
IS
THE
II
7
8
4702A ROM
DATA
INPUT
LEAD
CM.RAM,
""l
CM·RAM
Voo
CM·ROM
DURING
CONTROL
OUTPUTS
3
-15V
{MEMORY
CONTROL
.
OUTPUT
PROGRAMMING.
4002
RAM
I
16
BUS
1100,
0
3
""f
p~~i~}<p,
p~l~g}<P,
I~~~~}SYNC
6
7
8 9
4008
12
II
10
0,
OUTPUT
O2 LINES
'j
0
3
-15V
Voo
{MEMORY
CM
CONTROL
INPUT
·lHAROWIREO
Po
CHIPSELECT
INPUT
RESET
4003SR
PULSE
~~~~*p
PARALLEL{Oo
OUTPUTS
n,
PARALLEL
0
OUTPUTS
3
O.
f
I
3
6
4009
13
a.
a
PARALLEL
7
OUTPUTS
')
a.
05
MCS4 KIT A
SYSTEM INTERCONNECT
+5V
.1/,1
7400
HC-18/U
(XTAL)
5.185 MHZ
820n
1 2
50 .01/'1
~
Ipi
820n
74H04
47S1
47n
+5
11
on
11
on
5.6K
-10V
RESET
TEST
SUGGESTED CLOCK DRIVER, TEST AND RESET CIRCUITRY
III
9f
III
16
15
14
13
RESET
CM-ROM
SYNC
DO
Dl
D2
D3
RDO
RD1
RD2 7
RD3
RD4
RD5 2
RD6 3
RD7
CM-RAM 0
CM-RAM 1
CM-RAM 2
CM-RAM 3
5
6
8
1
4
1.
2322
21rf
i 4009
110 {
910
OUT
iN
'----y-----/
INPUT/OUTPUT
PORT
~
~
13
14
~
~
~2
~6
3
CIRCUITRY
**
TEST
~
~
NOTES:
••••
(V
ss
Jl2
CONSUL
SEE
4008/4009
SEE
4702A
THESE LINES
FOR
UP
=
+5V
!5%;
~
~
--2...
-1Q...
T
MCS
4 USER'S
DATA
DATA
MAY
TO 16
PROMS.
Voo = -10V
8
7
SHEET .
1 2 3 4
F/L
W
11
13
****
SHEET.
BE
DECODED
!5%)
i 4008
1415
C C C C
3 2 1 0
MANUAL.
I
7'
10
1
12
I I 1
I 1
I
221231121131151
3
2
1
21
i 4702A
20
PROM
19
18
17
14
24116
Voo
'{
16PROMS * * *
6
3 4
0
i C4004
CPU
81111
4
5
6
7
8
9
10
11
Vss
TEST
23
22
21
20
19
18
17
16
AO
Al
A2
A3
A4
A5
A6
Al
~
TO
DATA
IN
PO
0-----;-0
Vss
---
~
--
--
-
r-
1 2 14
f
RAM
i P4002-1
o 1 2 3
161514\131
I
I
I
CP
I I ENABLE
I
).,
16
1
i P4003
31416171819ttttl
00---------
'-----y----J
PARALLEL OUTPUTS
--
8 9
------
7 6
- -
-
-
----
-
--
- -
----
-
09
---
---
---
---
15
--
--
--
SERIAL
DATA
OUT
UP
16
4 RAMS
PER
TO
RAMS
*
BANK
INTEL CORPORATION, 3065 Bowers Avenue, Santa Clara, California
©Intel Corp. 1974jPrintec!.in U.SAjMCS-20S-0874-SK
95051
(408) 246-7501