LXD381 — Evaluation Board for
Octal E1 Applications
Developer Manual
January 2001
As of January 15, 2001, this document replaces the Level One document Order Number: 249213-001
LXD381 — Evaluation Board for Octal E1 Applications User Guide.
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXD381 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
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Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
LXD381 — Evaluation Board for Octal E1 Applications Developer Manual
Contents
1.0 General Description .................................................................................................. 5
1.1 Features ................................................................................................................ 5
2.0 Evaluation Board Set-Up......................................................................................... 7
2.1 LXD381 Packing List .............................................................................................7
2.2 Equipment Requirements ......................................................................................7
2.3 Power Connections ............................................................................................... 7
2.4 Loopback Mode Selection.....................................................................................7
2.5 Receive Polarity Selection.....................................................................................8
2.6 Output Enable Selection........................................................................................ 8
2.7 Unused Switches...................................................................................................8
2.8 Back-End Interface Connection.............................................................................8
2.9 Line Interface Connection ..................................................................................... 9
2.10 Line Interface Circuit ............................................................................................. 9
2.11 Board Protection....................................................................................................9
3.0 Evaluation Board Schematics.............................................................................10
Figures
Tables
1 LXD381 Evaluation Board.....................................................................................6
2 S2 Factory Switch Settings ................................................................................... 8
3 Typical Back-End Connector.................................................................................9
4 Evaluation Board Schematic — Data/Control .....................................................10
5 Evaluation Board Schematic — Digital I/O.......................................................... 11
6 Evaluation Board Schematic — Analog 1 ...........................................................12
7 Evaluation Board Schematic — Analog 2 ...........................................................13
1 LOOP0 - 7 Switch Settings....................................................................................7
LXD381 — Evaluation Board for Octal E1 Applications Developer Manual iii
Evaluation Board for Octal E1 Applications — LXD381
1.0 General Description
The LXD381 evaluation board is a versatile tool for engineers designing E1 short haul applications
using the LXT381.
The evaluation board operates in Hardware mode only. All device and channel controls are set
using jumper blocks and DIP switches.
The board provides banana jacks for both power and line interface connections. Connectors are
provided for each framer or back-end ASIC interface. An E1 pattern generator/analyzer may be
used to provide external signals for evaluation.
1.1 Features
• Hardware controllable
• ZIF LQFP socket for easy swapping of LXT381
• Banana jacks for power and line interfaces
• 10-pin connectors for framer/ASIC interface
• Socketed termination components for easy experimentation
• Built-in overvoltage protection for line interface and power supply
Developer Manual 5
LXD381 — Evaluation Board for Octal E1 Applications
Figure 1. LXD381 Evaluation Board
6 Developer Manual
Evaluation Board for Octal E1 Applications — LXD381
2.0 Evaluation Board Set-Up
Caution: CMOS devices are static (ESD) sensitive. Take all industry standard precautions when handling the
evaluation board, the LXT381 chip and other sensitive electronic components.
Before proceeding with any evaluation board operations, review the specifications for the LXT381
transceiver.
2.1 LXD381 Packing List
The evaluation board kit contains the following components:
• LXD381 board with LXT381 device installed.
• LXD381 User Guide.
• LXT381 Data Sheet.
2.2 Equipment Requirements
The evaluation board kit includes all the circuit components needed for a successful evaluation.
However, the following lab equipment is required:
• Power Supply (+3.3 VDC).
• Telecom cable or cable simulator (optional).
• E1 pattern generator/analyzer
2.3 Power Connections
The evaluation board has two power planes (VCC and TVCC) each of which is tied to a separate
red colored banana jack. Connect the +3.3 VDC power supply to both the VCC (B1) and TVCC
(B3) banana jacks. Connect the power supply ground lead to the black banana jack (B2).
2.4 Loopback Mode Selection
The LXT381 LOOP signals for channels 0 through 7 are set by the switches in switch block S1. As
shown in Table 1, these switches have three positions to select Remote Loopback, Analog
Loopback or No Loopback.
Table 1. LOOP0 - 7 Switch Settings
S1 Switch Position Operation
High Analog Loopback
Center No Loopback
Low Remote Loopback
Developer Manual 7
LXD381 — Evaluation Board for Octal E1 Applications
2.5 Receive Polarity Selection
The polarity of RPOS/RNEG is determined by the CLKE switch in switch block S2. When the
CLKE switch is OFF, RPOS/RNEG are active Low. When set to the ON position, RPOS/RNEG
are active High. Note that the CLKE switch controls the LXT381’s RPOL pin.
2.6 Output Enable Selection
The OE switch in switch block S3 controls the operation of the LXT381 output drivers. For normal
operation (driver outputs enabled), set the OE switch to the ON position. Setting the OE switch to
OFF forces the output drivers to the high impedance state.
2.7 Unused Switches
Switches 3 and 4, in switch block S2, have no function on the LXD381 and should be set to the
OFF position. Figure 2 shows the factory default settings for switch block S2.
Figure 2. S2 Factory Switch Settings
S2
F
F
NOTE: OFF position = Low
2.8 Back-End Interface Connection
Eight 10 pin connectors (JP1 - JP8) provide access to the LXT381 digital signals to allow
interfacing the back-end Framer/Mapper or ASIC with an external pattern generator. Figure 3
shows a typical connector (JP1 for channel 0) with the factory installed jumper connecting RCLK
to TCLK. This jumper is normally installed when feeding analog test data from the line interface
(TIP and RING).
O
1 2 3 4
CLKE
OE
8 Developer Manual
Figure 3. Typical Back-End Connector
Evaluation Board for Octal E1 Applications — LXD381
JP1
TCLK 0
TCLK 0
TPOS 0
TNEG 0
2.9 Line Interface Connection
Access to the line interface is provided through the green and white banana jacks. The TIP signal is
routed to the white jacks for both transmit and receive directions. The RING signal is routed to the
green jacks for both directions.
2.10 Line Interface Circuit
Two octal transformers are used for channels 0 to 3 and 4 to 7. Transformers, resistors and
capacitors for channels 0 and 4 are socketed for easy swapping (see the LXT381 data sheet for line
interface information). Jumper blocks are provided to configure the receive transformer operation
for 1:1 or 1:2 turns ratio (see “Evaluation Board Schematics” on page 10). Factory installed
jumpers configure the transformers for a 1:1 ratio.
12
34
56
78
10
9
GND
RCLK 0
RPOS 0
RNEG 0
GNDLOS 0
2.11 Board Protection
The evaluation board provides line surge protection for both the power supply and the line. Two
transient voltage suppressors (TVS) are included for power supply protection. The E1 line interface
transmitters are protected with Schottky diodes and the receivers are protected by series input
resistors. This protection is sufficient for G.703 Annex B compliance.
Developer Manual 9
LXD381 — Evaluation Board for Octal E1 Applications
3.0 Evaluation Board Schematics
Figure 4. Evaluation Board Schematic — Data/Control
LOS0
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
RN2_1
C1 0.1uF
C3 0.1uF
C2 0.1uF
VCC
VCC
C4 0.1uF
92
17
90
19
42357568113
LOS0
LOS1
LOS2
LOS3
VCCIO1
VCCIO0
VCC1
VCC0
1063140
LOS4
LOS5
LOS6
LOS7
97
GND
RN2_2
94
GND
GNDIO1
GND1
GNDIO0
GND0
91
89
18
20
RN2_8
RN2_9
CLKE
OE
876
5
S2
123
4
JA CONTROL
VCC
SW DIP-4
RN2
10
CM1
RN1_9
RN1_8
R8
RN1_7
RN1_6
R5R6R7
RN1_4
CM2
RN1_3
R4
RN1_2
RN2_2
RN2_1
213467895
R2R1R3
RN1_1
U1A
RPD
10
VCC
R.NETWORK 4.7K
11
MODE
CLKE
115
CLKE
GND
GND
43
88
RN2_9
RN2_8OERN1_1
16
GND
RN1_2
GND
RN1_3
TVCC
GND
131415
RN1_4
GND
12
RN1_6
GND
GND
87
RN1_8
S3_9
GND
114
OE
RN1_7
GND
848586
RN1_9
GND
C6
C5
D1
.01uf
68 uF
LOOP0/D0
LOOP1/D1
LOOP2/D2
21222324252627
S3
R1
VCC
TVS 5V
1
LOOP3/D3
LOOP4/D4
LOOP5/D5
118
-
4.7K
LOOP6/D6
LOOP7/D7
28
2103
BOPx
VCC
S3_9
4
5
6
7
8
9
+
TriState9
TVS 3.3V
D2
C8
.01uf
C7
68 uF
1
BN3
RED
+
3.3 VOLTS
BANANA JACK
RN1
BN1
RED1BN2
10
R8
CM1
213467895
R2R1R3
R4
R5R6R7
CM2
R.NETWORK 4.7K
+
TVCC
BANANA JACK
BLACK
-
GROUND
10 Developer Manual
Evaluation Board for Octal E1 Applications — LXD381
Figure 5. Evaluation Board Schematic — Digital I/O
RCLK4
RPOS4/RDATA4
RNEG4/BPV4
RNEG5/BPV5
RPOS5/RDATA5
RCLK5
RCLK6
RPOS6/RDATA6
RNEG6/BPV6
RCLK7
RPOS7/RDATA7
RNEG7/BPV7
JP2
12
34
56
TCLK4
TPOS4/TDATA4
RPOS0/RDATA0
RCLK0
JP1
12
34
56
CHANNEL 4
78
910
HEADER 5X2
LOS4
TNEG4/UBS4
RNEG0/BPV0
CHANNEL 0
78
910
HEADER 5X2
JP4
12
34
56
TCLK5
TPOS5/TDATA5
RPOS1/RDATA1
RCLK1
JP3
12
34
56
CHANNEL 5
78
910
HEADER 5X2
LOS5
TNEG5/UBS5
RNEG1/BPV1
CHANNEL 1
78
910
HEADER 5X2
JP6
12
34
56
TCLK6
TPOS6/TDATA6
RCLK2
RPOS2/RDATA2
JP5
12
34
56
CHANNEL 6
78
910
HEADER 5X2
LOS6
TNEG6/UBS6
RNEG2/BPV2
CHANNEL 2
78
910
HEADER 5X2
JP8
12
34
56
TCLK7
TPOS7/TDATA7
RCLK3
RPOS3/RDATA3
JP7
12
34
56
CHANNEL 7
78
910
HEADER 5X2
LOS7
TNEG7/UBS7
RNEG3/BPV3
CHANNEL 3
78
910
HEADER 5X2
LOS0
TCLK0
TNEG0/UBS0
TPOS0/TDATA0
RN3
10
TCLK0
R8
CM1
TCLK1
TCLK2
TCLK3
R5R6R7
TCLK4
R4
CM2
TCLK5
TCLK7
TCLK6
213467895
R2R1R3
TCLK1
LOS1
TPOS1/TDATA1
TNEG1/UBS1
10
CM1
RN4
R.NETWORK 100K
TPOS0/TDATA0
TPOS4/TDATA4
TPOS2/TDATA2
TPOS3/TDATA3
TPOS1/TDATA1
46789
5
R5R6R7
R8
CM2
TPOS7/TDATA7
TPOS6/TDATA6
TPOS5/TDATA5
213
R2R1R3
R4
LOS2
TCLK2
TPOS2/TDATA2
TNEG2/UBS2
TNEG1/UBS1
TNEG0/UBS0
10
R8
CM1
RN5
R.NETWORK 100K
TNEG2/UBS2
TNEG5/UBS5
TNEG4/UBS4
TNEG3/UBS3
R4
R5R6R7
CM2
TNEG7/UBS7
TNEG6/UBS6
213467895
R2R1R3
R.NETWORK 100K
LOS3
TCLK3
TPOS3/TDATA3
TNEG3/UBS3
Developer Manual 11
LXD381 — Evaluation Board for Octal E1 Applications
Figure 6. Evaluation Board Schematic — Analog 1
GREEN
B9
1
RTIP3x
B1
GREEN
1
RTIP2x
2
WHITE
B3
1
1
3
TTIP2x
RRING2x
JP9
2827302926
B5
1
TRING2x
B7
1
WHITE
GREEN
GREEN
1
TRING3x
WHITE
B14
1
WHITE
B12
B10
1
1
2
3
JP15
2322252421
TTIP3x
RRING3x
R2
B2
RTIP2
GREEN
1
RTIP0x
R14
B11
1K
RTIP3
GREEN
1
RTIP1x
2
T1D
2019161718
R16
60
R15
60
R18
C25
0.22uF
RRING3
WHITE
B13
1
1
JP16
3
3332353431
T1C
1514111213
R4
60
R6
60
1K
2
R8
C19
0.22uF
RRING2
WHITE
B4
1
1
JP10
3
3637394038
1K
TVCC
TTIP0x
RRING0x
JP11
D3
GREEN
B6
1
TRING0x
TG-49-1505-NX
C21 ?pF
11
TTIP2
R10
TVCC
D5
B8
C23
WHITE
1
560pF
D7
R12
11
TRING2
JP13
D9
1K
TVCC
TTIP1x
RRING1x
JP17
D11
GREEN
B15
1
TRING1x
TG-49-1505-NX
C27 ?pF
11
TTIP3
R22
TVCC
D12
B16
C28
WHITE
1
560pF
D14
R24
11
TRING3
JP19
D16
R3
RTIP0
T1A
45321
R5
60
R7
60
1K
R9
C20
0.22uF
RRING0
1K
TVCC
JP12
D4
TG-49-1505-NX
C22 ?pF
11
TTIP0
R11
TVCC
D6
560pF
C24
11
R13
JP14
D8
D10
TRING0
T1B
9
10
R20
60
R19
60
R17
1K
RTIP1
R21
C26
0.22uF
RRING1
1K
678
TVCC
JP18
TG-49-1505-NX
C29 ?pF
D13
11
TTIP1
R23
TVCC
D15
560pF
C30
11
R25
JP20
D17
D18
TRING1
12 Developer Manual
Evaluation Board for Octal E1 Applications — LXD381
Figure 7. Evaluation Board Schematic — Analog 2
B24
B18
GREEN1B20
WHITE1B22
1
RTIP6xRTIP4x
1
RRING6x
TTIP6x
2827302926
TRING6x
2
JP22
3
GREEN
WHITE
1
B25
1
RTIP7x
2
1
3
B26
GREEN
JP27
1
2322252421
WHITE
RRING7x
B28
TTIP7x
1
TRING7x
B30
GREEN
WHITE
1
T2C
1514111213
R29
60
R31
60
R27
RTIP6
B17
1
2
R33
1K
C32
0.22uF
RRING6
GREEN
B19
1
1
RRING4x
JP21
3
3637394038
1K
TVCC
WHITE
B21
TTIP4x
JP24
D20
TRING4x
TG-49-1505-NX
C34 ?pF
11
TTIP6
GREEN1B23
R35
TVCC
D22
1
560pF
C36
11
R37
JP26
D24
WHITE
D26
TRING6
T2D
2019161718
R39
60
R40
60
R38
RTIP7
B27
1
RTIP5x
R42
1K
C37
0.22uF
RRING7
B29
GREEN
1
1
2
JP28
3
3332353431
1K
TVCC
B31
WHITE
RRING5x
TTIP5x
JP29
D27
1
TRING5x
TG-49-1505-NX
C39 ?pF
11
TTIP7
B32
GREEN
R46
TVCC
D28
560pF
C40
11
R48
JP31
D30
WHITE
1
D32
TRING7
R41
RTIP5
T2B
9
10
R43
60
R44
60
R45
1K
C38
0.22uF
RRING5
T2A
45321
R28
60
R30
60
R26
RTIP4
R32
1K
C31
0.22uF
RRING4
1K
TVCC
JP23
D19
TG-49-1505-NX
C33 ?pF
11
TTIP4
R34
TVCC
D21
560pF
C35
11
R36
JP25
D23
D25
TRING4
1K
678
TVCC
JP30
TG-49-1505-NX
C41 ?pF
D29
11
TTIP5
R47
TVCC
D31
560pF
C42
11
R49
JP32
D33
D34
TRING5
Developer Manual 13
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