The LM440LX NLX motherboard may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are documented in the LM440LX NLX Motherboard Specification Update.
Revision History
RevisionRevision HistoryDate
-001First release of LM440LX Technical Product Specification.October 1997
This product specification applies only to standard LM440LX motherboards with BIOS identifier
4L4ML0X0.86A.
Changes to this specification will be published in the LM440LX Motherboard Specification
Update before being incorporated into a revision of this document.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The LM440LX motherboard may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
‡
Wake on LAN is a trademark of IBM Corporation.
†
Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call in North America 1-800-879-4683, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
Copyright 1997, Intel Corporation. All Rights Reserved.
The motherboard is designed to fit into a standard NLX form factor chassis. Figure 2 illustrates the
mechanical form factor for the motherboard. Location of the I/O connectors, riser connector, and
mounting holes is in strict compliance with the NLX I/O Shield Design Suggestions specification
(see Section 6.2).
6.05
9.80
8.70
6.225
0.20
0.00
0.45
0.00
3.40
Figure 2. Motherboard Dimensions
7.80
7.34
OM06337a
9
Motherboard Description
1.3 I/O Shield
The back panel I/O shield for the motherboard must meet specific dimensional and material
requirements. Computers built with this motherboard need the I/O shield to pass EMI certification
testing. Figure 3 shows the critical dimensions for the I/O shield and indicates the position of each
cutout. For more chassis design requirements, see the NLX specification (see Section 6.2).
The motherboard supports a single Pentium II processor. The processor’s VID pins automatically
program the motherboard’s voltage regulator to the required processor voltage. The motherboard
operates with processors that run internally at 233, 266, or 300 MHz and run externally at 66 MHz
host bus speed with either a 256 KB or 512 KB second-level cache.
The processor implements MMX technology and maintains full backward compatibility with the
8086, 80286, Intel386, Intel486, and Pentium processor. The processor’s numeric coprocessor
significantly increases the speed of floating-point operations and complies with ANSI/IEEE
standard 754-1985.
1.4.1 Microprocessor Packaging
The processor is packaged in a Single Edge Contact (S.E.C.) cartridge. The S.E.C. cartridge
includes the processor core, the second-level cache, a thermal plate, and a back cover.
The processor connects to the motherboard through the Slot 1 processor connector, a 242-pin edge
connector. When mounted in Slot 1, the processor is secured by a retention mechanism attached to
the motherboard. The processor’s heatsink is stabilized by a heatsink support that is attached to the
motherboard.
1.4.2 Second Level Cache
The second-level cache is located on the substrate of the S.E.C. cartridge. The cache includes burst
pipelined synchronous static RAM (BSRAM) and tag RAM. There can be two or four BSRAM
components totaling 256 KB or 512 KB in size. All supported onboard memory can be cached.
1.4.3 Microprocessor Upgrades
The motherboard can be upgraded with Pentium II processors that run at higher processor speeds.
When upgrading the processor, use the BIOS configuration mode to change the processor. See
Section 1.12.3 for information about configuration mode.
11
Motherboard Description
1.5 Memory
1.5.1 Main Memory
The motherboard has two dual inline memory module (DIMM) sockets. Minimum memory size is
16 MB; maximum memory size is 256 MB. The BIOS automatically detects memory type, size,
and speed.
The motherboard supports the following memory features:
• 168-pin DIMMs with gold-plated contacts
• 66 MHz SDRAM only
• Non-ECC (64-bit) and ECC (72-bit) memory
• 3.3 V memory only
• Single- or double-sided DIMMs in the following sizes:
DIMM SizeNon-ECC ConfigurationECC Configuration
16 MB2 Mbit x 642 Mbit x 72
32 MB4 Mbit x 644 Mbit x 72
64 MB8 Mbit x 648 Mbit x 72
128 MB16 Mbit x 6416 Mbit x 72
Memory can be installed in one or two sockets. Memory size can vary between sockets.
NOTE
✏
To function properly, SDRAM DIMMs must meet the Intel 4-clock, 66 MHz, unbuffered SDRAM
specification for either 64-bit or 72-bit SDRAM. See Section 6.2 for information about these
specifications.
1.5.2 ECC Memory
Error checking and correcting (ECC) memory detects multiple-bit errors and corrects single-bit
errors. When ECC memory is installed, the BIOS supports both ECC and non-ECC mode. ECC
mode is enabled in the Setup program. The BIOS automatically detects if ECC memory is
installed and provides the Setup option for selecting ECC mode. If any non-ECC memory is
installed, the Setup option for ECC mode does not appear.
The following table describes the effect of using Setup to put each memory type in each supported
mode. Whenever ECC mode is selected in Setup, some performance loss occurs.
Memory Error Detection Mode Established in Setup Program
ECC DisabledECC Enabled
Non-ECC DIMM
ECC DIMM
No error detectionN/A
No error detectionSingle-bit error correction, multiple-bit error
The Intel 440LX AGPset is designed for the Pentium II processor. It consists of the Intel 82443LX
PCI/A.G.P. controller (PAC) and the Intel 82371AB PCI/ISA IDE Xcelerator (PIIX4) bridge chip.
1.6.1 Intel 82443LX PCI/A.G.P. Controller (PAC)
The PAC provides bus-control signals, address paths, and data paths for transfers between the
processor’s host bus, PCI bus, Accelerated Graphics Port (A.G.P.), and main memory. The PAC
features:
• Processor interface control
Processor host bus speed of 66 MHz
32-bit addressing
GTL+ compliant host bus
• Integrated DRAM controller
Supports synchronous DRAM (SDRAM)
64/72-bit path-to-memory
Auto detection of memory type
Supports 4-, 16-, 64-Mbit DRAM devices
Symmetrical and asymmetrical DRAM addressing
Supports 3.3 V DRAMs
• Accelerated Graphics Port Interface
Complies with A.G.P. specification (see Section 6.2 for specification information)
Supports 3.3 V A.G.P. devices with data transfer rates up to 66 MHz
Synchronous coupling to the host-bus frequency
• Fully-synchronous PCI bus interface
Complies with PCI specification (see Section 6.2 for specification information)
PCI-to-DRAM access greater than 100 MB/sec
Supports five PCI bus masters in addition to the host and PCI-to-ISA I/O bridge
Delayed transactions
PCI parity checking and generation support
• Data Buffering
Host-to-DRAM, PCI-to-DRAM, and A.G.P.-to-DRAM write-data buffering
Write-combining for host-to-PCI burst writes
Supports concurrent host, PCI, and A.G.P. transactions to main memory
• Supports system management mode (SMM)
13
Motherboard Description
1.6.2 Intel 82371AB PCI ISA IDE Xcelerator (PIIX4)
The PIIX4 is a multifunction PCI device implementing the PCI-to-ISA bridge, PCI IDE
functionality, Universal Serial Bus (USB) host/hub function, and enhanced power management.
The PIIX4 features:
• Multifunction PCI-to-ISA bridge
Supports the PCI bus at 33 MHz
Complies with PCI specification (see Section 6.2 for specification information)
Full ISA or extended I/O (EIO) bus support
• USB controller
Two USB ports (see Section 6.2 for compliance level)
Supports legacy keyboard and mouse
Supports universal host controller interface (UHCI) design guide revision 1.1 interface
• Integrated dual-channel enhanced IDE interface
Supports up to four IDE devices
PIO Mode 4 transfers at up to 14 MB/sec
Supports Ultra DMA/33 synchronous DMA mode transfers up to 33 MB/sec
Bus master mode with an 8 x 32-bit buffer for bus master PCI IDE burst transfers
• Enhanced DMA controller
Two 8237-based DMA controllers
Supports PCI DMA with three PC/PCI channels and distributed DMA protocols
Fast type-F DMA for reduced PCI bus usage
• Interrupt controller based on 82C59
Supports 15 interrupts
Programmable for edge/level sensitivity
• Power management logic
Sleep/resume logic
Supports thermal alarm
Supports wake-on-modem through Ring Indicate input
Supports Wake on LAN
• Real-time Clock
256 byte battery-backed CMOS SRAM
Includes date alarm
A.G.P. is a high-performance interconnect for graphic-intensive applications, such as 3D
applications. A.G.P. is independent of the PCI bus and is intended for exclusive use with
graphical-display devices. A.G.P. provides these performance features:
• Pipelined-memory read and write operations that hide memory access latency
• Demultiplexing of address and data on the bus for near 100% bus efficiency
• AC timing for 66 MHz data transfer rates, allowing data throughput of 250 MB/sec
A.G.P. complies with the 66 MHz PCI specification. See Section 6.2 for information about the
A.G.P. and PCI specifications.
The CL-GD5465 supports A.G.P. for higher bandwidth between the system memory and the
graphics subsystem. It is a member of the Laguna family of RAMBUS-based graphics
accelerators, offering 3D-graphics capability while maintaining a high level of 2D performance.
The features include:
• 64-bit graphics engine with integrated 3D game acceleration
• High-performance 64-bit GUI accelerator
• Video playback acceleration
†
• Integrated VGA
• Integrated 230-MHz palette DAC and clock synthesizer
controller
Table 1. Supported Drivers and Resolutions
8 bit
Drivers
Microsoft Windows
Microsoft DCI* Provider
Microsoft Windows 95
Microsoft DirectDraw
AutoCAD
AutoShade with Renderman
3D Studio MicroStation
Microsoft Windows NT
OS/2† v3.x, Warp
VPM**Resolution-independent
* Display control interface
** Video port manager
*** Microsoft Windows NT only
†
†
†
†
256 colors
640 x 480
800 x 600
1024 x 768
1280 x 1024
1600 x 1200
640 x 480
800 x 600
1024 x 768
1280 x 1024
16 bit
65,536 colors
640 x 480
800 x 600
1024 x 768
1280 x 1024
640 x 480
800 x 600
1024 x 768
24 bit
16,777,216 colors
640 x 480
800 x 600
1024 x 768
32 bit
16,777,216 colors
640 x 480***
800 x 600***
1024 x 768***
15
Motherboard Description
1.6.4 Universal Serial Bus (USB)
The motherboard has two USB ports. The motherboard fully supports the universal host controller
interface (UHCI) and uses UHCI-compatible software drivers. See Section 6.2 for information
about the USB specification. USB features include:
• Self-identifying peripherals that can be plugged in while the computer is running
• Automatic mapping of function to driver and configuration
• Isochronous and asynchronous transfer types supported over the same set of wires
• Up to 127 physical devices supported
• Guaranteed bandwidth and low latencies appropriate for telephony, audio, and other
applications
• Error-handling and fault-recovery mechanisms built into the protocol
NOTE
✏
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device or a low-speed USB device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
1.6.5 IDE Support
The motherboard has two independent bus-mastering PCI IDE interfaces. These interfaces support
PIO Mode 3, PIO Mode 4, ATAPI devices (e.g., CD-ROM), and Ultra DMA/33 synchronousDMA mode transfers. The IDE interface signals are routed to the NLX riser connector.
The BIOS supports logical block addressing (LBA) and extended cylinder head sector (ECHS)
translation modes. The BIOS automatically detects the IDE device transfer rate and translation
mode.
Programmed I/O operations usually require a substantial amount of processor bandwidth.
However, in multitasking operating systems, the bandwidth freed by bus mastering IDE can be
devoted to other tasks while disk transfers are occurring.
1.6.6 Real-time Clock, CMOS SRAM, and Battery
The real-time clock is compatible with DS1287 and MC146818 components. The clock provides a
time-of-day clock and a multi-century calendar with alarm features and century rollover. The realtime clock supports 256 bytes of battery-backed CMOS SRAM in two banks that are reserved for
BIOS use.
The time, date, and CMOS values can be specified in the Setup program. The CMOS values can
be returned to their defaults by using the Setup program.
An external coin-cell battery powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the 3 V standby current from the power supply extends the life of the
battery. The clock is accurate to ± 13 minutes/year at 25 ºC with 5 V applied.
The motherboard uses the SMC FDC37C677 I/O controller which features:
• ISA Plug-and-Play compatible register set
• Two serial ports
• FIFO support on both serial and floppy interfaces
• One parallel port with ECP and EPP support
†
• PS/2
• Supports BIOS setup for various configuration options
1.7.1 Serial Ports
The motherboard has two 9-pin D-Sub serial port connectors located on the back panel. The
NS16C550-compatible UARTs support data transfers at speeds up to 115.2 Kbits/sec with BIOS
support.
1.7.2 Parallel Port
The connector for the multimode bidirectional parallel port is a 25-pin D-Sub connector located on
the back panel of the motherboard. In the Setup program, there are four options for parallel port
operation:
• Compatible (standard mode)
• Bidirectional (PS/2 compatible)
• Bidirectional Enhanced Parallel Port (EPP). A driver from the peripheral manufacturer is
• Bidirectional high-speed Extended Capabilities Port (ECP)
style mouse and keyboard interfaces
required for operation. See Section 6.2 for EPP compatibility.
1.7.3 Floppy Controller
The I/O controller is software compatible with the DP8473 and 82077 floppy drive controllers. In
the Setup program, the floppy interface can be configured for the following floppy drive capacities
and sizes:
The floppy disk interface signals are routed to the NLX riser connector.
17
Motherboard Description
1.7.4 PS/2 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel of the motherboard. The +5 V
lines to these connectors are protected with a PolySwitch
reestablishes the connection after an over-current condition is removed. While this device
eliminates the possibility of having to replace a fuse, power to the computer should be turned off
before connecting or disconnecting a keyboard or mouse.
NOTE
✏
You can plug the mouse and keyboard into either PS/2 connector.
The keyboard controller contains code which provides the traditional keyboard and mouse control
functions, and also supports Power On/Reset password protection. A Power On/Reset password
can be specified in the Setup program.
The keyboard controller also supports the hot-key sequence <Ctrl><Alt><Del>, software reset.
This key sequence resets the computer’s software by jumping to the beginning of the BIOS code
and running the Power On Self Test (POST).
†
circuit that, like a self-healing fuse,
1.8 Audio Subsystem
1.8.1 OPL3-SA3 Audio System
The onboard audio subsystem features the Yamaha OPL3-SA3 (YMF715) device. The features of
the device include:
• A 16-bit audio codec
• OPL3 FM synthesis
• An integrated 3D enhanced stereo controller
• Support for MPU-401
• Stereo analog-to-digital and digital-to-analog converters
• Analog mixing, anti-aliasing, and reconstruction filters
• 16-bit address decoding supported
• Line, microphone, and monaural inputs
• ADPCM, A-law, or µlaw digital audio compression and decompression
• Full digital control of all mixer and volume control functions
• Microphone input (Mic In) connector is jumper selectable between the back panel and the riser
The following table shows the IRQ, DMA channel, and base I/O address options for the audio
subsystem. Options are listed in order of preference specified by Yamaha. These options are
automatically chosen by the Plug and Play interface, so there are no default settings. Onboard
audio can be enabled or disabled in the Setup program.
Table 2.Audio Subsystem Resources
Resource
Sound Blaster
(DMA playback, DMA shared with
Windows Sound System capture)
Windows Sound System
(DMA playback)
MPU-401
(IRQ shared with Sound Blaster)
†
AdLib
†
IRQ
(Options)
5, 7, 10, 11
(5 is recommended)
5, 7, 10, 110, 1, 3530-537h
DMA channel
(Options)
0, 1, 3220-22Fh
I/O Address
(Options)
240-24Fh
16 bytes on 16-byte
boundary in the
range of 220-280h
E80-E87h
8 bytes on 8-byte
boundary in the
range of 530-F48h
330-331h
300-301h
2 bytes on 2-byte
boundary in the
range of 300-334h
388-38Dh
6 bytes on 8-byte
boundary in the
range of 388-3F8h
1.8.3 Audio Drivers and Utilities
Audio software and utilities are available from Intel’s World Wide Web site (see Section 6.2).
Audio driver support is provided for the Microsoft Windows 3.1, Microsoft Windows 95,
Microsoft Windows NT
operating systems.
(versions 3.51 and 4.0), and IBM OS/2 Warp (versions 3.0 and 4.0)
19
Motherboard Description
1.8.4 Audio Connectors
The back panel includes the following audio connectors:
• Line Out
• Mic In
1.9 Hardware Monitor
The optional hardware monitor component (National Semiconductor LM79) provides low-cost
instrumentation capabilities designed to reduce the total cost of owning a PC when used with
LANDesk
include:
• An integrated ambient temperature sensor
• Fan speed sensors
• Power supply voltage monitoring to detect levels above or below acceptable values
• Remote reset capabilities from a remote peer or server through LANDesk Client Manager,
®
Client Manager. The hardware implementation is a single-chip ASIC. Features
Version 3.0 and service layers (when available)
When suggested ratings for temperature, fan speed, or voltage are exceeded, an interrupt is
activated. The hardware monitor component (LM79) connects to the system management bus. For
more information on the LM79, see http://www.national.com.
20
Loading...
+ 46 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.