Intel IXP2800, NETWORK PROCESSOR IXP2800 User Manual

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Intel® IXP2800 Network

Processor

Hardware Reference Manual

August 2004

Order Number: 278882-010

Revision History

Date

Revision

Description

 

 

 

March 2002

001

First release for IXP2800 Customer Information Book V 0.4

 

 

 

May 2002

002

Update for the IXA SDK 3.0 release.

 

 

 

August 2002

003

Update for the IXA SDK 3.0 Pre-Release 4.

 

 

 

November 2002

004

Update for the IXA SDK 3.0 Pre-Release 5.

 

 

 

May 2003

005

Update for the IXA SDK 3.1 Alpha Release

 

 

 

September 2003

006

Update for the IXA SDK 3.5 Pre-Release 1

 

 

 

October 2003

007

Added information about Receiver and Transmitter

Interoperation with Framers and Switch Fabrics.

 

 

 

 

 

January 2004

008

Updated for new trademark usage: Intel XScale® technology.

 

 

Updated Sections 6.5.2, 8.5.2.2, 9.2.2.1, 9.3.1, 9.3.3.2,

 

 

9.5.1.4, 9.5.3.4, and 10.3.1.

May 2004

009

Updated Figure 123 and Timing Diagrams in Figures 43, 44,

 

 

46, 47, 50, 51, 54, and 55.

 

 

Added Chapter 11, “Performance Monitor Unit”.

 

 

 

August 2004

010

Preparation for web posting.

 

 

 

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT.

Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The IXP2800 Network Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel and XScale are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.

Copyright © 2004, Intel Corporation.

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Contents

Contents

 

 

1

Introduction..................................................................................................................................

 

 

25

 

1.1

About This Document .........................................................................................................

25

 

1.2

Related Documentation ......................................................................................................

25

 

1.3

Terminology ........................................................................................................................

 

26

2

Technical Description .................................................................................................................

 

27

 

2.1

Overview.............................................................................................................................

 

27

 

2.2 Intel XScale® Core Microarchitecture .................................................................................

30

 

 

2.2.1

ARM* Compatibility................................................................................................

30

 

 

2.2.2

Features.................................................................................................................

 

30

 

 

 

2.2.2.1

Multiply/Accumulate (MAC)....................................................................

30

 

 

 

2.2.2.2

Memory Management ............................................................................

30

 

 

 

2.2.2.3

Instruction Cache ...................................................................................

30

 

 

 

2.2.2.4

Branch Target Buffer..............................................................................

31

 

 

 

2.2.2.5

Data Cache ............................................................................................

31

 

 

 

2.2.2.6

Interrupt Controller .................................................................................

31

 

 

 

2.2.2.7

Address Map..........................................................................................

32

 

2.3

Microengines ......................................................................................................................

 

33

 

 

2.3.1

Microengine Bus Arrangement ..............................................................................

35

 

 

2.3.2

Control Store..........................................................................................................

35

 

 

2.3.3

Contexts.................................................................................................................

 

35

 

 

2.3.4

Datapath Registers ................................................................................................

37

 

 

 

2.3.4.1

General-Purpose Registers (GPRs) ......................................................

37

 

 

 

2.3.4.2

Transfer Registers .................................................................................

37

 

 

 

2.3.4.3

Next Neighbor Registers........................................................................

38

 

 

 

2.3.4.4

Local Memory .......................................................................................

39

 

 

2.3.5

Addressing Modes .................................................................................................

41

 

 

 

2.3.5.1

Context-Relative Addressing Mode .......................................................

41

 

 

 

2.3.5.2

Absolute Addressing Mode ....................................................................

42

 

 

 

2.3.5.3

Indexed Addressing Mode .....................................................................

42

 

 

2.3.6

Local CSRs............................................................................................................

43

 

 

2.3.7

Execution Datapath ...............................................................................................

43

 

 

 

2.3.7.1

Byte Align...............................................................................................

43

 

 

 

2.3.7.2

CAM .......................................................................................................

45

 

 

2.3.8

CRC Unit................................................................................................................

 

48

 

 

2.3.9

Event Signals.........................................................................................................

49

 

2.4

DRAM .................................................................................................................................

 

 

50

 

 

2.4.1

Size Configuration .................................................................................................

50

 

 

2.4.2 Read and Write Access .........................................................................................

51

 

2.5

SRAM .................................................................................................................................

 

 

51

 

 

2.5.1

QDR Clocking Scheme..........................................................................................

52

 

 

2.5.2

SRAM Controller Configurations............................................................................

52

 

 

2.5.3

SRAM Atomic Operations......................................................................................

53

 

 

2.5.4 Queue Data Structure Commands ........................................................................

54

 

 

2.5.5

Reference Ordering ...............................................................................................

54

 

 

 

2.5.5.1

Reference Order Tables ........................................................................

54

 

 

 

2.5.5.2 Microengine Software Restrictions to Maintain Ordering.......................

56

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2.6

Scratchpad Memory............................................................................................................

56

 

 

2.6.1

Scratchpad Atomic Operations ..............................................................................

57

 

 

2.6.2

Ring Commands ....................................................................................................

57

 

2.7

Media and Switch Fabric Interface .....................................................................................

59

 

 

2.7.1

SPI-4......................................................................................................................

 

60

 

 

2.7.2

CSIX ......................................................................................................................

 

61

 

 

2.7.3

Receive..................................................................................................................

 

61

 

 

 

2.7.3.1

RBUF .....................................................................................................

62

 

 

 

 

2.7.3.1.1 SPI-4 and the RBUF ..............................................................

62

 

 

 

 

2.7.3.1.2 CSIX and RBUF.....................................................................

63

 

 

 

2.7.3.2

Full Element List ....................................................................................

63

 

 

 

2.7.3.3 RX_THREAD_FREELIST ......................................................................

63

 

 

 

2.7.3.4

Receive Operation Summary.................................................................

64

 

 

2.7.4

Transmit.................................................................................................................

 

65

 

 

 

2.7.4.1

TBUF......................................................................................................

65

 

 

 

 

2.7.4.1.1 SPI-4 and TBUF.....................................................................

66

 

 

 

 

2.7.4.1.2 CSIX and TBUF .....................................................................

67

 

 

 

2.7.4.2

Transmit Operation Summary................................................................

67

 

 

2.7.5

The Flow Control Interface ....................................................................................

68

 

 

 

2.7.5.1

SPI-4......................................................................................................

68

 

 

 

2.7.5.2

CSIX.......................................................................................................

68

 

2.8

Hash Unit ............................................................................................................................

 

69

 

2.9

PCI Controller .....................................................................................................................

 

71

 

 

2.9.1

Target Access........................................................................................................

71

 

 

2.9.2

Master Access .......................................................................................................

71

 

 

2.9.3

DMA Channels.......................................................................................................

71

 

 

 

2.9.3.1

DMA Descriptor......................................................................................

72

 

 

 

2.9.3.2

DMA Channel Operation........................................................................

73

 

 

 

2.9.3.3 DMA Channel End Operation ................................................................

74

 

 

 

2.9.3.4 Adding Descriptors to an Unterminated Chain.......................................

74

 

 

2.9.4

Mailbox and Message Registers............................................................................

74

 

 

2.9.5

PCI Arbiter .............................................................................................................

75

 

2.10 Control and Status Register Access Proxy.........................................................................

76

 

2.11

Intel XScale® Core Peripherals ..........................................................................................

76

 

 

2.11.1

Interrupt Controller.................................................................................................

76

 

 

2.11.2

Timers....................................................................................................................

 

77

 

 

2.11.3

General Purpose I/O..............................................................................................

77

 

 

2.11.4

Universal Asynchronous Receiver/Transmitter......................................................

77

 

 

2.11.5

Slowport.................................................................................................................

 

77

 

2.12

I/O Latency .........................................................................................................................

 

78

 

2.13

Performance Monitor ..........................................................................................................

78

3

Intel XScale® Core .......................................................................................................................

 

79

 

3.1

Introduction.........................................................................................................................

 

79

 

3.2

Features..............................................................................................................................

 

80

 

 

3.2.1

Multiply/ACcumulate (MAC)...................................................................................

80

 

 

3.2.2

Memory Management............................................................................................

80

 

 

3.2.3

Instruction Cache...................................................................................................

81

 

 

3.2.4

Branch Target Buffer (BTB) ...................................................................................

81

 

 

3.2.5

Data Cache............................................................................................................

81

 

 

3.2.6

Performance Monitoring ........................................................................................

81

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3.2.7

Power Management...............................................................................................

81

 

3.2.8

Debugging .............................................................................................................

 

81

 

3.2.9

JTAG......................................................................................................................

 

 

81

3.3

Memory Management.........................................................................................................

 

82

 

3.3.1

Architecture Model.................................................................................................

 

82

 

 

3.3.1.1 Version 4 versus Version 5 ....................................................................

82

 

 

3.3.1.2

Memory Attributes..................................................................................

82

 

 

 

3.3.1.2.1

Page (P) Attribute Bit .............................................................

82

 

 

 

3.3.1.2.2

Instruction Cache ...................................................................

83

 

 

 

3.3.1.2.3

Data Cache and Write Buffer .................................................

83

 

 

 

3.3.1.2.4

Details on Data Cache and Write Buffer Behavior.................

83

 

 

 

3.3.1.2.5

Memory Operation Ordering ..................................................

84

 

3.3.2

Exceptions .............................................................................................................

 

84

 

3.3.3 Interaction of the MMU, Instruction Cache, and Data Cache.................................

85

 

3.3.4

Control ...................................................................................................................

 

 

85

 

 

3.3.4.1

Invalidate (Flush) Operation...................................................................

85

 

 

3.3.4.2

Enabling/Disabling .................................................................................

85

 

 

3.3.4.3

Locking Entries ......................................................................................

86

 

 

3.3.4.4

Round-Robin Replacement Algorithm ...................................................

87

3.4

Instruction Cache................................................................................................................

 

 

88

 

3.4.1

Instruction Cache Operation ..................................................................................

89

 

 

3.4.1.1 Operation when Instruction Cache is Enabled.......................................

89

 

 

3.4.1.2 Operation when Instruction Cache is Disabled ......................................

90

 

 

3.4.1.3

Fetch Policy ...........................................................................................

90

 

 

3.4.1.4

Round-Robin Replacement Algorithm ...................................................

90

 

 

3.4.1.5

Parity Protection.....................................................................................

91

 

 

3.4.1.6

Instruction Cache Coherency.................................................................

91

 

3.4.2

Instruction Cache Control ......................................................................................

92

 

 

3.4.2.1 Instruction Cache State at Reset ...........................................................

92

 

 

3.4.2.2

Enabling/Disabling .................................................................................

92

 

 

3.4.2.3 Invalidating the Instruction Cache..........................................................

92

 

 

3.4.2.4 Locking Instructions in the Instruction Cache ........................................

92

 

 

3.4.2.5 Unlocking Instructions in the Instruction Cache .....................................

94

3.5 Branch Target Buffer (BTB) ................................................................................................

 

94

 

3.5.1 Branch Target Buffer Operation.............................................................................

94

 

 

3.5.1.1

Reset......................................................................................................

 

95

 

3.5.2

Update Policy.........................................................................................................

 

96

 

3.5.3

BTB Control ...........................................................................................................

 

96

 

 

3.5.3.1

Disabling/Enabling .................................................................................

96

 

 

3.5.3.2

Invalidation.............................................................................................

96

3.6

Data Cache.........................................................................................................................

 

 

96

 

3.6.1

Overviews ..............................................................................................................

 

97

 

 

3.6.1.1

Data Cache Overview ............................................................................

97

 

 

3.6.1.2

Mini-Data Cache Overview ....................................................................

98

 

 

3.6.1.3 Write Buffer and Fill Buffer Overview.....................................................

99

 

3.6.2 Data Cache and Mini-Data Cache Operation ........................................................

99

 

 

3.6.2.1 Operation when Caching is Enabled......................................................

99

 

 

3.6.2.2 Operation when Data Caching is Disabled ............................................

99

 

 

3.6.2.3

Cache Policies .....................................................................................

100

 

 

 

3.6.2.3.1

Cacheability .........................................................................

100

 

 

 

3.6.2.3.2

Read Miss Policy .................................................................

100

 

 

 

3.6.2.3.3

Write Miss Policy..................................................................

101

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3.6.2.3.4

Write-Back versus Write-Through........................................

101

 

 

3.6.2.4

Round-Robin Replacement Algorithm .................................................

102

 

 

3.6.2.5

Parity Protection...................................................................................

102

 

 

3.6.2.6

Atomic Accesses..................................................................................

102

 

3.6.3

Data Cache and Mini-Data Cache Control ..........................................................

103

 

 

3.6.3.1

Data Memory State After Reset ...........................................................

103

 

 

3.6.3.2

Enabling/Disabling ...............................................................................

103

 

 

3.6.3.3

Invalidate and Clean Operations..........................................................

103

 

 

 

3.6.3.3.1

Global Clean and Invalidate Operation ................................

104

 

3.6.4

Reconfiguring the Data Cache as Data RAM ......................................................

105

 

3.6.5 Write Buffer/Fill Buffer Operation and Control .....................................................

106

3.7

Configuration ....................................................................................................................

 

 

106

3.8

Performance Monitoring ...................................................................................................

 

107

 

3.8.1

Performance Monitoring Events ..........................................................................

107

 

 

3.8.1.1

Instruction Cache Efficiency Mode.......................................................

108

 

 

3.8.1.2

Data Cache Efficiency Mode................................................................

109

 

 

3.8.1.3

Instruction Fetch Latency Mode...........................................................

109

 

 

3.8.1.4

Data/Bus Request Buffer Full Mode ....................................................

109

 

 

3.8.1.5

Stall/Writeback Statistics......................................................................

110

 

 

3.8.1.6

Instruction TLB Efficiency Mode ..........................................................

111

 

 

3.8.1.7

Data TLB Efficiency Mode ...................................................................

111

 

3.8.2

Multiple Performance Monitoring Run Statistics ..................................................

111

3.9

Performance Considerations ............................................................................................

111

 

3.9.1

Interrupt Latency..................................................................................................

 

112

 

3.9.2

Branch Prediction ................................................................................................

 

112

 

3.9.3

Addressing Modes ...............................................................................................

 

113

 

3.9.4

Instruction Latencies............................................................................................

113

 

 

3.9.4.1

Performance Terms .............................................................................

113

 

 

3.9.4.2

Branch Instruction Timings ..................................................................

115

 

 

3.9.4.3

Data Processing Instruction Timings ...................................................

115

 

 

3.9.4.4

Multiply Instruction Timings..................................................................

116

 

 

3.9.4.5

Saturated Arithmetic Instructions .........................................................

117

 

 

3.9.4.6

Status Register Access Instructions ....................................................

118

 

 

3.9.4.7

Load/Store Instructions ........................................................................

118

 

 

3.9.4.8

Semaphore Instructions .......................................................................

118

 

 

3.9.4.9

Coprocessor Instructions .....................................................................

119

 

 

3.9.4.10

Miscellaneous Instruction Timing.........................................................

119

 

 

3.9.4.11

Thumb Instructions ..............................................................................

119

3.10

Test Features....................................................................................................................

 

 

119

 

3.10.1

IXP2800 Network Processor Endianness............................................................

120

 

 

3.10.1.1 Read and Write Transactions Initiated by the Intel XScale® Core ......

121

 

 

 

3.10.1.1.1

Reads Initiated by the Intel XScale® Core ........................

121

 

 

 

3.10.1.1.2

The Intel XScale® Core Writing to the IXP2800

 

 

 

 

Network Processor ..................................................................

123

3.11 Intel XScale® Core Gasket Unit .......................................................................................

125

 

3.11.1

Overview..............................................................................................................

 

 

125

 

3.11.2

Intel XScale® Core Gasket Functional Description .............................................

127

 

 

3.11.2.1 Command Memory Bus to Command Push/Pull Conversion ..............

127

 

3.11.3

CAM Operation ....................................................................................................

 

127

 

3.11.4

Atomic Operations ...............................................................................................

 

128

 

 

3.11.4.1

Summary of Rules for the Atomic Command Regarding I/O ...............

129

 

 

3.11.4.2 Intel XScale® Core Access to SRAM Q-Array.....................................

129

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3.11.5

I/O Transaction ....................................................................................................

 

130

 

 

3.11.6

Hash Access........................................................................................................

 

130

 

 

3.11.7

Gasket Local CSR ...............................................................................................

 

131

 

 

3.11.8

Interrupt

...............................................................................................................

 

132

 

3.12

Intel XScale® Core ...........................................................................Peripheral Interface

134

 

 

3.12.1

XPI Overview .......................................................................................................

 

134

 

 

 

3.12.1.1 .....................................................................................

Data Transfers

135

 

 

 

3.12.1.2 ....................................................................................

Data Alignment

135

 

 

 

3.12.1.3 ............................................

Address Spaces for XPI Internal Devices

136

 

 

3.12.2

UART Overview ...................................................................................................

 

137

 

 

3.12.3

UART Operation ..................................................................................................

 

138

 

 

 

3.12.3.1 ....................................................................

UART FIFO OPERATION

138

 

 

 

 

3.12.3.1.1

UART FIFO Interrupt Mode Operation –

 

 

 

 

....................................................................

Receiver Interrupt

138

 

 

 

.............................................

3.12.3.1.2

FIFO Polled Mode Operation

139

 

 

3.12.4

Baud Rate ...........................................................................................Generator

139

 

 

3.12.5

General Purpose ...............................................................................I/O (GPIO)

140

 

 

3.12.6

Timers..................................................................................................................

 

 

141

 

 

 

3.12.6.1 ...................................................................................

Timer Operation

141

 

 

3.12.7

Slowport .......................................................................................................Unit

 

142

 

 

 

3.12.7.1 .........................................................................

PROM Device Support

143

 

 

 

3.12.7.2 ................................

Microprocessor Interface Support for the Framer

143

 

 

 

3.12.7.3 .......................................................................

Slowport Unit Interfaces

144

 

 

 

3.12.7.4 .....................................................................................

Address Space

145

 

 

 

3.12.7.5 .............................................................

Slowport Interfacing Topology

145

 

 

 

3.12.7.6 ...................................................

Slowport 8 - Bit Device Bus Protocols

146

 

 

 

......

3.12.7.6.1

Mode 0 Single Write Transfer for Fixed-Timed Device

147

 

 

 

........

3.12.7.6.2

Mode 0 Single Write Transfer for Self-Timing Device

148

 

 

 

......

3.12.7.6.3

Mode 0 Single Read Transfer for Fixed-Timed Device

149

 

 

 

..................

3.12.7.6.4

Single Read Transfer for a Self-Timing Device

150

 

 

 

3.12.7.7 ....................................

SONET/SDH Microprocessor Access Support

150

 

 

 

 

3.12.7.7.1

Mode 1: 16-Bit Microprocessor Interface Support with

 

 

 

 

................................................................

16 - Bit Address Lines

151

 

 

 

....

3.12.7.7.2

Mode 2: Interface with 8 Data Bits and 11 Address Bits

155

 

 

 

 

3.12.7.7.3 Mode 3: Support for the Intel and AMCC* 2488 Mbps

 

 

 

 

...................................

SONET/SDH Microprocessor Interface

157

4

Microengines

.............................................................................................................................

 

 

167

 

4.1

Overview...........................................................................................................................

 

 

167

 

 

4.1.1

Control Store........................................................................................................

 

169

 

 

4.1.2

Contexts...............................................................................................................

 

 

169

 

 

4.1.3

Datapath ..............................................................................................Registers

 

171

 

 

 

4.1.3.1 ....................................................

General - Purpose Registers (GPRs)

171

 

 

 

4.1.3.2 ...............................................................................

Transfer Registers

171

 

 

 

4.1.3.3 ......................................................................

Next Neighbor Registers

172

 

 

 

4.1.3.4 ......................................................................................

Local Memory

172

 

 

4.1.4

Addressing ...............................................................................................Modes

 

173

 

 

 

4.1.4.1 .....................................................

Context - Relative Addressing Mode

173

 

 

 

4.1.4.2 ..................................................................

Absolute Addressing Mode

174

 

 

 

4.1.4.3 ...................................................................

Indexed Addressing Mode

174

 

4.2

Local CSRs.......................................................................................................................

 

 

174

 

4.3

Execution Datapath ..........................................................................................................

 

174

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Contents

 

 

 

 

 

 

4.3.1

Byte Align.............................................................................................................

174

 

 

4.3.2

CAM.....................................................................................................................

 

176

 

4.4

CRC Unit...........................................................................................................................

 

179

 

4.5

Event Signals....................................................................................................................

 

180

 

 

4.5.1

Microengine Endianness .....................................................................................

181

 

 

 

4.5.1.1 Read from RBUF (64 Bits) ...................................................................

181

 

 

 

4.5.1.2

Write to TBUF ......................................................................................

182

 

 

 

4.5.1.3

Read/Write from/to SRAM ...................................................................

182

 

 

 

4.5.1.4

Read/Write from/to DRAM ...................................................................

182

 

 

 

4.5.1.5 Read/Write from/to SHaC and Other CSRs.........................................

182

 

 

 

4.5.1.6 Write to Hash Unit................................................................................

183

 

 

4.5.2

Media Access ......................................................................................................

183

 

 

 

4.5.2.1

Read from RBUF .................................................................................

184

 

 

 

4.5.2.2

Write to TBUF ......................................................................................

185

 

 

 

4.5.2.3 TBUF to SPI-4 Transfer .......................................................................

186

5

DRAM

..........................................................................................................................................

 

 

187

 

5.1

Overview...........................................................................................................................

 

187

 

5.2

Size Configuration ............................................................................................................

188

 

5.3

DRAM Clocking ................................................................................................................

 

189

 

5.4

Bank Policy .......................................................................................................................

 

190

 

5.5

Interleaving .......................................................................................................................

 

191

 

 

5.5.1

Three Channels Active (3-Way Interleave)..........................................................

191

 

 

5.5.2

Two Channels Active (2-Way Interleave) ............................................................

193

 

 

5.5.3

One Channel Active (No Interleave) ....................................................................

193

 

 

5.5.4

Interleaving Across RDRAMs and Banks ............................................................

194

 

5.6

Parity and ECC .................................................................................................................

 

194

 

 

5.6.1

Parity and ECC Disabled .....................................................................................

194

 

 

5.6.2

Parity Enabled .....................................................................................................

195

 

 

5.6.3

ECC Enabled .......................................................................................................

195

 

 

5.6.4

ECC Calculation and Syndrome ..........................................................................

196

 

5.7

Timing Configuration.........................................................................................................

196

 

5.8

Microengine Signals .........................................................................................................

197

 

5.9

Serial Port .........................................................................................................................

 

197

 

5.10 RDRAM Controller Block Diagram....................................................................................

198

 

 

5.10.1

Commands ..........................................................................................................

199

 

 

5.10.2

DRAM Write.........................................................................................................

199

 

 

 

5.10.2.1

Masked Write .......................................................................................

199

 

 

5.10.3

DRAM Read.........................................................................................................

200

 

 

5.10.4

CSR Write............................................................................................................

200

 

 

5.10.5

CSR Read............................................................................................................

200

 

 

5.10.6

Arbitration ............................................................................................................

201

 

 

5.10.7

Reference Ordering .............................................................................................

201

 

5.11

DRAM Push/Pull Arbiter ...................................................................................................

201

 

 

5.11.1

Arbiter Push/Pull Operation .................................................................................

202

 

 

5.11.2

DRAM Push Arbiter Description ..........................................................................

203

 

5.12

DRAM Pull Arbiter Description..........................................................................................

204

6

SRAM Interface..........................................................................................................................

 

207

 

6.1

Overview...........................................................................................................................

 

207

 

6.2

SRAM Interface Configurations ........................................................................................

208

8

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Contents

 

 

6.2.1

Internal Interface..................................................................................................

 

209

 

 

6.2.2

Number of Channels............................................................................................

209

 

 

6.2.3 Coprocessor and/or SRAMs Attached to a Channel............................................

209

 

6.3

SRAM Controller Configurations.......................................................................................

209

 

6.4

Command Overview .........................................................................................................

 

211

 

 

6.4.1

Basic Read/Write Commands..............................................................................

211

 

 

6.4.2

Atomic Operations ...............................................................................................

 

211

 

 

6.4.3 Queue Data Structure Commands ......................................................................

213

 

 

 

6.4.3.1

Read_Q_Descriptor Commands..........................................................

216

 

 

 

6.4.3.2

Write_Q_Descriptor Commands ..........................................................

216

 

 

 

6.4.3.3 ENQ and DEQ Commands ..................................................................

217

 

 

6.4.4 Ring Data Structure Commands..........................................................................

217

 

 

6.4.5

Journaling Commands.........................................................................................

217

 

 

6.4.6

CSR Accesses.....................................................................................................

 

217

 

6.5

Parity.................................................................................................................................

 

 

 

217

 

6.6

Address Map.....................................................................................................................

 

 

218

 

6.7

Reference Ordering ..........................................................................................................

 

219

 

 

6.7.1

Reference Order Tables ......................................................................................

219

 

 

6.7.2 Microcode Restrictions to Maintain Ordering.......................................................

220

 

6.8

Coprocessor Mode ...........................................................................................................

 

221

7

SHaC — Unit Expansion ...........................................................................................................

 

225

 

7.1

Overview...........................................................................................................................

 

 

225

 

 

7.1.1 SHaC Unit Block Diagram....................................................................................

225

 

 

7.1.2

Scratchpad...........................................................................................................

 

227

 

 

 

7.1.2.1

Scratchpad Description........................................................................

227

 

 

 

7.1.2.2

Scratchpad Interface............................................................................

229

 

 

 

 

7.1.2.2.1

Command Interface .............................................................

229

 

 

 

 

7.1.2.2.2

Push/Pull Interface...............................................................

229

 

 

 

 

7.1.2.2.3

CSR Bus Interface ...............................................................

229

 

 

 

 

7.1.2.2.4

Advanced Peripherals Bus Interface (APB) .........................

229

 

 

 

7.1.2.3 Scratchpad Block Level Diagram.........................................................

229

 

 

 

 

7.1.2.3.1 Scratchpad Commands .......................................................

230

 

 

 

 

7.1.2.3.2 Ring Commands ..................................................................

231

 

 

 

 

7.1.2.3.3

Clocks and Reset.................................................................

235

 

 

 

 

7.1.2.3.4

Reset Registers ...................................................................

235

 

 

7.1.3

Hash Unit

.............................................................................................................

 

236

 

 

 

7.1.3.1

Hashing Operation ...............................................................................

237

 

 

 

7.1.3.2

Hash Algorithm ....................................................................................

239

8

Media and Switch Fabric Interface...........................................................................................

241

 

8.1

Overview...........................................................................................................................

 

 

241

 

 

8.1.1

SPI-4....................................................................................................................

 

 

243

 

 

8.1.2

CSIX ....................................................................................................................

 

 

246

 

 

8.1.3

CSIX/SPI-4 Interleave Mode................................................................................

246

 

8.2

Receive

.............................................................................................................................

 

 

247

 

 

8.2.1

Receive Pins........................................................................................................

 

248

 

 

8.2.2

RBUF ...................................................................................................................

 

 

248

 

 

 

8.2.2.1

SPI-4 ....................................................................................................

 

250

 

 

 

8.2.2.2

CSIX.....................................................................................................

 

253

 

 

8.2.3

Full Element List ..................................................................................................

 

255

 

 

8.2.4

Rx_Thread_Freelist_# .........................................................................................

255

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Contents

 

 

 

 

8.2.5 Rx_Thread_Freelist_Timeout_# ..........................................................................

256

8.2.6

Receive Operation Summary...............................................................................

256

8.2.7 Receive Flow Control Status ...............................................................................

258

 

8.2.7.1

SPI-4....................................................................................................

 

258

 

8.2.7.2

CSIX.....................................................................................................

 

259

 

 

8.2.7.2.1

Link-Level.............................................................................

259

 

 

8.2.7.2.2

Virtual Output Queue ...........................................................

260

8.2.8

Parity....................................................................................................................

 

 

260

 

8.2.8.1

SPI-4....................................................................................................

 

260

 

8.2.8.2

CSIX.....................................................................................................

 

261

 

 

8.2.8.2.1

Horizontal Parity...................................................................

261

 

 

8.2.8.2.2

Vertical Parity.......................................................................

261

8.2.9

Error Cases..........................................................................................................

 

261

8.3 Transmit............................................................................................................................

 

 

262

8.3.1

Transmit Pins.......................................................................................................

 

262

8.3.2

TBUF ...................................................................................................................

 

 

263

 

8.3.2.1

SPI-4....................................................................................................

 

266

 

8.3.2.2

CSIX.....................................................................................................

 

267

8.3.3

Transmit Operation Summary..............................................................................

268

 

8.3.3.1

SPI-4....................................................................................................

 

268

 

8.3.3.2

CSIX.....................................................................................................

 

269

 

8.3.3.3

Transmit Summary...............................................................................

270

8.3.4 Transmit Flow Control Status ..............................................................................

270

 

8.3.4.1

SPI-4....................................................................................................

 

271

 

8.3.4.2

CSIX.....................................................................................................

 

273

 

 

8.3.4.2.1

Link-Level.............................................................................

273

 

 

8.3.4.2.2

Virtual Output Queue ...........................................................

273

8.3.5

Parity....................................................................................................................

 

 

273

 

8.3.5.1

SPI-4....................................................................................................

 

273

 

8.3.5.2

CSIX.....................................................................................................

 

274

 

 

8.3.5.2.1

Horizontal Parity...................................................................

274

 

 

8.3.5.2.2

Vertical Parity.......................................................................

274

8.4 RBUF and TBUF Summary ..............................................................................................

 

274

8.5 CSIX Flow Control Interface

.............................................................................................

275

8.5.1 TXCSRB and RXCSRB Signals ..........................................................................

275

8.5.2 FCIFIFO and FCEFIFO Buffers ...........................................................................

276

 

8.5.2.1

Full Duplex CSIX..................................................................................

277

 

8.5.2.2

Simplex CSIX.......................................................................................

278

8.5.3TXCDAT/RXCDAT, TXCSOF/RXCSOF, TXCPAR/RXCPAR,

 

 

and TXCFC/RXCFC Signals................................................................................

280

8.6

Deskew and Training ........................................................................................................

280

 

8.6.1

Data Training Pattern...........................................................................................

282

 

8.6.2 Flow Control Training Pattern ..............................................................................

282

 

8.6.3 Use of Dynamic Training .....................................................................................

283

8.7

CSIX Startup Sequence....................................................................................................

287

 

8.7.1

CSIX Full Duplex .................................................................................................

287

 

 

8.7.1.1 Ingress IXP2800 Network Processor ...................................................

287

 

 

8.7.1.2 Egress IXP2800 Network Processor....................................................

287

 

 

8.7.1.3 Single IXP2800 Network Processor.....................................................

288

 

8.7.2

CSIX Simplex.......................................................................................................

288

 

 

8.7.2.1 Ingress IXP2800 Network Processor ...................................................

288

 

 

8.7.2.2 Egress IXP2800 Network Processor....................................................

289

10

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Contents

8.7.2.3 Single IXP2800 Network Processor

.....................................................289

8.8 Interface to Command and Push and Pull Buses .............................................................

290

8.8.1RBUF or MSF CSR to Microengine S_TRANSFER_IN Register for Instruction:.291

8.8.2Microengine S_TRANSFER_OUT Register to TBUF or

MSF CSR for Instruction:.....................................................................................

291

8.8.3 Microengine to MSF CSR for Instruction: ............................................................

291

8.8.4 From RBUF to DRAM for Instruction: ..................................................................

291

8.8.5 From DRAM to TBUF for Instruction:...................................................................

292

8.9 Receiver and Transmitter Interoperation with Framers and Switch Fabrics .....................

292

8.9.1 Receiver and Transmitter Configurations ............................................................

293

8.9.1.1

Simplex Configuration..........................................................................

293

8.9.1.2

Hybrid Simplex Configuration ..............................................................

294

8.9.1.3 Dual Network Processor Full Duplex Configuration.............................

295

8.9.1.4 Single Network Processor Full Duplex Configuration (SPI-4.2)...........

296

8.9.1.5 Single Network Processor, Full Duplex Configuration

 

 

(SPI-4.2 and CSIX-L1) .........................................................................

297

8.9.2 System Configurations.........................................................................................

297

8.9.2.1Framer, Single Network Processor Ingress and Egress, and

Fabric Interface Chip............................................................................

298

8.9.2.2 Framer, Dual Network Processor Ingress, Single

 

Network Processor Egress, and Fabric Interface Chip ........................

298

8.9.2.3Framer, Single Network Processor Ingress and Egress, and

 

 

CSIX-L1 Chips for Translation and Fabric Interface ............................

299

 

8.9.2.4 CPU Complex, Network Processor, and Fabric Interface Chip ...........

299

 

8.9.2.5 Framer, Single Network Processor, Co-Processor, and

 

 

 

Fabric Interface Chip............................................................................

300

8.9.3

SPI-4.2 Support ...................................................................................................

 

301

 

8.9.3.1

SPI-4.2

Receiver..................................................................................

301

 

8.9.3.2

SPI-4.2

Transmitter..............................................................................

302

8.9.4

CSIX-L1 Protocol Support ...................................................................................

303

8.9.4.1CSIX-L1 Interface Reference Model: Traffic Manager and Fabric

 

Interface Chip.......................................................................................

303

 

8.9.4.2 Intel® IXP2800 Support of the CSIX-L1 Protocol ................................

304

 

8.9.4.2.1 Mapping to 16-Bit Wide DDR LVDS ....................................

304

 

8.9.4.2.2

Support for Dual Chip, Full - Duplex Operation .....................

305

 

8.9.4.2.3

Support for Simplex Operation .............................................

306

 

8.9.4.2.4

Support for Hybrid Simplex Operation .................................

307

 

8.9.4.2.5

Support for Dynamic De - Skew Training ...............................

308

 

8.9.4.3 CSIX-L1 Protocol Receiver Support ....................................................

309

 

8.9.4.4 CSIX-L1 Protocol Transmitter Support ................................................

310

 

8.9.4.5 Implementation of a Bridge Chip to CSIX-L1 .......................................

311

8.9.5 Dual Protocol (SPI and CSIX-L1) Support...........................................................

312

 

8.9.5.1 Dual Protocol Receiver Support...........................................................

312

 

8.9.5.2 Dual Protocol Transmitter Support.......................................................

312

 

8.9.5.3 Implementation of a Bridge Chip to CSIX-L1 and SPI-4.2 ...................

313

8.9.6

Transmit State Machine.......................................................................................

314

 

8.9.6.1 SPI-4.2 Transmitter State Machine......................................................

314

 

8.9.6.2 Training Transmitter State Machine.....................................................

315

 

8.9.6.3 CSIX-L1 Transmitter State Machine ....................................................

315

8.9.7

Dynamic De-Skew

...............................................................................................

316

8.9.8 Summary of Receiver ...................................................and Transmitter Signals

317

Hardware Reference Manual

11

Contents

 

 

 

 

9

PCI Unit.......................................................................................................................................

 

 

319

 

9.1

Overview...........................................................................................................................

 

319

 

9.2 PCI Pin Protocol Interface Block.......................................................................................

321

 

 

9.2.1

PCI Commands ...................................................................................................

322

 

 

9.2.2 IXP2800 Network Processor Initialization............................................................

323

 

 

 

9.2.2.1

Initialization by the Intel XScale® Core................................................

324

 

 

 

9.2.2.2

Initialization by a PCI Host ...................................................................

324

 

 

9.2.3

PCI Type 0 Configuration Cycles.........................................................................

325

 

 

 

9.2.3.1

Configuration Write ..............................................................................

325

 

 

 

9.2.3.2

Configuration Read ..............................................................................

325

 

 

9.2.4

PCI 64-Bit Bus Extension ....................................................................................

325

 

 

9.2.5

PCI Target Cycles................................................................................................

326

 

 

 

9.2.5.1

PCI Accesses to CSR ..........................................................................

326

 

 

 

9.2.5.2

PCI Accesses to DRAM .......................................................................

326

 

 

 

9.2.5.3

PCI Accesses to SRAM .......................................................................

326

 

 

 

9.2.5.4

Target Write Accesses from the PCI Bus ............................................

326

 

 

 

9.2.5.5

Target Read Accesses from the PCI Bus ............................................

327

 

 

9.2.6

PCI Initiator Transactions ....................................................................................

327

 

 

 

9.2.6.1

PCI Request Operation........................................................................

327

 

 

 

9.2.6.2

PCI Commands....................................................................................

328

 

 

 

9.2.6.3

Initiator Write Transactions ..................................................................

328

 

 

 

9.2.6.4

Initiator Read Transactions ..................................................................

328

 

 

 

9.2.6.5

Initiator Latency Timer .........................................................................

328

 

 

 

9.2.6.6

Special Cycle .......................................................................................

329

 

 

9.2.7 PCI Fast Back-to-Back Cycles.............................................................................

329

 

 

9.2.8

PCI Retry

.............................................................................................................

329

 

 

9.2.9

PCI Disconnect ....................................................................................................

329

 

 

9.2.10 PCI Built-In System Test......................................................................................

329

 

 

9.2.11

PCI Central Functions.........................................................................................

330

 

 

 

9.2.11.1

PCI Interrupt Inputs..............................................................................

330

 

 

 

9.2.11.2

PCI Reset Output.................................................................................

330

 

 

 

9.2.11.3

PCI Internal Arbiter ..............................................................................

331

 

9.3

Slave Interface Block ........................................................................................................

332

 

 

9.3.1

CSR Interface ......................................................................................................

332

 

 

9.3.2

SRAM Interface ...................................................................................................

333

 

 

 

9.3.2.1

SRAM Slave Writes .............................................................................

333

 

 

 

9.3.2.2

SRAM Slave Reads .............................................................................

334

 

 

9.3.3

DRAM Interface ...................................................................................................

334

 

 

 

9.3.3.1

DRAM Slave Writes .............................................................................

334

 

 

 

9.3.3.2

DRAM Slave Reads .............................................................................

335

 

 

9.3.4 Mailbox and Doorbell Registers...........................................................................

336

 

 

9.3.5

PCI Interrupt Pin ..................................................................................................

339

 

9.4

Master Interface Block ......................................................................................................

340

 

 

9.4.1

DMA Interface......................................................................................................

340

 

 

 

9.4.1.1 Allocation of the DMA Channels ..........................................................

341

 

 

 

9.4.1.2 Special Registers for Microengine Channels .......................................

341

 

 

 

9.4.1.3

DMA Descriptor....................................................................................

342

 

 

 

9.4.1.4

DMA Channel Operation......................................................................

343

 

 

 

9.4.1.5 DMA Channel End Operation ..............................................................

344

 

 

 

9.4.1.6 Adding Descriptor to an Unterminated Chain ......................................

344

 

 

 

9.4.1.7

DRAM to PCI Transfer.........................................................................

344

 

 

 

9.4.1.8

PCI to DRAM Transfer.........................................................................

345

12

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Contents

9.4.2 Push/Pull Command Bus Target Interface...........................................................

345

9.4.2.1 Command Bus Master Access to Local Configuration Registers ........

345

9.4.2.2 Command Bus Master Access to Local Control and

 

Status Registers...................................................................................

346

9.4.2.3 Command Bus Master Direct Access to PCI Bus ................................

346

9.4.2.3.1 PCI Address Generation for IO and MEM Cycles................

346

9.4.2.3.2

PCI Address Generation for Configuration Cycles...............

347

9.4.2.3.3

PCI Address Generation for Special and IACK Cycles........

347

9.4.2.3.4

PCI Enables .........................................................................

347

9.4.2.3.5 PCI Command .....................................................................

347

9.5 PCI Unit Error Behavior ....................................................................................................

 

348

9.5.1 PCI Target Error Behavior ...................................................................................

348

9.5.1.1 Target Access Has an Address Parity Error ........................................

348

9.5.1.2 Initiator Asserts PCI_PERR_L in Response to One of Our Data

 

Phases .................................................................................................

 

348

9.5.1.3 Discard Timer Expires on a Target Read.............................................

348

9.5.1.4 Target Access to the PCI_CSR_BAR Space Has Illegal

 

Byte Enables........................................................................................

348

9.5.1.5 Target Write Access Receives Bad Parity PCI_PAR with the Data.....

349

9.5.1.6SRAM Responds with a Memory Error on One or More Data Phases

on a Target Read .................................................................................

349

9.5.1.7DRAM Responds with a Memory Error on One or More Data Phases

on a Target Read .................................................................................

349

9.5.2 As a PCI Initiator During a DMA Transfer............................................................

349

9.5.2.1

DMA Read from DRAM (Memory-to-PCI Transaction) Gets a

 

 

Memory Error .......................................................................................

349

9.5.2.2

DMA Read from SRAM (Descriptor Read) Gets a Memory Error........

350

9.5.2.3DMA from DRAM Transfer (Write to PCI) Receives PCI_PERR_L on

 

 

 

PCI Bus ................................................................................................

350

 

 

 

9.5.2.4 DMA To DRAM (Read from PCI) Has Bad Data Parity .......................

350

 

 

 

9.5.2.5 DMA Transfer Experiences a Master Abort (Time - Out) on PCI ...........

351

 

 

 

9.5.2.6 DMA Transfer Receives a Target Abort Response During a

 

 

 

 

Data Phase ..........................................................................................

351

 

 

 

9.5.2.7 DMA Descriptor Has a 0x0 Word Count (Not an Error) .......................

351

 

 

9.5.3

As a PCI Initiator During a Direct Access from the Intel

 

 

 

 

XScale® Core or Microengine .............................................................................

351

 

 

 

9.5.3.1 Master Transfer Experiences a Master Abort (Time - Out) on PCI ........

351

 

 

 

9.5.3.2 Master Transfer Receives a Target Abort Response During

 

 

 

 

a Data Phase .......................................................................................

351

 

 

 

9.5.3.3 Master from the Intel XScale® Core or Microengine Transfer

 

 

 

 

(Write to PCI) Receives PCI _ PERR _ L on PCI Bus .............................

352

 

 

 

9.5.3.4 Master Read from PCI (Read from PCI) Has Bad Data Parity ............

352

 

 

 

9.5.3.5 Master Transfer Receives PCI _ SERR _ L from the PCI Bus ................

352

 

 

 

9.5.3.6 Intel XScale® Core Microengine Requests Direct Transfer when

 

 

 

 

the PCI Bus is in Reset ........................................................................

352

 

9.6 PCI Data Byte Lane Alignment .........................................................................................

352

 

 

9.6.1

Endian for Byte Enable ........................................................................................

355

10

Clocks and Reset.......................................................................................................................

359

 

10.1

Clocks

...............................................................................................................................

359

 

10.2 Synchronization Between Frequency Domains ................................................................

363

 

10.3

Reset ................................................................................................................................

 

364

 

 

10.3.1 .................................................

Hardware Reset Using nRESET or PCI _ RST _ L

364

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Contents

 

 

 

 

 

 

10.3.2

PCI-Initiated Reset...............................................................................................

366

 

 

10.3.3

Watchdog Timer-Initiated Reset ..........................................................................

366

 

 

 

10.3.3.1 Slave Network Processor (Non-Central Function) ...............................

367

 

 

 

10.3.3.2 Master Network Processor (PCI Host, Central Function) ....................

367

 

 

 

10.3.3.3 Master Network Processor (Central Function).....................................

367

 

 

10.3.4

Software-Initiated Reset ......................................................................................

367

 

 

10.3.5 Reset Removal Operation Based on CFG_PROM_BOOT..................................

368

 

 

 

10.3.5.1 When CFG_PROM_BOOT is 1 (BOOT_PROM is Present) ................

368

 

 

 

10.3.5.2 When CFG_PROM_BOOT is 0 (BOOT_PROM is Not Present) .........

368

 

 

10.3.6

Strap Pins ............................................................................................................

368

 

 

10.3.7

Powerup Reset Sequence ...................................................................................

370

 

10.4

Boot Mode ........................................................................................................................

 

370

 

 

10.4.1

Flash ROM...........................................................................................................

372

 

 

10.4.2

PCI Host Download .............................................................................................

372

 

10.5

Initialization.......................................................................................................................

 

373

11

Performance Monitor Unit ........................................................................................................

375

 

11.1

Introduction.......................................................................................................................

 

375

 

 

11.1.1 Motivation for Performance Monitors...................................................................

375

 

 

11.1.2 Motivation for Choosing CHAP Counters ............................................................

376

 

 

11.1.3 Functional Overview of CHAP Counters..............................................................

377

 

 

11.1.4 Basic Operation of the Performance Monitor Unit ...............................................

378

 

 

11.1.5 Definition of CHAP Terminology ..........................................................................

379

 

 

11.1.6 Definition of Clock Domains.................................................................................

380

 

11.2 Interface and CSR Description .........................................................................................

380

 

 

11.2.1

APB Peripheral ....................................................................................................

381

 

 

11.2.2

CAP Description ..................................................................................................

381

 

 

 

11.2.2.1 Selecting the Access Mode..................................................................

381

 

 

 

11.2.2.2

PMU CSR ............................................................................................

381

 

 

 

11.2.2.3

CAP Writes ..........................................................................................

381

 

 

 

11.2.2.4

CAP Reads ..........................................................................................

381

 

 

11.2.3

Configuration Registers .......................................................................................

382

 

11.3

Performance Measurements ............................................................................................

382

 

11.4 Events Monitored in Hardware .........................................................................................

385

 

 

11.4.1

Queue Statistics Events.......................................................................................

385

 

 

 

11.4.1.1

Queue Latency.....................................................................................

385

 

 

 

11.4.1.2

Queue Utilization..................................................................................

385

 

 

11.4.2

Count Events .......................................................................................................

385

 

 

 

11.4.2.1 Hardware Block Execution Count ........................................................

385

 

 

11.4.3 Design Block Select Definitions ...........................................................................

386

 

 

11.4.4

Null Event ............................................................................................................

387

 

 

11.4.5

Threshold Events.................................................................................................

388

 

 

11.4.6

External Input Events...........................................................................................

389

 

 

 

11.4.6.1 XPI Events Target ID(000001) / Design Block #(0100) .......................

389

 

 

 

11.4.6.2 SHaC Events Target ID(000010) / Design Block #(0101)....................

393

 

 

 

11.4.6.3 IXP2800 Network Processor MSF Events Target ID(000011) /

 

 

 

 

 

Design Block #(0110)...........................................................................

396

 

 

 

11.4.6.4 Intel XScale® Core Events Target ID(000100) /

 

 

 

 

 

Design Block #(0111)...........................................................................

402

 

 

 

11.4.6.5 PCI Events Target ID(000101) / Design Block #(1000) .......................

405

 

 

 

11.4.6.6 ME00 Events Target ID(100000) / Design Block #(1001)....................

409

14

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Contents

11.4.6.7 ME01 Events Target ID(100001) / Design Block #(1001)....................

410

11.4.6.8 ME02 Events Target ID(100010) / Design Block #(1001)....................

411

11.4.6.9 ME03 Events Target ID(100011) / Design Block #(1001)....................

411

11.4.6.10 ME04 Events Target ID(100100) / Design Block #(1001)....................

412

11.4.6.11 ME05 Events Target ID(100101) / Design Block #(1001)....................

412

11.4.6.12 ME06 Events Target ID(100110) / Design Block #(1001)....................

413

11.4.6.13 ME07 Events Target ID(100111) / Design Block #(1001)....................

413

11.4.6.14 ME10 Events Target ID(110000) / Design Block #(1010)....................

414

11.4.6.15 ME11 Events Target ID(110001) / Design Block #(1010)....................

414

11.4.6.16 ME12 Events Target ID(110010) / Design Block #(1010)....................

415

11.4.6.17 ME13 Events Target ID(110011) / Design Block #(1010)....................

415

11.4.6.18 ME14 Events Target ID(110100) / Design Block #(1010)....................

416

11.4.6.19 ME15 Events Target ID(110101) / Design Block #(1010)....................

416

11.4.6.20 ME16 Events Target ID(100110) / Design Block #(1010)....................

417

11.4.6.21 ME17 Events Target ID(110111) / Design Block #(1010)....................

417

11.4.6.22 SRAM DP1 Events Target ID(001001) / Design Block #(0010)...........

418

11.4.6.23 SRAM DP0 Events Target ID(001010) / Design Block #(0010)...........

418

11.4.6.24 SRAM CH3 Events Target ID(001011) / Design Block #(0010)...........

420

11.4.6.25 SRAM CH2 Events Target ID(001100) / Design Block #(0010)...........

421

11.4.6.26 SRAM CH1 Events Target ID(001101) / Design Block #(0010)...........

421

11.4.6.27 SRAM CH0 Events Target ID(001110) / Design Block #(0010)...........

422

11.4.6.28 DRAM DPLA Events Target ID(010010) / Design Block #(0011) ........

423

11.4.6.29 DRAM DPSA Events Target ID(010011) / Design Block #(0011)........

424

11.4.6.30 IXP2800 Network Processor DRAM CH2 Events Target ID(010100) /

 

Design Block #(0011)...........................................................................

425

11.4.6.31 IXP2800 Network Processor DRAM CH1 Events Target ID(010101) /

 

Design Block #(0011)...........................................................................

429

11.4.6.32 IXP2800 Network Processor DRAM CH0 Events Target ID(010110) /

 

Design Block #(0011)...........................................................................

429

Hardware Reference Manual

15

Contents

 

Figures

 

1

IXP2800 Network Processor Functional Block Diagram ............................................................

28

2

IXP2800 Network Processor Detailed Diagram..........................................................................

29

3

Intel XScale® Core 4-GB (32-Bit) Address Space .....................................................................

32

4

Microengine Block Diagram........................................................................................................

34

5

Context State Transition Diagram ..............................................................................................

36

6

Byte-Align Block Diagram...........................................................................................................

44

7

CAM Block Diagram ...................................................................................................................

46

8

Echo Clock Configuration ...........................................................................................................

52

9

Logical View of Rings .................................................................................................................

57

10

Example System Block Diagram ................................................................................................

59

11

Full-Duplex Block Diagram .........................................................................................................

60

12

Simplified MSF Receive Section Block Diagram ........................................................................

61

13

Simplified Transmit Section Block Diagram................................................................................

65

14

Hash Unit Block Diagram ...........................................................................................................

70

15

DMA Descriptor Reads...............................................................................................................

72

16

Intel XScale® Core Architecture Features ..................................................................................

80

17

Example of Locked Entries in TLB .............................................................................................

88

18

Instruction Cache Organization ..................................................................................................

89

19

Locked Line Effect on Round Robin Replacement.....................................................................

93

20

BTB Entry ...................................................................................................................................

95

21

Branch History ............................................................................................................................

95

22

Data Cache Organization ...........................................................................................................

97

23

Mini-Data Cache Organization ...................................................................................................

98

24

Byte Steering for Read and Byte-Enable Generation by the Intel XScale® Core .....................

122

25

Intel XScale® Core-Initiated Write to the IXP2800 Network Processor....................................

124

26

Intel XScale® Core-Initiated Write to the IXP2800 Network Processor (Continued)................

125

27

Global Buses Connection to the Intel XScale® Core Gasket ...................................................

126

28

Flow Through the Intel XScale® Core Interrupt Controller........................................................

132

29

Interrupt Mask Block Diagram ..................................................................................................

133

30

XPI Interfaces for IXP2800 Network Processor........................................................................

135

31

UART Data Frame....................................................................................................................

138

32

GPIO Functional Diagram ........................................................................................................

140

33

Timer Control Unit Interfacing Diagram ....................................................................................

141

34

Timer Internal Logic Diagram ...................................................................................................

142

35

Slowport Unit Interface Diagram...............................................................................................

144

36

Address Space Hole Diagram ..................................................................................................

145

37

Slowport Example Application Topology ..................................................................................

146

38

Mode 0 Single Write Transfer for a Fixed-Timed Device..........................................................

147

39

Mode 0 Single Write Transfer for a Self-Timing Device ...........................................................

148

40

Mode 0 Single Read Transfer for Fixed-Timed Device ............................................................

149

41

Mode 0 Single Read Transfer for a Self-Timing Device ...........................................................

150

42

An Interface Topology with Lucent* TDAT042G5 SONET/SDH...............................................

152

43

Mode 1 Single Write Transfer for Lucent* TDAT042G5 Device (B0) .......................................

153

44

Mode 1 Single Read Transfer for Lucent* TDAT042G5 Device (B0) .......................................

154

45

An Interface Topology with PMC-Sierra* PM5351 S/UNI-TETRA* ..........................................

155

46

Mode 2 Single Write Transfer for PMC-Sierra* PM5351 Device (B0) ......................................

156

47

Mode 2 Single Read Transfer for PMC-Sierra* PM5351 Device (B0) ......................................

157

16

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Contents

48

An Interface Topology with Intel / AMCC* SONET/SDH Device ..............................................

158

49

Mode 3 Second Interface Topology with Intel / AMCC* SONET/SDH Device..........................

159

50

Mode 3 Single Write Transfer Followed by Read (B0) .............................................................

160

51

Mode 3 Single Read Transfer Followed by Write (B0) .............................................................

161

52

An Interface Topology with Intel / AMCC* SONET/SDH Device in Motorola* Mode ................

162

53

Second Interface Topology with Intel / AMCC* SONET/SDH Device.......................................

163

54

Mode 4 Single Write Transfer (B0) ...........................................................................................

164

55

Mode 4 Single Read Transfer (B0) ...........................................................................................

165

56

Microengine Block Diagram......................................................................................................

168

57

Context State Transition Diagram.............................................................................................

170

58

Byte Align Block Diagram .........................................................................................................

175

59

CAM Block Diagram .................................................................................................................

177

60

Read from RBUF (64 Bits)........................................................................................................

181

61

Write to TBUF (64 Bits).............................................................................................................

182

62

48-, 64-, and 128-Bit Hash Operand Transfers ........................................................................

183

63

Bit, Byte, and Longword Organization in One RBUF Element..................................................

184

64

Write to TBUF ...........................................................................................................................

185

65

MSF Interface ...........................................................................................................................

186

66

Clock Configuration ..................................................................................................................

189

67

IXP2800 Clocking for RDRAM at 400 MHz ..............................................................................

190

68

IXP2800 Clocking for RDRAM at 508 MHz ..............................................................................

190

69

Address Mapping Flow .............................................................................................................

191

70

RDRAM Controller Block Diagram............................................................................................

198

71

DRAM Push/Pull Arbiter Functional Blocks ..............................................................................

202

72

DRAM Push Arbiter Functional Blocks .....................................................................................

204

73

DRAM Pull Arbiter Functional Blocks .......................................................................................

205

74

SRAM Controller/Chassis Block Diagram.................................................................................

208

75

SRAM Clock Connection on a Channel....................................................................................

210

76

External Pipeline Registers Block Diagram ..............................................................................

211

77

Queue Descriptor with Four Links ............................................................................................

213

78

Enqueueing One Buffer at a Time ............................................................................................

213

79

Previously Linked String of Buffers...........................................................................................

214

80

First Step to Enqueue a String of Buffers to a Queue (ENQ_Tail_and_Link)...........................

214

81

Second Step to Enqueue a String of Buffers to a Queue (ENQ_Tail) ......................................

214

82

Connection to a Coprocessor Though Standard QDR Interface ..............................................

221

83

Coprocessor with Memory Mapped FIFO Ports .......................................................................

222

84

SHaC Top Level Diagram.........................................................................................................

226

85

Scratchpad Block Diagram .......................................................................................................

228

86

Ring Communication Logic Diagram ........................................................................................

231

87

Hash Unit Block Diagram..........................................................................................................

236

88

Example System Block Diagram ..............................................................................................

242

89

Full-Duplex Block Diagram .......................................................................................................

243

90

Receive and Transmit Clock Generation ..................................................................................

245

91

Simplified Receive Section Block Diagram...............................................................................

247

92

RBUF Element State Diagram..................................................................................................

257

93

Extent of DIP-4 Codes ..............................................................................................................

260

94

Simplified Transmit Section Block Diagram..............................................................................

262

95

TBUF State Diagram ................................................................................................................

270

96

Tx Calendar Block Diagram......................................................................................................

271

97

CSIX Flow Control Interface — TXCSRB and RXCSRB ..........................................................

275

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17

Contents

 

98

CSIX Flow Control Interface — FCIFIFO and FCEFIFO in Full Duplex Mode .........................

277

99

CSIX Flow Control Interface — FCIFIFO and FCEFIFO in Simplex Mode ..............................

278

100

MSF to Command and Push and Pull Buses Interface Block Diagram....................................

290

101

Basic I/O Capability of the Intel® IXP2800 Network Processor................................................

292

102

Simplex Configuration ..............................................................................................................

293

103

Hybrid Simplex Configuration ...................................................................................................

294

104

Dual Network Processor, Full Duplex Configuration ................................................................

295

105

Single Network Processor, Full Duplex Configuration (SPI-4.2 Protocol) ................................

296

106

Single Network Processor, Full Duplex Configuration (SPI-4.2 and CSIX-L1 Protocols).........

297

107

Framer, Single Network Processor Ingress and Egress, and Fabric Interface Chip ................

298

108

Framer, Dual Processor Ingress, Single Processor Egress, and Fabric Interface Chip...........

298

109

Framer, Single Network Processor Ingress, Single Network Processor Egress,

 

 

CSIX-L1 Translation Chip and CSIX-L1 Fabric Interface Chip.................................................

299

110

CPU Complex, Network Processor, and Fabric Interface Chips ..............................................

299

111

Framer, Single Network Processor, Co-Processor, and Fabric Interface Chip ........................

300

112

SPI-4.2 Interface Reference Model with Receiver and Transmitter Labels

 

 

Corresponding to Link Layer Device Functions........................................................................

301

113

CSIX-L1 Interface Reference Model with Receiver and Transmitter Labels

 

 

Corresponding to Fabric Interface Chip Functions ...................................................................

303

114

Reference Model for IXP2800 Support of the Simplex Configuration Using

 

 

Independent Ingress and Egress Interfaces.............................................................................

306

115

Reference Model for Hybrid Simplex Operation .......................................................................

307

116

Block Diagram of Dual Protocol (SPI-4.2 and CSIX-L1) Bridge Chip.......................................

313

117

Summary of Receiver and Transmitter Signaling .....................................................................

317

118

PCI Functional Blocks ..............................................................................................................

320

119

Data Access Paths ...................................................................................................................

321

120

PCI Arbiter Configuration Using CFG_PCI_ARB(GPIO[2]) ......................................................

331

121

Example of Target Write to SRAM of 68 Bytes ........................................................................

333

122

Example of Target Write to DRAM of 68 Bytes ........................................................................

335

123

Example of Target Read from DRAM Using 64-Byte Burst......................................................

336

124

Generation of the Doorbell Interrupts to PCI ............................................................................

337

125

Generation of the Doorbell Interrupts to the Intel XScale® Core..............................................

338

126

PCI Interrupts ...........................................................................................................................

339

127

DMA Descriptor Reads.............................................................................................................

342

128

PCI Address Generation for Command Bus Master to PCI......................................................

346

129

PCI Address Generation for Command Bus Master to PCI Configuration Cycle .....................

347

130

Overall Clock Generation and Distribution ...............................................................................

360

131

IXP2800 Network Processor Clock Generation........................................................................

363

132

Synchronization Between Frequency Domains........................................................................

364

133

Reset Out Behavior ..................................................................................................................

365

134

Reset Generation .....................................................................................................................

366

135

Boot Process ............................................................................................................................

371

136

Performance Monitor Interface Block Diagram.........................................................................

376

137

Block Diagram of a Single CHAP Counter ...............................................................................

378

138

Basic Block Diagram of IXP2800 Network Processor with PMU..............................................

379

139

CAP Interface to the APB .........................................................................................................

380

140

Conceptual Diagram of Counter Array .....................................................................................

382

18

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Contents

Tables

 

1

Data Terminology .......................................................................................................................

26

2

Longword Formats......................................................................................................................

26

3

IXP2800 Network Processor Microengine Bus Arrangement .....................................................

35

4

Next Neighbor Write as a Function of CTX_ENABLE[NN_MODE] ............................................

38

5

Registers Used By Contexts in Context-Relative Addressing Mode ..........................................

41

6

Align Value and Shift Amount .....................................................................................................

43

7

Register Contents for Example 10..............................................................................................

44

8

Register Contents for Example 11..............................................................................................

45

9

RDRAM Sizes.............................................................................................................................

50

10

SRAM Controller Configurations.................................................................................................

52

11

Total Memory per Channel .........................................................................................................

53

12

Address Reference Order...........................................................................................................

55

13

Q_array Entry Reference Order..................................................................................................

55

14

Ring Full Signal Use – Number of Contexts and Length versus Ring Size ................................

58

15

TBUF SPI-4 Control Definition....................................................................................................

66

16

TBUF CSIX Control Definition ....................................................................................................

67

17

DMA Descriptor Format ..............................................................................................................

72

18

Doorbell Interrupt Registers........................................................................................................

75

19

I/O Latency .................................................................................................................................

78

20

Data Cache and Buffer Behavior when X = 0.............................................................................

83

21

Data Cache and Buffer Behavior when X = 1.............................................................................

83

22

Memory Operations that Impose a Fence ..................................................................................

84

23

Valid MMU and Data/Mini-Data Cache Combinations................................................................

85

24

Performance Monitoring Events ...............................................................................................

107

25

Some Common Uses of the PMU.............................................................................................

108

26

Branch Latency Penalty............................................................................................................

112

27

Latency Example ......................................................................................................................

114

28

Branch Instruction Timings (Predicted by the BTB)..................................................................

115

29

Branch Instruction Timings (Not Predicted by the BTB) ...........................................................

115

30

Data Processing Instruction Timings ........................................................................................

115

31

Multiply Instruction Timings ......................................................................................................

116

32

Multiply Implicit Accumulate Instruction Timings ......................................................................

117

33

Implicit Accumulator Access Instruction Timings......................................................................

117

34

Saturated Data Processing Instruction Timings........................................................................

117

35

Status Register Access Instruction Timings .............................................................................

118

36

Load and Store Instruction Timings ..........................................................................................

118

37

Load and Store Multiple Instruction Timings.............................................................................

118

38

Semaphore Instruction Timings ................................................................................................

118

39

CP15 Register Access Instruction Timings...............................................................................

119

40

CP14 Register Access Instruction Timings...............................................................................

119

41

SWI Instruction Timings............................................................................................................

119

42

Count Leading Zeros Instruction Timings .................................................................................

119

43

Little-Endian Encoding..............................................................................................................

120

44

Big-Endian Encoding ................................................................................................................

120

45

Byte-Enable Generation by the Intel XScale® Core for Byte Transfers in Littleand

 

 

Big-Endian Systems .................................................................................................................

121

46

Byte-Enable Generation by the Intel XScale® Core for 16-Bit Data Transfers in Little-

 

 

and Big-Endian Systems ..........................................................................................................

123

Hardware Reference Manual

19

Contents

 

47

Byte-Enable Generation by the Intel XScale® Core for Byte Writes in Littleand

 

 

Big-Endian Systems .................................................................................................................

123

48

Byte-Enable Generation by the Intel XScale® Core for Word Writes in Littleand

 

 

Big-Endian Systems .................................................................................................................

124

49

CMB Write Command to CPP Command Conversion .............................................................

127

50

IXP2800 Network Processor SRAM Q-Array Access Alias Addresses ....................................

129

51

GCSR Address Map (0xd700 0000).........................................................................................

131

52

Data Transaction Alignment .....................................................................................................

136

53

Address Spaces for XPI Internal Devices.................................................................................

136

54

8-Bit Flash Memory Device Density .........................................................................................

143

55

SONET/SDH Devices...............................................................................................................

143

56

Next Neighbor Write as a Function of CTX_Enable[NN_Mode] ...............................................

172

57

Registers Used by Contexts in Context-Relative Addressing Mode.........................................

173

58

Align Value and Shift Amount...................................................................................................

174

59

Register Contents for Example 23............................................................................................

175

60

Register Contents for Example 24............................................................................................

176

61

RDRAM Loading.......................................................................................................................

188

62

RDRAM Sizes...........................................................................................................................

188

63

Address Rearrangement for 3-Way Interleave (Sheet 1 of 2) ..................................................

192

64

Address Rearrangement for 3-Way Interleave (Sheet 2 of 2) (Rev B) ....................................

193

65

Address Bank Interleaving........................................................................................................

194

66

RDRAM Timing Parameter Settings.........................................................................................

196

67

Ordering of Reads and Writes to the Same Address for DRAM...............................................

201

68

DRAM Push Arbiter Operation .................................................................................................

203

69

DPLA Description .....................................................................................................................

204

70

SRAM Controller Configurations ..............................................................................................

209

71

Total Memory per Channel .......................................................................................................

210

72

Atomic Operations ....................................................................................................................

212

73

Queue Format ..........................................................................................................................

215

74

Ring/Journal Format .................................................................................................................

216

75

Ring Size Encoding ..................................................................................................................

216

76

Address Map ............................................................................................................................

218

77

Address Reference Order.........................................................................................................

219

78

Q_array Entry Reference Order ...............................................................................................

220

79

Ring Full Signal Use – Number of Contexts and Length versus Ring Size ..............................

232

80

Head/Tail, Base, and Full Threshold – by Ring Size ................................................................

233

81

Intel XScale® Core and Microengine Instructions ....................................................................

235

82

S_Transfer Registers Hash Operands .....................................................................................

237

83

SPI-4 Control Word Format ......................................................................................................

244

84

Order of Bytes within the SPI-4 Data Burst ..............................................................................

245

85

CFrame Types..........................................................................................................................

246

86

Receive Pins Usage by Protocol ..............................................................................................

248

87

Order in which Received Data Is Stored in RBUF....................................................................

248

88

Mapping of Received Data to RBUF Partitions ........................................................................

249

89

Number of Elements per RBUF Partition..................................................................................

249

90

RBUF SPIF-4 Status Definition ................................................................................................

252

91

RBUF CSIX Status Definition ...................................................................................................

254

92

Rx_Thread_Freelist Use...........................................................................................................

255

93

Summary of SPI-4 and CSIX RBUF Operations ......................................................................

258

94

Transmit Pins Usage by Protocol .............................................................................................

262

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Contents

95

Order in which Data is Transmitted from TBUF........................................................................

263

96

Mapping of TBUF Partitions to Transmit Protocol ....................................................................

263

97

Number of Elements per TBUF Partition ..................................................................................

264

98

TBUF SPI-4 Control Definition..................................................................................................

266

99

TBUF CSIX Control Definition ..................................................................................................

267

100

Transmit SPI-4 Control Word....................................................................................................

268

101

Transmit CSIX Header..............................................................................................................

269

102

Summary of RBUF and TBUF Operations................................................................................

274

103

SRB Definition by Clock Phase Number...................................................................................

276

104

Data Deskew Functions............................................................................................................

281

105

Calendar Deskew Functions.....................................................................................................

281

106

Flow Control Deskew Functions ...............................................................................................

281

107

Data Training Sequence ...........................................................................................................

282

108

Flow Control Training Sequence ..............................................................................................

282

109

Calendar Training Sequence ....................................................................................................

283

110

IXP2800 Network Processor Requires Data Training...............................................................

284

111

Switch Fabric or SPI-4 Framer Requires Data Training ...........................................................

285

112

IXP2800 Network Processor Requires Flow Control Training ..................................................

286

113

Switch Fabric Requires Flow Control Training..........................................................................

286

114

SPI-4.2 Transmitter State Machine Transitions on 16-Bit Bus Transfers .................................

314

115

Training Transmitter State Machine Transitions on 16-Bit Bus Transfers ................................

315

116

CSIX-L1 Transmitter State Machine Transitions on CWord Boundaries ..................................

315

117

PCI Block FIFO Sizes ...............................................................................................................

322

118

Maximum Loading ....................................................................................................................

322

119

PCI Commands ........................................................................................................................

322

120

PCI BAR Programmable Sizes .................................................................................................

324

121

PCI BAR Sizes with PCI Host Initialization ...............................................................................

324

122

Legal Combinations of the Strap Pin Options...........................................................................

330

123

Slave Interface Buffer Sizes .....................................................................................................

332

124

Doorbell Interrupt Registers......................................................................................................

337

125

IRQ Interrupt Options by Stepping............................................................................................

339

126

DMA Descriptor Format ............................................................................................................

342

127

PCI Maximum Burst Size..........................................................................................................

345

128

Command Bus Master Configuration Transactions ..................................................................

347

129

Command Bus Master Address Space Map to PCI..................................................................

347

130

Byte Lane Alignment for 64-Bit PCI Data In (64 Bits PCI Little-Endian to Big-Endian

 

 

with Swap) ................................................................................................................................

353

131

Byte Lane Alignment for 64-Bit PCI Data In (64 Bits PCI Big-Endian to Big-Endian

 

 

without Swap) ...........................................................................................................................

353

132

Byte Lane Alignment for 32-Bit PCI Data In (32 Bits PCI Little-Endian to Big-Endian

 

 

with Swap) ................................................................................................................................

353

133

Byte Lane Alignment for 32-Bit PCI Data In (32 Bits PCI Big-Endian to Big-Endian

 

 

without Swap) ...........................................................................................................................

353

134

Byte Lane Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Little

 

 

Endian with Swap) ....................................................................................................................

354

135

Byte Lane Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Big-Endian

 

 

without Swap) ...........................................................................................................................

354

136

Byte Lane Alignment for 32-Bit PCI Data Out (Big-Endian to 32 Bits PCI Little

 

 

Endian with Swap) ....................................................................................................................

354

137

Byte Lane Alignment for 32-Bit PCI Data Out (Big-Endian to 32 Bits PCI Big-Endian

 

 

without Swap) ...........................................................................................................................

354

Hardware Reference Manual

21

Contents

 

138

Byte Enable Alignment for 64-Bit PCI Data In (64 Bits PCI Little-Endian to Big-

 

 

Endian with Swap)....................................................................................................................

355

139

Byte Enable Alignment for 64-Bit PCI Data In (64 Bits PCI Big-Endian to Big-Endian

 

 

without Swap) ...........................................................................................................................

355

140

Byte Enable Alignment for 32-Bit PCI Data In (32 bits PCI Little-Endian to Big-

 

 

Endian with Swap)....................................................................................................................

355

141

Byte Enable Alignment for 32-Bit PCI Data In (32 Bits PCI Big-Endian to Big-Endian

 

 

without Swap) ...........................................................................................................................

356

142

Byte Enable Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Little

 

 

Endian with Swap)....................................................................................................................

356

143

Byte Enable Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Big

 

 

Endian without Swap)...............................................................................................................

356

144

Byte Enable Alignment for 32-Bit PCI Data Out (Big-Endian to 32 Bits PCI Little

 

 

Endian with Swap)....................................................................................................................

356

145

Byte Enable Alignment for 32-Bit PCI Data Out (Big-Endian to 32 Bits PCI Big

 

 

Endian without Swap)...............................................................................................................

357

146

PCI I/O Cycles with Data Swap Enable....................................................................................

358

147

Clock Usage Summary.............................................................................................................

360

148

Clock Rates Examples .............................................................................................................

362

149

IXP2800 Network Processor Strap Pins...................................................................................

369

150

Supported Strap Combinations ................................................................................................

370

151

APB Usage ...............................................................................................................................

381

152

Hardware Blocks and Their Performance Measurement Events..............................................

383

153

PMU Design Unit Selection ......................................................................................................

386

154

Chap Counter Threshold Events (Design Block # 0001)..........................................................

388

155

XPI PMU Event List ..................................................................................................................

389

156

SHaC PMU Event List ..............................................................................................................

393

157

IXP2800 Network Processor MSF PMU Event List ..................................................................

396

158

Intel XScale® Core Gasket PMU Event List.............................................................................

402

159

PCI PMU Event List..................................................................................................................

405

160

ME00 PMU Event List ..............................................................................................................

409

161

ME01 PMU Event List ..............................................................................................................

410

162

ME02 PMU Event List ..............................................................................................................

411

163

ME03 PMU Event List ..............................................................................................................

411

164

ME04 PMU Event List ..............................................................................................................

412

165

ME05 PMU Event List ..............................................................................................................

412

166

ME06 PMU Event List ..............................................................................................................

413

167

ME07 PMU Event List ..............................................................................................................

413

168

ME10 PMU Event List ..............................................................................................................

414

169

ME11 PMU Event List ..............................................................................................................

414

170

ME12 PMU Event List ..............................................................................................................

415

171

ME13 PMU Event List ..............................................................................................................

415

172

ME14 PMU Event List ..............................................................................................................

416

173

ME15 PMU Event List ..............................................................................................................

416

174

ME16 PMU Event List ..............................................................................................................

417

175

ME17 PMU Event List ..............................................................................................................

417

176

SRAM DP1 PMU Event List .....................................................................................................

418

177

SRAM DP0 PMU Event List .....................................................................................................

418

178

SRAM CH3 PMU Event List .....................................................................................................

420

179

SRAM CH3 PMU Event List .....................................................................................................

421

180

SRAM CH3 PMU Event List .....................................................................................................

421

22

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Contents

181

SRAM CH0 PMU Event List .....................................................................................................

422

182

IXP2800 Network Processor Dram DPLA PMU Event List.......................................................

423

183

IXP2800 Network Processor Dram DPSA PMU Event List ......................................................

424

184

IXP2800 Network Processor Dram CH2 PMU Event List.........................................................

425

185

IXP2800 Network Processor Dram CH1 PMU Event List.........................................................

429

186

IXP2800 Network Processor Dram CH0 PMU Event List.........................................................

429

Hardware Reference Manual

23

Contents

24

HardwareReferenceManual

Intel® IXP2800 Network Processor

Introduction

Introduction

1

1.1About This Document

This document is the hardware reference manual for the Intel® IXP2800 Network Processor. This information is intended for use by developers and is organized as follows:

Section 2, “Technical Description” contains a hardware overview.

Section 3, “Intel XScale® Core” describes the embedded core.

Section 4, “Microengines” describes Microengine operation.

Section 5, “DRAM” describes the DRAM Unit.

Section 6, “SRAM Interface” describes the SRAM Unit.

Section 7, “SHaC — Unit Expansion” describes the Scratchpad, Hash Unit, and CSRs (SHaC).

Section 8, “Media and Switch Fabric Interface” describes the Media and Switch Fabric (MSF) Interface used to connect the network processor to a physical layer device.

Section 9, “PCI Unit” describes the PCI Unit.

Section 10, “Clocks and Reset” describes the clocks, reset and initialization sequence.

Section 11, “Performance Monitor Unit” describes the PMU.

1.2Related Documentation

Further information on the IXP2800 is available in the following documents:

IXP2800 Network Processor Datasheet – Contains summary information on the IXP2800 Network Processor including a functional description, signal descriptions, electrical specifications, and mechanical specifications.

IXP2400 and IXP2800 Network Processor Programmer’s Reference Manual – Contains detailed programming information for designers.

IXP2400/IXP2800 Network Processor Development Tools User’s Guide – Describes the Developer Workbench and the development tools you can access through the use of the Workbench GUI.

Hardware Reference Manual

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Intel® IXP2800 Network Processor

Introduction

1.3Terminology

Table 1 and Table 2 list the terminology used in this manual.

Table 1. Data Terminology

Term

Words

Bytes

Bits

 

 

 

 

Byte

½

1

8

 

 

 

 

Word

1

2

16

 

 

 

 

Longword

2

4

32

 

 

 

 

Quadword

4

8

64

 

 

 

 

Table 2. Longword Formats

Endian Type

32-Bit

 

64-Bit

 

 

 

 

 

Little-Endian

(0x12345678) arranged as {12 34 56 78}

64-bit data 0x12345678

9ABCDE56

arranged as {12

34 56

78 9A BC DE 56}

 

 

 

 

Big-Endian

(0x12345678) arranged as {78 56 34 12}

64-bit data 0x12345678

9ABCDE56

arranged as {78

56 34

12, 56 DE BC 9A}

 

 

 

 

 

 

26

Hardware Reference Manual

Intel® IXP2800 Network Processor

Technical Description

Technical Description

2

2.1Overview

This section provides a brief overview of the IXP2800 Network Processor internal hardware. This section is intended as an overall hardware introduction to the network processor.

The major blocks are:

Intel XScale®core — General purpose 32-bit RISC processor (ARM* Version 5 Architecture compliant) used to initialize and manage the network processor, and can be used for higher layer network processing tasks.

Intel XScale® technology Peripherals (XPI) — Interrupt Controller, Timers, UART, General Purpose I/O (GPIO) and interface to low-speed off chip peripherals (such as maintenance port of network devices) and Flash ROM.

Microengines (MEs) — Sixteen 32-bit programmable engines specialized for Network Processing. Microengines do the main data plane processing per packet.

DRAM Controllers — Three independent controllers for Rambus* DRAM. Typically DRAM is used for data buffer storage.

SRAM Controllers — Four independent controllers for QDR SRAM. Typically SRAM is used for control information storage.

Scratchpad Memory — 16 Kbytes storage for general purpose use.

Hash Unit — Polynomial hash accelerator. The Intel XScale® core and Microengines can use it to offload hash calculations.

Control and Status Register Access Proxy (CAP) — These provide special inter-processor

communication features to allow flexible and efficient inter-Microengine and Microengine to Intel XScale® core communication.

Media and Switch Fabric Interface (MSF) — Interface for network framers and/or Switch Fabric. Contains receive and transmit buffers.

PCI Controller — PCI Local Bus Specification, Version 2.2* interface for 64-bit 66-MHz I/O. PCI can be used to either connect to a Host processor, or to attach PCI-compliant peripheral devices.

Performance Monitor — Counters that can be programmed to count selected internal chip hardware events, which can be used to analyze and tune performance.

Figure 1 is a simple block diagram of the network processor showing the major internal hardware blocks. Figure 2 is a detailed diagram of the network processor units and buses.

Hardware Reference Manual

27

Intel® IXP2800 Network Processor

Technical Description

Figure 1. IXP2800 Network Processor Functional Block Diagram

Media Switch

Fabric (MSF)

Scratched

Memory

SRAM

 

SRAM

 

SRAM

 

SRAM

 

DRAM

 

DRAM

 

DRAM

Controller

 

Controller

 

Controller

 

Controller

 

Controller

 

Controller

 

Controller

0

 

1

 

2

 

3

 

0

 

1

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

Hash

Unit

PCI

CAP

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Intel

 

 

Intel

ME

 

 

 

ME

 

 

 

ME

 

 

 

ME

 

 

 

 

 

 

 

 

 

 

 

 

 

XScale®

 

 

0x1

 

 

 

0x0

 

 

 

0x10

 

 

 

0x11

 

 

 

XScale®

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Core

 

 

Core

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripherals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(XPI)

 

 

 

 

ME

 

 

 

ME

 

 

 

ME

 

 

 

ME

 

 

0x2

 

 

 

0x3

 

 

 

0x13

 

 

 

0x12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ME

 

 

 

ME

 

 

 

ME

 

 

 

ME

 

 

 

 

 

 

 

0x5

 

 

 

0x4

 

 

 

0x14

 

 

 

0x15

 

 

Performance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Monitor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ME

 

 

 

ME

 

 

 

ME

 

 

 

ME

 

 

 

 

 

 

 

0x6

 

 

 

0x7

 

 

 

0x17

 

 

 

0x16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ME Cluster 0

ME Cluster 1

A9226-02

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Hardware Reference Manual

Intel® IXP2800 Network Processor

Technical Description

Figure 2. IXP2800 Network Processor Detailed Diagram

SRAM

SRAM

SRAM

DRAM

DRAM

DRAM

SHaC Unit

Scratch

Hash

CAP

SP14/CSIX

 

Media

Device

Controller

RBuf

TBuf

 

 

CSR

PCI Device

mast/targ

 

 

CSRs

 

PCI

 

space

 

DMA

 

transfers

 

PCI

 

Controller

Notes:

SRAM

 

SRAM

SRAM

DRAM

DRAM

DRAM

Controller Controller

Controller

Controller

Controller

Controller

 

 

 

 

 

D Push Bus

Arbiter

Pull Bus Arbiter

 

 

 

 

 

 

 

D

 

 

 

 

D_Push

 

 

 

 

 

 

 

D_Pull

 

 

 

 

 

 

 

Cmd_1

 

 

 

 

 

 

 

Cmd_0

 

 

 

 

 

 

S_Pull

S_Pull_0

 

 

 

S_Pull

S_Push

 

 

 

 

 

 

Arb 0

 

 

 

 

Arb 1

Arb 1

 

S_Push_0

 

 

 

S_Push

 

 

 

 

 

 

 

 

 

 

 

Arb 0

 

 

 

 

S_Pull_1

S_Push_1

 

 

 

 

S in

S out

D in

D out

Cmd

 

Cmd

S in

 

S out

D in

D out

 

 

Gasket

 

 

 

 

 

 

 

 

 

 

 

 

xfer

xfer

xfer

xfer

FIFO

 

FIFO

xfer

 

xfer

xfer

xfer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CSRs

ME0x10-0x17

 

CSRs

ME0x0-0x7

 

 

 

 

Intel

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XScale®

 

 

 

 

 

Cluster 1

 

 

Cluster 0

 

 

 

 

Core

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cmd_Arb_1

 

 

 

 

 

 

 

 

 

 

 

 

Cmd_Arb_0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(grant/request)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(grant/request)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Command Bus

 

 

 

Command Bus

 

 

 

 

 

 

 

 

 

 

Arbiter 1

 

 

 

 

Arbiter 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Connected to the S_Push/Pull Buses

Connected to the S_Push/Pull Buses and D_Push/Pull Buses

= Chassis Components

A9750-03

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29

Intel® IXP2800 Network Processor

Technical Description

2.2Intel XScale® Core Microarchitecture

The Intel XScale® microarchitecture consists of a 32-bit general purpose RISC processor that incorporates an extensive list of architecture features that allows it to achieve high performance.

2.2.1ARM* Compatibility

The Intel XScale® microarchitecture is ARM* Version 5 (V5) Architecture compliant. It implements the integer instruction set of ARM* V5, but does not provide hardware support of the floating point instructions.

The Intel XScale® microarchitecture provides the Thumb instruction set (ARM V5T) and the ARM V5E DSP extensions.

Backward compatibility with the first generation of StrongARM* products is maintained for usermode applications. Operating systems may require modifications to match the specific hardware features of the Intel XScale® microarchitecture and to take advantage of the performance enhancements added to the Intel XScale® core.

2.2.2Features

2.2.2.1Multiply/Accumulate (MAC)

The MAC unit supports early termination of multiplies/accumulates in two cycles and can sustain a throughput of a MAC operation every cycle. Several architectural enhancements were made to the MAC to support audio coding algorithms, which include a 40-bit accumulator and support for 16-bit packed values.

2.2.2.2Memory Management

The Intel XScale® microarchitecture implements the Memory Management Unit (MMU) Architecture specified in the ARM Architecture Reference Manual. The MMU provides access protection and virtual to physical address translation.

The MMU Architecture also specifies the caching policies for the instruction cache and data memory. These policies are specified as page attributes and include:

identifying code as cacheable or non-cacheable

selecting between the mini-data cache or data cache

write-back or write-through data caching

enabling data write allocation policy

and enabling the write buffer to coalesce stores to external memory

2.2.2.3Instruction Cache

The Intel XScale® microarchitecture implements a 32-Kbyte, 32-way set associative instruction cache with a line size of 32 bytes. All requests that “miss” the instruction cache generate a 32-byte read request to external memory. A mechanism to lock critical code within the cache is also provided.

30

Hardware Reference Manual

Intel® IXP2800 Network Processor

Technical Description

2.2.2.4Branch Target Buffer

The Intel XScale® microarchitecture provides a Branch Target Buffer (BTB) to predict the outcome of branch type instructions. It provides storage for the target address of branch type instructions and predicts the next address to present to the instruction cache when the current instruction address is that of a branch.

The BTB holds 128 entries.

2.2.2.5Data Cache

The Intel XScale® microarchitecture implements a 32-Kbyte, 32-way set associative data cache and a 2-Kbyte, 2-way set associative mini-data cache. Each cache has a line size of 32 bytes, and supports write-through or write-back caching.

The data/mini-data cache is controlled by page attributes defined in the MMU Architecture and by coprocessor 15.

The Intel XScale® microarchitecture allows applications to reconfigure a portion of the data cache as data RAM. Software may place special tables or frequently used variables in this RAM.

2.2.2.6Interrupt Controller

The Intel XScale® microarchitecture provides two levels of interrupt, IRQ and FIQ. They can be masked via coprocessor 13. Note that there is also a memory-mapped interrupt controller described with the Intel XScale® technology peripherals (see Section 3.12), which is used to mask and steer many chip-wide interrupt sources.

Hardware Reference Manual

31

Intel® IXP2800 Network Processor

Technical Description

2.2.2.7Address Map

Figure 3 shows the partitioning of the Intel XScale® core microarchitecture 4-Gbyte address space.

Figure 3. Intel XScale® Core 4-GB (32-Bit) Address Space

0XFFFF FFF

 

PCI MEM

 

 

 

(1/2 Gb)

 

 

 

 

3.5 Gb

PCI Local CSRs

0XDF00 0000

0XE000 0000

 

 

PCI Config Regs

0XDE00 0000

PCI Spec/IACK

0XDC00 0000

0XDFFF FFF

PCI CFG (32 Mb)

0XDA00 0000

 

Other

 

PCI I/O (32 Mb)

0XD800 0000

 

(1/2 Gb)

Intel XScale® Core CSR

0XD600 0000

0XC000 0000

 

 

RESERVED

 

(32 Mb x 2)

 

0XBFFF FFF

 

 

DRAM CSR (32 Mb)

0XD000 0000

 

 

 

 

 

 

SRAM Ring (32 Mb)

0XCE00 0000

 

 

 

SRAM CSR & Queue

0XCC00 0000

 

SRAM

Scratch (32 Mb)

0XCA00 0000

 

MSF (32 Mb)

0XC800 0000

 

(1 Gb)

 

FLASH ROM

 

 

 

 

 

 

 

 

(64 Mb)

0XC400 0000

 

 

 

 

 

 

 

 

0XC200 0000

 

 

 

RESERVED

 

 

3.0 Gb

CAP-CSRs (32 Mb)

0XC000 0000

0x8000 0000

 

 

 

 

0X7FFF FFFF

 

 

DRAM and Intel XScale® Core FLASH ROM (2 Gb)

0X0000 0000

A9693-02

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Hardware Reference Manual

Intel® IXP2800 Network Processor

Technical Description

2.3Microengines

The Microengines do most of the programmable pre-packet processing in the IXP2800 Network Processor. There are 16 Microengines, connected as shown in Figure 1. The Microengines have access to all shared resources (SRAM, DRAM, MSF, etc.) as well as private connections between adjacent Microengines (referred to as “next neighbors”).

The block diagram in Figure 4 is used in the Microengine description. Note that this block diagram is simplified for clarity; some blocks and connectivity have been omitted to make the diagram more readable. Also, this block diagram does not show any pipeline stages, rather it shows the logical flow of information.

Microengines provide support for software-controlled multi-threaded operation. Given the disparity in processor cycle times versus external memory times, a single thread of execution often blocks, waiting for external memory operations to complete. Multiple threads allow for threadinterleave operation, as there is often at least one thread ready to run while others are blocked.

Hardware Reference Manual

33

Intel® IXP2800 Network Processor

Technical Description

Figure 4. Microengine Block Diagram

 

 

 

 

D_Push

 

 

S_Push

 

 

 

 

 

 

(from SRAM

NNData_In

 

 

 

(from DRAM)

 

 

 

 

 

 

 

Scratchpad,

 

 

 

 

 

 

(from previous ME)

 

 

 

 

 

MSF, Hash,

 

 

 

 

 

 

 

PCI, CAP)

640

 

 

 

 

 

 

 

Local

 

 

 

 

 

 

 

Mem

d

 

 

 

 

 

 

 

128

128

128

128

128

Control

 

e

 

GPRs

GPRs

Next

D

S

Store

 

c

 

o

(A Bank)

(B Bank)

Neighbor

XFER

XFER

 

 

 

 

 

In

In

 

 

d

 

 

 

 

 

 

 

 

 

 

 

 

e

 

 

 

 

 

 

Lm_addr_1

 

 

 

 

 

 

 

Lm_addr_0

 

 

 

 

 

 

A_Src

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B_Src

 

 

 

 

 

 

T_Index

 

CRC_Remainder

 

 

 

 

NN_Get

 

 

 

 

 

 

 

CRC Unit

 

 

 

 

 

 

Immed

 

 

A_Operand

B_Operand

 

 

 

 

 

 

Execution

 

 

 

 

 

 

 

Datapath

 

 

 

 

 

(Shift, Add, Subtract, Multiply Logicals,

 

 

 

 

 

Find First Bit, CAM)

 

 

 

 

 

 

ALU_Out

 

 

 

Dest

S_Push

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NN_Data_Out

 

 

 

 

 

 

 

(to next ME)

 

128

 

D

Local

XFER

CSRs

Out

 

D_Pull

128

CMD

FIFO

S

(4)

XFER

 

Out

 

 

 

 

Control

Command

 

 

Data

 

 

 

 

 

S_Pull

B1670-01

34

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Intel® IXP2800 Network Processor

Technical Description

2.3.1Microengine Bus Arrangement

The IXP2800 Network Processor supports a single D_Push/D_Pull bus, and both Microengine clusters interface to the same bus. Also, it supports two command buses, and two sets of S_Push/S_Pull buses connected as shown in Table 3, which also shows the next neighbor relationship between the Microengine.

Table 3. IXP2800 Network Processor Microengine Bus Arrangement

Microengine

Microengine

Next

Previous

Command

S_Push and

Cluster

Number

Neighbor

Neighbor

Bus

S_Pull Bus

 

 

 

 

 

 

 

0x00

0x01

NA

 

 

 

 

 

 

 

 

 

0x01

0x02

0x00

 

 

 

 

 

 

 

 

 

0x02

0x03

0x01

 

 

 

 

 

 

 

 

0

0x03

0x04

0x02

0

0

 

 

 

0x04

0x05

0x03

 

 

 

 

 

 

 

 

 

 

0x05

0x06

0x04

 

 

 

 

 

 

 

 

 

0x06

0x07

0x05

 

 

 

 

 

 

 

 

 

0x07

0x10

0x06

 

 

 

 

 

 

 

 

 

0x10

0x11

0x07

 

 

 

 

 

 

 

 

 

0x11

0x12

0x10

 

 

 

 

 

 

 

 

 

0x12

0x13

0x11

 

 

 

 

 

 

 

 

1

0x13

0x14

0x12

1

1

 

 

 

0x14

0x15

0x13

 

 

 

 

 

 

 

 

 

 

0x15

0x16

0x14

 

 

 

 

 

 

 

 

 

0x16

0x17

0x15

 

 

 

 

 

 

 

 

 

0x17

NA

0x16

 

 

 

 

 

 

 

 

2.3.2Control Store

The Control Store is a RAM that holds the program that is executed by the Microengine. It holds 8192 instructions, each of which is 40 bits wide. It is initialized by the Intel XScale® core, which writes to USTORE_ADDR and USTORE_DATA Local CSRs.

The Control Store is protected by parity against soft errors. Parity checking is enabled by CTX_ENABLE[CONTROL STORE PARITY ENABLE]. A parity error on an instruction read will halt the Microengine and assert an interrupt to the Intel XScale® core.

2.3.3Contexts

There are eight hardware Contexts available in the Microengine. To allow for efficient context swapping, each Context has its own register set, Program Counter, and Context specific Local registers. Having a copy per Context eliminates the need to move Context specific information to/ from shared memory and Microengine registers for each Context swap. Fast context swapping allows a Context to do computation while other Contexts wait for I/O (typically external memory accesses) to complete or for a signal from another Context or hardware unit. (A context swap is similar to a taken branch in timing.)

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Each of the eight Contexts is in one of four states.

1.Inactive — Some applications may not require all eight contexts. A Context is in the Inactive state when its CTX_ENABLE CSR enable bit is a 0.

2.Executing — A Context is in Executing state when its context number is in ACTIVE_CTX_STS CSR. The executing Context’s PC is used to fetch instructions from the Control Store. A Context will stay in this state until it executes an instruction that causes it to go to Sleep state (there is no hardware interrupt or preemption; Context swapping is completely under software control). At most one Context can be in Executing state at any time.

3.Ready — In this state, a Context is ready to execute, but is not because a different Context is executing. When the Executing Context goes to the Sleep state, the Microengine’s context arbiter selects the next Context to go to the Executing state from among all the Contexts in the Ready state. The arbitration is round robin.

4.Sleep — Context is waiting for external event(s) specified in the INDIRECT_WAKEUP_EVENTS CSR to occur (typically, but not limited to, an I/O access). In this state the Context does not arbitrate to enter the Executing state.

The state diagram in Figure 5 illustrates the Context state transitions. Each of the eight Contexts will be in one of these states. At most one Context can be in Executing state at a time; any number of Contexts can be in any of the other states.

Figure 5. Context State Transition Diagram

Reset Inactive

CTX_ENABLE bit is cleared

Sleep

CTX_ENABLE bit is set by Intel XScale® Core

CTX_ENABLE bit is cleared

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

e

 

 

 

 

 

 

 

 

 

 

 

 

 

 

iv

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rr

 

 

 

 

 

 

 

 

 

 

 

 

 

 

l

a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ig

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

e

 

 

 

 

 

 

 

 

 

 

 

 

 

 

v

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

l

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

r

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

e

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Context executes CTX Arbitration instruction

Ready

Executing Context goes to Sleep state, and this Context is the highest round-robin priority.

Executing

Note:

After reset, the Intel XScale® Core processor must load the starting address of the CTX_PC, load the CTX_WAKEUP_EVENTS to 0x1 (voluntary), and then set the appropriate CTX_ENABLE bits to begin executing Context(s).

A9352-03

The Microengine is in Idle state whenever no Context is running (all Contexts are in either Inactive or Sleep states). This state is entered:

1.After reset (CTX_ENABLE Local CSR is clear, putting all Contexts into Inactive states).

2.When a context swap is executed, but no context is ready to wake up.

3.When a ctx_arb[bpt] instruction is executed by the Microengine (this is a special case of condition 2 above, since the ctx_arb[bpt] clears CTX_ENABLE, putting all Contexts into Inactive states).

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The Microengine provides the following functionality during the Idle state:

1.The Microengine continuously checks if a Context is in Ready state. If so, a new Context begins to execute. If no Context is Ready, the Microengine remains in the Idle state.

2.Only the ALU instructions are supported. They are used for debug via special hardware defined in number 3 below.

3.A write to the USTORE_ADDR Local CSR with the USTORE_ADDR[ECS] bit set, causing the Microengine to repeatedly execute the instruction pointed by the address specified in the USTORE_ADDR CSR. Only the ALU instructions are supported in this mode. Also, the result of the execution is written to the ALU_OUT Local CSR rather than a destination register.

4.A write to the USTORE_ADDR Local CSR with the USTORE_ADDR[ECS] bit set, followed by a write to the USTORE_DATA Local CSR loads an instruction into the Control Store. After the Control Store is loaded, execution proceeds as described in number 3 above.

2.3.4Datapath Registers

As shown in the block diagram in Figure 4, each Microengine contains four types of 32-bit datapath registers:

1.256 General Purpose registers

2.512 Transfer registers

3.128 Next Neighbor registers

4.640 32-bit words of Local Memory

2.3.4.1General-Purpose Registers (GPRs)

GPRs are used for general programming purposes. They are read and written exclusively under program control. GPRs, when used as a source in an instruction, supply operands to the execution datapath. When used as a destination in an instruction, they are written with the result of the execution datapath. The specific GPRs selected are encoded in the instruction.

The GPRs are physically and logically contained in two banks, GPR A, and GPR B, defined in Table 5.

2.3.4.2Transfer Registers

Transfer (abbreviated as Xfer) registers are used for transferring data to and from the Microengine and locations external to the Microengine, (for example DRAMs, SRAMs etc.). There are four types of transfer registers.

S_TRANSFER_IN

S_TRANSFER_OUT

D_TRANSFER_IN

D_TRANSFER_OUT

TRANSFER_IN registers, when used as a source in an instruction, supply operands to the execution datapath. The specific register selected is either encoded in the instruction, or selected indirectly via T_INDEX. TRANSFER_IN registers are written by external units (A typical case is when the external unit returns data in response to read instructions. However, there are other

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methods to write TRANSFER_IN registers, for example a read instruction executed by one Microengine may cause the data to be returned to a different Microengine. Details are covered in the instruction set descriptions).

TRANSFER_OUT registers, when used as a destination in an instruction, are written with the result from the execution datapath. The specific register selected is encoded in the instruction, or selected indirectly via T_INDEX. TRANSFER_OUT registers supply data to external units

(for example, write data for an SRAM write).

The S_TRANSFER_IN and S_TRANSFER_OUT registers connect to the S_PUSH and S_PULL buses, respectively.

The D_TRANSFER_IN and D_TRANSFER_OUT Transfer registers connect to the D_PUSH and D_PULL buses, respectively.

Typically, the external units access the Transfer registers in response to instructions executed by the Microengines. However, it is possible for an external unit to access a given Microengine’s Transfer registers either autonomously, or under control of a different Microengine, or the Intel XScale® core, etc. The Microengine interface signals controlling writing/reading of the TRANSFER_IN and TRANSFER_OUT registers are independent of the operation of the rest of the Microengine, therefore the data movement does not stall or impact other instruction processing

(it is the responsibility of software to synchronize usage of read data).

2.3.4.3Next Neighbor Registers

Next Neighbor registers, when used as a source in an instruction, supply operands to the execution datapath. They are written in two different ways:

1.By an adjacent Microengine (the “Previous Neighbor”).

2.By the same Microengine they are in, as controlled by CTX_ENABLE[NN_MODE].

The specific register is selected in one of two ways:

1.Context-relative, the register number is encoded in the instruction.

2.As a Ring, selected via NN_GET and NN_PUT CSR registers.

The usage is configured in CTX_ENABLE[NN_MODE].

When CTX_ENABLE[NN_MODE] is ‘0’ — when Next Neighbor is a destination in an instruction, the result is sent out of the Microengine, to the Next Neighbor Microengine.

When CTX_ENABLE[NN_MODE] is ‘1’ — when Next Neighbor is used as a destination in an instruction, the instruction result data is written to the selected Next Neighbor register in the same Microengine. Note that there is a 5-instruction latency until the newly written data may be read. The data is not sent out of the Microengine as it would be when CTX_ENABLE[NN_MODE] is ‘0’.

Table 4. Next Neighbor Write as a Function of CTX_ENABLE[NN_MODE]

 

 

Where the Write Goes

NN_MODE

 

 

 

External?

 

NN Register in this

 

 

 

 

Microengine?

 

 

 

 

 

 

 

0

Yes

 

No

 

 

 

 

1

No

 

Yes

 

 

 

 

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2.3.4.4Local Memory

Local Memory is addressable storage within the Microengine. Local Memory is read and written exclusively under program control. Local Memory supplies operands to the execution datapath as a source, and receives results as a destination. The specific Local Memory location selected is based on the value in one of the LM_ADDR registers, which are written by local_csr_wr instructions. There are two LM_ADDR registers per Context and a working copy of each. When a Context goes to the Sleep state, the value of the working copies is put into the Context’s copy of LM_ADDR. When the Context goes to the Executing state, the value in its copy of LM_ADDR are put into the working copies. The choice of LM_ADDR_0 or LM_ADDR_1 is selected in the instruction.

It is also possible to make use of both or one LM_ADDRs as global by setting CTX_ENABLE[LM_ADDR_0_GLOBAL] and/or CTX_ENABLE[LM_ADDR_1_GLOBAL]. When used globally, all Contexts use the working copy of LM_ADDR in place of their own Context specific one; the Context specific ones are unused. There is a three-instruction latency when writing a new value to the LM_ADDR, as shown in Example 1.

Example 1. Three-Cycle Latency when Writing a New Value to LM_ADDR

;some instruction to compute the address into gpr_m local_csr_wr[INDIRECT_LM_ADDR_0, gpr_m]; put gpr_m into lm_addr ;unrelated instruction 1

;unrelated instruction 2 ;unrelated instruction 3

alu[dest_reg, *l$index0, op, src_reg]

;dest_reg can be used as a source in next instruction

LM_ADDR can also be incremented or decremented in parallel with use as a source and/or destination (using the notation *l$index#++ and *l$index#--), as shown in Example 2, where three consecutive Local Memory locations are used in three consecutive instructions.

Example 2. Using LM_ADDR in Consecutive Instructions

alu[dest_reg1, src_reg1, op, *l$index0++] alu[dest_reg2, src_reg2, op, *l$index0++] alu[dest_reg3, src_reg3, op, *l$index0++]

Local Memory is written by selecting it as a destination. Example 3 shows copying a section of Local Memory to another section. Each instruction accesses the next sequential Local Memory location from the previous instruction.

Example 3. Copying One Section of Local Memory to Another Section

alu[*l$index1++, --, B, *l$index0++] alu[*l$index1++, --, B, *l$index0++] alu[*l$index1++, --, B, *l$index0++]

Example 4 shows loading and using both Local Memory addresses.

Example 4. Loading and Using Both Local Memory Addresses

local_csr_wr[INDIRECT_LM_ADDR_0, gpr_m] local_csr_wr[INDIRECT_LM_ADDR_1, gpr_n] ;unrelated instruction 1

;unrelated instruction 2

alu[dest_reg1, *l$index0, op, src_reg1] alu[dest_reg2, *l$index1, op, src_reg2]

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As shown in Example 1, there is a latency in loading LM_ADDR. Until the new value is loaded, the old value is still usable. Example 5 shows the maximum pipelined usage of LM_ADDR.

Example 5. Maximum Pipelined Usage of LM_ADDR

local_csr_wr[INDIRECT_LM_ADDR_0, gpr_m] local_csr_wr[INDIRECT_LM_ADDR_0, gpr_n] local_csr_wr[INDIRECT_LM_ADDR_0, gpr_o] local_csr_wr[INDIRECT_LM_ADDR_0, gpr_p]

alu[dest_reg1, *l$index0, op, src_reg1] ; uses address from gpr_m alu[dest_reg2, *l$index0, op, src_reg2] ; uses address from gpr_n alu[dest_reg3, *l$index0, op, src_reg3] ; uses address from gpr_o alu[dest_reg4, *l$index0, op, src_reg4] ; uses address from gpr_p

LM_ADDR can also be used as the base of a 16 32-bit word region of memory, with the instruction specifying the offset from that base, as shown in Example 6. The source and destination can use different offsets.

Example 6. LM_ADDR Used as Base of a 16 32-Bit Word Region of Local Memory

alu[*l$index0[3], *l$index0[4], +, 1]

Note: Local Memory has 640 32-bit words. The local memory pointers (LM_ADDR) have an addressing range of up to 1K longwords. However, only 640 longwords are currently populated with RAM. Therefore:

0 – 639 (0x0 – 0x27F) are addressable as local memory.

640 – 1023 (0x280 – 0x3FF) are addressable, but not populated with RAM.

To the programmer, all instructions using Local Memory act as follows, including read/modify/write instructions like immed_w0, ld_field, etc.

1.Read LM_ADDR location (if LM_ADDR is specified as source).

2.Execute logic function.

3.Write LM_ADDR location (if LM_ADDR is specified as destination).

4.If specified, increment or decrement LM_ADDR.

5.Proceed to next instruction.

Example 7 is legal because lm_addr_0[2] does not post-modify LM_ADDR.

Example 7. LM_ADDR Use as Source and Destination

alu[*l$index0[2], --, ~B, *l$index0]

In Example 7, the programmer sees:

1.Read Local Memory memory location pointed to by LM_ADDR.

2.Invert the data.

3.Write the data into the address pointed to by LM_ADDR with the value of 2 that is OR’ed into the lower bits.

4.Increment LM_ADDR.

5.Proceed to next instruction.

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In Example 8, the second instruction will access the Local Memory location one past the source/ destination of the first.

Example 8. LM_ADDR Post-Increment

alu[*l$index0++, --, ~B, gpr_n]

alu[gpr_m, --, ~B, *l$index0]

2.3.5Addressing Modes

GPRs can be accessed in either a context-relative or an absolute addressing mode. Some instructions can specify either mode; other instructions can specify only Context-Relative mode.

Transfer and Next Neighbor registers can be accessed in Context-Relative and Indexed modes, and Local Memory is accessed in Indexed mode. The addressing mode in use is encoded directly into each instruction, for each source and destination specifier.

2.3.5.1Context-Relative Addressing Mode

The GPRs are logically subdivided into equal regions such that each Context has relative access to one of the regions. The number of regions is configured in the CTX_ENABLE CSR, and can be either 4 or 8. Thus a Context-Relative register number is actually associated with multiple different physical registers. The actual register to be accessed is determined by the Context making the access request (the Context number is concatenated with the register number specified in the instruction). Context-Relative addressing is a powerful feature that enables eight (or four) different contexts to share the same code image, yet maintain separate data.

Table 5 shows how the Context number is used in selecting the register number in relative mode. The register number in Table 5 is the Absolute GPR address, or Transfer or Next Neighbor Index number to use to access the specific Context-Relative register. For example, with eight active Contexts, Context-Relative Register 0 for Context 2 is Absolute Register Number 32.

Table 5. Registers Used By Contexts in Context-Relative Addressing Mode

Number of

Active

 

 

GPR

S_Transfer or

 

Absolute Register Numbers

D_Transfer

Active

Context

Neighbor

 

 

 

 

Index Number

Contexts

Number

 

 

 

 

Index Number

A Port

 

B Port

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0 – 15

 

0 – 15

0 – 15

0 – 15

 

 

 

 

 

 

 

 

 

1

16

– 31

 

16 – 31

16 – 31

16 – 31

 

 

 

 

 

 

 

 

8

2

32

– 47

 

32 – 47

32 – 47

32 – 47

 

 

 

 

 

 

 

(Instruction

3

48

– 63

 

48 – 63

48 – 63

48 – 63

always specifies

 

 

 

 

 

 

 

4

64

– 79

 

64 – 79

64 – 79

64 – 79

registers in

 

range 0 – 15)

5

80

– 95

 

80 – 95

80 – 95

80 – 95

 

 

 

 

 

 

 

 

 

 

6

96 – 111

 

96 – 111

96 – 111

96 – 111

 

 

 

 

 

 

 

 

7

112 – 127

 

112 – 127

112 – 127

112 – 127

 

 

 

 

 

 

 

4

0

0 – 31

 

0 – 31

0 – 31

0 – 31

 

 

 

 

 

 

 

(Instruction

2

32

– 63

 

32 – 63

32 – 63

32 – 63

always specifies

 

 

 

 

 

 

 

4

64

– 95

 

64 – 95

64 – 95

64 – 95

registers in

 

range 0 – 31)

6

96 – 127

 

96 – 127

96 – 127

96 – 127

 

 

 

 

 

 

 

 

 

 

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2.3.5.2Absolute Addressing Mode

With Absolute addressing, any GPR can be read or written by any of the eight Contexts in a Microengine. Absolute addressing enables register data to be shared among all of the Contexts, e.g., for global variables or for parameter passing. All 256 GPRs can be read by Absolute address.

2.3.5.3Indexed Addressing Mode

With Indexed addressing, any Transfer or Next Neighbor register can be read or written by any one of the eight Contexts in a Microengine. Indexed addressing enables register data to be shared among all of the Contexts. For indexed addressing the register number comes from the T_INDEX register for Transfer registers or NN_PUT and NN_GET registers (for Next Neighbor registers). Example 9 shows the Index Mode usage. Assume that the numbered bytes have been moved into the S_TRANSFER_IN registers as shown.

Example 9. Use of Indexed Addressing Mode

Transfer

 

 

Data

 

Register

 

 

 

 

 

Number

31:24

23:16

 

15:8

7:0

 

 

 

 

 

 

0

0x00

0x01

 

0x02

0x03

 

 

 

 

 

 

1

0x04

0x05

 

0x06

0x07

 

 

 

 

 

 

2

0x08

0x09

 

0x0a

0x0b

 

 

 

 

 

 

3

0x0c

0x0d

 

0x0e

0x0f

 

 

 

 

 

 

4

0x10

0x11

 

0x12

0x013

 

 

 

 

 

 

5

0x14

0x15

 

0x16

0x17

 

 

 

 

 

 

6

0x18

0x19

 

0x1a

0x1b

 

 

 

 

 

 

7

0x1c

0x1d

 

0x1e

0x1f

 

 

 

 

 

 

If the software wants to access a specific byte that is known at compile-time, it will normally use context-relative addressing. For example to access the word in transfer register 3:

alu[dest, --, B, $xfer3] ; move the data from s_transfer 3 to gpr dest

If the location of the data is found at run-time, indexed mode can be used, e.g., if the start of an encapsulated header depends on an outer header value (the outer header byte is in a fixed location).

;Check byte 2 of transfer 0

;If value==5 header starts on byte 0x9, else byte 0x14 br=byte[$0, 2, 0x5, L1#], defer_[1] local_csr_wr[t_index_byte_index, 0x09] local_csr_wr[t_index_byte_index, 0x14]

nop ; wait for index registers to be loaded L1#:

;Move bytes right justified into destination registers nop ; wait for index registers to be loaded

nop ;

byte_align_be[dest1, *$index++] byte_align_be[dest2, *$index++] ;etc.

;The t_index and byte_index registers are loaded by the same instruction.

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2.3.6Local CSRs

Local Control and Status registers (CSRs) are external to the Execution Datapath, and hold specific data. They can be read and written by special instructions (local_csr_rd and local_csr_wr) and are accessed less frequently than datapath registers.

Because Local CSRs are not built in the datapath, there is a write-to-use delay of three instructions, and a read-to-consume penalty of two instructions.

2.3.7Execution Datapath

The Execution Datapath can take one or two operands, perform an operation, and optionally write back a result. The sources and destinations can be GPRs, Transfer registers, Next Neighbor registers, and Local Memory. The operations are shifts, add/subtract, logicals, multiply, byte align, and find first one bit.

2.3.7.1Byte Align

The datapath provides a mechanism to move data from source register(s) to any destination register(s) with byte aligning. Byte aligning takes four consecutive bytes from two concatenated values (8 bytes), starting at any of four byte boundaries (0, 1, 2, 3), and based on the endian-type (which is defined in the instruction opcode), as shown in Example 5. The four bytes are taken from two concatenated values. Four bytes are always supplied from a temporary register that always holds the A or B operand from the previous cycle, and the other four bytes from the B or A operand of the Byte Align instruction.

The operation is described below, using the block diagram in Figure 6. The alignment is controlled by the two LSBs of the BYTE_INDEX Local CSR.

Table 6. Align Value and Shift Amount

 

Right Shift Amount (Number of Bits)

Align Value

 

(Decimal)

(in Byte_Index[1:0])

 

 

 

Little-Endian

 

Big-Endian

 

 

 

 

 

 

0

0

 

32

 

 

 

 

1

8

 

24

 

 

 

 

2

16

 

16

 

 

 

 

3

24

 

8

 

 

 

 

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Figure 6. Byte-Align Block Diagram

Prev_B

Prev_A

...

. . .

A_Operand

B_Operand

Shift

Byte_Index

Result

 

 

A9353-01

Example 10 shows a big-endian align sequence of instructions and the value of the various operands. Table 7 shows the data in the registers for this example. The value in BYTE_INDEX[1:0] CSR (which controls the shift amount) for this example is 2.

Table 7. Register Contents for Example 10

Register

Byte 3

Byte 2

Byte 1

Byte 0

[31:24]

[23:16]

[15:8]

[7:0]

 

 

 

 

 

 

0

0

1

2

3

 

 

 

 

 

1

4

5

6

7

 

 

 

 

 

2

8

9

A

B

 

 

 

 

 

3

C

D

E

F

 

 

 

 

 

Example 10. Big-Endian Align

Instruction

Prev B

A Operand

B Operand

Result

 

 

 

 

 

Byte_align_be[--, r0]

--

--

0123

--

 

 

 

 

 

Byte_align_be[dest1, r1]

0123

0123

4567

2345

 

 

 

 

 

 

Byte_align_be[dest2,

r2]

4567

4567

89AB

6789

 

 

 

 

 

 

Byte_align_be[dest3,

r3]

89AB

89AB

CDEF

ABCD

 

 

 

 

 

 

NOTE: A Operand comes from Prev_B register during byte_align_be instructions.

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Example 11 shows a little-endian sequence of instructions and the value of the various operands. Table 8 shows the data in the registers for this example. The value in BYTE_INDEX[1:0] CSR (which controls the shift amount) for this example is 2.

Table 8. Register Contents for Example 11

Register

Byte 3

Byte 2

Byte 1

Byte 0

[31:24]

[23:16]

[15:8]

[7:0]

 

 

 

 

 

 

0

3

2

1

0

 

 

 

 

 

1

7

6

5

4

 

 

 

 

 

2

B

A

9

8

 

 

 

 

 

3

F

E

D

C

 

 

 

 

 

Example 11. Little-Endian Align

Instruction

A Operand

B Operand

Prev A

Result

 

 

 

 

 

Byte_align_le[--, r0]

3210

--

--

--

 

 

 

 

 

Byte_align_le[dest1, r1]

7654

3210

3210

5432

 

 

 

 

 

 

Byte_align_le[dest2,

r2]

BA98

7654

7654

9876

 

 

 

 

 

 

Byte_align_le[dest3,

r3]

FEDC

BA98

BA98

DCBA

 

 

 

 

 

 

NOTE: B Operand comes from Prev_A register during byte_align_le instructions.

As the examples show, byte aligning “n” words takes “n+1” cycles due to the first instruction needed to start the operation.

Another mode of operation is to use the T_INDEX register with post-increment, to select the source registers. T_INDEX operation is described later in this chapter.

2.3.7.2CAM

The block diagram in Figure 7 is used to explain the CAM operation.

The CAM has 16 entries. Each entry stores a 32-bit value, which can be compared against a source operand by instruction:

CAM_Lookup[dest_reg, source_reg]

All entries are compared in parallel, and the result of the lookup is a 9-bit value that is written into the specified destination register in bits 11:3, with all other bits of the register 0 (the choice of bits 11:3 is explained below). The result can also optionally be written into either of the LM_Addr registers (see below in this section for details).

The 9-bit result consists of four State bits (dest_reg[11:8]), concatenated with a 1-bit Hit/Miss indication (dest_reg[7]), concatenated with 4-bit entry number (dest_reg[6:3]). All other bits of dest_reg are written with 0. Possible results of the lookup are:

miss (0) — lookup value is not in CAM, entry number is Least Recently Used entry (which can be used as a suggested entry to replace), and State bits are 0000.

hit (1) — lookup value is in CAM, entry number is entry that has matched; State bits are the value from the entry that has matched.

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Figure 7. CAM Block Diagram

Lookup Value

 

 

 

 

(from A port)

 

 

 

 

Tag

State

Match

 

 

 

 

 

Tag

State

Match

 

 

 

 

 

Tag

State

Match

Status

 

 

 

 

 

 

and

 

 

 

 

LRU

 

 

 

 

Logic

 

Tag

State

Match

 

 

 

 

 

 

 

 

Lookup Status

 

 

 

(to Dest Req)

 

 

State

Status

Entry Number

 

 

0000

Miss 0

LRU Entry

 

 

State

Hit 1

Hit Entry

 

 

 

 

A9354-01

Note: The State bits are data associated with the entry. The use is only by software. There is no implication of ownership of the entry by any Context. The State bits hardware function is:

the value is set by software (at the time the entry is loaded, or changed in an already loaded entry).

its value is read out on a lookup that hits, and used as part of the status written into the destination register.

its value can be read out separately (normally only used for diagnostic or debug).

The LRU (Least Recently Used) Logic maintains a time-ordered list of CAM entry usage. When an entry is loaded, or matches on a lookup, it is marked as MRU (Most Recently Used). Note that a lookup that misses does not modify the LRU list.

The CAM is loaded by instruction:

CAM_Write[entry_reg, source_reg, state_value]

The value in the register specified by source_reg is put into the Tag field of the entry specified by entry_reg. The value for the State bits of the entry is specified in the instruction as state_value.

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The value in the State bits for an entry can be written, without modifying the Tag, by instruction:

CAM_Write_State[entry_reg, state_value]

Note: CAM_Write_State does not modify the LRU list.

One possible way to use the result of a lookup is to dispatch to the proper code using instruction:

jump[register, label#],defer [3]

where the register holds the result of the lookup. The State bits can be used to differentiate cases where the data associated with the CAM entry is in flight, or is pending a change, etc. Because the lookup result was loaded into bits[11:3] of the destination register, the jump destinations are spaced eight instructions apart. This is a balance between giving enough space for many applications to complete their task without having to jump to another region, versus consuming too much Control Store. Another way to use the lookup result is to branch on just the hit miss bit, and use the entry number as a base pointer into a block of Local Memory.

When enabled, the CAM lookup result is loaded into Local_Addr as follows:

LM_Addr[5:0] = 0 ([1:0] are read-only bits)

LM_Addr[9:6] = lookup result [6:3] (entry number)

LM_Addr[11:10] = constant specified in instruction

This function is useful when the CAM is used as a cache, and each entry is associated with a block of data in Local Memory. Note that the latency from when CAM_Lookup executes until the LM_Addr is loaded is the same as when LM_Addr is written by a Local_CSR_Wr instruction.

The Tag and State bits for a given entry can be read by instructions:

CAM_Read_Tag[dest_reg, entry_reg]

CAM_Read_State[dest_reg, entry_reg]

The Tag value and State bits value for the specified entry is written into the destination register, respectively for the two instructions (the State bits are placed into bits [11:8] of dest_reg, with all other bits 0). Reading the tag is useful in the case where an entry needs to be evicted to make room for a new value—the lookup of the new value results in a miss, with the LRU entry number returned as a result of the miss. The CAM_Read_Tag instruction can then be used to find the value that was stored in that entry. An alternative would be to keep the tag value in a GPR. These two instructions can also be used by debug and diagnostic software. Neither of these modify the state of the LRU pointer.

Note: The following rules must be adhered to when using the CAM.

CAM is not reset by Microengine reset. Software must either do a CAM_clear prior to using the CAM to initialize the LRU and clear the tags to 0, or explicitly write all entries with

CAM_write.

No two tags can be written to have same value. If this rule is violated, the result of a lookup that matches that value will be unpredictable, and LRU state is unpredictable.

The value 0x00000000 can be used as a valid lookup value. However, note that CAM_clear instruction puts 0x00000000 into all tags. To avoid violating rule 2 after doing CAM_clear, it is necessary to write all entries to unique values prior to doing a lookup of 0x00000000.

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An algorithm for debug software to find out the contents of the CAM is shown in Example 12.

Example 12. Algorithm for Debug Software to Find out the Contents of the CAM

;First read each of the tag entries. Note that these reads

;don’t modify the LRU list or any other CAM state.

tag[0] = CAM_Read_Tag(entry_0);

......

tag[15] = CAM_Read_Tag(entry_15);

;Now read each of the state bits state[0] = CAM_Read_State(entry_0);

...

state[15] = CAM_Read_State(entry_15);

;Knowing what tags are in the CAM makes it possible to

;create a value that is not in any tag, and will therefore

;miss on a lookup.

;Next loop through a sequence of 16 lookups, each of which will

;miss, to obtain the LRU values of the CAM.

for (i = 0; i < 16; i++) BEGIN_LOOP

;Do a lookup with a tag not present in the CAM. On a

;miss, the LRU entry will be returned. Since this lookup

;missed the LRU state is not modified.

LRU[i] = CAM_Lookup(some_tag_not_in_cam);

;Now do a lookup using the tag of the LRU entry. This

;lookup will hit, which makes that entry MRU.

;This is necessary to allow the next lookup miss to

;see the next LRU entry.

junk = CAM_Lookup(tag[LRU[i]]); END_LOOP

;Because all entries were hit in the same order as they were

;LRU, the LRU list is now back to where it started before the

;loop executed.

;LRU[0] through LRU[15] holds the LRU list.

The CAM can be cleared with CAM_Clear instruction. This instruction writes 0x00000000 simultaneously to all entries tag, clears all the state bits, and puts the LRU into an initial state (where entry 0 is LRU, ..., entry 15 is MRU).

2.3.8CRC Unit

The CRC Unit operates in parallel with the Execution Datapath. It takes two operands, performs a CRC operation, and writes back a result. CRC-CCITT, CRC-32, CRC-10, CRC-5, and iSCSI polynomials are supported. One of the operands is the CRC_Remainder Local CSR, and the other is a GPR, Transfer_In register, Next Neighbor, or Local Memory, specified in the instruction and passed through the Execution Datapath to the CRC Unit.

The instruction specifies the CRC operation type, whether to swap bytes and or bits, and which bytes of the operand to include in the operation. The result of the CRC operation is written back into CRC_Remainder. The source operand can also be written into a destination register (however the byte/bit swapping and masking do not affect the destination register; they only affect the CRC computation). This allows moving data, for example, from S_TRANSFER_IN registers to S_TRANSFER_OUT registers at the same time as computing the CRC.

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2.3.9Event Signals

Event Signals are used to coordinate a program with completion of external events. For example, when a Microengine executes an instruction to an external unit to read data (which will be written into a Transfer_In register), the program must insure that it does not try to use the data until the external unit has written it. This time is not deterministic due to queuing delays and other uncertainty in the external units (for example, DRAM refresh). There is no hardware mechanism to flag that a register write is pending, and then prevent the program from using it. Instead the coordination is under software control, with hardware support.

In the instructions that use external units (i.e., SRAM, DRAM, etc.) there are fields that direct the external unit to supply an indication (called an Event Signal) that the command has been completed. There are 15 Event Signals per Context that can be used, and Local CSRs per Context to track which Event Signals are pending and which have been returned. The Event Signals can be used to move a Context from Sleep state to Ready state, or alternatively, the program can test and branch on the status of Event Signals.

Event Signals can be set in nine different ways.

1.When data is written into S_TRANSFER_IN registers

2.When data is written into D_TRANSFER_IN registers

3.When data is taken from S_TRANSFER_OUT registers

4.When data is taken from D_TRANSFER_OUT registers

5.By a write to INTERTHREAD_SIGNAL register

6.By a write from Previous Neighbor Microengine to NEXT_NEIGHBOR_SIGNAL

7.By a write from Next Neighbor Microengine to PREVIOUS_NEIGHBOR_SIGNAL

8.By a write to SAME_ME_SIGNAL Local CSR

9.By Internal Timer

Any or all Event Signals can be set by any of the above sources.

When a Context goes to the Sleep state (executes a ctx_arb instruction, or an instruction with ctx_swap token), it specifies which Event Signal(s) it requires to be put in Ready state.

The ctx_arb instruction also specifies if the logical AND or logical OR of the Event Signal(s) is needed to put the Context into Ready state.

When all of the Context’s Event Signals arrive, the Context goes to Ready state, and then eventually to Executing state. In the case where the Event Signal is linked to moving data into or out of Transfer registers (numbers 1 through 4 in the list above), the code can safely use the Transfer register as the first instruction (for example, using a Transfer_In register as a source operand will get the new read data). The same is true when the Event Signal is tested for branches (br_=signal or br_!signal instructions).

The ctx_arb instruction, CTX_SIG_EVENTS, and ACTIVE_CTX_WAKEUP_#_EVENTS Local CSR descriptions provide details.

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2.4DRAM

The IXP2800 Network Processor has controllers for three Rambus* DRAM (RDRAM) channels. Each of the controllers independently accesses its own RDRAMs, and can operate concurrently with the other controllers (i.e., they are not operating as a single, wider memory). DRAM provides high-density, high-bandwidth storage and is typically used for data buffers.

RDRAM sizes of 64, 128, 256, or 512 Mbytes, and 1 Gbyte are supported; however, each of the channels must have the same number, size, and speed of RDRAMs populated. Refer to Section 5.2 for supported size and loading configurations.

Up to two Gbytes of DRAM is supported. If less than two Gbytes of memory is present, the upper part of the address space is not used. It is also possible, for system cost and area savings, to have Channels 0 and 1 populated with Channel 2 empty, or Channel 0 populated with Channels 1and 2 empty.

Reads and writes to RDRAM are generated by Microengines, The Intel XScale® core, and PCI (external Bus Masters and DMA Channels). The controllers also do refresh and calibration cycles to the RDRAMs, transparently to software.

RDRAM Powerdown and Nap modes are not supported.

Hardware interleaving (also known as striping) of addresses is done to provide balanced access to all populated channels. The interleave size is 128 bytes. Interleaving helps to maintain utilization of available bandwidth by spreading consecutive accesses to multiple channels. The interleaving is done in the hardware in such a way that the three channels appear to software as a single contiguous memory space.

ECC (Error Correcting Code) is supported, but can be disabled. Enabling ECC requires that x18 RDRAMs be used. If ECC is disabled x16 RDRAMs can be used. ECC can detect and correct all single-bit errors, and detect all double-bit errors. When ECC is enabled, partial writes (writes of less than 8 bytes) must be done as read-modify-writes.

2.4.1Size Configuration

Each channel can be populated with anywhere from one-to-four RDRAMs (Short Channel Mode). Refer to Section 5.2 for supported size and loading configurations. The RAM technology used will determine the increment size and maximum memory per channel as shown in Table 9.

Table 9. RDRAM Sizes

RDRAM Technology1

Increment Size

Maximum per Channel

64/72 MB

8 MB

256 MB

 

 

 

128/144 MB

16 MB

512 MB

 

 

 

256/288 MB

32 MB

1 GB2

512/576 MB

64 MB

2 GB2

NOTES:

1. The two numbers shown for each technology indicate x16 parts and x18 parts.

2. The maximum memory that can be addressed across all channels is 2 GB. This limitation is based on the partitioning of the 4-GB address space (32-bit addresses). Therefore, if all three channels are used, each can be populated up to a maximum of 768 MB. Two channels can be populated to a maximum of

1 GB each. A single channel can be populated to a maximum of 2 GB.

RDRAMs with 1 x 16 or 2 x 16 dependent banks, and 4 independent banks are supported.

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