Intel IXP43X User Manual

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Intel® IXP43X Product Line of

Network Processors

Hardware Design Guidelines

April 2007

Document Number: 316844; Revision: 001US

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548- 4725, or by visiting Intel’s Web Site.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details.

BunnyPeople, Celeron, Celeron Inside, Centrino, Centrino logo, Core Inside, FlashFile, i960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Core, Intel Inside, Intel Inside logo, Intel. Leap ahead., Intel. Leap ahead. logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel Viiv, Intel vPro, Intel XScale, Itanium, Itanium Inside, MCS, MMX, Oplus, OverDrive, PDCharm, Pentium, Pentium Inside, skoool, Sound Mark, The Journey Inside, VTune, Xeon, and Xeon Inside are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others. Copyright © 2007, Intel Corporation. All rights reserved.

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Contents

1.0

Introduction

..............................................................................................................

9

 

1.1

Content Overview................................................................................................

9

 

1.2

Related ......................................................................................Documentation

10

 

1.3

Acronyms.........................................................................................................

10

 

1.4

Overview .........................................................................................................

11

 

1.5

Typical ...........................................................................................Applications

14

2.0

System Architecture ................................................................................................

15

 

2.1

System ..........................................................................Architecture Description

15

 

2.2

System .........................................................................................Memory Map

15

3.0 General Hardware ................................................................Design Considerations

17

 

3.1

Soft Fusible .........................................................................................Features

17

 

3.2

DDRII/I ...................................................................................SDRAM Interface

18

 

 

3.2.1 .....................................................................................

Signal Interface

19

 

 

3.2.2 ...................................................................

DDRII/I SDRAM Initialization

20

 

3.3

Expansion ..................................................................................................Bus

21

 

 

3.3.1 .....................................................................................

Signal Interface

21

 

 

3.3.2 ......................................................................

Reset Configuration Straps

22

 

 

3.3.3 .............................................................................

8 - Bit Device Interface

24

 

 

3.3.4 ...........................................................................

16 - Bit Device Interface

25

 

 

3.3.5 .......................................................................................

Flash Interface

26

 

3.4

UART Interface .................................................................................................

26

 

 

3.4.1 .....................................................................................

Signal Interface

27

 

3.5

MII Interface ....................................................................................................

28

 

 

3.5.1 ................................................................................

Signal Interface MII

29

 

 

3.5.2 ...........................................................................

Device Connection, MII

30

 

3.6

GPIO Interface..................................................................................................

31

 

 

3.6.1 .....................................................................................

Signal Interface

32

 

 

3.6.2 .........................................................................................

Design Notes

32

 

3.7

USB Interface ...................................................................................................

32

 

 

3.7.1 .....................................................................................

Signal Interface

33

 

3.8

UTOPIA ...................................................................................Level 2 Interface

36

 

 

3.8.1 .....................................................................................

Signal Interface

36

 

 

3.8.2 ..................................................................................

Device Connection

40

 

3.9

HSS Interface ...................................................................................................

40

 

 

3.9.1 .....................................................................................

Signal Interface

41

 

 

3.9.2 ..................................................................................

Device Connection

41

 

3.10

SSP Interface ...................................................................................................

42

 

 

3.10.1 .....................................................................................

Signal Interface

43

 

 

3.10.2 ..................................................................................

Device Connection

43

 

3.11

PCI Interface ....................................................................................................

44

 

 

3.11.1 .....................................................................................

Signal Interface

45

 

 

3.11.2 ....................................................................

PCI Interface Block Diagram

46

 

 

3.11.3 ...............................................................................

PCI Option Interface

47

 

 

3.11.4 .........................................................................................

Design Notes

49

 

3.12

JTAG Interface ..................................................................................................

49

 

 

3.12.1 .....................................................................................

Signal Interface

50

 

3.13

Input System ...........................................................................................Clock

50

 

 

3.13.1 .........................................................................................

Clock Signals

50

 

 

3.13.2 ......................................................................................

Clock Oscillator

50

 

 

3.13.3 .....................................................

Recommendations for Crystal Selection

51

 

 

 

 

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3.14

Power

..............................................................................................................

 

52

 

 

3.14.1 .................................................

Decoupling Capacitance Recommendations

53

 

 

3.14.2 ......................................................................................

VCC Decoupling

53

 

 

3.14.3 ..................................................................................

VCC33 Decoupling

53

 

 

3.14.4 ................................................................................

VCCDDR Decoupling

53

 

 

3.14.5 .....................................................................................

Power Sequence

53

 

 

3.14.6 ..........................................................................................

Reset Timing

53

4.0

General PCB ...................................................................................................Guide

 

55

 

4.1

PCB Overview ...................................................................................................

 

55

 

4.2

General ..................................................................................Recommendations

55

 

4.3

Component .........................................................................................Selection

55

 

4.4

Component ........................................................................................Placement

55

 

4.5

Stack- .............................................................................................Up Selection

56

5.0 General Layout ...........................................................................and Routing Guide

59

 

5.1

Overview ..........................................................................................................

 

59

 

5.2

General ...................................................................................Layout Guidelines

59

 

 

5.2.1 ....................................................................

General Component Spacing

60

 

 

5.2.2 ......................................................................

Clock Signal Considerations

62

 

 

5.2.3 ........................................................................

MII Signal Considerations

63

 

 

5.2.4 .........................................................................

USB V2.0 Considerations

63

 

 

5.2.5 ...............................................................................................

Crosstalk

 

63

 

 

5.2.6 .......................................................................

EMI Design Considerations

64

 

 

5.2.7 ....................................................................................

Trace Impedance

64

 

 

5.2.8 ..........................................................................

Power and Ground Plane

64

6.0 PCI Interface ........................................................................Design Considerations

66

 

6.1

Electrical .............................................................................................Interface

66

 

6.2

Topology ..........................................................................................................

 

66

 

6.3

Clock Distribution ..............................................................................................

 

67

 

 

6.3.1 .................................................................................

Trace Length Limits

68

 

 

6.3.2 ..................................................................................

Routing Guidelines

69

 

 

6.3.3 ........................................................................................

Signal Loading

69

7.0 DDRII / DDRI ..............................................................................................SDRAM

70

 

7.1

Introduction......................................................................................................

 

70

 

7.2

DDRII/DDRI ...................................RCOMP and Slew Resistances Pin Requirements

74

 

7.3

DDRII ..............................................................................OCD Pin Requirements

75

 

 

7.3.1 ............................................................................

Signal - Timing Analysis

75

 

 

7.3.2 ...............................................................................

Timing Relationships

78

 

 

7.3.3 ..................................................................................

Routing Guidelines

81

 

 

..............................................................................

7.3.3.1

Clock Group

81

 

 

............................................................

7.3.3.2 Data and Control Groups

82

 

 

.....................................................................

7.3.3.3

Command Groups

84

Figures

 

 

 

 

1 Intel® IXP435 ..........................................................Network Processor Block Diagram

13

2 Example: Intel ..........® IXP43X Product Line of Network Processors System Block Diagram

16

3

8/16-Bit Device ..........................................................................................Interface

25

4

Flash Interface ............................................................................................Example

26

5

UART Interface ............................................................................................Example

28

6

MII Interface ...............................................................................................Example

 

31

7

Common Mode ...............................................................................................Choke

 

34

8 USB RCOMP .....................................................................and ICOMP Pin Requirement

35

9 USB Host Down ...................................................................Stream Interface Example

35

10

UTOPIA Interface .........................................................................................Example

40

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11

HSS Interface Example .............................................................................................

42

12

Serial Flash and SSP Port (SPI) Interface Example........................................................

44

13

PCI Interface...........................................................................................................

47

14

Clock Oscillator Interface Example..............................................................................

51

15

Recommended circuit design on PCB for crystal oscillator ..............................................

52

16

Component Placement on a PCB.................................................................................

56

17

8-Layer Stackup ......................................................................................................

58

18

6-Layer Stackup ......................................................................................................

58

19

Signal Changing Reference Planes ..............................................................................

60

20

Good Design Practice for VIA Hole Placement...............................................................

61

21

Poor Design Practice for VIA Placement.......................................................................

61

22

Pad-to-Pad Clearance of Passive Components to a PGA or BGA.......................................

62

23

PCI Address/Data Topology .......................................................................................

67

24

PCI Clock Topology ..................................................................................................

68

25

Processor-DDRII/I SDRAM Interface ...........................................................................

72

26

DDRII/DDRI RCOMP Pin External Resistor Requirements ...............................................

74

27

DDRII OCD Pin Requirements ....................................................................................

75

28

DDR Clock Timing Waveform .....................................................................................

75

29

DDR SDRAM Write Timings........................................................................................

76

30

DDR SDRAM Read Timings ........................................................................................

76

31

DDR - Write Preamble/Postamble Duration ..................................................................

77

32

DDRII Clock Simulation Results: CK Signals.................................................................

82

33

DDRII Data and Control Simulation Results: DQ and DQS signals ...................................

83

34

DDRII Command Simulation Results: ADDRESS signals.................................................

84

Tables

 

1

List of Acronyms and Abbreviations ............................................................................

10

2

Signal Type Definitions .............................................................................................

17

3

Soft Fusible Features ................................................................................................

17

4

DDRII/I SDRAM Interface Pin Description ....................................................................

19

5

Expansion Bus Signal Recommendations .....................................................................

21

6

Boot/Reset Strapping Configuration............................................................................

22

7

Setting Intel XScale® Processor Operation Speed .........................................................

24

8

UART Signal Recommendations..................................................................................

27

9

MII NPE A Signal Recommendations ...........................................................................

29

10

MII NPE C Signal Recommendations ...........................................................................

29

11

MAC Management Signal Recommendations NPE A and NPE C........................................

30

12

GPIO Signal Recommendations ..................................................................................

32

13

USB Host Signal Recommendations ............................................................................

33

14

UTOPIA Level 2/MII_A ..............................................................................................

36

15

High-Speed, Serial Interface 0 ...................................................................................

41

16

Synchronous Serial Peripheral Port Interface................................................................

43

17

PCI Controller..........................................................................................................

45

18

PCI Host/Option Interface Pin Description....................................................................

47

19

Synchronous Serial Peripheral Port Interface................................................................

50

20

Clock Signals...........................................................................................................

50

21

Power Supply ..........................................................................................................

52

22

PCI Address/Data Routing Guidelines..........................................................................

67

23

PCI Clock Routing Guidelines .....................................................................................

68

24

DDRII/I Signal Groups ..............................................................................................

71

25

Supported DDRI 32-bit SDRAM Configurations .............................................................

73

26

Supported DDRII 32-bit SDRAM Configurations ............................................................

73

27

Supported DDRI 16-bit SDRAM Configurations .............................................................

73

28

Supported DDRII 16-bit SDRAM Configurations ............................................................

74

 

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29

DDR Clock Timings ...................................................................................................

75

30

DDRII-400 MHz Interface -- Signal Timings..................................................................

77

31

DDR II/I SDRAM Interface -- Signal Timings.................................................................

78

32

Timing Relationships .................................................................................................

79

33

Signal Package Lengths.............................................................................................

79

34

Clock Signal Group Routing Guidelines ........................................................................

82

35

DDRII Data and Control Signal Group Routing Guidelines...............................................

83

36

DDRII Command Signal Group Routing Guidelines ........................................................

84

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Revision History

Date

Revision

Description

 

 

 

April 2007

001

Initial release

 

 

 

§ §

 

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Hardware Design Guidelines—Intel® IXP43X Product Line of Network Processors

1.0Introduction

This design guide provides recommendations for hardware and system designers who are developing with the Intel® IXP43X Product Line of Network Processors. This document should be used in conjunction with the Intel® IXP43X Product Line of Network Processors Datasheet and sample schematics provided for the Intel® IXP435 Multi-Service Residential Gateway Reference Platform.

Design recommendations are necessary to meet the timing and signal quality specifications. The guidelines recommended in this document are based on experience and simulation work done at Intel while developing the Intel® IXP435 Multi-Service Residential Gateway Reference Platform. These recommendations are subject to change.

Note: This document discusses all features supported on the IXP43X product line of network processors. A subset of these features is supported by certain processors in the IXP43X network processors, such as the Intel® IXP432 Network Processor. Refer to the Intel® IXP43X Product Line of Network Processors Datasheet for detailed information on various features listed by processor.

1.1Content Overview

Chapter Name

Description

 

 

Chapter 1.0, “Introduction”

Conventions used in this manual and related documentation

 

 

Chapter 2.0, “System Architecture”

System architectural block diagram and system memory map

 

 

Chapter 3.0, “General Hardware Design

Graphical representation of most common peripheral interfaces

Considerations”

 

 

 

Chapter 4.0, “General PCB Guide”

General PCB design practice and layer stack-up description

 

 

Chapter 5.0, “General Layout and Routing

More specific layout and routing recommendations for board

Guide”

designers

 

 

Chapter 6.0, “PCI Interface Design

Board-design recommendations when implementing PCI

Considerations”

interface

 

 

Chapter 7.0, “DDRII / DDRI SDRAM”

Board-design recommendations when implementing

DDRII/I memory interface

 

 

 

 

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1.2Related Documentation

The reader of this design guide should also be familiar with the material and concept presented in the following documents:

Title

Document #

 

 

Intel® IXP43X Product Line of Network Processors Datasheet

316842

Intel® IXP43X Product Line of Network Processors Developer’s

316843

Manual

 

 

 

Intel® IXP43X Product Line of Network Processors: Migrating from

316845

the Intel® IXP42X Product Line

Intel® IXP400 Software Programmer’s Guide

252539

Intel® IXP400 Software Specification Update

273795

Intel® XScale™ Core Developer’s Manual

273473

Intel StrataFlash® Embedded Memory (P30) Application Note

__

Intel XScale® Microarchitecture Technical Summary

Double Data Rate (DDR) SDRAM Specification, 2004; JEDEC Solid

JESD79D

State Technology Association

 

 

 

IEEE 802.3 Specification

N/A

 

 

PCI Local Bus Specification, Rev. 2.2

N/A

 

 

Universal Serial Bus Specification, Revision 2.0

N/A

 

 

UTOPIA Level 2 Specification, Revision 1.0

N/A

 

 

1.3Acronyms

 

Table 1 lists the acronyms and abbreviations used in this guide.

Table 1.

List of Acronyms and Abbreviations (Sheet 1 of 2)

 

 

 

 

Term

Explanation

 

 

 

 

AHB

Advanced High-Performance Bus

 

 

 

 

APB

Advanced Peripheral Bus

 

 

 

 

ATM

Asynchronous Transfer Mode

 

 

 

 

DDR

Double Data Rate

 

 

 

 

EMI

Electro-Magnetic Interference

 

 

 

 

GPIO

General Purpose Input/Output

 

 

 

 

HSS

High Speed Serial

 

 

 

 

IP

Internet Protocol

 

 

 

 

ISA

Instruction Set Architecture

 

 

 

 

LAN

Local Area Network

 

 

 

 

MII

Media-Independent Interface

 

 

 

 

NPE

Network Processor Engine

 

 

 

 

PCB

Printed Circuit Board

 

 

 

 

PCI

Peripheral Component Interface

 

 

 

 

PHY

Physical Layer Interface

 

 

 

 

PLL

Phase-Locked Loop

 

 

 

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Table 1.

List of Acronyms and Abbreviations (Sheet 2 of 2)

 

 

 

 

Term

Explanation

 

 

 

 

PMU

Performance Monitoring Unit

 

 

 

 

SME

Small-to-Medium Enterprise

 

 

 

 

SSP

Synchronous Serial Protocol

 

 

 

 

UART

Universal Asynchronous Receiver-Transmitter

 

 

 

 

USB

Universal Serial Bus

 

 

 

 

VTT

Termination Voltage Supply

 

 

 

1.4Overview

The Intel® IXP43X Product Line of Network Processors is a highly integrated device, capable of interfacing with most common industry standard peripherals, required for high-performance control applications.

Note: This document discusses all features supported on the IXP43X network processors. Refer to the Intel® IXP43X Product Line of Network Processors Datasheet for details on feature support listed by processor.

Some of the key features of the IXP43X network processors, when used as a single-chip solution for embedded applications are as follows:

Intel XScale® Processor (compliant with Intel® StrongARM* architecture) up to 667 MHz

32-bit PCI interface Master/Target 33 MHz

Two Universal Serial Bus (USB) V2.0 Host Controller

DDRI-266 SDRAM or DDRII-400 SDRAM—

Support for 16 MB, minimum for DDR II/I, 32 MB minimum for DDRII-400; 1 GB, maximum for DDR II/I, 512 MBs maximum for DDRII-400

User-enabled ECC.

16bit Data / 24bit Address Expansion Bus Interface

One UART interface

Two NPEs

UTOPIA Level 2 Interface

Synchronous Serial Port Interface (SSP)

One High-Speed Serial Port Interfaces (HSS)

Network interfaces that can be configured in the following manner: Note 1

Two MII interfaces

One MII interface + 1 UTOPIA Level 2 interface

MII interfaces are: Note 1

802.3 MII interfaces

Single MDIO interface to control the MII interfaces

UTOPIA Level 2 Interface is: Note 1

Eight-bit interface

Up to 33-MHz clock speed

Five transmit and five receive address lines

 

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16 GPIO (General Purpose Input Output)

Packaging

460-pin PBGA

31 mm by 31 mm

Commercial temperature (0° to 70° C)

Lead free support

Refer to the Intel® IXP43X Product Line of Network Processors Datasheet for complete feature list and block diagram description.

Note:

1.This feature requires Intel-supplied software. To determine if this feature is enabled in a particular software release, refer to the Intel® IXP400 Software Programmer’s Guide.

A block diagram of all major internal hardware components of IXP43X network processors is shown in Figure 1. The illustration also shows how the components interface with each other through the various bus interfaces such as the North AHB, South AHB, and APB.

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Figure 1. Intel® IXP435 Network Processor Block Diagram

 

 

HSS

 

 

 

 

 

 

 

 

 

 

UTOPIA 2/ MII

 

 

NPE A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII

 

NPE C

 

North AHB133. 32

MHz x32bits

 

 

 

ts

AES/ 3DES/

 

North AHB

 

 

 

 

 

 

 

DES/

us B us

 

 

 

 

 

x 32 bi

 

 

 

 

 

 

 

SHA/ MD-5

Arbiter

 

 

 

 

SSP

 

 

 

 

 

 

 

 

 

High Speed

66. 66MHz

 

 

 

Queue Stat

 

 

 

 

 

 

UART

 

 

 

 

 

 

 

 

 

921 Kbaud

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 GPIO

GPIO

APB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16/ 32 BITS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AHB

 

 

 

 

 

 

 

+ ECC

 

Interrupt

 

 

 

 

 

 

 

DDRII/ I MEMORY

DDR 266 /

 

 

Slave /

 

 

 

 

 

 

 

Controller

 

APB

 

 

QUEUE

AHB/ AHB

 

CONTROLLER

DDRII 400

 

 

 

 

 

 

 

 

 

Master

 

 

MANAGER

BRIDGE

 

UNIT

 

 

IBPMU

 

BRIDGE

 

 

 

 

 

 

266/ 400

 

 

 

 

 

 

 

 

 

 

M PI 13 3 . 3 2MHz /200 MH z x 6 4 bit s

 

 

 

 

 

 

South AHB133. 32

MHz x32 bits

 

 

 

Timers

 

 

 

 

 

South AHB

 

 

 

 

 

 

 

 

Arbiter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USB Port

 

USB Port

EXPANSION

PCI

 

 

 

 

 

 

HOST

 

HOST

 

 

 

 

 

 

CONTROLLER

CONTROLLER

BUS Controller

CONTROLLER

XScale Processor

 

 

 

 

VERSION2.0

 

VERSION 2.0

8/16 bit 80MHz

32 bit 33 MHz

 

 

 

 

 

 

 

 

UTMI

 

 

 

 

32 KB I - CACHE

 

 

 

 

UTMI

 

 

 

 

 

32 KB D - CACHE

 

 

 

 

2.0 PHY

 

2.0 PHY

 

 

 

 

2KB MINI D- CACHE

 

 

 

 

 

 

 

 

 

266/400/533/667 MHz

 

 

 

 

Master on South AHB

 

Bus Arbiters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Master on North AHB

 

Slave Only

 

 

 

 

 

 

 

 

 

 

 

AHB Slave/APB Master

 

Note: Figure 1 shows the Intel® IXP435 Network Processor. For details on feature and SKU support listed by processor, see the Intel® IXP43X Product Line of Network Processors Datasheet.

 

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1.5Typical Applications

SOHO-Small Business/Residential

Modular Router

Wireless Gateway(802.11a/b/g)

Network-Attached Storage

Wired/Wireless RFID Readers

Digital Media Adapter

Digital Media Player

VoIP Router

Video Phone

Secure Gateway/Router

Network Printer

Wireless Media Gateway

IP Set Top box

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Hardware Design Guidelines—Intel® IXP43X Product Line of Network Processors

2.0System Architecture

2.1System Architecture Description

The Intel® IXP43X Product Line of Network Processors is a multifunction processor that integrates the Intel XScale® Processor (ARM* architecture compliant) with highly integrated peripheral controllers and network processor engines.

The processor is a highly integrated design, manufactured with Intel’s 0.13-µm production semiconductor process technology. This process technology, along with numerous, dedicated function peripheral interfaces and many features with the Intel XScale processor, addresses the needs of many system applications and helps reduce system costs. The processors can be configured to meet many system application and implementation needs.

Figure 2 illustrates one of the many applications for which the IXP43X network processors can be implemented. For detailed functional description, see the Intel® IXP43X Product Line of Network Processors Developer’s Manual.

2.2System Memory Map

Refer to the Intel® IXP43X Product Line of Network Processors Developer’s Manual for a complete memory map and register description of each individual module.

 

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 2. Example: Intel® IXP43X Product Line of Network Processors System Block Diagram

 

 

 

 

JTAG

 

 

 

 

 

 

 

 

 

 

 

Header

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR

 

Flash

 

 

 

 

 

 

 

CB[7:0]

DDR

 

 

 

 

 

 

 

 

DDR

AM

 

 

 

 

 

 

 

 

 

 

S

 

32 Mbyte

 

Expansion Bus

 

 

 

 

 

SDRAM

 

 

 

 

 

 

 

SDRAM

 

 

 

 

 

Bus Memory

 

 

D[31:0]

16Mx4x16

 

 

 

CS_N0

 

 

 

DDRII/I

 

 

 

 

 

 

 

16Mx4x16

 

 

 

 

 

 

 

 

16Mx4x16

 

 

 

 

 

 

 

 

512 Mbyte

 

 

 

 

 

 

 

BA[1:0]

SDRAM

 

 

 

 

 

 

 

512 Mbyte

 

 

 

 

 

 

 

 

512 Mbyte

 

 

 

 

 

 

 

 

(Four Chips)

 

 

 

 

 

 

 

 

Max 1 Gbyte

 

 

 

D[15:0]

 

 

 

A[13:0]

(Four Chips)

 

 

 

 

 

 

(Four Chips)

 

 

 

 

 

RAS, CAS, WE, CS,CLK

 

 

 

Board

 

A[23:0]

 

SDRAMDDRII/I

 

 

 

 

 

Configuration

 

 

 

 

 

 

 

 

 

 

Reset Logic

 

 

 

 

 

 

 

 

 

 

 

 

 

Intel® IXP43X Product

SSP

 

SLIC/CODEC or

 

 

 

 

HSS 0

 

 

 

 

 

 

Line of Network

 

 

 

T1/E1/J1 Framer

 

 

 

 

 

 

 

 

 

 

 

LCD/LED

 

 

 

Processors

 

 

 

 

 

 

 

Diagnostics

Buff

 

 

 

 

 

SSP

 

CODEC or

 

Display

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A/D

 

 

 

 

 

 

 

 

 

 

 

 

RS 232

 

 

 

 

 

UTOPIA Level 2

xDSL

 

 

 

 

 

 

 

xDSL

 

DB9

 

 

 

 

 

 

 

 

xDSL

 

 

Serial Port 0

 

 

 

 

 

 

 

xDSL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Buffer

PLL

OSC

RJ45

10/100

 

 

 

 

 

Slots PCI

 

 

 

 

Port 0

2-MII

 

PCI Bus

 

 

Ethernet

PCI

 

 

PHYs

 

 

 

 

 

RJ45

Up to 2 Ports

 

 

 

 

Clocks

Clock

 

 

 

 

 

 

 

 

 

 

 

Port 1

 

 

 

 

 

 

 

5 V

 

 

 

 

USB Host

USB v2.0

 

 

 

 

 

 

 

 

 

 

 

 

3.3 V

 

 

 

 

Connector

 

 

 

 

 

 

Power Supply

 

 

USB Host

USB v2.0

 

 

 

 

2.5/1.8 V

 

 

Transparent PCI Bridge

 

 

 

 

 

Connector

 

 

 

1.3 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cPCI Bus

 

 

 

 

 

 

 

 

 

 

 

J2 cPCI

J1 cPCI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B4835-003

 

 

 

 

 

 

§ §

 

 

 

 

 

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3.0General Hardware Design Considerations

 

This chapter contains information for implementing and interfacing with major

 

hardware blocks of the Intel® IXP43X Product Line of Network Processors. Such blocks

 

include DDRII/I SDRAM, Flash, Ethernet PHYs, UART and other peripherals interfaces.

 

Signal definition tables list resistor recommendations for pull-ups and pull-downs.

 

Features disabled by a specific part number, do not require pull-ups or pull-downs.

 

Therefore, all pins can be left unconnected. Features enabled by a specific part number

 

and required to be Soft Fuse-disabled, only require pull-ups or pull-downs in the

 

clock-input signals. Other conditions can require pull-up or pull-down resistors for

 

configuration purposes at power on or reset. In the same way, open-drain outputs must

 

be pulled high.

Warning:

With the exception of USB_V5REF all other I/O pins of the IXP43X network processors

 

are not 5.0-V tolerant.

 

Table 2 gives the legend for interpreting the Type field used in the signal-definition

 

tables that are covered in this chapter.

Table 2.

Signal Type Definitions

 

 

 

 

 

Symbol

Description

 

 

 

 

 

 

I

Input pin only

 

 

 

 

 

 

O

Output pin only

 

 

 

 

 

 

I/O

Pin can be an input or output

 

 

 

 

 

 

OD

Open-drain pin

 

 

 

 

 

 

TRI

Tri-State pin

 

 

 

 

 

 

PWR

Power pin

 

 

 

 

 

 

GND

Ground pin

 

 

 

 

 

3.1Soft Fusible Features

Soft Fuse Enable/Disable is a method to enable or disable features in hardware, virtually disconnecting the hardware modules from the processor.

Some of the features offered in the IXP43X product line of network processors can be Soft Fuse Enabled/Disabled during boot. It is recommended that if a feature is not used in the design, the feature be soft disabled. This helps reduce power and maintain the part running at a cooler temperature. When Soft Fuse Disabled, a pull-up resistor must be connected to each clock input pins of the disabled feature interface. All other signals can be left unconnected.

Soft Fuse Enable/Disable can be done by writing to EXP_UNIT_FUSE_RESET register. For more information refer to the Intel® IXP43X Product Line of Network Processors Developer’s Manual and review the register description.

Table 3.

Soft Fusible Features (Sheet 1 of 2)

 

 

 

 

 

 

Name

Description

 

 

 

 

 

 

PCI

The complete bus must be enabled or disable.

 

 

 

 

 

 

HSS0

Can only be disable as a pair.

 

 

 

 

 

 

UTOPIA

while enabling UTOPIA, MACs on NPE A is disabled.

 

 

while enabling MACs on NPE A, UTOPIA is disabled.

 

 

 

 

 

 

 

 

 

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Table 3.

Soft Fusible Features (Sheet 2 of 2)

 

 

 

 

Name

Description

 

 

 

 

ETHERNET

Can enable MII MACs. Enable of MACs can be separately done per each NPE.

 

 

 

 

USB Host

Each USB can be Enable separately.

 

 

 

 

DDR ECC

ECC can be enabled or disabled separately from the rest of the DDR interface.

 

 

 

3.2 DDRII/I SDRAM Interface

The IXP43X network processors support unbuffered, DDRI-266 or DDRII-400 SDRAM technology, capable of addressing two memory banks (one bank per CS). Each bank can be configured to support 32/64/128/256/512-Mbyte for a total combined memory support of 1 Gbyte.

The IXP43X network processors integrate a high-performance, multi-ported Memory Controller Unit (MCU) to provide a direct interface with its local memory subsystem. The MCU supports:

DDR II/I or DDRII-400 SDRAM

128/256/512-Mbit, 1-Gbit DDRI SDRAM technology support

Supports 256/512-Mbit technologies for the DDRII-400

Only unbuffered DRAM support (No registered DRAM support)

Dedicated port for Intel XScale processor to the DDRII/DDRI SDRAM

Between 32 MBs and 1-GB of 32-bit DDRI SDRAM

Between 64MBs and 512 MBs of 32-bit DDRII SDRAM

16MB for 16-bit memory systems for DDRI SDRAM (non-ECC) supporting 128-Mbit technology only

32MB for 16-bit memory systems for DDRII SDRAM (non-ECC) supporting 256-Mbit technology only

Single-bit error correction, multi-bit detection support (ECC)

32-bit, 40-bit wide memory interfaces (non-ECC and ECC support), and 16-bit wide memory interfaces (non-ECC)

The DDRII/DDRI SDRAM interface provides a direct connection to a high-bandwidth and reliable memory subsystem. The DDRII/DDRI SDRAM interface is a 16 or 32-bit-wide data path.

The device supports non-ECC and ECC for error correction, which can be enable or disable by software as required. Banks have a bus width of 32 bits for non ECC or 40 bits for ECC enable (32-bit data + 8-bit ECC).

An 8-bit Error Correction Code (ECC) across each 32-bit word improves system reliability. It is important to note that ECC is also referred to as CB in many DIMM specifications. The pins on the IXP43X network processors are called DDR_CB[7:0]. ECC is only implemented in the 32-bit mode of operation, while the algorithm used to generate the 8-bit ECC is implemented over 64-bit.

The ECC circuitry is designed to operate always on a 64-bit data and when operating in 32-bit mode, the upper 32 bits are driven to zeros internally. To summarize the impact to the customer, the full 8 bits of ECC is stored and read from a memory array for the ECC logic to work. An 8-bit-wide memory is used when implementing ECC.

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The memory controller only corrects single bit ECC errors on read cycles. The ECC is stored into the DDRII/DDRI SDRAM array along with the data and is checked when the data is read. If the code is incorrect, the MCU corrects the data before reaching the initiator of the read. ECC error scrubbing is done with software. User-defined fault correction software is responsible for The value written back into the memory location contains the 32-bit word with the modified byte and the new ECC value.

Refer to the Intel® IXP43X Product Line of Network Processors Datasheet for a detailed list of features.

General DDRII/I SDRAM routing guidelines can be found in Section 7.3.3, “Routing Guidelines” on page 82. For more detailed information, see the PC266 and PC400 DDR SDRAM specification.

3.2.1Signal Interface

Table 4.

DDRII/I SDRAM Interface Pin Description (Sheet 1 of 2)

 

 

 

 

 

 

 

 

Type

 

VTT

 

Name

 

Device-Pin Connection

Terminatio

Description

 

Field

 

 

 

n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Connect a pair of differential clock

 

 

D_CK[2:0] /

 

O

signals to every device; When

 

DDRII/I SDRAM Clock Out — Provides the

 

using both banks, daisy chain

No

positive differential clocks to the external

DDR_CK[2:0]

 

 

 

devices with same data bit

 

SDRAM memory subsystem.

 

 

 

 

 

 

 

sequence.

 

 

 

 

 

 

 

 

D_CK_N[2:0] /

 

 

 

 

DDRII/I SDRAM Clock Out — Provides the

 

O

Same as above

No

negative differential clocks to the external

DDR_CK_N[2:0]

 

 

 

 

 

SDRAM memory subsystem.

 

 

 

 

 

 

 

 

 

 

 

D_CS_N[1:0] /

 

 

Use the same CS to control 32-bit

 

Chip Select — Must be asserted for all

 

O

Yes

transactions to the DDRII/I SDRAM device.

C_CS_N[1:0]

 

data + 8-bit ECC, per bank

 

 

 

One per bank.

 

 

 

 

 

 

 

 

 

 

 

D_RAS_N /

 

 

The RAS signal must be connected

 

Row Address Strobe — Indicates that the

 

O

to each device in a daisy chain

Yes

current address on D_MA[13:0] /

DDR_RAS_N

 

 

 

manner

 

DDR_MA[13:0] is the row.

 

 

 

 

 

 

 

 

 

 

D_CAS_N /

 

 

The CAS signal must be connected

 

Column Address Strobe — Indicates that the

 

O

to each device in a daisy chain

Yes

current address on D_MA[13:0] /

DDR_CAS_N

 

 

 

manner

 

DDR_MA[13:0] is the column.

 

 

 

 

 

 

 

 

 

 

 

 

 

The WE signal must be connected

 

Write Strobe — Defines whether or not the

D_WE_N / DDR_WE_N

O

to each device in a daisy chain

Yes

current operation by the DDRII/I SDRAM is to

 

 

 

manner

 

be a read or a write.

 

 

 

 

 

 

 

 

 

 

 

Data Bus Mask — Controls the DDRII/I SDRAM

 

 

 

Connect to each DM device pin.

 

data input buffers. Asserting D_WE_N/

 

 

 

 

DDR_WE_N causes the data on D_DQ[31:0]/

 

 

 

For the 8-bit devices connect one

 

DDR_DQ[31:0] and D_CB[7:0]/DDR_CB[7:0]

D_DM[4:0] /

 

 

DM signal per device.

 

to be written into the DDRII/I SDRAM devices.

 

O

For the 16-bit devices connect two

Yes

D_DM[4:0]/DDR_DM[4:0] controls this

DDR_DM[4:0]

 

 

 

DM signal per device (depending

 

operation on a per-byte basis. D_DM[3:0]/

 

 

 

 

 

 

 

on how many data bits are being

 

DDR_DM[3:0] are intended to correspond to

 

 

 

used).

 

each byte of a word of data. D/DM[4]/

 

 

 

 

 

DDR_DM[4] is intended to be utilized for the

 

 

 

 

 

ECC byte of data.

 

 

 

 

 

 

D_BA[1:0] /

 

 

The BA signals must be connected

 

DDRII/I SDRAM Bank Selects — Controls which

 

 

 

of the internal DDRII/I SDRAM banks to read

 

O

to each device in a daisy chain

Yes

DDR_BA[1:0]

 

or write. D_BA[1:0]/DDR_BA[1:0] are used for

 

 

manner.

 

 

 

 

 

all technology types supported.

 

 

 

 

 

 

 

 

 

 

 

D_MA[13:0] /

 

 

All address signals must be

 

Address bits 13 through 0 — Indicates the row

 

 

 

or column to access depending on the state of

 

O

connected to each device in a

Yes

DDR_MA[13:0]

 

D_RAS_N/DDR_RAS_N and D_CAS_N/

 

 

daisy chain manner.

 

 

 

 

 

DDR_CAS_N.

 

 

 

 

 

 

 

 

 

 

 

D_DQ[31:0] /

 

I/O

Must be connected in parallel to

Yes

Data Bus — 32-bit wide data bus.

DDR_DQ[31:0]

 

achieve a 32-bit bus width.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 4.

DDRII/I SDRAM Interface Pin Description (Sheet 2 of 2)

 

 

 

 

 

 

 

 

Type

 

VTT

 

Name

 

Device-Pin Connection

Terminatio

Description

 

Field

 

 

 

n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ECC Bus — Eight-bit error correction code

 

 

 

 

 

which accompanies the data on D_DQ[31:0]/

D_CB[7:0] /

 

I/O

Connect to ECC memory devices.

Yes

DDR_DQ[31:0].

DDR_CB[7:0]

 

When ECC is disabled and not being used in a

 

 

 

 

 

 

 

 

 

system design, these signals can be left un-

 

 

 

 

 

connected.

 

 

 

 

 

 

 

 

 

 

 

Data Strobes Differential — Strobes that

 

 

 

 

 

accompany the data to be read or written from

 

 

 

Connect DQS[3:0] to devices with

 

the DDRII/I SDRAM devices. Data is sampled

D_DQS[4:0] /

 

 

 

on the negative and positive edges of these

 

I/O

data signals and DQS[4] to

Yes

DDR_DQS[4:0]

 

strobes. D_DQS[3:0]/DDR_DQS[3:0] are

 

 

devices with ECC signals.

 

 

 

 

 

intended to correspond to each byte of a word

 

 

 

 

 

 

 

 

 

 

of data. D_DQS[4]/DDR_DQS[4] is intended to

 

 

 

 

 

be utilized for the ECC byte of data.

 

 

 

 

 

 

 

 

 

 

 

Clock enables — One clock after D_CKE[1:0]/

 

 

 

 

 

DDR_CKE[1:0] is de-asserted, data is latched

 

 

 

Use one CKE per bank, never mix

 

on D_DQ[31:0]/DDR_DQ[31:0] and

D_CKE[1:0] /

 

 

 

D_CB[7:0]/DDR_CB[7:0]. Burst counters

 

O

the CKE on the same bank. Use

Yes

 

within DDRII/I SDRAM device are not

DDR_CKE[1:0]

 

CKE[0] for bank0 and CKE[1] for

 

 

 

incremented. De-asserting this signal places

 

 

 

bank1

 

 

 

 

 

the DDRII/I SDRAM in self-refresh mode. For

 

 

 

 

 

 

 

 

 

 

normal operation, D_CKE[1:0]/DDR_CKE[1:0]

 

 

 

 

 

must be asserted.

 

 

 

 

 

 

D_ODT[1:0]

 

 

 

 

On Die Termination Control — Turns on DDR II

 

 

 

 

SDRAM termination during writes.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Compensation for DDR OCD (analog) DDRII

D_RES[2:1]

 

 

Refer to Figure 27

 

mode only. This function is not enable and

 

 

 

 

 

special connection is required.

 

 

 

 

 

 

 

 

 

 

 

Compensation Voltage Reference (analog) for

D_SLWCRES

 

 

Refer to Figure 27

 

DDR driver slew rate control connected

 

 

 

 

 

through a resistor to D_CRES0.

 

 

 

 

 

 

 

 

 

 

 

Compensation Voltage Reference (analog) for

D_IMPCRES

 

 

Refer to Figure 27

 

DDR driver impedance control connected

 

 

 

 

 

through a resistor to D_CRES0.

 

 

 

 

 

 

 

 

 

 

 

Analog VSS Ref Pin (analog) both D_SLWCRES

 

 

 

 

 

and D_IMPCRES signals connect to this pin

 

 

 

 

 

through a reference resistor. For DDRII/I

 

 

 

 

 

respectively:

D_CRES0

 

O

Tied off to a resistor

Tied off to a

- 285 / 387Ohm Resistor connected to

 

resistor

DDR_IMPCRES used for process and

 

 

 

 

 

 

 

 

 

temperature adjustments.

 

 

 

 

 

- 825 / 845Ohm Resistor connected to

 

 

 

 

 

DDR_SLWCRES used for process and

 

 

 

 

 

temperature adjustments.

 

 

 

 

 

 

 

 

 

 

 

DDRII/IDDRII/I SDRAM Voltage Reference — is

D_VREF / DDR_VREF

I

VCCDDR/2

VCCDDR/2

used to supply the reference voltage to the

differential inputs of the memory controller

 

 

 

 

 

pins.

 

 

 

 

 

 

3.2.2DDRII/I SDRAM Initialization

For instructions on DDRII/I SDRAM initialization, refer to DDR SDRAM Initialization subsection in the Memory Controller chapter of the Intel® IXP43X Product Line of Network Processors Developer’s Manual.

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3.3Expansion Bus

The Expansion Bus of the IXP43X network processors is specifically designed for compatibility with Intel-and Motorola* style microprocessor interfaces.

The expansion bus controller includes a 24-bit address bus and a 16-bit wide data path, running at a maximum speed of 80 MHz from an external clock oscillator. The bus can be configure to support the following target devices:

Intel multiplexed

Intel non-multiplexed

Intel StrataFlash®

Synchronous Intel StrataFlash® Memory

Motorola non multiplexed

Motorola multiplexed

The expansion bus controller also has an arbiter that supports up to four external devices that can master the expansion bus. External masters can be used to access external slave devices that reside on the expansion bus, including access to internal memory mapped regions within the IXP43X network processors.

All supported modes are seamless and no additional glue logic is required. Other cycle types can be supported by configuring the Timing and Control Register for Chip Select.

The expansion interface functions support 8-bit or 16-bit data operation and allows an address range of 512 bytes to 16 MBs, using 24 address lines for each of the four independent chip selects.

Access to the expansion-bus interface is completed in five phases. Each of the five phases can be lengthened or shortened by setting various configuration registers on a per-chip-select basis. This feature allows the IXP43X network processors to connect to a wide variety of peripheral devices with varying speeds.The expansion interface supports Intel or Motorola* microprocessor style bus cycles. The bus cycles can be configured to be multiplexed address/data cycles or separate address/data cycles for each of the four chip-selects.

The expansion interface is an asynchronous interface to externally connected chips. A clock is supplied to the IXP43X network processors expansion interface for the interface to operate. This clock can be driven from GPIO 15 or an external source. Devices on the expansion bus can be clocked by an external clock at a rate of up to 80 MHz. If GPIO 15 is used as the clock source, the Expansion Bus interface can only be clocked at a maximum of 33.33 MHz. GPIO 15’s maximum clock rate is 33.33 MHz.

3.3.1Signal Interface

Table 5.

Expansion Bus Signal Recommendations (Sheet 1 of 2)

 

 

 

 

 

 

 

Type

Pull

 

Name

 

Up

Recommendations

 

Field

 

 

Down

 

 

 

 

 

 

 

 

 

 

EX_CLK

 

I

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

EX_ALE

 

TRI O

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

 

 

 

 

Use 470Ω resistors for pull-downs; required for boot strapping for initial configuration of

 

 

 

 

Configuration Register 0. Pull-ups are not required as for when the system comes out of

EX_ADDR[23:0]

 

I/O

Yes

reset, all bits are initially set HIGH. For more details, see Table 6.

 

 

 

 

For additional details on address strapping, see the Intel® IXP43X Product Line of Network

 

 

 

 

Processors Developer’s Manual.

 

 

 

 

 

EX_WR_N

 

I/O

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

EX_RD_N

 

I/O

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

 

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April 2007

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Document Number: 316844; Revision: 001US

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 5.

Expansion Bus Signal Recommendations (Sheet 2 of 2)

 

 

 

 

 

Name

 

Type

Pull

 

 

Up

Recommendations

 

Field

 

 

Down

 

 

 

 

 

 

 

 

 

 

EX_CS_N[3:0]

 

I/O

Yes

Use series termination resistor, 10Ω to 33Ω at the source.

 

Use 10KΩ resistors pull-ups to ensure that the signal remains de-asserted.

 

 

 

 

 

 

 

 

 

EX_DATA[15:0]

 

I/O

No

Expansion-bus, bidirectional data.

 

 

 

 

 

EX_IOWAIT_N

 

I

Yes

Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

 

 

 

 

 

3.3.2Reset Configuration Straps

At power up or whenever RESET_IN_N is asserted, the Expansion-bus address outputs are switched to inputs and the state of the inputs are captured and stored in Configuration Register 0, bits 23 through 0. This occurs when PLL_LOCKED is deasserted.

The strapping of Expansion-bus address pins can be done by placing external pull-down resistors at the required address pin. It is not required to use external pull-up resistors, by default upon reset all bits on Configuration Register 0 are set High, unless an external pull down is used to set them Low. For example to register a bit low or high in the Configuration Register 0, do the following:

Place an external 470Ω pull-down resistor to register a bit LOW in the Configuration Register 0.

No external pull-up is required; upon reset, bits are set high by default.

The state of the boot-strapping resistor is registered on the first cycle after the synchronous de-assertion of the reset signal. These bits can be read or written as needed for desired configurations. It is recommended that only Bit 31, Memory Map, be changed from 1 to 0 after execution of boot code from external flash.

Refer to the Intel® IXP43X Product Line of Network Processors Developer’s Manual for a complete bit description of Configuration Register 0.

Table 6.

Boot/Reset Strapping Configuration (Sheet 1 of 2)

 

 

 

 

Name

 

Function

Description

 

 

 

 

 

 

Intel XScale®

Allow a slower Intel XScale® Processor clock speed to override device fuse settings.

EX_ADDR[23:21]

Processor

But cannot be used to over clock core speed. Refer to Table 7 for additional

 

 

Clock Set[2:0]

information.

 

 

 

EX_ADDR[20:17]

Customer

Customer-defined bits. (Might be used for board revision.)

 

 

 

EX_ADDR[16:12]

(Reserved)

(Reserved)

 

 

 

 

 

 

 

DDRI or DDRII mode selection:

 

 

 

0 - DDRII mode (400MHz)

EX_ADDR[11]

 

DDR_MODE

1 - DDRI mode (266MHz)

 

 

 

DDR_mode or DDR clock speed selection bit is read only and strapped in from exp

 

 

 

address bit 11 upon activation of reset_early_n and reset_cold_n.

 

 

 

 

Intel® IXP43X Product Line of Network Processors

 

HDG

April 2007

22

Document Number: 316844; Revision: 001US

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