The Intel® Desktop Board D975XBX2 may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current
characterized errata are documented in the Intel Desktop Board D975XBX2 Specification Update.
October 2006
Order Number: D73645-001
US
Revision History
Revision Revision History Date
-001 First release of the Intel® Desktop Board D975XBX2 Technical Product
Specification
This product specification applies to only the standard Intel® Desktop Board D975XBX2 with
BIOS identifier BX97520J.86A.
Changes to this specification will be published in the Intel Desktop Board D975XBX2.
Specification Update before being incorporated into a revision of this document.
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®
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desktop boards are evaluated as Information Technology Equipment (I.T.E.) for use in personal
October 2006
Preface
This Technical Product Specification (TPS) specifies the board layout, components,
connectors, power and environmental requirements, and the BIOS for the Intel
Desktop Board D975XBX2. It describes the standard product and available
manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the Intel Desktop
Board D975XBX2 and its components to the vendors, system integrators, and other
engineers and technicians who need this level of information. It is specifically not
intended for general audiences.
What This Document Contains
Chapter Description
1 A description of the hardware used on the Desktop Board D975XBX2
2 A map of the resources of the Desktop Board
3 The features supported by the BIOS Setup program
4 A description of the BIOS error messages, beep codes, and POST codes
5 Regulatory compliance and battery disposal information
®
Typographical Conventions
This section contains information about the conventions used in this specification. Not
all of these symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
#
NOTE
Notes call attention to important information.
INTEGRATOR’S NOTES
Integrator’s notes are used to call attention to information that may be useful to
system integrators.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
# Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX) When used in the description of a component, N indicates component type, xn are the
relative coordinates of its location on the Desktop Board D975XBX2, and X is the instance of
the particular part at that general location. For example, J5J1 is a connector, located at 5J.
It is the first connector in the 5J area.
GB Gigabyte (1,073,741,824 bytes)
GB/sec Gigabytes per second
Gbits/sec Gigabits per second
KB Kilobyte (1024 bytes)
Kbit Kilobit (1024 bits)
kbits/sec 1000 bits per second
MB Megabyte (1,048,576 bytes)
MB/sec Megabytes per second
Mbit Megabit (1,048,576 bits)
Mbits/sec Megabits per second
xxh An address or data value ending with a lowercase h indicates a hexadecimal value.
x.x V Volts. Voltages are DC unless otherwise specified.
* This symbol is used to indicate third-party brands and names that are the property of their
Table 1 summarizes the major features of the board.
Table 1. Feature Summary
Form Factor
Processor
Memory
Chipset
Audio Intel® High Definition Audio subsystem
Legacy I/O Control Legacy I/O controller for diskette drive, serial, parallel, and PS/2 ports
USB Support for USB 2.0 devices
Peripheral
Interfaces
BIOS
Instantly Available
PC Technology
LAN Support
ATX (12.00 inches by 9.60 inches [304.80 millimeters by 243.84 millimeters])
®
• Intel
Core™2 Extreme Processor in an LGA775 socket with a 1066 MHz
system bus
®
• Intel
Core™2 Duo Processor in an LGA775 socket with a 1066 MHz system
bus
®
• Intel
Pentium® Processor Extreme Edition in an LGA775 socket with a 1066
or 800 MHz system bus
®
• Intel
Pentium® 4 Processor Extreme Edition in an LGA775 socket with a
1066 MHz system bus
®
• Intel
Pentium® D Processor in an LGA775 socket with an 800 MHz system
bus
®
• Intel
Pentium® 4 Processor in an LGA775 socket with an 800 MHz system
• Support for DDR2 800, DDR2 667, and DDR2 533 MHz DIMMs
• Support for up to 8 GB of system memory
• Support for ECC and non-ECC memory
®
Intel
975X Chipset, consisting of:
®
• Intel
• Intel
82975X Memory Controller Hub (MCH)
®
82801GR I/O Controller Hub (ICH7-R) or
®
Intel
82801GH I/O Controller Hub (ICH7-DH)
• Eight USB ports
• One serial port
• One parallel port
• Four Serial ATA interfaces with RAID support
• One Parallel ATA IDE interface with UDMA 33, ATA-66/100 support
• One diskette drive interface
• PS/2* keyboard and mouse ports
®
• Intel
BIOS resident in the SPI Flash device
• Support for Advanced Configuration and Power Interface (ACPI), Plug and
Play, and SMBIOS
• Watchdog timer providing automatic recovery after two failed power-on
self-tests (POSTs)
• Support for PCI Local Bus Specification Revision 2.2
• Support for PCI Express* Revision 1.0a
• Suspend to RAM support
• Wake on PCI, RS-232, front panel, PS/2 devices, and USB ports
Gigabit (10/100/1000 Mbits/sec) LAN subsystem using the
®
82573E/82573L Gigabit Ethernet Controller
Intel
continued
12
Product Description
Table 1. Feature Summary (continued)
Expansion
Capabilities
Hardware Monitor
Subsystem
• Two PCI* Conventional bus add-in card connectors (SMBus routed to both PCI
Conventional bus add-in card connectors)
• One Primary PCI Express x16 (electrical x16 or x8) bus add-in card connector
• One Secondary PCI Express x16 (electrical x8) bus add-in card connector
• One PCI Express x16 (electrical x4) bus add-in card connector
• Hardware monitoring and fan control ASIC
• Voltage sense to detect out of range power supply voltages
• Thermal sense to detect out of range thermal values
• Three fan headers
• Three fan sense inputs used to monitor fan activity
• Fan speed control
• Support for Product Environmental Control Interface (PECI)
1.1.2 Manufacturing Options
Table 2 describes the manufacturing options. Not every manufacturing option is
available in all marketing channels. Please contact your Intel representative to
determine which manufacturing options are available to you.
Table 2. Manufacturing Options
AMT
ATAPI CD-ROM
Connector
Audio Subsystem Intel High Definition Audio subsystem in one of the following configurations:
Auxiliary PCI
Express Graphics
Power Connector
Discrete SATA
RAID Controller
IEEE-1394a
Interface
MCH Fan Header
Processor Core
Power Connector
SCSI Hard Drive
LED Header
Trusted Platform
Module (TPM)
BIOS support for Intel
A 1 x 4-pin ATAPI-style connector for connecting an internal ATAPI CD-ROM drive
to the audio mixer
• 8-channel (7.1) audio subsystem with five analog audio outputs and two S/PDIF
digital audio outputs (coaxial and optical) using the SigmaTel* 9274D audio
codec
• 6-channel (5.1) audio subsystem with three analog audio outputs using the
Sigmatel 9227 audio codec
Provides required additional power when using high power (75 W or greater) add-in
cards in either or both the Secondary PCI Express x16 (electrical x8) and the PCI
Express x16 (electrical x4) bus add-in card connectors
• Marvell* 88SE6145 SATA RAID controller
• Four SATA connectors (in addition to the four SATA connectors on the
ICH7-R/ICH7-DH SATA interface)
IEEE-1394a controller and two IEEE-1394a connectors: one back panel connector
and one front-panel header
A 3-pin header for powering a fan for the Intel
(MCH)
One of the following connectors for providing +12 V power to the processor voltage
regulator:
• 2 x 4-pin (requires a power supply with a dual-rail 2 x 4 power cable). Boards
equipped with the 2 x 4-pin processor core power connector will also include
heatsinks in the processor voltage regulator area.
• 2 x 2-pin
Allows add-in hard drive controllers (SCSI or other) to use the same LED as the
Available configurations for the board Section 1.2, page 17
1.1.3 Board Layout
Figure 1 shows the location of the major components.
Table 3 lists the components identified in Figure 1.
14
Figure 1. Desktop Board Components
Table 3. Components Shown in Figure 1
Item/callout
from
Figure 1 Description
A
B
C
D
E
F
G
H
I
J Auxiliary PCI Express Graphics Power Connector (optional)
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
AA
BB
CC
DD
EE
FF
GG
HH
II
JJ
Auxiliary rear fan header
PCI Conventional bus add-in card connector 2
PCI Express x16 (electrical x4) bus add-in card connector
PCI Conventional bus add-in card connector 1
Secondary PCI Express x16 (electrical x8) bus add-in card connector
Front panel audio header
®
Intel
82801G I/O Controller Hub (ICH7-R or ICH7-DH)
Primary PCI Express x16 (electrical x16 or x8) bus add-in card connector
Rear chassis fan header
Back panel connectors
ATAPI CD-ROM connector (optional)
Processor core power connector
Memory Controller Hub (MCH) fan header (optional)
LGA775 processor socket
Intel 82975X MCH
DIMM Channel A sockets [2]
Processor fan header
DIMM Channel B sockets [2]
Main power connector
Diskette drive connector
BIOS Setup configuration jumper block
Chassis intrusion header
Onboard power button
Battery
Parallel ATE IDE connector
Serial ATA connectors (ICH7-R/ICH7-DH RAID) [4]
Front chassis fan header
Auxiliary front panel power LED header
Front panel USB headers [2]
IEEE-1394a front panel header
Serial ATA RAID connectors (Discrete RAID) (optional) [3]
Serial ATA RAID connector compatible with external Serial ATA adapter (red)
SCSI Hard Drive Activity LED header (optional)
Front panel header
Speaker
•Remove the Primary PCI Express x16 (electrical x16 or x8) video card before
installing or upgrading memory to avoid interference with the memory retention
mechanism.
•To be fully compliant with all applicable DDR SDRAM memory specifications, the
board should be populated with DIMMs that support the Serial Presence Detect
(SPD) data structure. This allows the BIOS to read the SPD data and program the
chipset to accurately configure memory settings for optimum performance. If nonSPD memory is installed, the BIOS will attempt to correctly configure the memory
settings, but performance and reliability may be impacted or the DIMMs may not
function under the determined frequency.
Table 4 lists the supported DIMM configurations.
Table 4. Supported Memory Configurations
DIMM
Capacity
128 MB SS 256 Mbit 16 M x 16/empty 4 [5]
256 MB SS 256 Mbit 32 M x 8/empty 8 [9]
256 MB SS 512 Mbit 32 M x 16/empty 4 [5]
512 MB DS 256 Mbit 32 M x 8/32 M x 8 16 [18]
512 MB SS 512 Mbit 64 M x 8/empty 8 [9]
512 MB SS 1 Gbit 64 M x 16/empty 4 [5]
1024 MB DS 512 Mbit 64 M x 8/64 M x 8 16 [18]
1024 MB SS 1 Gbit 128 M x 8/empty 8 [9]
2048 MB DS 1 Gbit 128 M x 8/128 M x 8 16 [18]
Notes:
In the second column, “DS” refers to double-sided memory modules (containing two rows of SDRAM)
1.
and “SS” refers to single-sided memory modules (containing one row of SDRAM).
In the fifth column, the number in brackets specifies the number of SDRAM devices on an ECC DIMM.
2.
Configuration
(Note 1)
SDRAM
Density
SDRAM Organization
Front-side/Back-side
Number of SDRAM
Devices
(Note 2)
18
Product Description
INTEGRATOR’S NOTE
#
Refer to Section 2.1.1, on page 49 for additional information on available memory.
NOTE
Regardless of the DIMM type used, the memory frequency will either be equal to or
less than the processor system bus frequency. For example, if DDR2 800 memory
is used with a 533 MHz system bus frequency processor, the memory will operate at
533 MHz.
combination of DIMMs and processors.
Table 5. Memory Operating Frequencies
DIMM Type Processor System Bus Frequency Resulting Memory Frequency
The Intel 82975X MCH supports two types of memory organization:
•Dual channel (Interleaved) mode. This mode offers the highest throughput for
real world applications. Dual channel mode is enabled when the installed memory
capacities of both DIMM channels are equal. Technology and device width can vary
from one channel to the other but the installed memory capacity for each channel
must be equal. If different speed DIMMs are used between channels, the slowest
memory timing will be used.
•Single channel (Asymmetric) mode. This mode is equivalent to single channel
bandwidth operation for real world applications. This mode is used when only a
single DIMM is installed or the memory capacities are unequal. Technology and
device width can vary from one channel to the other. If different speed DIMMs are
used between channels, the slowest memory timing will be used.
Figure 3 illustrates the memory channel and DIMM configuration.
NOTE
The DIMM0 sockets of both channels are blue. The DIMM1 sockets of both channels
are black.
Figure 4 shows a dual channel configuration using two DIMMs. In this example, the
DIMM0 (blue) sockets of both channels are populated with identical DIMMs.
Figure 4. Dual Channel (Interleaved) Mode Configuration with Two DIMMs
Figure 5 shows a dual channel configuration using three DIMMs. In this example, the
combined capacity of the two DIMMs in Channel A equal the capacity of the single
DIMM in the DIMM0 (blue) socket of Channel B.
Figure 5. Dual Channel (Interleaved) Mode Configuration with Three DIMMs
Figure 6 shows a dual channel configuration using four DIMMs. In this example, the
combined capacity of the two DIMMs in Channel A equal the combined capacity of the
two DIMMs in Channel B. Also, the DIMMs are matched between DIMM0 and DIMM1 of
both channels.
Figure 6. Dual Channel (Interleaved) Mode Configuration with Four DIMMs
22
Product Description
1.4.1.2 Single Channel (Asymmetric) Mode Configurations
NOTE
Dual channel (Interleaved) mode configurations provide the highest memory
throughput.
Figure 7 shows a single channel configuration using one DIMM. In this example, only
the DIMM0 (blue) socket of Channel A is populated. Channel B is not populated.
Figure 7. Single Channel (Asymmetric) Mode Configuration with One DIMM
Figure 8 shows a single channel configuration using three DIMMs. In this example, the
combined capacity of the two DIMMs in Channel A does not equal the capacity of the
single DIMM in the DIMM0 (blue) socket of Channel B.
Figure 8. Single Channel (Asymmetric) Mode Configuration with Three DIMMs
The Intel 975X chipset consists of the following devices:
•Intel 82975X Memory Controller Hub (MCH) with Direct Media Interface (DMI)
interconnect
• One of the following:
⎯ Intel 82801GR I/O Controller Hub (ICH7-R) with DMI interconnect
⎯ Intel 82801GH I/O Controller Hub (ICH7-DH) with DMI interconnect
The MCH is a centralized controller for the system bus, the memory bus, the PCI
Express bus, and the DMI interconnect. The ICH7 is a centralized controller for the
board’s I/O paths. The BIOS code is stored in the Serial Peripheral Interface (SPI)
Flash device.
For information about Refer to
The Intel 975X chipset http://developer.intel.com/
Resources used by the chipset Chapter 2
1.5.1 USB
The board supports up to eight USB 2.0 ports, supports UHCI and EHCI, and uses
UHCI- and EHCI-compatible drivers.
The ICH7-R/ICH7-DH provides the USB controller for all ports. The port arrangement
is as follows:
•Four ports are implemented with dual stacked back panel connectors adjacent to
the audio connectors
•Four ports are routed to two separate front panel USB headers
NOTES
Computer systems that have an unshielded cable attached to a USB port may not meet
FCC Class B requirements, even if no device is attached to the cable. Use shielded
cable that meets the requirements for full-speed devices.
For information about Refer to
The location of the USB connectors on the back panel Figure 19, page 58
The location of the front panel USB headers Figure 20, page 59
24
Product Description
1.5.2 IDE Support
The board provides five IDE interface connectors:
• One parallel ATA IDE connector that supports two devices
• Four serial ATA IDE connectors that support one device per connector
1.5.2.1 Parallel ATE IDE Interface
The ICH7-R/ICH7-DH’s Parallel ATA IDE controller has one bus-mastering Parallel ATA
IDE interface. The Parallel ATA IDE interface supports the following modes:
• Programmed I/O (PIO): processor controls data transfer.
• 8237-style DMA: DMA offloads the processor, supporting transfer rates of up to
16 MB/sec.
•Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and
transfer rates of up to 33 MB/sec.
•ATA-66: DMA protocol on IDE bus supporting host and target throttling and
transfer rates of up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is
device driver compatible.
•ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH7-R/
ICH7-DH’s ATA-100 logic can achieve read transfer rates up to 100 MB/sec and
write transfer rates up to 88 MB/sec.
NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce
reflections, noise, and inductive coupling.
The Parallel ATA IDE interface also supports ATAPI devices (such as CD-ROM drives)
and ATA devices using the transfer modes.
The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector
(ECHS) translation modes. The drive reports the transfer rate and translation mode to
the BIOS.
For information about Refer to
The location of the Parallel ATA IDE connector Figure 20, page 59
1.5.2.2 Serial ATA Interfaces
The ICH7-R/ICH7-DH’s Serial ATA controller offers four independent Serial ATA ports
with a theoretical maximum transfer rate of 3 Gbits/sec per port. One device can be
installed on each port for a maximum of four Serial ATA devices. A point-to-point
interface is used for host to device connections, unlike Parallel ATA IDE which supports
a master/slave configuration and two devices per channel.
For compatibility, the underlying Serial ATA functionality is transparent to the
operating system. The Serial ATA controller can operate in both legacy and native
modes. In legacy mode, standard IDE I/O and IRQ resources are assigned (IRQ 14
and 15). In Native mode, standard PCI Conventional bus resource steering is used.
Native mode is the preferred mode for configurations using the Microsoft Windows* XP
and Microsoft Windows 2000 operating systems.
NOTE
Many Serial ATA drives use new low-voltage power connectors and require adaptors or
power supplies equipped with low-voltage power connectors.
For more information, see:
For information about Refer to
The location of the Serial ATA IDE connectors on the D975XBX2 board Figure 20, page 59
http://www.serialata.org/
1.5.2.3 Serial ATA RAID
The ICH7-R/ICH7-DH supports the following RAID (Redundant Array of Independent
Drives) levels:
• RAID 0 - data striping
• RAID 1 - data mirroring
• RAID 0+1 (or RAID 10) - data striping and mirroring
• RAID 5 - distributed parity
1.5.2.4 SCSI Hard Drive Activity LED Header (Optional)
The SCSI hard drive activity LED header is a 1 x 2-pin header that allows an add-in
hard drive controller to use the same LED as the onboard IDE controller. For proper
operation, this header should be wired to the LED output of the add-in hard drive
controller. The LED indicates when data is being read from, or written to, either the
add-in hard drive controller or the onboard IDE controller (Parallel ATA or Serial ATA).
For information about Refer to
The location of the SCSI hard drive activity LED header Figure 20, page 59
The signal names of the SCSI hard drive activity LED header Table 22, page 62
1.5.3 Real-Time Clock, CMOS SRAM, and Battery
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the
computer is not plugged into a wall socket, the battery has an estimated life of three
years. When the computer is plugged in, the standby current from the power supply
extends the life of the battery. The clock is accurate to ± 13 minutes/year at 25 ºC
with 3.3 VSB applied.
NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded
into CMOS RAM at power-on.
When the voltage drops below a certain level, the BIOS Setup program settings stored
in CMOS RAM (for example, the date and time) might not be accurate. Replace the
battery with an equivalent one.
26
Figure 1 on page 14 shows the location of the battery.
Product Description
1.6 Discrete Serial ATA Interface (Optional)
1.6.1 Serial ATA Controller
As a manufacturing option, the board provides a Marvell 88SE6145 Serial ATA (SATA)
controller and four connectors (that support one device per connector) for SATA
devices. These connectors are in addition to the four SATA connectors of the
ICH7-R/ICH7-DH SATA interface.
The Marvell 88SE6145 controller uses the PCI bus for data transfer with a theoretical
maximum transfer rate of 3 Gbits/sec per port. The discrete SATA interface supports
the following RAID levels:
• RAID 0
• RAID 1
NOTE
The Marvell 88SE6145 controller supports single drive non-RAID configurations as well
as RAID configurations.
For information about Refer to
The location of the discrete SATA RAID connectors Figure 20, page 59
1.6.2 External Serial ATA Support
The red Serial ATA connector can be used with a back panel adapter for an external
SATA drive.
port.
Figure 9 shows the location of the External Serial ATA-compatible SATA
Figure 9. Location of External Serial ATA-Compatible SATA Port
The board provides the following PCI Express connectors:
•One Primary PCI Express x16 (electrical x16 or x8) bus add-in card connector. The
x16 interface supports simultaneous (full duplex) transfers up to 8 GBytes/sec.
Single-ended (half duplex) transfers are supported at up to 4 GBytes/sec.
•One Secondary PCI Express x16 (electrical x8) bus add-in card connector: The
board provides a PCI Express add-in card connector in the form of a physical x16
connector with electrical routing of x8. This connector is an electrical equivalent of
a PCI Express x8 bus add-in card connector. This connector also supports x4 and
x1 PCI Express add-in cards.
•One PCI Express x16 (electrical x4) bus add-in card connector: The board provides
a PCI Express add-in card connector in the form of a physical x16 connector with
electrical routing of x4. This connector is an electrical equivalent of a PCI Express
x4 bus add-in card connector. This connector supports x4 and x1 PCI Express
add-in cards.
For optimum performance, observe the following recommendations for the PCI Express
add-in card connectors:
•If you are installing a single PCI Express Graphics card, install it in the Primary
PCI Express x16 (electrical x16 or x8) bus add-in card connector.
•If you are installing two PCI Express Graphics cards, install them in the Primary
PCI Express x16 (electrical x16 or x8) bus add-in card connector and the
Secondary PCI Express x16 (electrical x8) bus add-in card connector.
The PCI Express interfaces for the Primary and Secondary PCI Express x16 connectors
are routed through the MCH. The PCI Express interface for the PCI Express x16
(electrical x4) connector is routed through the ICH7-R/ICH7-DH. Therefore, the
Primary and Secondary PCI Express x16 connectors provide higher performance than
the PCI Express x16 (electrical x4) bus add-in card connector.
For information about Refer to
The locations of the specific PCI Express x16 add-in card connectors Figure 1, page 14
INTEGRATOR’S NOTE
#
Although the PCI Express specification allows x16 cards to auto-negotiate down from
x16 to x4 and x1 and may function properly, such configurations have not been
validated on this board. Please consult your add-in card vendor prior to attempting to
use a PCI Express x16 add-in card in this connector.
The PCI Express interface supports the PCI Conventional bus configuration mechanism
so that the underlying PCI Express architecture is compatible with PCI Conventional
compliant operating systems. Additional features of the PCI Express interface includes
the following:
• Support for the PCI Express enhanced configuration mechanism
• Automatic discovery, link training, and initialization
• Support for Active State Power Management (ASPM)
• SMBus 2.0 support
28
Product Description
• Wake# signal supporting wake events from ACPI S1, S3, S4, or S5
• Software compatible with the PCI Power Management Event (PME) mechanism
defined in the PCI Power Management Interface Specification, Rev. 1.1
1.8 IEEE-1394a Connectors (Optional)
The optional IEEE-1394 interface addresses interconnection of both computer
peripherals and consumer electronics with these features:
• IEEE-1394a operation
• Support for up to 63 peer-to-peer devices
• Operation ranging from 100 Mbits/sec to 400 Mbits/sec (depending on cable type)
• Connection over short and long distances
• Support for both asynchronous and isochronous data transfer
As a manufacturing option, the board includes two IEEE-1394a connectors as follows:
• One IEEE-1394a connector located on the back panel.
• One IEEE-1394a front-panel header located on the component side.
For information about Refer to
The location of the back panel IEEE-1394a connector Figure 18, page 57
The location of the front panel IEEE-1394a header Figure 20, page 59
The signal names of the front panel IEEE-1394a header Section 2.7.2.6, page 69
1.9 Legacy I/O Controller
The legacy I/O controller provides the following features:
• One serial port
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
•Serial IRQ interface compatible with serialized IRQ support for PCI Conventional
bus systems
• PS/2-style mouse and keyboard interfaces
• Interface for one 1.44 MB or 2.88 MB diskette drive
• Intelligent power management, including a programmable wake-up event interface
• PCI Conventional bus power management support
The BIOS Setup program provides configuration options for the legacy I/O controller.
1.9.1 Serial Port
The board has one serial port connector located on the back panel. The serial port
supports data transfers at rates of up to 115.2 kbits/sec with BIOS support.
For information about Refer to
The location of the serial port A connector Figure 19, page 58
The 25-pin D-Sub parallel port connector is located on the back panel. Use the BIOS
Setup program to set the parallel port mode.
For information about Refer to
The location of the parallel port connector Figure 19, page 58
1.9.3 Diskette Drive Controller
The legacy I/O controller supports one diskette drive. Use the BIOS Setup program to
configure the diskette drive interface.
For information about Refer to
The location of the diskette drive connector on the D975XBX2 board Figure 20, page 59
1.9.4 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel.
NOTE
The keyboard is supported in the bottom PS/2 connector and the mouse is supported
in the top PS/2 connector. Power to the computer should be turned off before a
keyboard or mouse is connected or disconnected.
For information about Refer to
The location of the keyboard and mouse connectors Figure 19, page 58
30
Product Description
1.10 Audio Subsystem
The board supports the Intel High Definition audio subsystem based on the
SigmaTel 9274D or the SigmaTel 9227 audio codec. The audio subsystem supports
the following features:
•Advanced jack sense for the back panel audio jacks that enables the audio codec to
recognize the device that is connected to an audio port. The back panel audio
jacks are capable of retasking according to user’s definition, or can be
automatically switched depending on the recognized device type.
• Stereo input and output for all back panel jacks
• Line out and Mic in functions for front panel audio jacks
• A signal-to-noise (S/N) ratio of 90 dB
1.10.1 Audio Subsystem Software
Audio software and drivers are available from Intel’s World Wide Web site.
For information about Refer to
Obtaining audio software and drivers Section 1.2, page 17
1.10.2 Audio Connectors
The board contains audio connectors and headers on both the back panel and the
component side of the board. The component-side audio connectors include the
following:
•Front panel audio (a 2 x 5-pin header that provides mic in and line out signals for
front panel audio connectors)
•ATAPI CD-ROM (an optional 1 x 4-pin ATAPI-style connector for connecting an
internal ATAPI CD-ROM drive to the audio mixer)
The functions of the back panel audio connectors are dependent on which subsystem is
present. The 8-channel (7.1) audio subsystem is described in Section
6-channel (5.1) audio subsystem is described in Section
For information about Refer to
The locations of the front panel audio header and the optional ATAPI
CD-ROM connector
The signal names of the front panel audio header Table 18, page 61
The signal names of the optional ATAPI CD-ROM connector Table 17, page 61
The back panel audio connectors Section 2.7.1, page 56
The LAN subsystem includes the Intel® 82573 Gigabit (10/100/1000 Mbits/sec)
Ethernet Controller and an RJ-45 LAN connector with integrated status LEDs.
1.11.1 Intel® 82573E/82573L Gigabit Ethernet
Controller
The Intel 82573E/82573L Gigabit Ethernet Controller supports the following features:
• PCI Express link
• 10/100/1000 IEEE 802.3 compliant
• Compliant to IEEE 802.3x flow control support
• Jumbo frame support
• TCP, IP, UDP checksum offload
• Transmit TCP segmentation
• Advanced packet filtering
• Full device driver compatibility
• PCI Express Power Management Support
The 82573E Gigabit Ethernet Controller supports Alert Standard Format (ASF) 2.0 and
Intel Active Management Technology (Intel AMT).
1.11.2 RJ-45 LAN Connector with Integrated LEDs
Two LEDs are built into the RJ-45 LAN connector (shown in Figure 12 below).
Link LED
(Green)
Figure 12. LAN Connector LED Locations
Table 6 describes the LED states when the board is powered up and the LAN
subsystem is operating.
Table 6. LAN Connector LED States
LED LED Color LED State Condition
Off LAN link is not established.
Link Green
Data Rate Green/Yellow
On LAN link is established.
Blinking LAN activity is occurring.
Off 10 Mbits/sec data rate is selected.
Green 100 Mbits/sec data rate is selected.
Yellow 1000 Mbits/sec data rate is selected.
Data Rate LED
(Green/Yellow)
OM18329
34
Product Description
1.11.3 Alert Standard Format (ASF) Support
The board provides the following ASF support for PCI Express x1 bus add-in LAN cards
and PCI Conventional bus add-in LAN cards:
• Monitoring of system firmware progress events, including:
⎯ BIOS present
⎯ Primary processor initialization
⎯ Memory initialization
⎯ Video initialization
⎯ PCI resource configuration
⎯ Hard-disk initialization
⎯ User authentication
⎯ Starting operating system boot process
• Monitoring of system firmware error events, including:
⎯ Memory missing
⎯ Memory failure
⎯ No video device
⎯ Keyboard failure
⎯ Hard-disk failure
⎯ No boot media
• Boot options to boot from different types of boot devices
• Reset, shutdown, power cycle, and power up options
• LAN Subsystem Software
LAN software and drivers are available from Intel’s World Wide Web site.
1.11.4 Intel® Active Management Technology (Optional)
Intel Active Management Technology (Intel AMT) offers IT organizations tamperresistant and persistent management capabilities. Specifically, Intel AMT is a
hardware-based solution that offers encrypted and persistent asset management and
remote diagnostics and/or recovery capabilities for networked platforms. With
Intel AMT, IT organizations can easily get accurate platform information, and can
perform remote updating, diagnostics, debugging and repair of a system, regardless of
the state of the operating system and the power state of the system. Intel AMT
enables IT organizations to discover, heal, and protect all of their computing assets,
regardless of system state in the manner described below.
• Discovering hardware and software computing assets:
⎯ Intel AMT stores hardware and software asset information in non-volatile
memory and allows IT to read the asset information anytime, even if the PC is
off
⎯ Users cannot remove or prevent IT organization access to the information
• Healing systems remotely, regardless of the operating system or system state:
⎯ Intel AMT provides out-of-band diagnostics and recovery capabilities for IT
organizations to remotely diagnose and repair PCs after software, operating
system, or hardware failures
⎯ Alerting and event logging help IT organizations detect and diagnose problems
quickly to reduce end-user downtime
• Protecting the enterprise against malicious software attacks:
⎯ Intel AMT helps IT organizations keep software versions and virus protection
consistent and up-to-date across the enterprise
⎯ Version information is stored in non-volatile memory for access anytime by
third party software to check and, if necessary, wake a system to perform offhours updates.
The key features of Intel AMT include:
•Secure Out of Band (OOB) system management that allows remote management of
PCs regardless of system power or operating system state:
⎯ SSL3.1/TLS encryption
⎯ HTTP authentication
⎯ TCP/IP
⎯ HTTP web GUI
⎯ XML/SOAP API
• Remote troubleshooting and recovery that can significantly reduce desk-side visits
and potentially increasing efficiency of IT technical staff:
⎯ System event log
⎯ IDE-R or PXE boot; Network drive or remote CD boot
⎯ Serial over LAN
⎯ OOB diagnostics
⎯ Remote control
⎯ Remote BIOS update
• Proactive alerting that decreases downtime and minimizes time to repair:
⎯ Programmable policies
⎯ Operating system lock-up alert
⎯ Boot failure alert
⎯ Hardware failure alerts
• Third party non-volatile storage that prevents users from removing critical
inventory, remote control, or virus protection agents:
⎯ Nonvolatile storage for agents
⎯ Tamper-resistant
• Remote hardware and software asset tracking that eliminates time-consuming
manual inventory tracking, which also reduces asset accounting costs:
⎯ E-Asset Tag
⎯ HW/SW inventory
For information about Refer to
Intel Active Management Technology http://www.intel.com/technology/manage/iamt/index.htm
36
Product Description
1.11.5 LAN Subsystem Software
LAN software and drivers are available from Intel’s World Wide Web site.
For information about Refer to
Obtaining LAN software and drivers Section 1.2, page 17
1.12 Hardware Management Subsystem
The hardware management features enable the board to be compatible with the Wired
for Management (WfM) specification. The board has several hardware management
features, including the following:
•Fan monitoring and control (through the hardware monitoring and fan control
ASIC)
• Thermal and voltage monitoring
• Chassis intrusion detection
• Support for Product Environmental Control Interface (PECI)
1.12.1 Hardware Monitoring and Fan Control ASIC
The features of the hardware monitoring and fan control ASIC include:
• Internal ambient temperature sensor
• Two remote thermal diode sensors for direct monitoring of processor temperature
and ambient temperature sensing
•Power supply monitoring of five voltages (+5 V, +12 V, +3.3 VSB, +1.5 V, and
+VCCP) to detect levels above or below acceptable values
•Thermally monitored closed-loop fan control, for all three fans, that can adjust the
fan speed or switch the fans on or off as needed
•SMBus interface
For information about Refer to
The location of the fan headers and sensors for thermal monitoring Figure 13, page 38
Figure 13 shows the location of the sensors and fan headers.
Item Description
A Thermal diode, located on processor die
B Ambient temperature sensor, internal to hardware monitoring and fan control ASIC
C Remote ambient temperature sensor
D Processor fan header
E Rear chassis fan header
F Front chassis fan header
G Auxiliary chassis fan header
Figure 13. Sensors and Fan Connectors
38
Product Description
1.12.3 Fan Monitoring
Fan monitoring can be implemented using Intel Desktop Utilities or third-party
software. The level of monitoring and control is dependent on the hardware
monitoring ASIC used with the Desktop Board.
For information about Refer to
The functions of the fan headers Section 1.13.2.2, page 43
1.12.4 Chassis Intrusion and Detection
The board supports a chassis security feature that detects if the chassis cover is
removed. The security feature uses a mechanical switch on the chassis that attaches
to the chassis intrusion header. When the chassis cover is removed, the mechanical
switch is in the closed position.
1.13 Power Management
Power management is implemented at several levels, including:
• Software support through Advanced Configuration and Power Interface (ACPI)
• Hardware support:
⎯ Power connector
⎯ Fan headers
⎯ LAN wake capabilities
⎯ Instantly Available PC technology
⎯ Resume on Ring
⎯ Wake from USB
⎯ Wake from PS/2 devices
⎯ Power Management Event signal (PME#) wake-up support
⎯ PCI Express WAKE# signal support
1.13.1 ACPI
ACPI gives the operating system direct control over the power management and Plug
and Play functions of a computer. The use of ACPI with this board requires an
operating system that provides full ACPI support. ACPI features include:
• Plug and Play (including bus and device enumeration)
• Power management control of individual devices, add-in boards (some add-in
boards may require an ACPI-aware driver), video displays, and hard disk drives
•Methods for achieving less than 15-watt system operation in the power-on/standby
sleeping state
• A Soft-off feature that enables the operating system to power-off the computer
• Support for multiple wake-up events (see
• Support for a front panel power and sleep mode switch
Table 7 lists the system states based on how long the power switch is pressed,
depending on how ACPI is configured with an ACPI-aware operating system.
Table 7. Effects of Pressing the Power Switch
If the system is in this
state…
Off
(ACPI G2/G5 – Soft off)
On
(ACPI G0 – working state)
On
(ACPI G0 – working state)
Sleep
(ACPI G1 – sleeping state)
Sleep
(ACPI G1 – sleeping state)
…and the power switch is
pressed for
Less than four seconds Power-on
Less than four seconds Soft-off/Standby
More than four seconds Fail safe power-off
Less than four seconds Wake-up
More than four seconds Power-off
…the system enters this state
(ACPI G0 – working state)
(ACPI G1 – sleeping state)
(ACPI G2/G5 – Soft off)
(ACPI G0 – working state)
(ACPI G2/G5 – Soft off)
1.13.1.1 System States and Power States
Under ACPI, the operating system directs all system and device power state
transitions. The operating system puts devices in and out of low-power states based
on user preferences and knowledge of how devices are being used by applications.
Devices that are not being used can be turned off. The operating system uses
information from applications and user settings to put the system as a whole into a
low-power state.
40
Product Description
Table 8 lists the power states supported by the board along with the associated system
power targets. See the ACPI specification for a complete description of the various
system and power states.
Table 8. Power States and Targeted System Power
Global States Sleeping States
G0 – working
state
G1 – sleeping
state
G1 – sleeping
state
G1 – sleeping
state
G2/S5 S5 – Soft off.
G3 –
mechanical off
AC power is
disconnected
from the
computer.
Notes:
Total system power is dependent on the system configuration, including add-in boards and peripherals
1.
powered by the system chassis’ power supply.
Dependent on the standby power consumption of wake-up devices used in the system.
2.
S0 – working C0 – working D0 – working
S1 – Processor
stopped
S3 – Suspend to
RAM. Context
saved to RAM.
S4 – Suspend to
disk. Context
saved to disk.
Context not saved.
Cold boot is
required.
No power to the
system.
Processor
States
C1 – stop
grant
No power D3 – no power
No power D3 – no power
No power D3 – no power
No power D3 – no power for
Device States
state.
D1, D2, D3 –
device
specification
specific.
except for
wake-up logic.
except for
wake-up logic.
except for
wake-up logic.
wake-up logic,
except when
provided by
battery or
external source.
Targeted System
Power
Full power > 30 W
5 W < power < 52.5 W
Power < 5 W
Power < 5 W
Power < 5 W
No power to the system.
Service can be performed
safely.
Table 9 lists the devices or specific events that can wake the computer from specific
states.
Table 9. Wake-up Devices and Events
These devices/events can wake up the computer… …from this state
LAN S1, S3, S4, S5
Modem (back panel Serial Port A) S1, S3
PME# signal S1, S3, S4, S5
Power switch S1, S3, S4, S5
PS/2 devices S1, S3
RTC alarm S1, S3, S4, S5
USB S1, S3
WAKE# S1, S3, S4, S5
Note: For LAN and PME# signal, S5 is disabled by default in the BIOS Setup program. Setting this option
to Power On will enable a wake-up event from LAN in the S5 state.
(Note)
(Note)
NOTE
The use of these wake-up events from an ACPI state requires an operating system that
provides full ACPI support. In addition, software, drivers, and peripherals must fully
support ACPI wake events.
1.13.2 Hardware Support
CAUTION
Ensure that the power supply provides adequate +5 V standby current if LAN wake
capabilities and Instantly Available PC technology features are used. Failure to do so
can damage the power supply. The total amount of standby current required depends
on the wake devices supported and manufacturing options.
The board provides several power management hardware features, including:
• Power connector
• Fan headers
• LAN wake capabilities
• Instantly Available PC technology
• Resume on Ring
• Wake from USB
• Wake from PS/2 keyboard
• PME# signal wake-up support
• WAKE# signal wake-up support
LAN wake capabilities and Instantly Available PC technology require power from the
+5 V standby line.
42
Product Description
Resume on Ring enables telephony devices to access the computer when it is in a
power-managed state. The method used depends on the type of telephony device
(external or internal).
NOTE
The use of Resume on Ring and Wake from USB technologies from an ACPI state
requires an operating system that provides full ACPI support.
1.13.2.1 Power Connector
When an ACPI-enabled system receives the appropriate command, the power supply
removes all non-standby voltages.
When resuming from an AC power failure, the computer returns to the power state it
was in before power was interrupted (on or off). The computer’s response can be set
using the Last Power State feature in the BIOS Setup program’s Boot menu.
For information about Refer to
The location of the main power connector Figure 20, page 59
The signal names of the main power connector Table 24, page 63
1.13.2.2 Fan Headers
The function/operation of the fan headers is as follows:
• The fans are on when the board is in the S0 or S1 state.
• The fans are off when the board is off or in the S3, S4, or S5 state.
• Each fan header is wired to a fan tachometer input of the hardware monitoring and
fan control ASIC
•All fan headers support closed-loop fan control that can adjust the fan speed or
switch the fan on or off as needed
•All fan headers have a +12 V DC connection
For information about Refer to
The location of the fan headers Figure 20, page 59
The location of the fan headers and sensors for thermal monitoring Figure 13, page 38
The signal names of the fan headers Section 2.7.1.1, page 57
For LAN wake capabilities, the +5 V standby line for the power supply must be capable
of providing adequate +5 V standby current. Failure to provide adequate standby
current when implementing LAN wake capabilities can damage the power supply.
LAN wake capabilities enable remote wake-up of the computer through a network. The
LAN network adapter monitors network traffic at the Media Independent Interface.
Upon detecting a Magic Packet* frame, the LAN subsystem asserts a wake-up signal
that powers up the computer. Depending on the LAN implementation, the board
supports LAN wake capabilities with ACPI in the following ways:
• The PCI Express WAKE# signal
• The PCI Conventional bus PME# signal for PCI 2.2 compliant LAN designs
• The onboard LAN subsystem
1.13.2.4 Instantly Available PC Technology
CAUTION
For Instantly Available PC technology, the +5 V standby line for the power supply must
be capable of providing adequate +5 V standby current. Failure to provide adequate
standby current when implementing Instantly Available PC technology can damage the
power supply.
Instantly Available PC technology enables the board to enter the ACPI S3 (Suspend-toRAM) sleep-state. While in the S3 sleep-state, the computer will appear to be off (the
power supply is off, and the front panel LED is amber if dual colored, or off if single
colored.) When signaled by a wake-up device or event, the system quickly returns to
its last known wake state.
wake the computer from the S3 state.
The board supports the PCI Bus Power Management Interface Specification. Add-in
boards that also support this specification can participate in power management and
can be used to wake the computer.
The use of Instantly Available PC technology requires operating system support and
PCI 2.2 compliant add-in cards, PCI Express add-in cards, and drivers.
Table 9 on page 42 lists the devices and events that can
1.13.2.5 Resume on Ring
The operation of Resume on Ring can be summarized as follows:
• Resumes operation from ACPI S1 or S3 states
• Detects incoming call similarly for external and internal modems
• Requires modem interrupt be unmasked for correct operation
44
1.13.2.6 Wake from USB
USB bus activity wakes the computer from ACPI S1 or S3 states.
Product Description
NOTE
Wake from USB requires the use of a USB peripheral that supports Wake from USB.
1.13.2.7 Wake from PS/2 Devices
PS/2 device activity wakes the computer from an ACPI S1 or S3 state.
1.13.2.8 PME# Signal Wake-up Support
When the PME# signal on the PCI Conventional bus is asserted, the computer wakes
from an ACPI S1, S3, S4, or S5 state (with Wake on PME enabled in the BIOS).
1.13.2.9 WAKE# Signal Wake-up Support
When the WAKE# signal on the PCI Express bus is asserted, the computer wakes from
an ACPI S1, S3, S4, or S5 state.
1.13.2.10 +5 V Standby Power Indicator LED
The +5 V standby power indicator LED shows that power is still present even when the
computer appears to be off.
indicator LED on the D975XBX2 board.
Figure 14 shows the location of the standby power
CAUTION
If AC power has been switched off and the standby power indicator is still lit,
disconnect the power cord before installing or removing any devices connected to the
board. Failure to do so could damage the board and any attached devices.
OM18534
Figure 14. Location of the Standby Power Indicator LED
Electrostatic discharge (ESD) can damage components. The onboard power button
should be used only at an ESD workstation using an antistatic wrist strap and a
conductive foam pad. If such a station is not available, some ESD protection can be
provided by wearing an antistatic wrist strap and attaching it to a metal part of the
computer chassis.
The board provides a power button that can be used to turn the computer on or off.
This button is intended for use at integration facilities to remove standby power before
making changes to the system configuration, or for testing purposes.
The power button on the front panel is recommended for all other instances of turning
the computer on or off. To turn the computer off using the onboard power button,
keep the button pressed down for three seconds.
Figure 15. Location of the Onboard Power Button
46
Product Description
1.15 Onboard LEDs
In addition to the standby power indicator, the board contains two LEDs that indicate
the following:
•The CPU LED indicates an elevated temperature on the processor that could effect
performance
•The VR LED indicates an elevated temperature in the processor voltage regulator
circuit that could effect performance
Figure 16 shows the locations of the LEDs.
Figure 16. Location of the CPU and Processor Voltage Regulator LEDs
The optional Trusted Platform Module (TPM) is a component on the desktop board that
is specifically designed to enhance platform security above-and-beyond the capabilities
of today’s software by providing a protected space for key operations and other
security critical tasks. Using both hardware and software, the TPM protects encryption
and signature keys at their most vulnerable stages—operations when the keys are
being used unencrypted in plain-text form. The TPM is specifically designed to shield
unencrypted keys and platform authentication information from software-based
attacks.
The board utilizes 8 GB of addressable system memory. Typically the address space
that is allocated for PCI Conventional bus add-in cards, PCI Express configuration
space, BIOS (SPI Flash device), and chipset overhead resides above the top of DRAM
(total system memory). On a system that has 8 GB of system memory installed, it is
not possible to use all of the installed memory due to system address space being
allocated for other system critical functions. These functions include the following:
• BIOS/SPI Flash device (8 Mbit)
• Local APIC (19 MB)
• Digital Media Interface (40 MB)
• Front side bus interrupts (17 MB)
• PCI Express configuration space (256 MB)
• MCH base address registers, internal graphics ranges, PCI Express ports (up to
512 MB)
•Memory-mapped I/O that is dynamically allocated for PCI Conventional and PCI
Express add-in cards
The board provides the capability to reclaim the physical memory overlapped by the
memory mapped I/O logical address space. The board remaps physical memory from
the top of usable DRAM boundary to the 4 GB boundary to an equivalent sized logical
address range located just above the 4 GB boundary.
the system memory map. All installed system memory can be used when there is no
overlap of system addresses.
PCI Memory Range -
contains PCI, chipsets,
Direct Media Interface
(DMI), and ICH ranges
(approximately 750 MB)
DRAM
Range
DOS
Compatibility
Memory
Top of System Address Space
8 GB
FLASH
APIC
Reserved
Top of usable
DRAM (memory
visible to the
operating system)
1 MB
640 KB
0 MB
Upper
4 GB of
address
space
~20 MB
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0C0000H
0BFFFFH
0A0000H
09FFFFH
00000H
Upper BIOS
area (64 KB)
Lower BIOS
area
(64 KB;
16 KB x 4)
Add-in Card
BIOS and
Buffer area
(128 KB;
16 KB x 8)
Standard PCI/
ISA Video
Memory (SMM
Memory)
128 KB
DOS area
(640 KB)
1 MB
960 KB
896 KB
768 KB
640 KB
0 KB
OM18311
Figure 17. Detailed System Memory Address Map
50
2.1.2 Memory Map
Table 10 lists the system memory map.
Table 10. System Memory Map
Address Range (decimal) Address Range (hex) Size Description
1024 K - 8388608 K 100000 - 1FFFFFFFF 8191 MB Extended memory
960 K - 1024 K F0000 - FFFFF 64 KB Runtime BIOS
896 K - 960 K E0000 - EFFFF 64 KB Reserved
800 K - 896 K C8000 - DFFFF 96 KB Potential available high DOS
640 K - 800 K A0000 - C7FFF 160 KB Video memory and BIOS
639 K - 640 K 9FC00 - 9FFFF 1 KB Extended BIOS data (movable by
512 K - 639 K 80000 - 9FBFF 127 KB Extended conventional memory
0 K - 512 K 00000 - 7FFFF 512 KB Conventional memory
Technical Reference
memory (open to the PCI
Conventional bus). Dependent on
video adapter used.
memory manager software)
2.2 DMA Channels
Table 11. DMA Channels
DMA Channel Number Data Width System Resource
0 8 or 16 bits Open
1 8 or 16 bits Parallel port
2 8 or 16 bits Diskette drive
3 8 or 16 bits Parallel port (for ECP or EPP)
4 8 or 16 bits DMA controller
5 16 bits Open
6 16 bits Open
7 16 bits Open
0000 - 00FF 256 bytes Used by the Desktop Board D975XBX2. Refer to the
ICH7-R/ICH7-DH data sheet for dynamic addressing
information.
0170 - 0177 8 bytes Secondary Parallel ATA IDE channel command block
01F0 - 01F7 8 bytes Primary Parallel ATA IDE channel command block
0228 - 022F
0278 - 027F
02E8 - 02EF
02F8 - 02FF
0374 - 0377 4 bytes Secondary Parallel ATA IDE channel control block
0377, bits 6:0 7 bits Secondary IDE channel status port
0378 - 037F 8 bytes LPT1
03E8 - 03EF 8 bytes COM3
03F0 - 03F5 6 bytes Diskette channel
03F4 – 03F7 1 byte Primary Parallel ATA IDE channel control block
03F8 - 03FF 8 bytes COM1
04D0 - 04D1 2 bytes Edge/level triggered PIC
LPTn + 400 8 bytes ECP port, LPTn base address + 400h
0CF8 - 0CFB
0CF9
0CFC - 0CFF 4 bytes PCI Conventional bus configuration data register
FFA0 - FFA7 8 bytes Primary Parallel ATA IDE bus master registers
FFA8 - FFAF 8 bytes Secondary Parallel ATA IDE bus master registers
Notes:
Default, but can be changed to another address range.
1.
Dword access only.
2.
Byte access only.
3.
(Note 1)
8 bytes LPT3
(Note 1)
8 bytes LPT2
(Note 1)
8 bytes COM4
(Note 1)
8 bytes COM2
(Note 2)
4 bytes PCI Conventional bus configuration address register
(Note 3)
1 byte Reset control register
NOTE
Some additional I/O addresses are not available due to ICH7-R/ICH7-DH address
aliasing. The ICH7-R/ICH7-DH data sheet provides more information on address
aliasing.
For information about Refer to
Obtaining the ICH7-R/ICH7-DH data sheet Section 1.2 on page 17
52
2.4 PCI Configuration Space Map
Table 13. PCI Configuration Space Map
Technical Reference
Bus
Number (hex)
00 00 00 Memory controller of Intel 82975X component
00 01 00 PCI Express x16 graphics port
00 1B 00 Intel High Definition Audio controller
00 1C 00 PCI Express port 1
00 1C 01 PCI Express port 2 (Gigabit Ethernet controller
00 1C 02 PCI Express port 3
00 1C 03 PCI Express port 4 (not used)
00 1D 00 USB UHCI controller 1
00 1D 01 USB UHCI controller 2
00 1D 02 USB UHCI controller 3
00 1D 03 USB UHCI controller 4
00 1D 07 EHCI controller
00 1E 00 PCI bridge
00 1F 00 PCI controller
00 1F 01 Parallel ATA IDE controller
00 1F 02 Serial ATA controller
00 1F 03 SMBus controller
(Note)
(Note)
(Note)
(Note)
Note: Bus number is dynamic and can change based on add-in cards used.
The interrupts can be routed through either the Programmable Interrupt Controller
(PIC) or the Advanced Programmable Interrupt Controller (APIC) portion of the
ICH7-R/ICH7-DH component. The PIC is supported in Microsoft Windows 98 SE and
Microsoft Windows ME and uses the first 16 interrupts. The APIC is supported in
Microsoft Windows 2000 and Microsoft Windows XP and supports a total of
24 interrupts.
Table 14. Interrupts
IRQ System Resource
NMI I/O channel check
0 Reserved, interval timer
1 Reserved, keyboard buffer full
2 Reserved, cascade interrupt from slave PIC
3 User available
4 COM1
5 User available
6 Diskette drive
7 LPT1
8 Real-time clock
9 User available
10 User available
11 User available
12 Onboard mouse port (if present, else user available)
13 Reserved, math coprocessor
14 Primary Parallel ATA/Serial ATA – Legacy Mode (if present, else user available)
15 Secondary Parallel ATA/Serial ATA – Legacy Mode (if present, else user available)
(Note 2)
16
17
18
19
20
21
22
23
Notes:
Default, but can be changed to another IRQ.
1.
Available in APIC mode only.
2.
User available (through PIRQA)
(Note 2)
User available (through PIRQB)
(Note 2)
User available (through PIRQC)
(Note 2)
User available (through PIRQD)
(Note 2)
User available (through PIRQE)
(Note 2)
User available (through PIRQF)
(Note 2)
User available (through PIRQG)
(Note 2)
User available (through PIRQH)
(Note 1)
(Note 1)
54
Technical Reference
2.6 PCI Conventional Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected
between the PCI Conventional bus connectors and onboard PCI Conventional devices.
The PCI Conventional specification describes how interrupts can be shared between
devices attached to the PCI Conventional bus. In most cases, the small amount of
latency added by interrupt sharing does not affect the operation or throughput of the
devices. In some special cases where maximum performance is needed from a device,
a PCI Conventional device should not share an interrupt with other PCI Conventional
devices. Use the following information to avoid sharing an interrupt with a PCI
Conventional add-in card.
PCI Conventional devices are categorized as follows to specify their interrupt grouping:
•INTA: By default, all add-in cards that require only one interrupt are in this
category. For almost all cards that require more than one interrupt, the first
interrupt on the card is also classified as INTA.
•INTB: Generally, the second interrupt on add-in cards that require two or more
interrupts is classified as INTB. (This is not an absolute requirement.)
•INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC
and a fourth interrupt is classified as INTD.
The ICH7-R/ICH7-DH has eight Programmable Interrupt Request (PIRQ) input signals.
All PCI Conventional interrupt sources either onboard or from a PCI Conventional
add-in card connect to one of these PIRQ signals. Some PCI Conventional interrupt
sources are electrically tied together on the board and therefore share the same
interrupt.
Table 15 shows an example of how the PIRQ signals are routed.
Table 15. PCI Interrupt Routing Map
PCI Interrupt Source
PCI bus connector 1 INTD INTA INTB INTC
PCI bus connector 2 INTD INTC INTA INTB
IEEE-1394a controller INTA
Discrete SATA Controller INTA
PIRQA PIRQB PIRQC PIRQD PIRQE PIRQF PIRQG PIRQH
NOTE
ICH7-R/ICH7-DH PIRQ Signal Name
In PIC mode, the ICH7-R/ICH7-DH can connect each PIRQ line internally to one of the
IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not
share a PIRQ line will have a unique interrupt. However, in certain interruptconstrained situations, it is possible for two or more of the PIRQ lines to be connected
to the same IRQ signal. Refer to
Table 14 for the allocation of PIRQ lines to IRQ
signals in APIC mode.
PCI interrupt assignments to the USB ports, Serial ATA ports, and PCI Express ports
Only the following connectors have overcurrent protection: back panel USB, front
panel USB, and PS/2.
The other internal connectors and headers are not overcurrent protected and should
connect only to devices inside the computer’s chassis, such as fans and internal
peripherals. Do not use these connectors or headers to power devices external to the
computer’s chassis. A fault in the load presented by the external devices could cause
damage to the computer, the power cable, and the external devices themselves.
This section describes the board’s connectors. The connectors can be divided into
these groups:
• Back panel I/O connectors
• Component-side I/O connectors and headers (see page
2.7.1 Back Panel Connectors
The back panel configuration is dependent upon which audio subsystem is present.
The configurations are as follows:
•8-channel (7.1) audio subsystem (five analog audio output connectors and two
digital audio output connectors), described on page
•6-channel (5.1) audio subsystem (three analog audio output connectors), described
on page
58
59)
57
56
Technical Reference
2.7.1.1 Back Panel Connectors For 8-Channel (7.1) Audio
Subsystem
Figure 18 shows the location of the back panel connectors for boards equipped with the
8-channel (7.1) audio subsystem.
A
B
Item Description
A
B
C
D
E
F
G USB ports (four)
H
I
J
K
L
M Mic in/Retasking Jack B
N
PS/2 mouse port
PS/2 keyboard port
Serial port A
Parallel port
Digital audio out coaxial
IEEE-1394a connector
LAN
Center channel and LFE (subwoofer) audio out/ Retasking Jack G
Surround left/right channel audio out/Retasking Jack H
Audio line in/Retasking Jack C
Digital audio out optical
Front left/right channel audio out/Two channel audio line out/Retasking Jack D
C
D
E
F
G
I
H
J
L
K
MN
OM18535
Figure 18. Back Panel Connectors for 8-Channel (7.1) Audio Subsystem
NOTE
The back panel audio line out connector is designed to power headphones or amplified
speakers only. Poor audio quality occurs if passive (non-amplified) speakers are
connected to this output.
2.7.1.2 Back Panel Connectors For 6-Channel (5.1) Audio
Subsystem
Figure 19 shows the location of the back panel connectors for boards equipped with the
6-channel (5.1) audio subsystem.
A
B
Item Description
A
B
C
D
E USB ports (four)
F
G
H Mic in/Retasking Jack B
I
PS/2 mouse port
PS/2 keyboard port
Serial port A
Parallel port
LAN
Audio line in/Retasking Jack C
Front left/right channel audio out/Two channel audio line out/Retasking Jack D
CE
DF
G
HI
OM18536
Figure 19. Back Panel Connectors for 6-Channel (5.1) Audio Subsystem
NOTE
The back panel audio line out connector is designed to power headphones or amplified
speakers only. Poor audio quality occurs if passive (non-amplified) speakers are
connected to this output.
58
Technical Reference
2.7.2 Component-side Connectors and Headers
Figure 20 shows the locations of the component-side connectors and headers.
Figure 20. Component-side Connectors and Headers
Table 16 lists the component-side connectors and headers identified in Figure 20.
Table 16. Component-side Connectors and Headers Shown in Figure 20
Item/callout
from
Figure 20 Description
A
B
C
D
E
F
G
H
I Auxiliary PCI Express Graphics Power connector (optional)
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
AA
BB
CC
DD
EE
Auxiliary rear fan header
PCI Conventional bus add-in card connector 2
PCI Express x16 (electrical x4) bus add-in card connector
PCI Conventional bus add-in card connector 1
Secondary PCI Express x16 (electrical x8) bus add-in card connector
Front panel audio header
Primary PCI Express x16 (electrical x16 or x8) bus add-in card connector
Rear chassis fan header
ATAPI CD-ROM connector (optional)
Processor core power connector
MCH fan header (optional)
Processor fan header
Main power connector
Diskette drive connector
Chassis intrusion header
Parallel ATA IDE connector
Serial ATA connector 3 (ICH7-R/ICH7-DH RAID)
Serial ATA connector 2(ICH7-R/ICH7-DH RAID)
Serial ATA connector 1 (ICH7-R/ICH7-DH RAID)
Front chassis fan header
Serial ATA connector 0 (ICH7-R/ICH7-DH RAID)
Auxiliary front panel power LED header
Front panel USB headers
Front panel IEEE-1394a header [blue] (optional)
Serial ATA connector 7 (Discrete RAID) (optional)
Serial ATA connector 6 (Discrete RAID) (optional)
Serial ATA connector 5 (Discrete RAID) (optional)
Serial ATA RAID connector compatible with external Serial ATA adapter (optional)
SCSI hard drive activity indicator LED header (optional)
Front panel header
60
Table 17. ATAPI CD-ROM Connector (Optional)
Pin Signal Name
1 Left audio input from CD-ROM
2 CD audio differential ground
3 CD audio differential ground
4 Right audio input from CD-ROM
Table 18. Front Panel Audio Header
Pin Signal Name Pin Signal Name
1 Port E [Port 1] Left Channel 2 Ground
3 Port E [Port 1] Right Channel 4 Presence# (dongle present)
5 Port F [Port 2] Right Channel 6 Port E [Port 1] Sense return
7 Port E [Port 1] and Port F [Port 2]
Sense send (jack detection)
9 Port F [Port 2] Left Channel 10 Port F [Port 2] Sense return
Technical Reference
(jack detection)
8 Key
(jack detection)
INTEGRATOR’S NOTE
#
The front panel audio header is colored yellow.
Table 19. Front Chassis, Rear Chassis, and MCH Fan Headers
Pin Signal Name
1 Control
2 +12 V
3 Tach
Table 20. Processor Fan and Auxiliary Rear Fan Header
• Main power – a 2 x 12 connector. The board requires a power supply with a
2 x 12 main power cable.
• Processor core power – This connector provides power directly to the processor
voltage regulator and must always be used. Depending on manufacturing options,
the board will contain either a 2 x 4 or a 2 x 2 connector for the processor voltage
regulator.
• Auxiliary PCI Express graphics power – a 1 x 4 connector. This connector
provides the required additional power when using high power (75 W or greater)
add-in cards in either or both the Secondary PCI Express x16 (electrical x8) and
the PCI Express x16 (electrical x4) bus add-in card connectors.
CAUTION
Regardless of the connector type (2 x 4 or a 2 x 2), the Processor core power
connector must always be used. Failure to do so will prevent the board from booting.
If the board is equipped with a 2 x 4 power connector, you must use a power supply
with a dual-rail 2 x 4 Processor core power cable. Failure to do so may cause damage
to the board.
CAUTION
If high power (75 W or greater) add-in cards are installed in either or both the
Secondary PCI Express x16 (electrical x8) and the PCI Express x16 (electrical x4) bus
add-in card connectors, the Auxiliary PCI Express graphics power connector must be
used. Failure to do so may cause damage to the board and the add-in cards.
This section describes the functions of the front panel header. Table 29 lists the signal
names of the front panel header.
header.
Table 29. Front Panel Header
Figure 21 is a connection diagram for the front panel
Pin Signal In/
Out
Hard Drive Activity LED
[Orange]
1 HD_PWR Out Hard disk LED pull-up
3 HAD# Out Hard disk active LED 4 HDR_BLNK_
Reset Switch
[Blue]
5 Ground Ground 6 FPBUT_IN In Power switch
7 FP_RESET# In Reset switch 8 Ground Ground
Power Not Connected
9 +5 V Power 10 N/C Not connected
Description Pin Signal In/
Out
Power LED
[Green]
to +5 V
N/C
Power
Switch
2 HDR_BLNK_
GRN
YEL
9
87
Out Front panel green
Out Front panel yellow
On/Off Switch
[Red]
+5 V DC
Reset
Switch
Description
LED
LED
65
-
423
+
1
+
Hard Drive
Activity LED
Dual-
colored
Power LED
+
-
Singlecolored
Power LED
Figure 21. Connection Diagram for Front Panel Header
66
OM18331
Technical Reference
2.7.2.4.1 Hard Drive Activity LED Header [Orange]
Pins 1 and 3 [Orange] can be connected to an LED to provide a visual indicator that
data is being read from or written to a hard drive. Proper LED function requires one of
the following:
• A Serial ATA hard drive connected to an onboard Serial ATA connector
• An IDE hard drive connected to an onboard IDE connector
2.7.2.4.2 Reset Switch Header [Blue]
Pins 5 and 7 [Blue] can be connected to a momentary single pole, single throw (SPST)
type switch that is normally open. When the switch is closed, the board resets and
runs the POST.
2.7.2.4.3 Power/Sleep LED Header [Green]
Pins 2 and 4 [Green] can be connected to a one- or two-color LED. Table 30 shows the
possible states for a one-color LED.
Table 31 shows the possible states for a two-color
LED.
Table 30. States for a One-Color Power LED
LED State Description
Off Power off/sleeping
Steady Green Running
Table 31. States for a Two-Color Power LED
LED State Description
Off Power off
Steady Green Running
Steady Yellow Sleeping
NOTE
The colors listed in Table 30 and Table 31 are suggested colors only. Actual LED colors
are product- or customer-specific.
2.7.2.4.4 Power Switch Header [Red]
Pins 6 and 8 [Red] can be connected to a front panel momentary-contact power
switch. The switch must pull the SW_ON# pin to ground for at least 50 ms to signal
the power supply to switch on or off. (The time requirement is due to internal
debounce circuitry on the board.) At least two seconds must pass before the power
supply will recognize another on/off signal.
Do not move the jumper with the power on. Always turn off the power and unplug the
power cord from the computer before changing a jumper setting. Otherwise, the board
could be damaged.
Figure 24 shows the location of the jumper block. The 3-pin jumper block determines
the BIOS Setup program’s mode.
modes: normal, configure, and recovery. When the jumper is set to configure mode
and the computer is powered-up, the BIOS compares the processor version and the
microcode version in the BIOS and reports if the two match.
Table 32 describes the jumper settings for the three
The BIOS uses current configuration information and
passwords for booting.
After the POST runs, Setup runs automatically. The
maintenance menu is displayed.
The BIOS attempts to recover the BIOS configuration. A
recovery diskette is required.
70
Technical Reference
2.9 Mechanical Considerations
2.9.1 Form Factor
The board is designed to fit into an ATX-form-factor chassis. Figure 25 illustrates the
mechanical form factor for the board. Dimensions are given in inches [millimeters].
The outer dimensions are 12.00 inches by 9.60 inches [304.80 millimeters by
243.84 millimeters]. Location of the I/O connectors and mounting holes are in
compliance with the ATX specification.
The back panel I/O shield for the board must meet specific dimension and material
requirements. Systems based on this board need the back panel I/O shield to pass
certification testing.
(7.1) audio subsystem.
(5.1) audio subsystem. Dimensions are given in inches to a tolerance of ±0.02 inches.
The figures also indicate the position of each cutout. Additional design considerations
for I/O shields relative to chassis requirements are described in the ATX specification.
Figure 26 shows the I/O shield for boards with the 8-channel
Figure 27 shows the I/O shield for boards with the 6-channel
NOTE
The I/O shield drawings in this document are for reference only. I/O shields compliant
with the ATX chassis specification are available from Intel.
162.3 REF
1.55 REF
[0.061]
[0.884]
7.01
[0.276]
[0.039]
0.00
[0.00]
[0.465]
12.04
[0.474]
[0.504]
22.45
1.00
11.81
12.81
[6.390]
20 – 0.254 TYP
[0.787 – 0.10]
A
8.81
0.00
[0.00]
20.28
[0.347]
26.91
[0.799]
[1.059]
159.2 – 0.12
[6.268 – 0.005]
61.54
[2.423]
93.74
[3.690]
113.63
[4.473]
146.88
[5.783]
1.6 – 0.12
[0.063 – 0.005]
8x R 0.5 MIN
A
11.81
[0.465]
14.17
[0.558]
Figure 26. I/O Shield Dimensions for Boards with the 8-Channel (7.1)
72
Audio Subsystem
Pictorial
View
OM18540
1.55 REF
[0.061]
[0.884]
7.012
[0.276]
[0.039]
0.00
[0.00]
[0.465]
12.04
[0.474]
22.45
1.00
11.811
Technical Reference
162.3 REF
[6.390]
20 – 0.254 TYP
[0.787 – 0.10]
A
0.00
8.805
20.283
[0.347]
26.911
[0.799]
[1.059]
[0.00]
159.2 – 0.12
[6.268 – 0.005]
93.74
[3.690]
113.63
[4.473]
146.88
[5.783]
1.6 – 0.12
[0.063 – 0.005]
8x R 0.5 MIN
A
11.81
[0.465]
14.17
[0.558]
Pictorial
View
OM18541
Figure 27. I/O Shield Dimensions for Boards with the 6-Channel (5.1)
Table 33 lists the DC loading characteristics of the board. This data is based on a DC
analysis of all active components within the board that impact its power delivery
subsystems. The analysis does not include PCI add-in cards. Minimum values assume
a light load placed on the board that is similar to an environment with no applications
running and no USB current draw. Maximum values assume a load placed on the
board that is similar to a heavy gaming environment with a 500 mA current draw per
USB port. These calculations are not based on specific processor values or memory
configurations but are based on the minimum and maximum current draw possible
from the board’s power delivery subsystems to the processor, memory, and USB ports.
Use the datasheets for add-in cards, such as PCI, to determine the overall system
power requirements. The selection of a power supply at the system level is dependent
on the system’s usage model and not necessarily tied to a particular processor clock
frequency.
Table 33. DC Loading Characteristics
DC Current at:
Mode DC Power +3.3 V +5 V +12 V -12 V +5 VSB
Minimum loading 300 W 5 A 11 A 19 A 0 A 0.34 A (S0)
Maximum loading 750 W 25 A 27 A 46 A 0.40 A 0.34 A (S0)
2.10.2 Add-in Board Considerations
The board is designed to provide 2 A (average) of +5 V current for each add-in board.
The total +5 V current draw for add-in boards for the desktop board is as follows: a
fully loaded board (all five expansion slots) must not exceed 10 A.
1.25 A (S3)
1.25 A (S3)
74
Technical Reference
2.10.3 Fan Header Current Capability
CAUTION
The processor fan must be connected to the processor fan header, not to a chassis fan
header. Connecting the processor fan to a chassis fan header may result in onboard
component damage that will halt fan operation.
Table 34 lists the current capability of the fan headers.
Table 34. Fan Header Current Capability
Fan Connector Maximum Available Current
Processor fan 3.0 A
Front chassis fan 1.5 A
Rear chassis fan 1.5 A
Auxiliary rear fan 3.0 A
MCH fan (optional) 1.5 A
2.10.4 Power Supply Considerations
CAUTION
The +5 V standby line for the power supply must be capable of providing adequate
+5 V standby current. Failure to do so can damage the power supply. The total
amount of standby current required depends on the wake devices supported and
manufacturing options.
System integrators should refer to the power usage values listed in Table 33 when
selecting a power supply for use with the board.
Additional power required will depend on configurations chosen by the integrator.
The power supply must comply with the following recommendations found in the ATX
form factor specification.
• The potential relation between 3.3 VDC and +5 VDC power rails
This board features a thermal protection circuit in the processor voltage regulator area.
This circuit protects the processor voltage regulator from overheating and damaging
the board. The thermal protection circuit in the processor voltage regulator sensor is
triggered at approximately 120
throttling mode (slowing down the processor if it exceeds its maximum operating
temperature) and allow the processor voltage regulator to cool down.
INTEGRATOR’S NOTE
#
Use a processor heatsink that provides omni-directional airflow to maintain required
airflow across the processor voltage regulator area.
CAUTION
When using BIOS Setup program options to increase processor voltage and frequency
above the supported ranges, the temperature in the processor voltage regulator area
will rise. This area of the board will require increased airflow. Direct airflow over the
processor voltage regulator is crucial to preventing throttling and keeping the
processor voltage regulator area cool. This is particularly important when using liquid
cooling.
o
C. This trigger will cause the processor to enter a
All responsibility for determining the adequacy of any thermal or system design
remains solely with the reader. Intel makes no warranties or representations that
merely following the instructions presented in this document will result in a system
with adequate thermal performance.
Figure 28 shows the locations of the localized high temperature zones.
76
Technical Reference
Item Description
A Intel 82801G ICH7-R/ICH7-DH
B Intel 82975X MCH
C Processor voltage regulator area
D Processor
Figure 28. Localized High Temperature Zones
CAUTION
Ensure that the ambient temperature does not exceed the board’s maximum operating
temperature. Failure to do so could cause components to exceed their maximum case
temperature and malfunction. For information about the maximum operating
temperature, see the environmental specifications in Section
Table 35 provides maximum case temperatures for the components that are sensitive
to thermal changes. The operating temperature, current load, or operating frequency
could affect case temperatures. Maximum case temperatures are important when
considering proper airflow to cool the board.
Table 35. Thermal Considerations for Components
Component Temperature
Intel 82801G ICH7-R/ICH7-DH 110 oC (under bias)
Intel 82975X MCH 99 oC (under bias)
Processor For processor case temperature, see processor datasheets and
processor specification updates
Processor voltage regulator area 120 oC (under bias)
NOTE
For hardware monitoring application software, an alert point of 110 oC is recommended
as a starting point for the processor voltage regulator area.
The Mean Time Between Failures (MTBF) prediction is calculated using component and
subassembly random failure rates. The calculation is based on the Bellcore Reliability
Prediction Procedure, TR-NWT-000332, Issue 4, September 1991. The MTBF
prediction is used to estimate repair rates and spare parts requirements.
The MTBF data is calculated from predicted data at 55 ºC. The MTBF for the board is
99,721 hours.
78
2.13 Environmental
Table 36 lists the environmental specifications for the board.
Table 36. Environmental Specifications
Parameter Specification
Temperature
-40
Non-Operating
Operating
Shock
Unpackaged 50 g trapezoidal waveform
Velocity change of 170 inches/second²
Packaged Half sine 2 millisecond
Product Weight (pounds) Free Fall (inches) Velocity Change (inches/sec²)
<20 36 167
21-40 30 152
41-80 24 136
81-100 18 118
Vibration
Unpackaged 5 Hz to 20 Hz: 0.01 g² Hz sloping up to 0.02 g² Hz
20 Hz to 500 Hz: 0.02 g² Hz (flat)
Packaged 5 Hz to 40 Hz: 0.015 g² Hz (flat)
40 Hz to 500 Hz: 0.015 g² Hz sloping down to 0.00015 g² Hz
3.8 BIOS Security Features ..................................................................... 87
3.1 Introduction
The BIOS is stored in the Serial Peripheral Interface (SPI) Flash device and can be
updated using a disk-based program. The SPI contains the BIOS Setup program,
POST, the PCI auto-configuration utility, and Plug and Play support.
The BIOS displays a message during POST identifying the type of BIOS and a revision
code. The initial production BIOSs are identified as BX97520J.86A.
When the BIOS Setup configuration jumper is set to configure mode and the computer
is powered-up, the BIOS compares the CPU version and the microcode version in the
BIOS and reports if the two match.
The BIOS Setup program can be used to view and change the BIOS settings for the
computer. The BIOS Setup program is accessed by pressing the <F2> key after the
Power-On Self-Test (POST) memory test begins and before the operating system boot
begins. The menu bar is shown below.
Maintenance Main Advanced PerformanceSecurity Power Boot Exit
NOTE
The maintenance menu is displayed only when the board is in configure mode.
Section
The performance menu is an optional menu and not present on all versions of the
board.
2.8 on page 70 shows how to put the board in configure mode.
Table 37 lists the BIOS Setup program menu features.
Table 37. BIOS Setup Program Menu Bar
Menu Function
Maintenance Clears passwords and displays processor information
Main Displays processor and memory configuration
Advanced Configures advanced features available through the chipset
Performance Allows adjustment of processor and memory timing parameters
Security Sets passwords and security features
Power Configures power management features and power supply controls
Boot Selects boot options
Exit Saves or discards changes to Setup program options
Table 38 lists the function keys available for menu screens.
Table 38. BIOS Setup Program Function Keys
BIOS Setup Program Function Key Description
<←> or <→>
<↑> or <↓>
<Tab> Selects a field (not implemented)
<Enter> Executes command or selects the submenu
<F9> Load the default configuration values for the current menu
<F10> Save the current values and exits the BIOS Setup program
<Esc> Exits the menu
Selects a different menu screen (moves the cursor left or right)
Selects an item (moves the cursor up or down)
3.2 Resource Configuration
3.2.1 PCI Autoconfiguration
The BIOS automatically configures PCI devices. PCI devices may be onboard or add-in
cards. Autoconfiguration lets a user insert or remove PCI cards without having to
configure the system. When a user turns on the system after adding a PCI card, the
BIOS automatically configures interrupts, the I/O space, and other system resources.
Any interrupts set to Available in Setup are considered to be available for use by the
add-in card.
3.2.2 PCI IDE Support
If you select Auto in the BIOS Setup program, the BIOS automatically sets up the
PCI IDE connector with independent I/O channel support. The IDE interface supports
hard drives up to ATA-66/100 and recognizes any ATAPI compliant devices, including
CD-ROM drives, tape drives, and Ultra DMA drives. The interface also supports
second-generation SATA drives. The BIOS determines the capabilities of each drive
and configures them to optimize capacity and performance. To take advantage of the
high capacities typically available today, hard drives are automatically configured for
82
Overview of BIOS Features
Logical Block Addressing (LBA) and to PIO Mode 3 or 4, depending on the capability of
the drive. You can override the auto-configuration options by specifying manual
configuration in the BIOS Setup program.
To use ATA-66/100 features the following items are required:
• An ATA-66/100 peripheral device
• An ATA-66/100 compatible cable
• ATA-66/100 operating system device drivers
NOTE
Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master
device. For example, do not connect an ATA hard drive as a slave to an ATAPI CDROM drive.
3.3 System Management BIOS (SMBIOS)
SMBIOS is a Desktop Management Interface (DMI) compliant method for managing
computers in a managed network.
The main component of SMBIOS is the Management Information Format (MIF)
database, which contains information about the computing system and its
components. Using SMBIOS, a system administrator can obtain the system types,
capabilities, operational status, and installation dates for system components. The MIF
database defines the data and provides the method for accessing this information. The
BIOS enables applications such as third-party management software to use SMBIOS.
The BIOS stores and reports the following SMBIOS information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor clock frequency
• Dynamic data, such as event detection and error logging
Non-Plug and Play operating systems, such as Microsoft Windows NT*, require an
additional interface for obtaining the SMBIOS information. The BIOS supports an
SMBIOS table interface for such operating systems. Using this support, an SMBIOS
service-level application running on a non-Plug and Play operating system can obtain
the SMBIOS information.
3.4 Watchdog Timer
The board includes a watchdog timer circuit. The watchdog timer provides automatic
recovery after two failed power-on self-tests (POSTs) following use of the BIOS
performance menu.
Legacy USB support enables USB devices to be used even when the operating system’s
USB drivers are not yet available. Legacy USB support is used to access the BIOS
Setup program, and to install an operating system that supports USB.
Legacy USB support operates as follows:
1.
When you apply power to the computer, legacy support is disabled.
2.
POST begins.
3.
Legacy USB support is enabled by the BIOS allowing you to use a USB keyboard to
enter and configure the BIOS Setup program and the maintenance menu.
4.
POST completes.
5.
The operating system loads. While the operating system is loading, USB keyboards
and mice are recognized and may be used to configure the operating system.
6.
After the operating system loads the USB drivers, all legacy and non-legacy USB
devices are recognized by the operating system, and Legacy USB support from the
BIOS is no longer used.
To install an operating system that supports USB, follow the operating system’s
installation instructions.
3.6 BIOS Updates
The BIOS can be updated using either of the following utilities, which are available on
the Intel World Wide Web site:
• Intel
• Intel
Both utilities verify that the updated BIOS matches the target system to prevent
accidentally installing an incompatible BIOS.
Review the instructions distributed with the upgrade utility before attempting a BIOS
update.
For information about Refer to
The Intel World Wide Web site Section 1.2, page 17
®
Express BIOS Update utility, which enables automated updating while in the
Microsoft Windows environment. Using this utility, the BIOS can be updated from a
file on a hard disk, a 1.44 MB diskette, or a CD-ROM, or from the file location on
the Web.
®
Flash Memory Update Utility, which requires creation of a boot diskette and
manual rebooting of the system. Using this utility, the BIOS can be updated from
a file on a 1.44 MB diskette or a CD-ROM.
NOTE
84
Overview of BIOS Features
3.6.1 Language Support
The BIOS Setup program and help messages are supported in US English. Additional
languages are available in the Integrator’s Toolkit utility. Check the Intel website for
details.
3.6.2 Custom Splash Screen
During POST, an Intel® splash screen is displayed by default. This splash screen can be
augmented with a custom splash screen. The Integrator’s Toolkit that is available
from Intel can be used to create a custom splash screen.
NOTE
If you add a custom splash screen, it will share space with the Intel branded logo.
For information about
The Intel World Wide Web site Section 1.2, page 17
Refer to
3.7 Boot Options
In the BIOS Setup program, the user can choose to boot from a diskette drive, hard
drives, CD-ROM, or the network. The default setting is for the diskette drive to be the
first boot device, the hard drive second, and the ATAPI CD-ROM third. The fourth
device is disabled.
3.7.1 CD-ROM Boot
Booting from CD-ROM is supported in compliance to the El Torito bootable CD-ROM
format specification. Under the Boot menu in the BIOS Setup program, ATAPI CD-ROM
is listed as a boot device. Boot devices are defined in priority order. Accordingly, if
there is not a bootable CD in the CD-ROM drive, the system will attempt to boot from
the next defined drive.
3.7.2 Network Boot
The network can be selected as a boot device. This selection allows booting from the
onboard LAN or a network add-in card with a remote boot ROM installed.
Pressing the <F12> key during POST automatically forces booting from the LAN. To
use this key during POST, the User Access Level in the BIOS Setup program's Security
menu must be set to Full.
For use in embedded applications, the BIOS has been designed so that after passing
the POST, the operating system loader is invoked even if the following devices are not
present:
• Video adapter
• Keyboard
• Mouse
3.7.4 Changing the Default Boot Device During POST
Pressing the <F10> key during POST causes a boot device menu to be displayed. This
menu displays the list of available boot devices (as set in the BIOS setup program’s
Boot Device Priority Submenu).
Table 39. Boot Device Menu Options
Boot Device Menu Function Keys Description
<↑> or <↓>
<Enter> Exits the menu, saves changes, and boots from the selected device
<Esc> Exits the menu without saving changes
Table 39 lists the boot device menu options.
Selects a default boot device
86
Overview of BIOS Features
3.8 BIOS Security Features
The BIOS includes security features that restrict access to the BIOS Setup program
and who can boot the computer. A supervisor password and a user password can be
set for the BIOS Setup program and for booting the computer, with the following
restrictions:
• The supervisor password gives unrestricted access to view and change all the Setup
options in the BIOS Setup program. This is the supervisor mode.
• The user password gives restricted access to view and change Setup options in the
BIOS Setup program. This is the user mode.
• If only the supervisor password is set, pressing the <Enter> key at the password
prompt of the BIOS Setup program allows the user restricted access to Setup.
• If both the supervisor and user passwords are set, users can enter either the
supervisor password or the user password to access Setup. Users have access to
Setup respective to which password is entered.
• Setting the user password restricts who can boot the computer. The password
prompt will be displayed before the computer is booted. If only the supervisor
password is set, the computer boots without asking for a password. If both
passwords are set, the user can enter either password to boot the computer.
• For enhanced security, use different passwords for the supervisor and user
passwords.
• Valid password characters are A-Z, a-z, and 0-9. Passwords may be up to
16 characters in length.
Table 40 shows the effects of setting the supervisor password and user password. This
table is for reference only and is not displayed on the screen.
Table 40. Supervisor and User Password Functions
Password
Set
Neither Can change all
Supervisor
only
User only N/A Can change all
Supervisor
and user set
Note: If no password is set, any user can change all Setup options.
During the POST, the BIOS generates diagnostic progress codes (POST-codes) to I/O
port 80h. If the POST fails, execution stops and the last POST code generated is left at
port 80h. This code is useful for determining the point where an error occurred.
Displaying the POST-codes requires a PCI bus add-in card, often called a POST card.
The POST card can decode the port and display the contents on a medium such as a
seven-segment display.
NOTE
The POST card must be installed in PCI bus connector 1.
The following tables provide information about the POST codes generated by the BIOS:
• Table 43 lists the Port 80h POST code ranges
• Table 44 lists the Port 80h POST codes themselves
• Table 45 lists the Port 80h POST sequence
NOTE
In the tables listed above, all POST codes and range values are listed in hexadecimal.
Table 43. Port 80h POST Code Ranges
Range Category/Subsystem
00 – 0F Debug codes: Can be used by any PEIM/driver for debug.
10 – 1F Host Processors: 1F is an unrecoverable CPU error.
20 – 2F Memory/Chipset: 2F is no memory detected or no useful memory detected.
30 – 3F Recovery: 3F indicated recovery failure.
40 – 4F Reserved for future use
50 – 5F I/O buses: PCI, USB, ISA, ATA, etc. 5F is an unrecoverable error. Start with PCI.
60 – 6F Reserved for future use (for new buses)
70 – 7F Output devices: All output consoles. 7F is an unrecoverable error.
80 – 8F Reserved for future use (new output console codes)
90 – 9F Input devices: Keyboard/Mouse. 9F is an unrecoverable error.
A0 – AF Reserved for future use (new input console codes)
B0 – BF Boot devices: Includes fixed media and removable media. BF is an unrecoverable error.
C0 – CF Reserved for future use
D0 – DF Boot device selection
E0 – FF F0 – FF: FF processor exception.
E0 – EE: Miscellaneous codes. See
EF boot/S3: resume failure.
Table 44.
90
Error Messages and Beep Codes
Table 44. Port 80h POST Codes
POST Code Description of POST Operation
Host Processor
10 Power-on initialization of the host processor (Boot Strap Processor)
11 Host processor Cache initialization (including APs)
12 Starting Application processor initialization
13 SMM initialization
Chipset
21 Initializing a chipset component
Memory
22 Reading SPD from memory DIMMs
23 Detecting presence of memory DIMMs
24 Programming timing parameters in the memory controller and the DIMMs
25 Configuring memory
26 Optimizing memory settings
27 Initializing memory, such as ECC init
28 Testing memory
PCI Bus
50 Enumerating PCI buses
51 Allocating resources to PCI bus
52 Hot Plug PCI controller initialization
53 – 57 Reserved for PCI Bus
USB
58 Resetting USB bus
59 Reserved for USB
ATA/ATAPI/SATA
5A Resetting PATA/SATA bus and all devices
5B Reserved for ATA
SMBus
5C Resetting SMBUS
5D Reserved for SMBUS
Local Console
70 Resetting the VGA controller
71 Disabling the VGA controller
72 Enabling the VGA controller
Remote Console
78 Resetting the console controller
79 Disabling the console controller
7A Enabling the console controller
Keyboard (PS2 or USB)
90 Resetting keyboard
91 Disabling the keyboard
92 Detecting the presence of the keyboard
93 Enabling the keyboard
94 Clearing keyboard input buffer
95 Instructing keyboard controller to run Self Test (PS2 only)
Mouse (PS2 or USB)
98 Resetting mouse
99 Detecting mouse
9A Detecting presence of mouse
9B Enabling mouse
Fixed Media
B0 Resetting fixed media
B1 Disabling fixed media
B2 Detecting presence of a fixed media (IDE hard drive detection, etc.)
B3 Enabling/configuring a fixed media
Removable media
B8 Resetting removable media
B9 Disabling removable media
BA Detecting presence of a removable media (IDE, CD-ROM detection, etc.)
BC Enabling/configuring a removable media
BDS
DyTrying boot selection y (y=0 to 15)
PEI Core
E0 Started dispatching PEIMs (emitted on first report of EFI_SW_PC_INIT_BEGIN
EFI_SW_PEI_PC_HANDOFF_TO_NEXT)
E2 Permanent memory found
E1, E3 Reserved for PEI/PEIMs
DXE Core
E4 Entered DXE phase
E5 Started dispatching drivers
E6 Started connecting drivers
continued
92
Error Messages and Beep Codes
Table 44. Port 80h POST Codes (continued)
POST Code Description of POST Operation
DXE Drivers
E7 Waiting for user input
E8 Checking password
E9 Entering BIOS setup
EB Calling Legacy Option ROMs
Runtime Phase/EFI OS Boot
F4 Entering Sleep state
F5 Exiting Sleep state
F8 EFI boot service ExitBootServices ( ) has been called
F9 EFI runtime service SetVirtualAddressMap ( ) has been called
FA EFI runtime service ResetSystem ( ) has been called
PEIMs/Recovery
30 Crisis Recovery has initiated per user request
31 Crisis Recovery has initiated by software (corrupt flash)
34 Loading recovery capsule
35 Handing off control to the recovery capsule
3F Unable to recover
21 Initializing a chipset component
22 Reading SPD from memory DIMMs
23 Detecting presence of memory DIMMs
25 Configuring memory
28 Testing memory
34 Loading recovery capsule
E4 Entered DXE phase
12 Starting Application processor initialization
13 SMM initialization
50 Enumerating PCI buses
51 Allocating resourced to PCI bus
92 Detecting the presence of the keyboard
90 Resetting keyboard
94 Clearing keyboard input buffer
95 Keyboard Self Test
EB Calling Video BIOS
58 Resetting USB bus
5A Resetting PATA/SATA bus and all devices
92 Detecting the presence of the keyboard
90 Resetting keyboard
94 Clearing keyboard input buffer
5A Resetting PATA/SATA bus and all devices
28 Testing memory
90 Resetting keyboard
94 Clearing keyboard input buffer
E7 Waiting for user input
01 INT 19
00 Ready to boot
This section contains the following regulatory compliance information for Desktop
Board D975XBX2:
• Safety regulations
• European Union Declaration of Conformity statement
• Product Ecology statements
• Electromagnetic Compatibility (EMC) regulations
• Product certification markings
5.1.1 Safety Regulations
Desktop Board D975XBX2 complies with the safety regulations stated in Table 46 when
correctly installed in a compatible host system.
Table 46. Safety Regulations
Regulation Title
UL 60950-1:2003/
CSA C22.2 No. 60950-1-03
EN 60950-1:2002 Information Technology Equipment – Safety - Part 1: General
IEC 60950-1:2001, First Edition Information Technology Equipment – Safety - Part 1: General
Information Technology Equipment – Safety - Part 1: General
Requirements (USA and Canada)
Requirements (European Union)
Requirements (International)
5.1.2 European Union Declaration of Conformity
Statement
We, Intel Corporation, declare under our sole responsibility that the product Intel®
Desktop Board D975XBX2 is in conformity with all applicable essential requirements
necessary for CE marking, following the provisions of the European Council Directive
89/336/EEC (EMC Directive) and Council Directive 73/23/EEC (Safety/Low Voltage
Directive).
Magyar E termék megfelel a 89/336/EEC és 73/23/EEC Európai Irányelv előírásainak.
Icelandic Þessi vara stenst reglugerð Evrópska Efnahags Bandalagsins númer
89/336/ EEC & 73/23/EEC.
Italiano Questo prodotto è conforme alla Direttiva Europea 89/336/EEC & 73/23/EEC.
Latviešu Šis produkts atbilst Eiropas Direktīvu 89/336/EEC un 73/23/EEC
noteikumiem.
Lietuvių
nuostatas.
Šis produktas atitinka Europos direktyvų 89/336/EEC ir 73/23/EEC
Malti Dan il-prodott hu konformi mal-provvedimenti tad-Direttivi Ewropej 89/336/EEC
u 73/23/EEC.
Norsk Dette produktet er i henhold til bestemmelsene i det europeiske direktivet
89/336/ EEC & 73/23/EEC.
Polski Niniejszy produkt jest zgodny z postanowieniami Dyrektyw Unii Europejskiej
89/336/EWG i 73/23/EWG.
Portuguese
Este produto cumpre com as normas da Diretiva Européia 89/336/EEC &
73/23/EEC.
96
Regulatory Compliance and Battery Disposal Information
Español Este producto cumple con las normas del Directivo Europeo 89/336/EEC &
73/23/EEC.
Slovensky Tento produkt je v súlade s ustanoveniami európskych direktív
89/336/EEC a 73/23/EEC.
Slovenščina Izdelek je skladen z določbami evropskih direktiv 89/336/EGS in
73/23/EGS.
Svenska Denna produkt har tillverkats i enlighet med EG-direktiv 89/336/EEC &
73/23/EEC.
TürkçeBu ürün, Avrupa Birliği’nin 89/336/EEC ve 73/23/EEC yönergelerine uyar.
5.1.3 Product Ecology Statements
The following information is provided to address worldwide product ecology concerns
and regulations.
5.1.3.1 Disposal Considerations
This product contains the following materials that may be regulated upon disposal:
lead solder on the printed wiring board assembly.
5.1.3.2 Recycling Considerations
As part of its commitment to environmental responsibility, Intel has implemented the
Intel Product Recycling Program to allow retail consumers of Intel’s branded products
to return used products to select locations for proper recycling.
Please consult the
http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm for the
details of this program, including the scope of covered products, available locations,
shipping instructions, terms and conditions, etc.
中文
作为其对环境责任之承诺的部分,英特尔已实施 Intel Product Recycling Program
(英特尔产品回收计划),以允许英特尔品牌产品的零售消费者将使用过的产品退还至指定地点作恰
当的重复使用处理。
Als Teil von Intels Engagement für den Umweltschutz hat das Unternehmen das Intel
Produkt-Recyclingprogramm implementiert, das Einzelhandelskunden von Intel
Markenprodukten ermöglicht, gebrauchte Produkte an ausgewählte Standorte für
ordnungsgemäßes Recycling zurückzugeben.
Details zu diesem Programm, einschließlich der darin eingeschlossenen Produkte,
verfügbaren Standorte, Versandanweisungen, Bedingungen usw., finden Sie auf der
Como parte de su compromiso de responsabilidad medioambiental, Intel ha
implantado el programa de reciclaje de productos Intel, que permite que los
consumidores al detalle de los productos Intel devuelvan los productos usados en los
lugares seleccionados para su correspondiente reciclado.
para ver los detalles del programa, que incluye los productos que abarca, los lugares
disponibles, instrucciones de envío, términos y condiciones, etc.
Français
Dans le cadre de son engagement pour la protection de l'environnement, Intel a mis
en œuvre le programme Intel Product Recycling Program (Programme de recyclage des
produits Intel) pour permettre aux consommateurs de produits Intel de recycler les
produits usés en les retournant à des adresses spécifiées.
Visitez la page Web
http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm pour en savoir
plus sur ce programme, à savoir les produits concernés, les adresses disponibles, les
instructions d'expédition, les conditions générales, etc.
Sebagai sebahagian daripada komitmennya terhadap tanggungjawab persekitaran,
Intel telah melaksanakan Program Kitar Semula Produk untuk membenarkan
pengguna-pengguna runcit produk jenama Intel memulangkan produk terguna ke
lokasi-lokasi terpilih untuk dikitarkan semula dengan betul.
untuk mendapatkan butir-butir program ini, termasuklah skop produk yang
dirangkumi, lokasi-lokasi tersedia, arahan penghantaran, terma & syarat, dsb.
98
Regulatory Compliance and Battery Disposal Information
Portuguese
Como parte deste compromisso com o respeito ao ambiente, a Intel implementou o
Programa de Reciclagem de Produtos para que os consumidores finais possam enviar
produtos Intel usados para locais selecionados, onde esses produtos são reciclados de
maneira adequada.
(em Inglês) para obter os detalhes sobre este programa, inclusive o escopo dos
produtos cobertos, os locais disponíveis, as instruções de envio, os termos e condições,
etc.
Russian
В качестве части своих обязательств к окружающей среде, в Intel создана
программа утилизации продукции Intel (Product Recycling Program) для
предоставления конечным пользователям марок продукции Intel возможности
возврата используемой продукции в специализированные пункты для должной
утилизации.
Пожалуйста, обратитесь на веб-сайт
http://www.intel.com/intel/other/ehs/product_ecology/Recycling_Program.htm за
информацией об этой программе, принимаемых продуктах, местах приема,
инструкциях об отправке, положениях и условиях и т.д.
Türkçe
Intel, çevre sorumluluğuna bağımlılığının bir parçası olarak, perakende tüketicilerin
Intel markalı kullanılmış ürünlerini belirlenmiş merkezlere iade edip uygun şekilde geri
dönüştürmesini amaçlayan Intel Ürünleri Geri Dönüşüm Programı’nı uygulamaya
koymuştur.
Bu programın ürün kapsamı, ürün iade merkezleri, nakliye talimatları, kayıtlar ve şartlar v.s dahil bütün ayrıntılarını ögrenmek için lütfen
This desktop board is lead free although certain discrete components used on the
board contain a small amount of lead which is necessary for component performance
and/or reliability. This desktop board is referred to as “Lead-free second level
interconnect.” The board substrate and the solder connections from the board to the
components (second-level connections) are all lead free.
forms of the “Lead-Free 2
nd
Level Interconnect” mark as it appears on the board and
used to identify electrical and
electronic assemblies and
components in which the lead
(Pb) concentration level in the
desktop board substrate and the
solder connections from the board
to the components (second-level
interconnect) is not greater than
0.1% by weight (1000 ppm).
nd
Level
This symbol is
or
or
100
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