Intel CONTROLLERS 413808 User Manual

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Intel® 413808 and 413812 I/O

Controllers in TPER Mode

Developer’s Manual

October 2007

Order Number: 317805-001US

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® I/O controllers may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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Copyright © 2007, Intel Corporation

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

October 2007

2

Order Number: 317805-001US

Contents—Intel® 413808 and 413812

Contents

1.0

Introduction...............................................................................................................

 

 

36

 

1.1

Design-in Considerations ....................................................................................

38

 

 

1.1.1

Software

...............................................................................................

39

 

1.2

Documentation References .................................................................................

40

 

1.3

About This Document.........................................................................................

41

 

 

1.3.1

How To Read ...................................................................This Document

41

 

 

1.3.2

Other Relevant ......................................................................Documents

41

 

1.4 About the Intel® .........................413808 and 413812 I/O Controllers in TPER Mode

42

 

1.5 Intel® 413808 and ...........................413812 I/O Controllers in TPER Mode Features

44

 

 

1.5.1

Host Interface........................................................................................

44

 

 

1.5.2

Intel XScale ..........................................................................® Processor

44

 

 

1.5.3

Internal Busses......................................................................................

45

 

 

1.5.4

Application ......................................................................DMA Controller

45

 

 

1.5.5

Address Translation .........................................................................Unit

45

 

 

1.5.6

Messaging ......................................................................................Unit

46

 

 

1.5.7

DDR Memory ...........................................................................Controller

46

 

 

1.5.8

Peripheral ..........................................................................Bus Interface

46

 

 

1.5.9

Performance ....................................................................Monitoring Unit

46

 

 

1.5.10

I2C Bus Interface .............................................................................Unit

46

 

 

1.5.11

UART Unit .............................................................................................

46

 

 

1.5.12

Interrupt ..........................................................................Controller Unit

46

 

 

1.5.13

Internal Bus .................................................................System Controller

47

 

 

1.5.14

Inter-Processor ................................................................Communication

47

 

 

1.5.15

Inter-Processor ................................................................Messaging Unit

47

 

 

1.5.16

Timers ..................................................................................................

 

47

 

 

1.5.17

GPIO ....................................................................................................

 

47

 

 

1.5.18

FSENG ..................................................................................................

 

47

 

1.6

Terminology and .............................................................................Conventions

48

 

 

1.6.1

Representing ............................................................................Numbers

48

 

 

1.6.2

Fields ...................................................................................................

 

48

 

 

1.6.3

Specifying ...............................................................Bit and Signal Values

49

 

 

1.6.4

Signal Name ........................................................................Conventions

49

 

 

1.6.5

Terminology ..........................................................................................

49

2.0

Address Translation Unit ..................................................................................(PCI-X)

50

 

2.1

Overview .........................................................................................................

 

50

 

2.2

ATU Address Translation ....................................................................................

53

 

 

2.2.1

Inbound .............................................................................Transactions

55

 

 

 

2.2.1.1 ......................................................

Inbound Address Translation

56

 

 

 

2.2.1.2 .........................................................

Inbound Write Transaction

59

 

 

 

2.2.1.3 ..........................................................

Inbound Read Transaction

61

 

 

 

2.2.1.4 ......................................

Inbound Configuration Cycle Translation

64

 

 

 

2.2.1.5 .........................................................................

Discard Timers

66

 

 

2.2.2

Outbound TransactionsSingle Address Cycle (SAC) Internal Bus Transactions

...

 

 

 

67

 

 

 

 

 

2.2.2.1 ..............Outbound Address Translation - Internal Bus Transactions

68

 

 

 

2.2.2.2 .......................................Outbound Address Translation Windows

69

 

 

2.2.3

Outbound ....................................................................Write Transaction

72

 

 

2.2.4

Outbound .....................................................................Read Transaction

74

 

 

2.2.5

Outbound ..................................................Configuration Cycle Translation

75

 

 

 

2.2.5.1 .....PCI-X Mode 1 Considerations for Outbound Configuration Cycles

75

 

 

 

2.2.5.2 .....PCI-X Mode 2 Considerations for Outbound Configuration Cycles

76

 

 

 

2.2.5.3 .............................Outbound Configuration Cycle Error Conditions

76

 

 

 

 

Intel ® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

 

 

Developer’s Manual

Order Number: 317805-001US

 

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Intel® 413808 and 413812—Contents

 

2.2.6

Internal Bus Operation ............................................................................

77

2.3 Big Endian Byte Swapping...................................................................................

 

78

 

2.3.1

Inbound Byte Swapping...........................................................................

78

 

2.3.2

Outbound Byte Swapping.........................................................................

79

2.4

CompactPCI Hot-Swap .......................................................................................

 

80

 

2.4.1

Pin Interface ..........................................................................................

 

80

 

 

2.4.1.1 Compact PCI Hot-Swap Mode Select ............................................

81

2.5

Expansion ROM Translation Unit...........................................................................

82

2.6

ATU Queue Architecture......................................................................................

 

83

 

2.6.1

Inbound Queues .....................................................................................

 

83

 

 

2.6.1.1

Inbound Write Queue Structure...................................................

83

 

 

2.6.1.2

Inbound Read Queue Structure ...................................................

84

 

 

2.6.1.3

Inbound Delayed Write Queue.....................................................

85

 

 

2.6.1.4 Inbound Transaction Queues Command Translation Summary .........

85

 

2.6.2

Outbound Queues...................................................................................

 

86

 

 

2.6.2.1 Relaxed Ordering and No Snoop Outbound Request Attributes.........

86

 

2.6.3

Transaction Ordering...............................................................................

 

87

 

 

2.6.3.1

Transaction Ordering Summary ...................................................

90

 

2.6.4 Byte Parity Checking and Generation.........................................................

92

 

 

2.6.4.1

Parity Generation ......................................................................

92

 

 

2.6.4.2

Parity Checking.........................................................................

93

 

 

2.6.4.3

Parity Disabled..........................................................................

93

2.7

ATU Error Conditions..........................................................................................

 

94

 

2.7.1 Uncorrectable Address and Uncorrectable Attribute Errors on the PCI Interface ..

 

 

95

 

 

 

 

2.7.2 Correctable Address and Correctable Attribute Errors on the PCI Interface......

96

 

2.7.3 Uncorrectable Data Errors on the PCI Interface...........................................

97

 

 

2.7.3.1 Outbound Read Request Uncorrectable Data Errors ........................

98

 

 

 

2.7.3.1.1

Immediate Data Transfer ....................................................

98

 

 

 

2.7.3.1.2

Split Response Termination ................................................

99

 

 

2.7.3.2 Outbound Write Request Uncorrectable Data Errors .....................

100

2.7.3.2.1Outbound Writes that are not MSI (Message Signaled Interrupts)100

2.7.3.2.2 MSI Outbound Writes........................................................

100

2.7.3.3 Inbound Read Completions Uncorrectable Data Errors ..................

101

2.7.3.4Inbound Configuration Write Completion Message Uncorrectable Data

 

Errors101

 

 

2.7.3.5

Inbound Read Request Uncorrectable Data Errors ........................

101

 

2.7.3.5.1

Immediate Data Transfer ..................................................

101

 

2.7.3.5.2

Split Response Termination ..............................................

101

2.7.3.6

Inbound Write Request Uncorrectable Data Errors........................

101

2.7.3.7

Outbound Read Completion Uncorrectable Data Errors .................

102

2.7.3.8

Outbound Split Write Uncorrectable Data Error Message ...............

103

2.7.3.9

Inbound Configuration Write Request.........................................

104

 

2.7.3.9.1

Conventional PCI Mode ....................................................

104

 

2.7.3.9.2

PCI-X Mode.......................................................................

105

2.7.3.10

Split Completion Messages .......................................................

106

2.7.4 Correctable Data Errors on the PCI Interface ............................................

107

2.7.4.1

Inbound Read Request Correctable Data Errors ...........................

107

 

2.7.4.1.1

Immediate Data Transfer ..................................................

107

 

2.7.4.1.2

Split Response Termination ..............................................

107

2.7.4.2

Inbound Write Request Correctable Data Errors...........................

107

2.7.4.3

Outbound Read Completion Correctable Data Errors.....................

108

2.7.4.4

Inbound Configuration Write Request.........................................

108

2.7.4.5

Split Completion Messages .......................................................

108

2.7.5 Master Aborts on the PCI Interface..........................................................

109

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

 

 

October 2007

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Order Number: 317805-001US

Contents—Intel® 413808 and 413812

2.7.5.1 Master Aborts for Outbound Read or Write Request .....................

109

2.7.5.2Inbound Read Completion or Inbound Configuration Write Completion

Message110

 

2.7.5.3 Master-Aborts Signaled by the ATU as a Target...........................

110

2.7.5.3.1

Uncorrectable Address Errors ...........................................

110

2.7.5.3.2

Internal Bus Master-Abort .................................................

110

2.7.6 Target Aborts on the PCI Interface..........................................................

111

2.7.6.1Target Aborts for Outbound Read Request or Outbound Write Request . 111

2.7.6.2Inbound Read Completion or Inbound Configuration Write Completion

Message112

 

2.7.6.3 Target-Aborts Signaled by the ATU as a Target ...........................

112

2.7.6.3.1 Internal Bus Master Abort..................................................

112

 

 

 

2.7.6.3.2 Internal Bus Target Abort ..................................................

112

 

 

 

2.7.6.3.3 Inbound EROM Memory Write ..........................................

112

 

2.7.7

Corrupted or Unexpected Split Completions .............................................

113

 

 

2.7.7.1

Completer Address..................................................................

113

 

 

2.7.7.2

Completer Attributes ...............................................................

113

 

2.7.8

SERR# Assertion and Detection..............................................................

114

 

2.7.9

Internal Bus Error Conditions .................................................................

115

 

 

2.7.9.1 Master Abort on the Internal Bus ..............................................

115

 

 

 

2.7.9.1.1

Inbound Write Request ......................................................

115

 

 

 

2.7.9.1.2

Inbound Read Request .....................................................

116

 

 

2.7.9.2 Target Abort on the Internal Bus...............................................

117

 

 

 

2.7.9.2.1

Conventional Mode ...........................................................

117

 

 

 

2.7.9.2.2

PCI - X Mode .......................................................................

117

 

 

2.7.9.3 Parity Error on the Internal Bus ................................................

118

 

 

 

2.7.9.3.1

Conventional Mode ...........................................................

118

 

 

 

2.7.9.3.2

PCI - X Mode .......................................................................

118

 

2.7.10

ATU Error Summary

.............................................................................

119

2.8

Message-Signaled Interrupts.............................................................................

 

125

2.9

Internal Interrupts ..........................................................................................

 

126

2.10

Vital Product Data ...........................................................................................

 

127

 

2.10.1

Configuring Vital Product .................................................Data Operation

127

 

2.10.2

Accessing Vital Product ..................................................................Data

128

 

 

2.10.2.1

Reading Vital .......................................................Product Data

128

 

 

2.10.2.2

Writing Vital ........................................................Product Data

129

2.11

Multi-Function Support.....................................................................................

 

130

 

2.11.1

PCI-X Interface Control ........................................................Parameters

130

 

2.11.2

PCI-X Interface Status ............................................................Reporting

131

2.12

Central Resource Functionality ..........................................................................

132

 

2.12.1

Multi-Function Support..........................................................................

132

 

2.12.2

Outbound Transactions .........................................................................

132

 

2.12.3

PCI Reset (P_RSTOUT# ......................................................................)

132

 

2.12.4

PCI Clock Outputs (P ......................................_CLKOUT, P_CLKO[3:0])

132

 

2.12.5

External Clock Driver ..................................................(CR_FREQ[1:0])

133

 

2.12.6

Bus Mode and Frequency .....................................................Initialization

134

2.13

Embedded Bridge Functionality .........................................................................

138

2.14

Register Definitions .........................................................................................

 

139

 

2.14.1

PCI Configuration Registers ...................................................................

139

 

2.14.2

Internal Bus Registers...........................................................................

143

 

2.14.3

ATU Vendor ID Register ..........................................................- ATUVID

147

 

2.14.4

ATU Device ID Register ...........................................................- ATUDID

147

 

2.14.5

ATU Command Register .........................................................- ATUCMD

148

 

2.14.6

ATU Status Register - .................................................................ATUSR

149

 

2.14.7

ATU Revision ID Register .........................................................- ATURID

151

 

 

 

 

Intel ® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

 

 

 

 

Developer’s Manual

Order Number: 317805-001US

 

 

5

Intel® 413808 and 413812—Contents

2.14.8

ATU

Class Code Register - ATUCCR .........................................................

151

2.14.9

ATU

Cacheline Size Register - ATUCLSR ...................................................

152

2.14.10ATU

Latency Timer Register - ATULT .......................................................

152

2.14.11ATU

Header Type Register - ATUHTR.......................................................

153

2.14.12ATU BIST Register - ATUBISTR ...............................................................

154

2.14.13Inbound ATU Base Address Register 0 - IABAR0........................................

155

2.14.14Inbound ATU Upper Base Address Register 0 - IAUBAR0 ............................

156

2.14.15Inbound ATU Base Address Register 1 - IABAR1........................................

157

2.14.16Inbound ATU Upper Base Address Register 1 - IAUBAR1 ............................

158

2.14.17Inbound ATU Base Address Register 2 - IABAR2........................................

159

2.14.18Inbound ATU Upper Base Address Register 2 - IAUBAR2 ............................

160

2.14.19ATU Subsystem Vendor ID Register - ASVIR.............................................

161

2.14.20ATU Subsystem ID Register - ASIR .........................................................

161

2.14.21Expansion ROM Base Address Register - ERBAR ........................................

162

2.14.22ATU Capabilities Pointer Register - ATU_Cap_Ptr.......................................

163

2.14.23Determining Block Sizes for Base Address Registers ..................................

164

2.14.24ATU Interrupt Line Register - ATUILR ......................................................

166

2.14.25ATU Interrupt Pin Register - ATUIPR........................................................

167

2.14.26ATU Minimum Grant Register - ATUMGNT.................................................

167

2.14.27ATU Maximum Latency Register - ATUMLAT..............................................

168

2.14.28Inbound ATU Limit Register 0 - IALR0......................................................

169

2.14.29Inbound ATU Translate Value Register 0 - IATVR0.....................................

170

2.14.30Inbound ATU Upper Translate Value Register 0 - IAUTVR0..........................

170

2.14.31Inbound ATU Limit Register 1 - IALR1......................................................

171

2.14.32Inbound ATU Translate Value Register 1 - IATVR1.....................................

172

2.14.33Inbound ATU Upper Translate Value Register 1 - IAUTVR1..........................

172

2.14.34Inbound ATU Limit Register 2 - IALR2......................................................

173

2.14.35Inbound ATU Translate Value Register 2 - IATVR2.....................................

174

2.14.36Inbound ATU Upper Translate Value Register 2 - IAUTVR2..........................

174

2.14.37Expansion ROM Limit Register - ERLR ......................................................

175

2.14.38Expansion ROM Translate Value Register - ERTVR .....................................

176

2.14.39Expansion ROM Upper Translate Value Register - ERUTVR ..........................

176

2.14.40ATU Configuration Register - ATUCR........................................................

177

2.14.41PCI Configuration and Status Register - PCSR...........................................

178

2.14.42ATU Interrupt Status Register - ATUISR...................................................

181

2.14.43ATU Interrupt Mask Register - ATUIMR ....................................................

183

2.14.44VPD Capability Identifier Register - VPD_Cap_ID.......................................

185

2.14.45VPD Next Item Pointer Register - VPD_Next_Item_Ptr ...............................

185

2.14.46VPD Address Register - VPDAR ...............................................................

186

2.14.47 VPD Data Register - VPDDR...................................................................

186

2.14.48PM Capability Identifier Register - PM_Cap_ID ..........................................

187

2.14.49PM Next Item Pointer Register - PM_Next_Item_Ptr...................................

187

2.14.50ATU Power Management Capabilities Register - APMCR ..............................

188

2.14.51ATU Power Management Control/Status Register - APMCSR........................

189

2.14.52ATU Scratch Pad Register - ATUSPR ........................................................

190

2.14.53PCI-X Capability Identifier Register - PCI-X_Cap_ID ..................................

190

2.14.54PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr...........................

191

2.14.55PCI-X Command Register - PCIXCMD ......................................................

191

2.14.56PCI-X Status Register - PCIXSR ..............................................................

193

2.14.57ECC Control and Status Register - ECCCSR...............................................

195

2.14.58ECC First Address Register - ECCFAR.......................................................

198

2.14.59ECC Second Address Register - ECCSAR ..................................................

199

2.14.60ECC Attribute Register - ECCAR ..............................................................

200

2.14.61CompactPCI Hot-Swap Capability ID Register ...........................................

200

2.14.62Offset EDh: HS_NXTP - Next Item Pointer ................................................

201

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

 

 

October 2007

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Order Number: 317805-001US

Contents—Intel® 413808 and 413812

2.14.63HS_CNTRL - Hot-Swap Control/Status Register ........................................

202

2.14.64Inbound ATU Base Address Register 3 - IABAR3 .......................................

204

2.14.65Inbound ATU Upper Base Address Register 3 - IAUBAR3 ............................

205

2.14.66Inbound ATU Limit Register 3 - IALR3 .....................................................

206

2.14.67Inbound ATU Translate Value Register 3 - IATVR3 ....................................

207

2.14.68Inbound ATU Upper Translate Value Register 3 - IAUTVR3 .........................

207

2.14.69Outbound I/O Base Address Register - OIOBAR ........................................

208

2.14.70Outbound I/O Window Translate Value Register - OIOWTVR.......................

209

2.14.71Outbound Upper Memory Window Base Address Register 0 - OUMBAR0 .......

210

2.14.72Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0

211

 

2.14.73Outbound Upper Memory Window Base Address Register 1 - OUMBAR1 .......

212

2.14.74Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1

213

 

2.14.75Outbound Upper Memory Window Base Address Register 2 - OUMBAR2 .......

214

2.14.76Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2

215

 

2.14.77Outbound Upper Memory Window Base Address Register 3 - OUMBAR3 .......

216

2.14.78Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3

217

 

2.14.79Outbound Configuration Cycle Address Register - OCCAR...........................

218

2.14.80Outbound Configuration Cycle Data Register - OCCDR ...............................

219

2.14.81Outbound Configuration Cycle Function Number - OCCFN ..........................

219

2.14.82PCI Interface Error Control and Status Register - PIECSR...........................

220

2.14.83PCI Interface Error Address Register - PCIEAR..........................................

221

2.14.84PCI Interface Error Upper Address Register - PCIEUAR ..............................

222

2.14.85PCI Interface Error Context Address Register — PCIECAR ..........................

223

2.14.86Internal Arbiter Control Register - IACR...................................................

224

2.14.87Multi-Transaction Timer - MTT................................................................

225

2.14.88PCIX RCOMP Control Register — PRCR ....................................................

226

2.14.89PCIX Pad ODT Drive Strength Manual Override Values

Registers — PPODSMOVR

227

 

2.14.90PCIX PAD DRIVE STRENGTH Manual Override Values ........

Register (3.3 V/1.5 V

Switch Supply Voltage) — PPDSMOVR3.3_1.5228

 

2.14.91PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated Supply Voltage) — PPDSMOVR3.3229

3.0 Address Translation Unit (PCI Express)........................................................................

 

230

3.1

Overview .......................................................................................................

 

 

230

3.2

PCI Express Link Characteristics ........................................................................

 

233

3.3

ATU Address Translation ..................................................................................

 

234

 

3.3.1

Inbound Transactions ...........................................................................

 

237

 

 

3.3.1.1

Inbound Address Translation ....................................................

 

237

 

 

3.3.1.2

Inbound Memory Write Transaction ...........................................

 

240

 

 

3.3.1.3

Inbound Memory Read Transaction ...........................................

 

241

 

 

3.3.1.4 Inbound I/O Cycle Translation ..................................................

 

242

 

 

3.3.1.5 Inbound Configuration Cycle Translation (ID Routed)...................

 

242

 

 

3.3.1.6 Inbound Vendor_Defined Message Transactions ..........................

 

243

 

3.3.2

Outbound Transactions .........................................................................

 

244

 

 

3.3.2.1 Outbound Address Translation - Internal Bus Transactions............

245

 

 

3.3.2.2 Outbound Address Translation Windows.....................................

 

246

 

 

3.3.2.3

Outbound DMA Transactions.....................................................

 

250

 

 

3.3.2.4

Outbound Function Number......................................................

 

250

 

3.3.3

Outbound Write Transaction ..................................................................

 

251

 

3.3.4

Outbound Read Transaction ...................................................................

 

252

 

3.3.5

Outbound Configuration Cycle Translation................................................

 

253

 

 

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

 

 

 

Developer’s Manual

Order Number: 317805-001US

 

 

7

Intel® 413808 and 413812—Contents

 

 

3.3.5.1

Outbound Configuration Cycle Error Conditions............................

253

 

 

3.3.5.2

Outbound Configuration Completions with Retry Status (CRS) .......

253

 

 

3.3.5.3

Outbound PCI Express Message Transactions ..............................

254

 

 

3.3.5.4

Completion Timeout Mechanism ................................................

254

3.4

Big Endian Byte Swapping.................................................................................

255

 

3.4.1

Inbound Byte Swapping.........................................................................

255

 

3.4.2

Outbound Byte Swapping.......................................................................

256

3.5

Messaging Unit................................................................................................

 

257

3.6

PCI Express Messages ......................................................................................

258

3.7

Expansion ROM Translation Unit.........................................................................

260

3.8

ATU Queue Architecture....................................................................................

261

 

3.8.1

Inbound Queues ...................................................................................

261

 

 

3.8.1.1

Inbound Posted Queue Structure ...............................................

261

 

 

3.8.1.2

Inbound Non Posted Queue Structure ........................................

262

 

 

3.8.1.3

Inbound Completion Queue Structure ........................................

262

 

 

3.8.1.4

Inbound Transaction Queues Command Translation Summary .......

262

 

3.8.2

Outbound Queues.................................................................................

263

 

 

3.8.2.1

Relaxed Ordering and No Snoop Outbound Request Attributes.......

263

 

3.8.3

Transaction Ordering.............................................................................

264

 

 

3.8.3.1

Transaction Ordering Summary .................................................

267

 

3.8.4

Byte Parity Checking and Generation.......................................................

268

 

 

3.8.4.1

Parity Generation ....................................................................

268

 

 

3.8.4.2

Parity Checking.......................................................................

269

 

 

3.8.4.3

Parity Disabled........................................................................

269

3.9

ATU Error Conditions........................................................................................

270

 

3.9.1

PCI Express Errors ................................................................................

271

 

 

3.9.1.1

Role Based Error Reporting.......................................................

271

 

 

3.9.1.2

Malformed Packets ..................................................................

272

 

 

3.9.1.3

ECRC Check Failed ..................................................................

272

 

 

3.9.1.4

Unsupported Request...............................................................

273

 

 

3.9.1.5

Completer Abort......................................................................

273

 

 

3.9.1.6

Unexpected Completions ..........................................................

273

 

 

3.9.1.7

Poisoned TLP Received .............................................................

274

 

 

3.9.1.8

Completion Timeout ................................................................

274

 

3.9.2

Parity Error on the Internal Bus ..............................................................

275

 

3.9.3

ATU Error Summary..............................................................................

275

3.10

PCI Express Hot-Plug Support ...........................................................................

279

3.11

Reset .............................................................................................................

 

 

280

3.12

Message-Signaled Interrupts .............................................................................

281

 

3.12.1

Legacy Interrupts .................................................................................

281

 

3.12.2

Internal Interrupts ................................................................................

281

3.13

Vital Product Data............................................................................................

282

 

3.13.1

Configuring Vital Product Data Operation .................................................

282

 

3.13.2

Accessing Vital Product Data ..................................................................

283

 

 

3.13.2.1

Reading Vital Product Data .......................................................

283

 

 

3.13.2.2

Writing Vital Product Data ........................................................

284

3.14

Multi-Function Support .....................................................................................

285

 

3.14.1

PCI Express Interface Control Parameters ................................................

285

 

3.14.2

PCI Express Interface Status Reporting....................................................

287

3.15

Root Complex Functionality...............................................................................

288

3.16

Embedded Bridge Functionality..........................................................................

288

3.17

Register Definitions..........................................................................................

289

 

3.17.1

Extended Capabilities Registers ..............................................................

290

 

3.17.2

Internal Bus Addresses..........................................................................

293

 

3.17.3

ATU Vendor ID Register - ATUVID...........................................................

297

 

3.17.4

ATU Device ID Register - ATUDID ...........................................................

297

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

 

October 2007

8

 

 

Order Number: 317805-001US

Contents—Intel® 413808 and 413812

3.17.5

ATU

Command Register - ATUCMD .........................................................

298

3.17.6

ATU

Status Register - ATUSR .................................................................

299

3.17.7

ATU

Revision ID Register - ATURID.........................................................

300

3.17.8

ATU

Class Code Register - ATUCCR.........................................................

300

3.17.9

ATU

Cacheline Size Register - ATUCLSR...................................................

301

3.17.10ATU

Latency Timer Register - ATULT .......................................................

301

3.17.11ATU

Header Type Register - ATUHTR.......................................................

302

3.17.12ATU BIST Register - ATUBISTR...............................................................

303

3.17.13Inbound ATU Base Address Register 0 - IABAR0 .......................................

304

3.17.14Inbound ATU Upper Base Address Register 0 - IAUBAR0 ............................

305

3.17.15Determining Block Sizes for Base Address Registers..................................

306

3.17.16Inbound ATU Base Address Register 1 - IABAR1 .......................................

308

3.17.17Inbound ATU Upper Base Address Register 1 - IAUBAR1 ............................

309

3.17.18Inbound ATU Base Address Register 2 - IABAR2 .......................................

310

3.17.19Inbound ATU Upper Base Address Register 2 - IAUBAR2 ............................

311

3.17.20ATU Subsystem Vendor ID Register - ASVIR ............................................

312

3.17.21ATU Subsystem ID Register - ASIR .........................................................

312

3.17.22Expansion ROM Base Address Register - ERBAR........................................

313

3.17.23ATU Capabilities Pointer Register - ATU_Cap_Ptr.......................................

314

3.17.24ATU Interrupt Line Register - ATUILR ......................................................

315

3.17.25ATU Interrupt Pin Register - ATUIPR .......................................................

316

3.17.26ATU Minimum Grant Register - ATUMGNT ................................................

316

3.17.27ATU Maximum Latency Register - ATUMLAT .............................................

317

3.17.28Inbound ATU Limit Register 0 - IALR0 .....................................................

318

3.17.29Inbound ATU Translate Value Register 0 - IATVR0 ....................................

319

3.17.30Inbound ATU Upper Translate Value Register 0 - IAUTVR0 .........................

319

3.17.31Inbound ATU Limit Register 1 - IALR1 .....................................................

320

3.17.32Inbound ATU Translate Value Register 1 - IATVR1 ....................................

321

3.17.33Inbound ATU Upper Translate Value Register 1 - IAUTVR1 .........................

321

3.17.34Inbound ATU Limit Register 2 - IALR2 .....................................................

322

3.17.35Inbound ATU Translate Value Register 2 - IATVR2 ....................................

323

3.17.36Inbound ATU Upper Translate Value Register 2 - IAUTVR2 .........................

324

3.17.37Expansion ROM Limit Register - ERLR......................................................

324

3.17.38Expansion ROM Translate Value Register - ERTVR .....................................

325

3.17.39Expansion ROM Upper Translate Value Register - ERUTVR..........................

325

3.17.40ATU Configuration Register - ATUCR .......................................................

326

3.17.41PCI Configuration and Status Register - PCSR ..........................................

327

3.17.42ATU Interrupt Status Register - ATUISR ..................................................

329

3.17.43ATU Interrupt Mask Register - ATUIMR....................................................

332

3.17.44PCI Express Message Control/Status Register - PEMCSR ............................

333

3.17.45PCI Express Link Control/Status Register - PELCSR ...................................

334

3.17.46VPD Capability Identifier Register - VPD_Cap_ID ......................................

335

3.17.47VPD Next Item Pointer Register - VPD_Next_Item_Ptr...............................

335

3.17.48VPD Address Register - VPDAR...............................................................

336

3.17.49VPD Data Register - VPDDR ...................................................................

336

3.17.50PM Capability Identifier Register - PM_Cap_ID..........................................

337

3.17.51PM Next Item Pointer Register - PM_Next_Item_Ptr ..................................

337

3.17.52ATU Power Management Capabilities Register - APMCR..............................

338

3.17.53ATU Power Management Control/Status Register - APMCSR .......................

339

3.17.54ATU Scratch Pad Register - ATUSPR........................................................

340

3.17.55PCI Express Capability List Register - PCIE_CAPID ....................................

340

3.17.56PCI Express Next Item Pointer Register - PCIE_NXTP ................................

341

3.17.57PCI Express Capabilities Register - PCIE_CAP ...........................................

342

3.17.58PCI Express Device Capabilities Register - PCIE_DCAP...............................

343

3.17.59PCI Express Device Control Register - PE_DCTL........................................

344

 

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

 

 

Developer’s Manual

Order Number: 317805-001US

 

9

Intel® 413808 and 413812—Contents

3.17.60PCI Express Device Status Register - PE_DSTS .........................................

 

346

3.17.61PCI Express Link Capabilities Register - PE_LCAP ......................................

 

347

3.17.62PCI Express Link Control Register - PE_LCTL ............................................

 

348

3.17.63PCI Express Link Status Register - PE_LSTS .............................................

 

349

3.17.64PCI Express Slot Capabilities Register - PE_SCAP ......................................

 

350

3.17.65PCI Express Slot Control Register - PE_SCR..............................................

 

351

3.17.66PCI Express Slot Status Register - PE_SSTS .............................................

 

352

3.17.67PCI Express Root Control Register - PE_RCR.............................................

 

353

3.17.68PCI Express Root Status Register - PE_RSR..............................................

 

354

3.17.69PCI Express Advanced Error Capability Identifier - ADVERR_CAPID..............

354

3.17.70PCI Express Uncorrectable Error Status - ERRUNC_STS..............................

 

355

3.17.71PCI Express Uncorrectable Error Mask - ERRUNC_MSK...............................

 

356

3.17.72PCI Express Uncorrectable Error Severity - ERRUNC_SEV ...........................

357

3.17.73PCI Express Correctable Error Status - ERRCOR_STS.................................

 

358

3.17.74PCI Express Correctable Error Mask - ERRCOR_MSK ..................................

 

359

3.17.75Advanced Error Control and Capability Register - ADVERR_CTL ...................

360

3.17.76PCI Express Advanced Error Header Log - ADVERR_LOG0 ..........................

360

3.17.77PCI Express Advanced Error Header Log - ADVERR_LOG1 ..........................

361

3.17.78PCI Express Advanced Error Header Log - ADVERR_LOG2 ..........................

361

3.17.79PCI Express Advanced Error Header Log - ADVERR_LOG3 ..........................

362

3.17.80Root Error Command Register - RERR_CMD .............................................

 

362

3.17.81Root Error Status Register .....................................................................

 

363

3.17.82Error Source Identification Register - RERR_ID .........................................

 

364

3.17.83Device Serial Number Capability - DSN_CAP.............................................

 

364

3.17.84Device Serial Number Lower DW Register - DSN_LDW ...............................

 

365

3.17.85Device Serial Number Upper DW Register - DSN_UDW...............................

 

365

3.17.86PCI Express Advisory Error Control Register - PIE_AEC ..............................

 

366

3.17.87Power Budgeting Enhanced Capability Header - PWRBGT_CAPID .................

367

3.17.88Power Budgeting Data Select Register - PWRBGT_DSEL .............................

 

367

3.17.89Power Budgeting Data Register - PWRBGT_DATA ......................................

 

368

3.17.90Power Budgeting Capability Register - PWRBGT_CAP .................................

 

369

3.17.91Power Budgeting Information Registers[0:23]—PWRBGT_INFO[0:23] ..........

370

3.17.92Outbound I/O Base Address Register - OIOBAR.........................................

 

371

3.17.93Outbound I/O Window Translate Value Register - OIOWTVR .......................

372

3.17.94Outbound Upper Memory Window Base Address Register 0 - OUMBAR0........

373

3.17.95Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0

374

 

 

3.17.96Outbound Upper Memory Window Base Address Register 1 - OUMBAR1........

375

3.17.97Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1

376

 

 

3.17.98Outbound Upper Memory Window Base Address Register 2 - OUMBAR2........

377

3.17.99Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2

378

 

 

3.17.100Outbound Upper Memory Window Base Address Register 3 - OUMBAR3 ......

379

3.17.101Outbound Upper 32-bit Memory Window Translate Value Register 3 -

 

OUMWTVR3380

 

 

3.17.102Outbound Configuration Cycle Address Register - OCCAR..........................

381

3.17.103Outbound Configuration Cycle Data Register - OCCDR..............................

 

382

3.17.104Outbound Configuration Cycle Function Number - OCCFN .........................

383

3.17.105Inbound Vendor Message Header Register 0 - IVMHR0 .............................

 

384

3.17.106Inbound Vendor Message Header Register 1 - IVMHR1 .............................

 

385

3.17.107Inbound Vendor Message Header Register 2 - IVMHR2 .............................

 

386

3.17.108Inbound Vendor Message Header Register 3 - IVMHR3 .............................

 

387

3.17.109Inbound Vendor Message Payload Register - IVMPR .................................

 

387

3.17.110Outbound Vendor Message Header Register 0 - OVMHR0 ..........................

388

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

 

Developer’s Manual

October 2007

10

Order Number: 317805-001US

Contents—Intel® 413808 and 413812

 

3.17.111Outbound Vendor Message Header Register 1 - OVMHR1..........................

389

 

3.17.112Outbound Vendor Message Header Register 2 - OVMHR2..........................

390

 

3.17.113Outbound Vendor Message Header Register 3 - OVMHR3..........................

390

 

3.17.114Outbound Vendor Message Payload Register - OVMPR..............................

391

 

3.17.115PCI Interface Error Control and Status Register - PIE_CSR .......................

392

 

3.17.116PCI Interface Error Status - PIE_STS .....................................................

393

 

3.17.117PCI Interface Error Mask - PIE_MSK ......................................................

394

 

3.17.118PCI Interface Error Header Log - PIE_LOG0 ............................................

395

 

3.17.119PCI Interface Error Header Log 1 - PIE_LOG1 .........................................

395

 

3.17.120PCI Interface Error Header Log 2 - PIE_LOG2 .........................................

396

 

3.17.121PCI Interface Error Header Log - PIE_LOG3 ............................................

396

 

3.17.122PCI Interface Error Descriptor Log.........................................................

397

 

3.17.123ATU Reset Control Register - ATURCR....................................................

397

4.0 Messaging Unit.........................................................................................................

398

4.1

Overview .......................................................................................................

398

4.2

Theory of Operation.........................................................................................

399

 

4.2.1

Transaction Ordering ............................................................................

402

4.3

Message Registers...........................................................................................

403

 

4.3.1

Outbound Messages..............................................................................

403

 

4.3.2

Inbound Messages................................................................................

403

4.4

Doorbell Registers ...........................................................................................

404

 

4.4.1

Outbound Doorbells ..............................................................................

404

 

4.4.2

Inbound Doorbells ................................................................................

404

4.5

Messaging Unit Error Conditions ........................................................................

405

4.6

Message-Signaled Interrupts.............................................................................

406

 

4.6.1

MSI Capability Structure .......................................................................

406

 

4.6.2

MSI-X Capability and Table Structures ....................................................

407

 

4.6.3

Level-Triggered Versus Edge-Triggered Interrupts ....................................

409

4.7

Register Definitions .........................................................................................

410

 

4.7.1

Inbound Message Register - IMRx...........................................................

412

 

4.7.2

Outbound Message Register - OMRx .......................................................

412

 

4.7.3

Inbound Doorbell Register - IDR.............................................................

413

 

4.7.4

Inbound Interrupt Status Register - IISR .................................................

414

 

4.7.5

Inbound Interrupt Mask Register - IIMR ..................................................

415

 

4.7.6

Outbound Doorbell Register - ODR..........................................................

416

 

4.7.7

Outbound Interrupt Status Register - OISR..............................................

417

 

4.7.8

Outbound Interrupt Mask Register - OIMR ...............................................

418

 

4.7.9

Inbound Reset Control and Status Register - IRCSR ..................................

419

 

4.7.10

Outbound Reset Control and Status Register - ORCSR ...............................

420

 

4.7.11

MSI Inbound Message Register — MIMR ..................................................

421

 

4.7.12

MU Configuration Register - MUCR..........................................................

422

 

4.7.13

MU Base Address Register - MUBAR ........................................................

423

 

4.7.14

MU Upper Base Address Register - MUUBAR.............................................

424

 

4.7.15

MU MSI-X Table Message Address Registers - M_MT_MAR[0:7] ..................

425

 

4.7.16

MU MSI-X Table Message Upper Address Registers - M_MT_MUAR[0:7] .......

426

 

4.7.17

MU MSI-X Table Message Data Registers - M_MT_MDR[0:7].......................

427

 

4.7.18

MU MSI-X Table Message Vector Control Registers - M_MT_MVCR[0:7]........

428

 

4.7.19

MU MSI-X Pending Bits Array Register - M_MPBAR....................................

429

 

4.7.20

MSI Capability Identifier Register - Cap_ID ..............................................

429

 

4.7.21

MSI Next Item Pointer Register - MSI_Next_Ptr........................................

430

 

4.7.22

Message Control Register - Message_Control ...........................................

431

 

4.7.23

Message Address Register - Message_Address..........................................

432

 

4.7.24

Message Upper Address Register - Message_Upper_Address ......................

433

 

4.7.25

Message Data RegisterMessage_Data ...................................................

434

 

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

 

Developer’s Manual

Order Number: 317805-001US

11

Intel® 413808 and 413812—Contents

 

 

4.7.26

MSI-X Capability Identifier Register - MSI-X_Cap_ID .................................

435

 

 

4.7.27

MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr..........................

436

 

 

4.7.28

MSI-X Message Control Register - MSI-X_MCR..........................................

437

 

 

4.7.29

MSI-X Table Offset Register — MSI-X_Table_Offset ...................................

438

 

 

4.7.30

MSI-X Pending Bit Array Offset Register - MSI-X_PBA_Offset......................

439

 

 

4.7.31

MU MSI-X Control Register X — MMCRx ...................................................

440

 

 

4.7.32

Inbound MSI Interrupt Pending Register x — IMIPRx .................................

441

 

4.8

Power/Default Status .......................................................................................

441

5.0

SRAM DMA Unit (SDMA) ............................................................................................

442

 

5.1

Introduction....................................................................................................

442

 

5.2

Overview........................................................................................................

442

 

5.3

Theory of Operation .........................................................................................

443

 

 

5.3.1

Interrupt Control for SDMA ....................................................................

445

 

5.4

Register Definitions..........................................................................................

446

 

 

5.4.1

LocalToHost Destination Lower Address Register - L2H_DLAR .....................

447

 

 

5.4.2

LocalToHost Destination Upper Address Register - L2H_DUAR.....................

447

 

 

5.4.3

LocalToHost Source Lower Address Register - L2H_SLAR............................

448

 

 

5.4.4

LocalToHost Byte Count Register - L2H_BCR.............................................

449

 

 

5.4.5

LocalToHost Interrupt Counter/Acknowledge Register L2H_ICAR .................

450

 

 

5.4.6

LocalToHost Control/Status Register - L2H_CSR........................................

451

 

 

5.4.7

LocalToHost Byte Swap Control Register - L2H_BSCR ................................

452

 

 

5.4.8

HostToLocal Destination Lower Address Register - H2L_DLAR .....................

452

 

 

5.4.9

HostToLocal Source Upper Address Register - H2L_SUAR ...........................

453

 

 

5.4.10

HostToLocal Source Lower Address Register - H2L_SLAR............................

453

 

 

5.4.11

HostToLocal Byte Count Register - H2L_BCR.............................................

454

 

 

5.4.12

HostToLocal Interrupt Counter/Acknowledge Register - H2L_ICAR ...............

455

 

 

5.4.13

HostToLocal Control/Status Register - H2L_CSR........................................

456

 

 

5.4.14

HostToLocal Byte Swap Control Register - H2L_BSCR ................................

457

6.0

SGPIO Unit ..............................................................................................................

 

458

 

6.1

Overview........................................................................................................

458

 

6.2

Theory of Operation .........................................................................................

460

 

 

6.2.1

SGPIO SClock Output Signal...................................................................

460

 

 

6.2.2

SGPIO SLoad Output Signal ...................................................................

460

 

 

6.2.3

SDataOut ............................................................................................

461

 

 

6.2.4

SGPIO SDataIn Signal ...........................................................................

461

 

6.3

Clock Requirements .........................................................................................

462

 

6.4

Output Signals ................................................................................................

463

 

 

6.4.1

Protocol Engine Input Signals .................................................................

465

 

 

 

6.4.1.1 JOG Requirements...................................................................

467

 

 

 

6.4.1.2 Protocol Engine Pre-Conditioning Requirements ...........................

467

 

 

6.4.2

Programmable Blink Patterns .................................................................

468

 

6.5 SGPIO Unit Mode of Operations .........................................................................

469

 

 

6.5.1

Pin Multiplexing ....................................................................................

472

 

6.6

Register Definitions..........................................................................................

474

 

 

6.6.1

SGPIO Interface Control Register x — SGICRx ..........................................

475

 

 

6.6.2

SGPIO Programmable Blink Register x — SGPBRx .....................................

476

 

 

6.6.3

SGPIO Start Drive Lower Register x — SGSDLRx.......................................

478

 

 

6.6.4

SGPIO Start Drive Upper Register x — SGSDURx ......................................

480

 

 

6.6.5

SGPIO Serial Input Data Lower Register x — SGSIDLRx .............................

482

 

 

6.6.6

SGPIO Serial Input Data Upper Register x — SGSIDURx.............................

483

 

 

6.6.7

SGPIO Vendor Specific Code Register x — SGVSCRx..................................

483

 

 

6.6.8

SGPIO Output Data Select Register[0:7] x — SGODSR[0:7]x......................

484

7.0 System Controller (SC) and Internal Bus Bridge ............................................................

485

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

 

October 2007

12

 

 

Order Number: 317805-001US

Contents—Intel® 413808 and 413812

7.1

Overview .......................................................................................................

 

 

485

7.2

Theory of Operation.........................................................................................

 

486

 

7.2.1

System Controller ................................................................................

 

486

 

7.2.2

Internal Bus Requester IDs....................................................................

487

 

7.2.3

Parity Testing ......................................................................................

 

488

7.3

Internal Bus Bridge..........................................................................................

 

490

 

7.3.1

Theory of Operation..............................................................................

 

490

 

7.3.2

Internal Bus Commands ........................................................................

491

 

7.3.3

Transaction Queues ..............................................................................

 

491

 

7.3.4

Bridge Memory Window.........................................................................

492

 

7.3.5

Ordering and Passing Rules ...................................................................

493

 

 

7.3.5.1

Strong Ordering Rule Requirements ..........................................

493

 

7.3.6

Parity Support .....................................................................................

 

494

 

 

7.3.6.1

Address Parity Generation........................................................

494

 

 

7.3.6.2

Address Parity Checking ..........................................................

494

 

 

7.3.6.3 Data Parity on Outbound Transactions .......................................

494

 

 

7.3.6.4 Data Parity on Inbound Transactions .........................................

494

 

7.3.7

Error Detection and Handling .................................................................

495

 

 

7.3.7.1 Bridge North Internal Bus Interface Error ...................................

495

 

 

7.3.7.2 Bridge South Internal Bus Interface Error...................................

496

7.4

System Controller Register Definitions................................................................

497

7.5 Internal Bus Bridge Register Definitions..............................................................

498

 

7.5.1

Internal Bus Arbitration Control Register — IBACR ....................................

499

 

7.5.2

South Internal Bus Address Test Control Register — SIBATCR ....................

501

 

7.5.3

South Internal Bus Data Test Control Register — SIBDTCR ........................

502

 

7.5.4

Peripheral Memory-Mapped Register Base Address Register — PMMRBAR.....

503

 

7.5.5

Determining Block Sizes for Memory Windows..........................................

504

 

7.5.6

Bridge Window Base Address Register — BWBAR......................................

505

 

7.5.7

Bridge Window Upper Base Address Register — BWUBAR...........................

506

 

7.5.8

Bridge Window Limit Register — BWLR ....................................................

507

 

7.5.9

Bridge Error Control and Status Register — BECSR ...................................

508

 

7.5.10

Bridge Error Address Register — BERAR ..................................................

510

 

7.5.11

Bridge Error Upper Address Register — BERUAR .......................................

510

8.0 SRAM Memory Controller ...........................................................................................

 

511

8.1

Overview .......................................................................................................

 

 

511

8.2

Glossary ........................................................................................................

 

 

512

8.3

Theory of Operation.........................................................................................

 

513

 

8.3.1

Functional Block...................................................................................

 

513

 

 

8.3.1.1

North Internal Bus Ports ..........................................................

513

 

 

8.3.1.2

Address Decode Blocks ............................................................

514

 

 

 

8.3.1.2.1 SRAM Memory Array Space .............................................

514

 

 

 

8.3.1.2.2

Memory-Mapped Register Space......................................

514

 

 

 

8.3.1.2.3 North Internal Bus Port Address Decode ..........................

514

 

 

8.3.1.3

Memory Transaction Queues ....................................................

514

 

 

 

8.3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ) .....

514

 

 

8.3.1.4

Configuration Registers............................................................

514

 

 

8.3.1.5

SRAM Control Block.................................................................

514

 

 

 

8.3.1.5.1 SRAM State Machine and Pipeline Queues......................

514

 

 

 

8.3.1.5.2

Error Correction Logic .......................................................

515

 

 

8.3.1.6 North Internal Bus Port Transaction Ordering..............................

516

 

 

8.3.1.7

SMCU Port Coherency..............................................................

516

 

8.3.2

SRAM Memory Interface Support............................................................

517

 

 

8.3.2.1

SRAM Initialization ..................................................................

517

 

 

8.3.2.2

SRAM Read Sequence..............................................................

517

 

 

8.3.2.3

SRAM Write Sequence .............................................................

518

 

 

 

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

 

 

 

Developer’s Manual

Order Number: 317805-001US

 

 

13

Intel® 413808 and 413812—Contents

 

 

8.3.3

Error Correction and Detection ...............................................................

 

519

 

 

 

8.3.3.1

ECC Generation.......................................................................

 

520

 

 

 

8.3.3.2 ECC Generation for Partial Writes ..............................................

 

521

 

 

 

8.3.3.3

ECC Checking .........................................................................

 

522

 

 

 

8.3.3.4

Scrubbing ..............................................................................

 

526

 

 

 

 

8.3.3.4.1 ECC Example Using the H-Matrix.....................................

 

526

 

 

 

8.3.3.5

ECC Disabled ..........................................................................

 

527

 

 

 

8.3.3.6

ECC Testing............................................................................

 

527

 

 

8.3.4

Byte Parity Checking and Generation.......................................................

 

528

 

 

 

8.3.4.1

Parity Generation ....................................................................

 

529

 

 

 

8.3.4.2

Parity Checking.......................................................................

 

530

 

 

 

8.3.4.3

Parity Disabled........................................................................

 

530

 

 

 

8.3.4.4

Parity Testing .........................................................................

 

530

 

8.4

ECC Interrupts/Error Conditions.........................................................................

 

531

 

 

8.4.1

Single-Bit Error Detection ......................................................................

 

532

 

 

8.4.2

Multi-bit Error Detection ........................................................................

 

533

 

8.5

Parity Interrupts/Error Conditions ......................................................................

 

534

 

8.6

Register Definitions..........................................................................................

 

535

 

 

8.6.1

SRAM Base Address Register — SRAMBAR................................................

 

536

 

 

8.6.2

SRAM Upper Base Address Register — SRAMUBAR ....................................

 

536

 

 

8.6.3

SRAM ECC Control Register — SECR........................................................

 

536

 

 

8.6.4

SRAM ECC Log Register — SELOGR .........................................................

 

538

 

 

8.6.5

SRAM ECC Address Register — SEAR.......................................................

 

540

 

 

8.6.6

SRAM ECC Context Address Register — SECAR .........................................

 

540

 

 

8.6.7

SRAM ECC Test Register — SECTST.........................................................

 

541

 

 

8.6.8

SRAM Parity Control and Status Register — SPARCSR ................................

 

542

 

 

8.6.9

SRAM Parity Address Register — SPAR.....................................................

 

543

 

 

8.6.10

SRAM Parity Upper Address Register — SPUAR .........................................

 

543

 

 

8.6.11

SRAM Memory Controller Interrupt Status Register — SMCISR

.................... 544

9.0

Peripheral Bus Interface Unit ......................................................................................

 

545

 

9.1

Overview........................................................................................................

 

 

546

 

9.2

Peripheral Bus Signals ......................................................................................

 

547

 

 

9.2.1

Address Signal Definitions......................................................................

 

547

 

 

9.2.2

Data Signal Definitions ..........................................................................

 

547

 

 

9.2.3

Control/Status Signal Definitions.............................................................

 

547

 

 

9.2.4

Bus Width............................................................................................

 

548

 

 

9.2.5

Detailed Signal Descriptions ...................................................................

 

549

 

 

9.2.6

Flash Memory Support...........................................................................

 

550

 

 

 

9.2.6.1

Flash Read Cycle .....................................................................

 

551

 

 

 

9.2.6.2

Flash Write Cycle ....................................................................

 

553

 

9.3

Register Definitions..........................................................................................

 

554

 

 

9.3.1

PBI Control Register — PBCR..................................................................

 

555

 

 

9.3.2

PBI Status Register — PBISR..................................................................

 

555

 

 

9.3.3

Determining Block Sizes for Memory Windows ..........................................

 

556

 

 

9.3.4

PBI Base Address Register 0 — PBBAR0...................................................

 

557

 

 

9.3.5

PBI Limit Register 0 — PBLR0.................................................................

 

558

 

 

9.3.6

PBI Base Address Register 1 — PBBAR1...................................................

 

559

 

 

9.3.7

PBI Limit Register 1 — PBLR1.................................................................

 

560

 

 

9.3.8

PBI Drive Strength Control Register — PBDSCR ........................................

 

561

 

 

9.3.9

Processor Frequency Register - PFR.........................................................

 

562

 

 

9.3.10

External Strap Status Register 0 — ESSTSR0............................................

 

563

 

 

9.3.11

Unique ID Register 0 — UID0 .................................................................

 

564

 

 

9.3.12

Unique ID Register 1 — UID1 .................................................................

 

564

10.0

Interrupt Controller Unit

............................................................................................

 

565

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

 

Developer’s Manual

 

 

 

October 2007

14

 

 

 

 

Order Number: 317805-001US

Contents—Intel® 413808 and 413812

10.1

Overview .......................................................................................................

 

565

10.2

Theory of Operation.........................................................................................

566

 

10.2.1

Interrupt Controller Unit........................................................................

566

10.3

The Intel XScale® Processor Exceptions Architecture............................................

567

 

10.3.1

CPSR and SPSR....................................................................................

567

 

10.3.2

The Exception Process ..........................................................................

567

 

10.3.3

Exception Priorities and Vectors..............................................................

568

 

10.3.4

Software Requirements For Exception Handling ........................................

568

 

 

10.3.4.1 Nesting FIQ and IRQ Exceptions................................................

568

10.4

Intel® 413808 and 413812 I/O Controllers in TPER Mode External Interrupt Interface ....

 

569

 

 

 

 

10.4.1

Interrupt Inputs ...................................................................................

569

 

10.4.2

Outbound Interrupts .............................................................................

571

10.5

The Intel® 413808 and 413812 I/O Controllers in TPER Mode Interrupt Controller Unit ...

 

572

 

 

 

 

10.5.1

Programmer Model ...............................................................................

573

 

 

10.5.1.1

Active Interrupt Source Control and Status.................................

573

 

 

10.5.1.2

Prioritization and Vector Generation for Active Interrupt Sources ...

573

 

10.5.2

Operational Blocks................................................................................

575

10.5.3Intel® 413808 and 413812 I/O Controllers in TPER Mode: Internal Peripheral Interrupt576

 

 

10.5.3.1

Normal Interrupt Sources.........................................................

577

 

 

10.5.3.2

Error Interrupt Sources............................................................

578

 

10.5.4

High-Priority Interrupt (HPI#)...............................................................

579

 

10.5.5

Timer Interrupts ..................................................................................

579

 

10.5.6

Inter-Processor Interrupts .....................................................................

579

 

10.5.7

Intel XScale® Processor Interrupts .........................................................

579

 

10.5.8

Software Interrupts ..............................................................................

579

10.6

Default Status.................................................................................................

 

580

10.7

Interrupt Control Unit Registers.........................................................................

581

 

10.7.1

Interrupt Base Register — INTBASE ........................................................

583

 

10.7.2

Interrupt Size Register — INTSIZE..........................................................

584

 

10.7.3

IRQ Interrupt Vector Register — IINTVEC ................................................

585

 

10.7.4

FIQ Interrupt Vector Register — FINTVEC ................................................

586

 

10.7.5

Interrupt Pending Register 0 — INTPND0.................................................

587

 

10.7.6

Interrupt Pending Register 1 — INTPND1.................................................

588

 

10.7.7

Interrupt Pending Register 2 — INTPND2.................................................

589

 

10.7.8

Interrupt Pending Register 3 — INTPND3.................................................

590

 

10.7.9

Interrupt Control Register 0 — INTCTL0 ..................................................

591

 

10.7.10Interrupt Control Register 1 — INTCTL1 ..................................................

593

 

10.7.11Interrupt Control Register 2 — INTCTL2 ..................................................

595

 

10.7.12Interrupt Control Register 3 — INTCTL3 ..................................................

596

 

10.7.13Interrupt Steering Register 0 — INTSTR0 ................................................

598

 

10.7.14Interrupt Steering Register 1 — INTSTR1 ................................................

600

 

10.7.15Interrupt Steering Register 2 — INTSTR2 ................................................

602

 

10.7.16Interrupt Steering Register 3 — INTSTR3 ................................................

603

 

10.7.17IRQ Interrupt Source Register 0 — IINTSRC0...........................................

605

 

10.7.18IRQ Interrupt Source Register 1 — IINTSRC1...........................................

607

 

10.7.19IRQ Interrupt Source Register 2 — IINTSRC2...........................................

609

 

10.7.20IRQ Interrupt Source Register 3 — IINTSRC3...........................................

610

 

10.7.21FIQ Interrupt Source Register 0 — FINTSRC0...........................................

612

 

10.7.22FIQ Interrupt Source Register 1 — FINTSRC1...........................................

614

 

10.7.23FIQ Interrupt Source Register 2 — FINTSRC2...........................................

616

 

10.7.24FIQ Interrupt Source Register 3 — FINTSRC3...........................................

617

 

10.7.25Interrupt Priority Register 0 — IPR0........................................................

619

 

 

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

 

 

 

Developer’s Manual

Order Number: 317805-001US

 

15

Intel® 413808 and 413812—Contents

 

 

10.7.26Interrupt Priority Register 1 — IPR1 ........................................................

620

 

 

10.7.27Interrupt Priority Register 2 — IPR2 ........................................................

621

 

 

10.7.28Interrupt Priority Register 3 — IPR3 ........................................................

622

 

 

10.7.29Interrupt Priority Register 4 — IPR4 ........................................................

623

 

 

10.7.30Interrupt Priority Register 5 — IPR5 ........................................................

624

 

 

10.7.31Interrupt Priority Register 6 — IPR6 ........................................................

625

 

 

10.7.32Interrupt Priority Register 7 — IPR7 ........................................................

626

11.0

Timers.....................................................................................................................

 

 

627

 

11.1

Timer Operation ..............................................................................................

 

628

 

 

11.1.1

Basic Programmable Timer Operation ......................................................

628

 

 

11.1.2

Watch Dog Timer Operation ...................................................................

629

 

 

11.1.3

Load/Store Access Latency for Timer Registers .........................................

630

 

11.2

Timer Interrupts ..............................................................................................

 

631

 

11.3

Timer State Diagram........................................................................................

 

632

 

11.4

Timer Registers ...............................................................................................

 

633

 

 

11.4.1

Power Up/Reset Initialization..................................................................

633

 

 

11.4.2

Timer Mode Registers – TMR0:1 .............................................................

634

 

 

 

11.4.2.1 Bit 0 — Terminal Count Status Bit (TMRx.tc) ...............................

635

 

 

 

11.4.2.2 Bit 1 — Timer Enable (TMRx.enable) ..........................................

635

 

 

 

11.4.2.3 Bit 2 — Timer Auto Reload Enable (TMRx.reload).........................

635

 

 

 

11.4.2.4 Bit 3 — Timer Register Privileged Read/Write Control (TMRx.pri) ... 636

 

 

 

11.4.2.5 Bits 4, 5 — Timer Input Clock Select (TMRx.csel1:0) ....................

636

 

 

11.4.3

Timer Count Register – TCR0:1 ..............................................................

637

 

 

11.4.4

Timer Reload Register – TRR0:1 .............................................................

637

 

 

11.4.5

Timer Interrupt Status Register – TISR....................................................

638

 

 

11.4.6

Watch Dog Timer Control Register – WDTCR ............................................

639

 

 

11.4.7

Watch Dog Timer Setup Register – WDTSR ..............................................

639

 

11.5 Uncommon TCRX and TRRX Conditions ...............................................................

640

12.0

SMBus Interface Unit.................................................................................................

 

641

 

12.1

Overview........................................................................................................

 

641

 

12.2

SMBus Interface ..............................................................................................

 

641

 

12.3

System Management Bus Interface ....................................................................

642

 

 

12.3.1

SMBus Controller..................................................................................

 

643

 

 

 

12.3.1.1 SMBus Commands...................................................................

643

 

 

 

12.3.1.2 Initialization Sequence .............................................................

644

 

 

12.3.2

SMBus Signaling...................................................................................

 

645

 

 

 

12.3.2.1 Overview ...............................................................................

 

645

 

 

 

12.3.2.2 Waveforms.............................................................................

 

645

 

 

 

12.3.2.2.1

Start Phase .......................................................................

645

 

 

 

12.3.2.2.2

Stop Phase........................................................................

646

 

 

 

12.3.2.2.3

ACK/NACK........................................................................

646

 

 

 

12.3.2.2.4

Wait States........................................................................

646

 

 

12.3.3

Architecture .........................................................................................

 

647

 

 

 

12.3.3.1 Data Transfer Examples ...........................................................

649

 

 

 

12.3.3.2 Configuration and Memory Reads ..............................................

649

 

 

 

12.3.3.3 Configuration and Memory Writes ..............................................

652

 

 

12.3.4

Error Handling......................................................................................

 

654

 

 

12.3.5

SMBus Interface Reset ..........................................................................

654

 

12.4

Register Definitions..........................................................................................

 

655

 

 

12.4.1

SMBus Controller Command Register — SM_CMD......................................

655

 

 

12.4.2

SMBus Controller Byte Count Register — SM_BC.......................................

656

 

 

12.4.3

SMBus Controller ADDR3 Register — SM_ADDR3.......................................

656

 

 

12.4.4

SMBus Controller ADDR2 Register — SM_ADDR2.......................................

656

 

 

12.4.5

SMBus Controller ADDR1 Register Number — SM_ADDR1...........................

657

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

 

 

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Order Number: 317805-001US

Contents—Intel® 413808 and 413812

 

 

12.4.6

SMBus Controller ADDR0 Register Number — SM_ADDR0

.......................... 657

 

 

12.4.7

SMBus Controller Data Register — SM_DATA............................................

658

 

 

12.4.8

SMBus Controller Status Register — SM_STS ...........................................

658

13.0

UARTs

.....................................................................................................................

 

 

659

 

13.1 .......................................................................................................

Overview

 

659

 

.......................................................

13.1.1

Compatibility with 16550 and 16750

660

 

13.2 ..........................................................................................

Signal Descriptions

661

 

13.3 .........................................................................................

Theory of Operation

662

 

...............................................................

13.3.1

FIFO Interrupt Mode Operation

663

 

...................................................................

 

13.3.1.1

Receiver Interrupt

663

 

..................................................................

 

13.3.1.2

Transmit Interrupt

663

 

..............................................

13.3.2

Removing Trailing Bytes In Interrupt Mode

664

 

...................................................

 

13.3.2.1

Character Time-out Interrupt

664

 

...................................................................

13.3.3

FIFO Polled Mode Operation

664

 

...............................................................

 

13.3.3.1

Receive Data Service

664

 

.............................................................

 

13.3.3.2

Transmit Data Service

664

 

..................................................................................

13.3.4

Autoflow Control

665

 

.........................................................................

 

13.3.4.1 RTS Autoflow

665

 

.........................................................................

 

13.3.4.2 CTS Autoflow

665

 

.....................................................................

13.3.5

Auto-Baud-Rate Detection

666

 

...................................................................

13.3.6

Manual Baud Rate Selection

667

 

13.4 .......................................................................................

Register Descriptions

668

 

..............................................................

13.4.1

UART x Receive Buffer Register

670

 

..........................................................

13.4.2

UART x Transmit Holding Register

670

 

...........................................................

13.4.3

UART x Interrupt Enable Register

671

 

..................................................

13.4.4

UART x Interrupt Identification Register

672

 

.................................................................

13.4.5

UART x FIFO Control Register

674

 

.................................................................

13.4.6

UART x Line Control Register

676

 

.............................................................

13.4.7

UART x Modem Control Register

678

 

..................................................................

13.4.8

UART x Line Status Register

680

 

..................................................................

13.4.9

UART x Scratchpad Register

684

 

..........................................................................

13.4.10Divisor Latch Registers

685

 

............................................................

13.4.11UART x FIFO Occupancy Register

686

 

........................................................

13.4.12UART x Auto - Baud Control Register

687

 

..........................................................

13.4.13UART x Auto - Baud Count Register

688

14.0

I2C Bus ..............................................................................................Interface Units

 

689

 

14.1 .......................................................................................................

Overview

 

689

 

14.2 .........................................................................................

Theory of Operation

690

 

................................................................................

14.2.1

Operational Blocks

692

 

........................................................................

14.2.2

I2C Bus Interface Modes

694

 

.....................................................................

14.2.3

Start and Stop Bus States

695

 

.....................................................................

 

14.2.3.1 START Condition

696

 

....................................................

 

14.2.3.2 No START or STOP Condition

696

 

......................................................................

 

14.2.3.3 STOP Condition

696

 

14.3 ...........................................................................................

I 2 C Bus Operation

697

 

..........................................................

14.3.1

Data and Addressing Management

697

 

.......................................................

 

14.3.1.1

Addressing a Slave Device

698

 

..................................................................................

14.3.2

I2C Acknowledge

699

 

...........................................................................................

14.3.3

Arbitration

700

 

.......................................................................

 

14.3.3.1

SCL Arbitration

700

 

......................................................................

 

14.3.3.2

SDA Arbitration

701

 

................................................................................

14.3.4

Master Operations

702

 

..................................................................................

14.3.5

Slave Operations

705

 

.............................................................................

14.3.6

General Call Address

707

 

 

 

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

 

 

 

Developer’s Manual

Order Number: 317805-001US

 

17

Intel® 413808 and 413812—Contents

 

14.4

Slave Mode Programming Examples ...................................................................

708

 

 

14.4.1

Initialize Unit .......................................................................................

708

 

 

14.4.2

Write 1 Byte as a Slave .........................................................................

708

 

 

14.4.3

Read 2 Bytes as a Slave ........................................................................

708

 

14.5

Master Programming Examples..........................................................................

709

 

 

14.5.1

Initialize Unit .......................................................................................

709

 

 

14.5.2

Write 1 Byte as a Master........................................................................

709

 

 

14.5.3

Read 1 Byte as a Master ........................................................................

709

 

 

14.5.4

Write 2 Bytes and Repeated Start Read 1 Byte as a Master ........................

710

 

 

14.5.5

Read 2 Bytes as a Master — Send STOP Using the Abort ............................

711

 

14.6

Glitch Suppression Logic ...................................................................................

712

 

14.7

Reset Conditions..............................................................................................

713

 

14.8

Register Definitions..........................................................................................

714

 

 

14.8.1

I2C Control Register x — ICRx ................................................................

715

 

 

14.8.2

I2C Status Register x — ISRx .................................................................

717

 

 

14.8.3

I2C Slave Address Register x — ISARx.....................................................

719

 

 

14.8.4

I2C Data Buffer Register x — IDBRx ........................................................

720

 

 

14.8.5

I2C Bus Monitor Register x — IBMRx .......................................................

721

 

 

14.8.6

I2C Manual Bus Control Register x — IMBCRx ...........................................

722

15.0

General Purpose I/O Unit ...........................................................................................

723

 

15.1

General Purpose Input Output Support ...............................................................

723

 

 

15.1.1

General Purpose Inputs .........................................................................

723

 

 

15.1.2

General Purpose Outputs .......................................................................

723

 

 

15.1.3

Reset Initialization of General Purpose I/O Function...................................

723

 

15.2

Register Definitions..........................................................................................

724

 

 

15.2.1

GPIO Output Enable Register — GPOE .....................................................

725

 

 

15.2.2

GPIO Input Data Register — GPID...........................................................

726

 

 

15.2.3

GPIO Output Data Register — GPOD........................................................

728

16.0

PMON Unit ..............................................................................................................

 

729

 

16.1

PMON Counters ..............................................................................................

729

 

16.2

Overview........................................................................................................

729

 

 

16.2.1

Clock Counter Control ...........................................................................

730

 

16.3

Definitions ......................................................................................................

731

 

16.4

Data Collection................................................................................................

732

 

 

16.4.1

Time Based Sampling............................................................................

732

 

 

16.4.2

Hardware Event Based Control ...............................................................

734

 

 

16.4.3

Incrementing By More Than 1.................................................................

736

 

 

16.4.4

Queue Analysis.....................................................................................

737

 

16.5

Non-Register-Based Interfaces ..........................................................................

743

 

 

16.5.1

Events Input Port..................................................................................

743

 

 

16.5.2

Output Signals .....................................................................................

743

 

 

 

16.5.2.1 Indicator Output .....................................................................

744

 

 

 

16.5.2.2 Interrupt Output .....................................................................

744

 

 

16.5.3

Internal Bus Addresses..........................................................................

745

 

 

16.5.4

PMON Feature Enable Register - PMONEN ..............................................

746

 

 

16.5.5

PMON Status Register - PMONSTAT.......................................................

746

 

 

16.5.6

PMON Memory Mapped Registers ...........................................................

747

 

 

 

16.5.6.1 PMON Command Register 0-7 - PMON_CMD[0:7] ......................

749

 

 

 

16.5.6.2 PMON Event Register 0-7 - PMON_EVR[0:7] .............................

753

 

 

 

16.5.6.3 PMON Status Register 0-7 - PMON_STS[0:7] ............................

754

 

 

 

16.5.6.4 PMON Data Register 0-7 - PMON_DATA[0:7].............................

756

 

 

16.5.7

PMON Events ......................................................................................

757

 

 

 

16.5.7.1 Null Event ..............................................................................

757

 

 

 

16.5.7.2 Clock Events...........................................................................

758

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

 

October 2007

18

 

 

Order Number: 317805-001US

Contents—Intel® 413808 and 413812

 

 

16.5.7.3

Threshold Events ....................................................................

 

758

 

 

16.5.7.4

PCI Interface Events ...............................................................

 

759

 

 

16.5.7.5

PCI Express Interface Events....................................................

 

760

 

 

16.5.7.6

North Internal Bus Events ........................................................

 

761

 

 

16.5.7.7

South Internal Bus Events........................................................

 

762

17.0 Clocking and Reset ...................................................................................................

 

 

763

17.1

Clocking Overview ...........................................................................................

 

763

 

17.1.1 Clocking Theory of Operation .................................................................

 

764

 

 

17.1.1.1

Clocking Region 1 (PCI Express) ...............................................

 

764

 

 

17.1.1.2

Clocking Region 2 (PCI) ...........................................................

 

764

 

 

 

17.1.1.2.1 Central Resource Mode (PCIX_EP# = ‘1’) ........................

 

765

 

 

 

17.1.1.2.2 cPCI Hot-Swap Mode (PCIX_EP# = ‘0’ and HS_SM# = ‘0’) ...

 

 

 

766

 

 

 

 

 

17.1.1.2.3 End Point Mode (PCIX_EP# = 0 and HS_SM# = 1)..........

766

 

 

 

17.1.1.2.4 Secondary Clock Outputs..................................................

 

767

 

 

17.1.1.3

Clocking Region 3 (Internal Bus)...............................................

 

768

 

 

17.1.1.4

Clocking Region 4 (Peripheral Bus Interface) ..............................

 

768

 

 

17.1.1.5

Clocking Region 5 ...................................................................

 

768

 

 

17.1.1.6

Clocking Region 7 (Intel XScale® Processor)...............................

 

768

 

17.1.2

Clocking Region Summary .....................................................................

 

769

17.2

Reset Overview...............................................................................................

 

 

770

 

17.2.1

Fundamental Reset...............................................................................

 

770

 

17.2.2

Software Reset ....................................................................................

 

771

 

17.2.3

Secondary Bus Reset ............................................................................

 

771

 

17.2.4

PCI Reset

............................................................................................

 

772

 

17.2.5

PCI Express Hot Reset ..........................................................................

 

772

 

17.2.6

WARM_RST# Reset Mechanism ..............................................................

 

772

 

17.2.7

Intel XScale® Processor Reset Mechanism ...............................................

 

773

 

17.2.8

Internal Bus Reset................................................................................

 

774

17.3

Reset Pins ......................................................................................................

 

 

777

17.4

Device Function Select .....................................................................................

 

778

17.5

Reset Strapping Options...................................................................................

 

779

18.0 Test Logic Unit and Testability....................................................................................

 

782

18.1

Overview .......................................................................................................

 

 

782

18.2 IEEE 1149.1 Standard Test Access Port (TAP) .....................................................

 

783

 

18.2.1

TAP Pin Description...............................................................................

 

784

 

 

18.2.1.1

Test Clock (TCK) ....................................................................

 

784

 

 

18.2.1.2

Test Mode Select (TMS) ..........................................................

 

784

 

 

18.2.1.3

Test Data Input (TDI)..............................................................

 

784

 

 

18.2.1.4

Test Data Output (TDO) ..........................................................

 

784

 

 

18.2.1.5 Asynchronous Reset (TRST#) ..................................................

 

784

 

18.2.2

TAP Controller......................................................................................

 

785

 

 

18.2.2.1

Test-Logic-Reset State ............................................................

 

786

 

 

18.2.2.2

Run-Test/Idle State.................................................................

 

786

 

 

18.2.2.3

Select-DR-Scan State ..............................................................

 

786

 

 

18.2.2.4 Capture-DR State ...................................................................

 

786

 

 

18.2.2.5

Shift-DR State ........................................................................

 

787

 

 

18.2.2.6

Exit1-DR State .......................................................................

 

787

 

 

18.2.2.7 Pause-DR State ......................................................................

 

787

 

 

18.2.2.8

Exit2-DR State .......................................................................

 

787

 

 

18.2.2.9 Update-DR State ....................................................................

 

787

 

 

18.2.2.10Select-IR-Scan State ...............................................................

 

788

 

 

18.2.2.11Capture-IR State ....................................................................

 

788

 

 

18.2.2.12Shift-IR State.........................................................................

 

788

 

 

18.2.2.13Exit1-IR State ........................................................................

 

788

 

 

18.2.2.14Pause-IR State .......................................................................

 

788

 

 

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

 

 

 

Developer’s Manual

Order Number: 317805-001US

 

 

19

Intel® 413808 and 413812—Contents

 

 

18.2.2.15Exit2-IR State.........................................................................

789

 

 

18.2.2.16Update-IR State......................................................................

789

 

18.2.3

TAP Controller Registers ........................................................................

790

 

 

18.2.3.1

Instruction Register .................................................................

790

 

 

18.2.3.2

Instructions ............................................................................

791

 

 

18.2.3.3 Boundary-Scan Register...........................................................

792

 

 

18.2.3.4 Bypass Register ......................................................................

792

 

 

18.2.3.5

Device Identification Register....................................................

792

18.3

Definition of Terms ..........................................................................................

793

19.0 Peripheral Registers ..................................................................................................

 

794

19.1

Overview........................................................................................................

 

794

19.2

Accessing Peripheral Memory-Mapped Registers...................................................

795

19.3

Accessing Peripheral Registers Using the Core Coprocessor Register Interface..........

795

19.4

Architecturally Reserved Memory Space..............................................................

795

19.5

Default Memory Space Setup ............................................................................

796

19.6

Peripheral Memory-Mapped Register Address Space .............................................

798

 

19.6.1

Internal Units.......................................................................................

801

 

 

19.6.1.1

Peripheral Bus Interface Unit ....................................................

801

 

 

19.6.1.2 System Controller ...................................................................

802

 

 

19.6.1.3 Internal Bus Bridge..................................................................

802

 

 

19.6.1.4 I/O Pad Control.......................................................................

803

 

 

19.6.1.5 UART 0-1 ...............................................................................

804

 

 

19.6.1.6 GPIO .....................................................................................

805

 

 

19.6.1.7 I2C Bus Interface Unit 0-2 ........................................................

805

 

 

19.6.1.8 Messaging Unit .......................................................................

806

 

 

19.6.1.9 PMON Unit ............................................................................

808

 

19.6.2

Host Interface Units ..............................................................................

809

 

 

19.6.2.1 Address Translation Unit (PCI-X) ...............................................

810

 

 

19.6.2.2 Address Translation Unit (PCI-E) ...............................................

814

19.7

PCI Configuration Space ...................................................................................

819

19.8

Coprocessor Register Space ..............................................................................

819

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

October 2007

20

Order Number: 317805-001US

Contents—Intel® 413808 and 413812

Figures

 

 

1

TPER Architecture Overview ......................................................................................

 

37

2

Intel® 413808 and 413812 I/O Controllers in TPER Mode Functional Block Diagram ..........

43

3

ATU Block Diagram ..................................................................................................

 

51

4

ATU Queue Architecture Block Diagram.......................................................................

 

52

5

Inbound Address Detection........................................................................................

 

57

6

Inbound Translation Example.....................................................................................

 

58

7

4 Gbyte Section 0 of the Internal Bus Memory Map.......................................................

 

68

8

Outbound Address Translation Windows ......................................................................

 

69

9

Inbound Byte Swapping for 32-bit PCI ........................................................................

 

78

10

Inbound Byte Swapping for 64-bit PCI ........................................................................

 

78

11

Outbound Byte Swapping for Transaction with Byte Count of 1.......................................

 

79

12

Outbound Byte Swapping for Transaction with Byte Count of 2.......................................

 

79

13

Outbound Byte Swapping for Transaction with Byte Count of 3 or Larger .........................

 

79

14

PCI-X Initialization Pattern Setting / Drive .................................................................

 

137

15

ATU Interface Configuration Header Format...............................................................

 

139

16

ATU Interface Extended Configuration Header Format (Power Management) ..................

 

140

17

ATU Interface Extended Configuration Header Format (MSI-X Capability) ......................

 

140

18

ATU Interface Extended Configuration Header Format (MSI Capability)..........................

 

141

19

ATU Interface Extended Configuration Header Format (PCI-X Capability Type 1).............

141

20

ATU Extended Configuration Header Format (Compact PCI Hot-Swap Capability) ............

142

21

ATU Interface Extended Configuration Header Format (VPD Capability) .........................

 

142

22

ATU Block Diagram ................................................................................................

 

231

23

ATU Queue Architecture Block Diagram.....................................................................

 

232

24

Inbound Address Detection......................................................................................

 

238

25

Inbound Translation Example...................................................................................

 

239

26

4 Gbyte Section 0 of the Internal Bus Memory Map.....................................................

 

247

27

Outbound Address Translation Windows ....................................................................

 

249

28

Inbound Byte Swapping ..........................................................................................

 

255

29

Outbound Byte Swapping for Transaction with Byte Count of 1.....................................

 

256

30

Outbound Byte Swapping for Transactions with Byte Count of 2 ...................................

 

256

31

Outbound Byte Swapping Transaction with Byte Count of 3 or Larger ............................

 

256

32

ATU Interface Configuration Header Format...............................................................

 

289

33

ATU Interface Extended Configuration Header Format (Power Management) ..................

 

290

34

ATU Interface Extended Configuration Header Format (MSI-X Capability) ......................

 

290

35

ATU Interface Extended Configuration Header Format (MSI Capability)..........................

 

291

36

ATU Interface Extended Configuration Header Format (PCI Express Capability)...............

 

291

37

ATU Interface Extended Configuration Header Format (VPD Capability) .........................

 

291

38

PCI Express Vendor_Defined Message Header............................................................

 

384

39

PCI Memory Map....................................................................................................

 

400

40

Internal Bus Memory Map .......................................................................................

 

401

41

MSI-X Table and PBA Address Mapping Layout relative to the Host Interface..................

 

408

42

MSI-X Table and PBA Address Mapping Layout relative to the Internal Bus.....................

 

409

43

SGPIO Bus Overview ..............................................................................................

 

459

44

SGPIO Repeating Bit Stream....................................................................................

 

460

45

SLoad Signal .........................................................................................................

 

460

46

SDataOut Signal ....................................................................................................

 

461

47

SDataIn Signal ......................................................................................................

 

461

48

Clock Structure......................................................................................................

 

462

49

SGPIO Output OD0 Signal .......................................................................................

 

463

50

SGPIO Output OD1 Signal .......................................................................................

 

464

51

SGPIO Output OD2 Signal .......................................................................................

 

464

52

Output Signal Routing.............................................................................................

 

469

53

Intel® 413808 and 413812 I/O Controllers in TPER Mode SGPIO Unit 0 Pin Mapping .......

472

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

 

21

Intel® 413808 and 413812—Contents

54

4138xx SGPIO Unit 1 Pin Mapping ............................................................................

473

55

Typical Internal Bus System Controller Block Diagram .................................................

488

56Intel® 413808 and 413812 I/O Controllers in TPER Mode SRAM Memory Controller Block Diagram513

57

ECC Write Flow ......................................................................................................

520

58

Intel® 413808 and 413812 I/O Controllers G-Matrix (generates the ECC) .....................

521

59

ECC Read Data Flow ...............................................................................................

523

60

4138xx H-Matrix (indicates the single-bit error location) ..............................................

524

61

Logical Data Access Paths with Parity Protection .........................................................

528

62

The Peripheral Bus Interface Unit..............................................................................

545

63

Data Width and Low Order Address Lines...................................................................

548

64

Sixty-Four Mbyte Flash Memory System ....................................................................

550

65

120 ns Flash Single Transfer Read Cycle ....................................................................

551

66

120 ns Flash Burst Read Cycle..................................................................................

552

67

120 ns Flash Single Write Cycle1 ..............................................................................

553

68

Interrupt Controller Block Diagram (Active Interrupt Source Registers) ..........................

573

69

Interrupt Controller Block Diagram (FIQ/IRQ Interrupt Vector Generation) .....................

574

70

Intel® 413808 and 413812 I/O Controllers in TPER Mode Interrupt Controller Connections ....

 

575

 

71

Programmable Timer Functional Diagram...................................................................

627

72

Timer Unit State Diagram ........................................................................................

632

73

Basic SMBus Transfer Waveform...............................................................................

645

74

Start (S) / Repeat Start (Sr) Signaling ......................................................................

645

75

Stop (P) Signaling ..................................................................................................

646

76

ACK (A) Signaling...................................................................................................

646

77

NACK (N) Signaling.................................................................................................

646

78

DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Enabled) ........

649

79

DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Enabled) ...............

650

80

DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled) ........

650

81

DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Disabled) .......

650

82

DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Disabled)...............

650

83

DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Disabled) .......

651

84

DWORD Memory Read Protocol (SMBus Word Write/(Word, Byte) Read, PEC Enabled) .....

651

85

DWORD Memory Read Protocol (SMBus Word Write/Byte Read, PEC Enabled).................

651

86

DWORD Configuration Write Protocol (SMBus Block Write, PEC Enabled) ........................

652

87

DWORD Memory Write Protocol (SMBus Word Write, PEC Enabled)................................

652

88

DWORD Configuration Write Protocol (SMBus Byte Write, PEC Enabled) .........................

653

89

Example UART Data Frame ......................................................................................

662

90

NRZ Bit Encoding Example – (0100 1011)..................................................................

662

91

I2C Bus Configuration Example.................................................................................

690

92

I2C Bus Interface Unit Block Diagram ........................................................................

692

93

Start and Stop Conditions........................................................................................

695

94

START and STOP Conditions.....................................................................................

696

95

Data Format of First Byte in Master Transaction..........................................................

698

96

Acknowledge on the I2C Bus ....................................................................................

699

97

Clock Synchronization During the Arbitration Procedure ...............................................

700

98

Arbitration Procedure of Two Masters ........................................................................

701

99

Master-Receiver Read from Slave-Transmitter ............................................................

704

100Master-Receiver Read from Slave-Transmitter / Repeated Start /Master-Transmitter Write to Slave-Receiver704

101

A Complete Data Transfer........................................................................................

704

102

Master-Transmitter Write to Slave-Receiver ...............................................................

706

103

Master-Receiver Read to Slave-Transmitter................................................................

706

104Master-Receiver Read to Slave-Transmitter, Repeated START, Master-Transmitter Write to Slave-Receiver706

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

October 2007

22

Order Number: 317805-001US

Contents—Intel® 413808 and 413812

105

General Call Address ..............................................................................................

707

106

Example Block Diagram of Component with Counter ...................................................

729

107

Conceptual Diagram of Counter Array .......................................................................

730

108

Example Block Diagram of Single PMON Counter .......................................................

731

109

Flowchart of Example Commands Sequence...............................................................

732

110

Block Diagram and Waveforms of Time Based Sampling Example .................................

733

111

Block Diagram and Waveforms of Time Based Sampling Example .................................

735

112

Block Diagram & Waveforms of Time Based Sampling Example ....................................

736

113

Block Diagram & Waveforms of Time Based Sampling Example ....................................

737

114

Block Diagram of HOQ Histogram Example ................................................................

740

115

Waveforms of HOQ Histogram Example.....................................................................

741

116

Processing of HOQ Histogram Example......................................................................

742

117

Output from HOQ Histogram Example.......................................................................

742

118

Indicator Tree........................................................................................................

744

119

Intel® 413808 and 413812 I/O Controllers in TPER Mode Clocking Regions Diagram .......

763

120

IEEE 1149.1 Std. Block Diagram ..............................................................................

783

121

Timing of Actions in a TAP Controller State ................................................................

785

122

TAP Controller State Diagram ..................................................................................

785

123

IOP Device ID Register ...........................................................................................

792

124

Intel® 413808 and 413812 I/O Controllers in TPER Mode Memory Address Space ...........

797

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

23

Intel® 413808 and 413812—Contents

Tables

 

1

Intel® 413808 and 413812 I/O Controllers in TPER Mode/Firmware Mapping

....................36

2

Documentation References ........................................................................................

40

3

ATU Command Support .............................................................................................

54

4

Outbound Address Translation Control.........................................................................

68

5

Internal Bus-to-PCI Command Translation for Memory Windows .....................................

70

6

Internal Bus-to-PCI Command Translation for I/O Window .............................................

70

7

Compact PCI Hot-Swap .............................................................................................

80

8

HS_FREQ Encoding ..................................................................................................

81

9

Inbound Queues.......................................................................................................

83

10

Inbound Read Prefetch Data Sizes ..............................................................................

84

11

PCI to Internal Bus Command Translation for All Inbound Transactions ............................

85

12

Outbound Queues.....................................................................................................

86

13

ATU Inbound Data Flow Ordering Rules .......................................................................

87

14

ATU Outbound Data Flow Ordering Rules .....................................................................

88

15

Inbound Transaction Ordering Summary......................................................................

90

16

Outbound Transaction Ordering Summary....................................................................

91

17

Parity Generation .....................................................................................................

92

18

ATU Error Reporting Summary - PCI Interface ............................................................

119

19

ATU Error Reporting Summary - Internal Bus Interface................................................

124

20

PCI-X Interface Control Parameters Usage .................................................................

130

21

PCI-X Host Interface Status Reporting Usage .............................................................

131

22

CR_FREQ[1:0] Encoding........................................................................................

133

23

Device Mode/Frequency Capability Reporting..............................................................

134

24

PCI Bus Frequency Initialization................................................................................

135

25

PCI-X Initialization Pattern.......................................................................................

136

26

Address Translation Unit Registers ............................................................................

143

27

ATU Internal Bus Memory Mapped Register Range Offsets............................................

146

28

PCI-X Pad Registers ................................................................................................

146

29

ATU Vendor ID Register - ATUVID.............................................................................

147

30

ATU Device ID Register - ATUDID .............................................................................

147

31

ATU Command Register - ATUCMD...........................................................................

148

32

ATU Status Register - ATUSR ...................................................................................

149

33

ATU Revision ID Register - ATURID ...........................................................................

151

34

ATU Class Code Register - ATUCCR ...........................................................................

151

35

ATU Cacheline Size Register - ATUCLSR.....................................................................

152

36

ATU Latency Timer Register - ATULT .........................................................................

152

37

ATU Header Type Register - ATUHTR.........................................................................

153

38

ATU BIST Register - ATUBISTR.................................................................................

154

39

Inbound ATU Base Address Register 0 - IABAR0 .........................................................

155

40

Inbound ATU Upper Base Address Register 0 - IAUBAR0 ..............................................

156

41

Inbound ATU Base Address Register 1 - IABAR1 .........................................................

157

42

Inbound ATU Upper Base Address Register 1 - IAUBAR1 ..............................................

158

43

Inbound ATU Base Address Register 2 - IABAR2 .........................................................

159

44

Inbound ATU Upper Base Address Register 2 - IAUBAR2 ..............................................

160

45

ATU Subsystem Vendor ID Register - ASVIR...............................................................

161

46

ATU Subsystem ID Register - ASIR ...........................................................................

161

47

Expansion ROM Base Address Register -ERBAR...........................................................

162

48

ATU Capabilities Pointer Register - ATU_Cap_Ptr.........................................................

163

49

Memory Block Size Read Response ...........................................................................

164

50

ATU Base Registers and Associated Limit Registers .....................................................

165

51

ATU Interrupt Line Register - ATUILR ........................................................................

166

52

ATU Interrupt Pin Register - ATUIPR..........................................................................

167

53

ATU Minimum Grant Register - ATUMGNT ..................................................................

167

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

October 2007

24

Order Number: 317805-001US

Contents—Intel® 413808 and 413812

54

ATU Maximum Latency Register - ATUMLAT ...............................................................

 

168

55

Inbound ATU Limit Register 0 - IALR0.......................................................................

 

169

56

Inbound ATU Translate Value Register 0 - IATVR0 ......................................................

 

170

57

Inbound ATU Upper Translate Value Register 0 - IAUTVR0

...........................................

170

58

Inbound ATU Limit Register 1 - IALR1.......................................................................

 

171

59

Inbound ATU Translate Value Register 1 - IATVR1 ......................................................

 

172

60

Inbound ATU Upper Translate Value Register 1 - IAUTVR1

...........................................

172

61

Inbound ATU Limit Register 2 - IALR2.......................................................................

 

173

62

Inbound ATU Translate Value Register 2 - IATVR2 ......................................................

 

174

63

Inbound ATU Upper Translate Value Register 2 - IAUTVR2

...........................................

174

64

Expansion ROM Limit Register - ERLR .......................................................................

 

175

65

Expansion ROM Translate Value Register - ERTVR.......................................................

 

176

66

Expansion ROM Upper Translate Value Register - ERUTVR

...........................................

176

67

ATU Configuration Register - ATUCR .........................................................................

 

177

68

PCI Configuration and Status Register - PCSR ............................................................

 

178

69

ATU Interrupt Status Register - ATUISR ....................................................................

 

181

70

ATU Interrupt Mask Register - ATUIMR......................................................................

 

183

71

VPD Capability Identifier Register - VPD_Cap_ID ........................................................

 

185

72

VPD Next Item Pointer Register - VPD_Next_Item_Ptr.................................................

 

185

73

VPD Address Register - VPDAR.................................................................................

 

186

74

VPD Data Register - VPDDR.....................................................................................

 

186

75

PM_Capability Identifier Register - PM_Cap_ID...........................................................

 

187

76

PM Next Item Pointer Register - PM_Next_Item_Ptr ....................................................

 

187

77

ATU Power Management Capabilities Register - APMCR ...............................................

 

188

78

ATU Power Management Control/Status Register - APMCSR .........................................

189

79

Scratch Pad Register - ATUSPR ................................................................................

 

190

80

PCI-X_Capability Identifier Register - PCI-X_Cap_ID...................................................

 

190

81

PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr ............................................

 

191

82

PCI-X Command Register - PCIXCMD........................................................................

 

191

83

PCI-X Status Register - PCIXSR ...............................................................................

 

193

84

ECC Control and Status Register - ECCCSR................................................................

 

195

85

ECC First Address Register - ECCFAR ........................................................................

 

198

86

ECC Second Address Register - ECCSAR....................................................................

 

199

87

ECC Attribute Register - ECCAR................................................................................

 

200

88

HS_CAPID - Hot-Swap Cap ID .................................................................................

 

200

89

HS_NXTP - Next Item Pointer ..................................................................................

 

201

90

HS_CNTRL - Hot-Swap Control/Status Register ..........................................................

 

202

91

Inbound ATU Base Address Register 3 - IABAR3.........................................................

 

204

92

Inbound ATU Upper Base Address Register 3 - IAUBAR3..............................................

 

205

93

Inbound ATU Limit Register 3 - IALR3.......................................................................

 

206

94

Inbound ATU Translate Value Register 3 - IATVR3 ......................................................

 

207

95

Inbound ATU Upper Translate Value Register 3 - IAUTVR3

...........................................

207

96

Outbound I/O Base Address Register - OIOBAR..........................................................

 

208

97

Outbound I/O Window Translate Value Register - OIOWTVR.........................................

209

98

Outbound Upper Memory Window Base Address Register

0 - OUMBAR0........................

210

99

Outbound Upper 32-bit Memory Window Translate Value Register 0- OUMWTVR0 ...........

211

100

Outbound Upper Memory Window Base Address Register

1 - OUMBAR1........................

212

101

Outbound Upper 32-bit Memory Window Translate Value Register 1- OUMWTVR1 ...........

213

102

Outbound Upper Memory Window Base Address Register

2- OUMBAR2.........................

214

103

Outbound Upper 32-bit Memory Window Translate Value Register 2- OUMWTVR2 ...........

215

104

Outbound Upper Memory Window Base Address Register

3 - OUMBAR3........................

216

105

Outbound Upper 32-bit Memory Window Translate Value Register 3- OUMWTVR3 ...........

217

106

Outbound Configuration Cycle Address Register - OCCAR ............................................

 

218

107

Outbound Configuration Cycle Data Register - OCCDR.................................................

 

219

108

Outbound Configuration Cycle Function Number Register - OCCFN................................

219

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

 

25

Intel® 413808 and 413812—Contents

109

PCI Interface Error Control and Status Register - PIECSR.............................................

220

110

PCI Interface Error Address Register - PCIEAR............................................................

221

111

PCI Interface Error Upper Address Register - PCIEUAR.................................................

222

112

PCI Interface Error Context Address Register - PCIECAR ..............................................

223

113

Internal Arbiter Control Register - IACR .....................................................................

224

114

Multi-Transaction Timer - MTT..................................................................................

225

115

PCIX RCOMP Control Register - PRCR ........................................................................

226

116

PCIX Pad ODT Drive Strength Manual Override Values Registers - PPODSMOVR ..............

227

117

PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3V/1.5V Switch

 

 

Supply Voltage) — PPDSMOVR3.3_1.5 ......................................................................

228

118

PCIX PAD DRIVE STRENGTH Manual Override Values Register

 

 

(3.3 V Dedicated Supply Voltage) — PPDSMOVR3.3 ....................................................

229

119

Supported Address Spaces and Transaction Types ......................................................

235

120

ATU Command Support ...........................................................................................

236

121

Inbound Vendor_Defined Message Type 0 Response....................................................

243

122

Outbound Address Translation Control.......................................................................

245

123

Internal Bus-to-PCI Command Translation for Memory Windows ...................................

246

124

Internal Bus-to-PCI Command Translation for I/O Window ...........................................

246

125

Supported Message Types .......................................................................................

258

126

Inbound Queues.....................................................................................................

261

127

PCI to Internal Bus Command Translation for All Inbound Transactions ..........................

262

128

Outbound Queues...................................................................................................

263

129

ATU Inbound Data Flow Ordering Rules .....................................................................

264

130

ATU Outbound Data Flow Ordering Rules ...................................................................

265

131

Inbound Transaction Ordering Summary....................................................................

267

132

Outbound Transaction Ordering Summary..................................................................

267

133

Parity Generation ...................................................................................................

268

134

Advisory Error Cases...............................................................................................

271

135

PCI Express Error Summary.....................................................................................

276

137

Internal Bus Error Summary ....................................................................................

278

136

Root Complex Error Summary ..................................................................................

278

138

PCI Express Interface Control Parameters Usage ........................................................

285

139

PCI Express Interface Status Reporting Usage ...........................................................

287

140

ATU Internal Bus Memory Mapped Register Range Offsets............................................

293

141

ATU PCI Configuration Register Space .......................................................................

294

142

ATU Vendor ID Register - ATUVID.............................................................................

297

143

ATU Device ID Register - ATUDID .............................................................................

297

144

ATU Command Register - ATUCMD...........................................................................

298

145

ATU Status Register - ATUSR ...................................................................................

299

146

ATU Revision ID Register - ATURID ...........................................................................

300

147

ATU Class Code Register - ATUCCR ...........................................................................

300

148

ATU Cacheline Size Register - ATUCLSR.....................................................................

301

149

ATU Latency Timer Register - ATULT .........................................................................

301

150

ATU Header Type Register - ATUHTR.........................................................................

302

151

ATU BIST Register - ATUBISTR.................................................................................

303

152

Inbound ATU Base Address Register 0 - IABAR0 .........................................................

304

153

Inbound ATU Upper Base Address Register 0 - IAUBAR0 ..............................................

305

154

Memory Block Size Read Response ...........................................................................

306

155

ATU Base Registers and Associated Limit Registers .....................................................

307

156

Inbound ATU Base Address Register 1 - IABAR1 .........................................................

308

157

Inbound ATU Upper Base Address Register 1 - IAUBAR1 ..............................................

309

158

Inbound ATU Base Address Register 2 - IABAR2 .........................................................

310

159

Inbound ATU Upper Base Address Register 2 - IAUBAR2 ..............................................

311

160

ATU Subsystem Vendor ID Register - ASVIR...............................................................

312

161

ATU Subsystem ID Register - ASIR ...........................................................................

312

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

October 2007

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Order Number: 317805-001US

Contents—Intel® 413808 and 413812

162

Expansion ROM Base Address Register -ERBAR ..........................................................

313

163

ATU Capabilities Pointer Register - ATU_Cap_Ptr ........................................................

314

164

ATU Interrupt Line Register - ATUILR........................................................................

315

165

ATU Interrupt Pin Register - ATUIPR .........................................................................

316

166

ATU Minimum Grant Register - ATUMGNT..................................................................

316

167

ATU Maximum Latency Register - ATUMLAT ...............................................................

317

168

Inbound ATU Limit Register 0 - IALR0.......................................................................

318

169

Inbound ATU Translate Value Register 0 - IATVR0 ......................................................

319

170

Inbound ATU Upper Translate Value Register 0 - IAUTVR0 ...........................................

319

171

Inbound ATU Limit Register 1 - IALR1.......................................................................

320

172

Inbound ATU Translate Value Register 1 - IATVR1 ......................................................

321

173

Inbound ATU Upper Translate Value Register 1 - IAUTVR1 ...........................................

321

174

Inbound ATU Limit Register 2 - IALR2.......................................................................

322

175

Inbound ATU Translate Value Register 2 - IATVR2 ......................................................

323

176

Inbound ATU Upper Translate Value Register 2 - IAUTVR2 ...........................................

324

177

Expansion ROM Limit Register - ERLR .......................................................................

324

178

Expansion ROM Translate Value Register - ERTVR.......................................................

325

179

Expansion ROM Upper Translate Value Register - ERUTVR ...........................................

325

180

ATU Configuration Register - ATUCR .........................................................................

326

181

PCI Configuration and Status Register - PCSR ............................................................

327

182

ATU Interrupt Status Register - ATUISR ....................................................................

329

183

ATU Interrupt Mask Register - ATUIMR......................................................................

332

184

PCI Express Message Control and Status Register - PEMCSR ........................................

333

185

PCI Express Link Control and Status Register - PELCSR ...............................................

334

186

VPD Capability Identifier Register - VPD_Cap_ID ........................................................

335

187

VPD Next Item Pointer Register - VPD_Next_Item_Ptr.................................................

335

188

VPD Address Register - VPDAR.................................................................................

336

189

VPD Data Register - VPDDR.....................................................................................

336

190

PM_Capability Identifier Register - PM_Cap_ID...........................................................

337

191

PM Next Item Pointer Register - PM_Next_Item_Ptr ....................................................

337

192

ATU Power Management Capabilities Register - APMCR ...............................................

338

193

ATU Power Management Control/Status Register - APMCSR .........................................

339

194

Scratch Pad Register - ATUSPR ................................................................................

340

195

PCI Express Capability Identifier Register - PCIE_CAPID ..............................................

340

196

PCI Express Next Item Pointer Register - PCIE_NXTP ..................................................

341

197

PCI Express Capabilities Register PCIE_CAP ...............................................................

342

198

PCI Express Device Capabilities Register - PCIE_DCAP ................................................

343

199

PCI Express Device Control Register - PE_DCTL..........................................................

344

200

PCI Express Device Status Register PE_DSTS.............................................................

346

201

PCI Express Link Capabilities Register - PE_LCAP........................................................

347

202

PCI Express Link Control Register PE_LCTL ................................................................

348

203

PCI Express Link Status Register PE_LSTS.................................................................

349

204

PCI Express Slot Capabilities Register - PE_SCAP........................................................

350

205

PCI Express Slot Control Register PE_SCR .................................................................

351

206

PCI Express Slot Status Register PE_SSTS.................................................................

352

207

PCI Express Root Control Register - PE_RCR ..............................................................

353

208

PCI Express Root Status Register PE_RSR .................................................................

354

209

PCI Express Advanced Error Capability Identifier - ADVERR_CAPID ...............................

354

210

PCI Express Uncorrectable Error Status - ERRUNC_STS ...............................................

355

211

PCI Express Uncorrectable Error Mask - ERRUNC_MSK ................................................

356

212

PCI Express Uncorrectable Error Severity - ERRUNC_SEV ............................................

357

213

PCI Express Correctable Error Status - ERRCOR_STS ..................................................

358

214

PCI Express Correctable Error Mask - ERRCOR_MSK ...................................................

359

215

Advanced Error Control and Capability Register - ADVERR_CTL ....................................

360

216

PCI Express Advanced Error Header Log - ADVERR_LOG0............................................

360

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

27

Intel® 413808 and 413812—Contents

217

PCI Express Advanced Error Header Log - ADVERR_LOG1 ............................................

361

218

PCI Express Advanced Error Header Log - ADVERR_LOG2 ............................................

361

219

PCI Express Advanced Error Header Log - ADVERR_LOG3 ............................................

362

220

Root Error Command Register - RERR_CMD ...............................................................

362

221

Root Error Status Register - RERR_SR .......................................................................

363

222

Error Source Identification Register RERR_ID .............................................................

364

223

Device Serial Number Capability - DSN_CAP...............................................................

364

224

Device Serial Number Lower DW Register - DSN_LDW.................................................

365

225

Device Serial Number Upper DW Register - DSN_UDW ................................................

365

226

PCI Express Advisory Error Control Register PIE_AEC ..................................................

366

227

Power Budgeting Enhanced Capability Header - PWRBGT_CAPID...................................

367

228

Power Budgeting Data Select Register - PWRBGT_DSEL...............................................

367

229

Power Budgeting Data Register - PWRBGT_DATA ........................................................

368

230

Power Budgeting Capability Register - PWRBGT_CAP ...................................................

369

231

Power Budgeting Information Registers[0:23]—PWRBGT_INFO[0:23]............................

370

232

Outbound I/O Base Address Register - OIOBAR ..........................................................

371

233

Outbound I/O Window Translate Value Register - OIOWTVR .........................................

372

234

Outbound Upper Memory Window Base Address Register 0 - OUMBAR0 ........................

373

235

Outbound Upper 32-bit Memory Window Translate Value Register 0- OUMWTVR0............

374

236

Outbound Upper Memory Window Base Address Register 1 - OUMBAR1 ........................

375

237

Outbound Upper 32-bit Memory Window Translate Value Register 1- OUMWTVR1............

376

238

Outbound Upper Memory Window Base Address Register 2- OUMBAR2 .........................

377

239

Outbound Upper 32-bit Memory Window Translate Value Register 2- OUMWTVR2............

378

240

Outbound Upper Memory Window Base Address Register 3 - OUMBAR3 ........................

379

241

Outbound Upper 32-bit Memory Window Translate Value Register 3- OUMWTVR3............

380

242

Outbound Configuration Cycle Address Register - OCCAR .............................................

381

243

Outbound Configuration Cycle Data Register - OCCDR .................................................

382

244

Outbound Configuration Cycle Function Number - OCCFN.............................................

383

245

Inbound Vendor Defined Message Header Register0 - IVMHR0......................................

384

246

Inbound Vendor Defined Message Header Register 1 - IVMHR1.....................................

385

247

Inbound Vendor Defined Message Header Register 2 - IVMHR2.....................................

386

248

Inbound Vendor Defined Message Header Register 3 - IVMHR3.....................................

387

249

Inbound Vendor Defined Message Payload Register - IVMPR.........................................

387

250

Outbound Vendor Defined Message Header Register0 - OVMHR0...................................

388

251

Outbound Vendor Defined Message Header Register 1 - OVMHR1..................................

389

252

Outbound Vendor Defined Message Header Register 2 - OVMHR2..................................

390

253

Outbound Vendor Defined Message Header Register 3 - OVMHR3..................................

390

254

Outbound Vendor Defined Message Payload Register - OVMPR......................................

391

255

PCI Interface Error Control and Status Register - PIE_CSR ...........................................

392

256

PCI Interface Error Status - PIE_STS.........................................................................

393

257

PCI Interface Error Mask - PIE_MSK..........................................................................

394

258

PCI Interface Error Header Log - PIE_LOG0................................................................

395

259

PCI Interface Error Header Log 1 - PIE_LOG1 .............................................................

395

260

PCI Interface Error Header Log 2 - PIE_LOG2 .............................................................

396

261

PCI Interface Error Header Log - PIE_LOG3................................................................

396

262

PCI Interface Error Descriptor Log - PIE_DLOG ...........................................................

397

263

ATU Reset Control Register - ATURCR .......................................................................

397

264

MU Summary.........................................................................................................

401

265

Message Unit Registers ...........................................................................................

411

266

Inbound Message Register - IMRx.............................................................................

412

267

Outbound Message Register - OMRx..........................................................................

412

268

Inbound Doorbell Register - IDR ...............................................................................

413

269

Inbound Interrupt Status Register - IISR ...................................................................

414

270

Inbound Interrupt Mask Register - IIMR.....................................................................

415

271

Outbound Doorbell Register - ODR............................................................................

416

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

October 2007

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Order Number: 317805-001US

Contents—Intel® 413808 and 413812

272

Outbound Interrupt Status Register - OISR................................................................

417

273

Outbound Interrupt Mask Register - OIMR .................................................................

418

274

Inbound Reset Control and Status Register - IRCSR....................................................

419

275

Outbound Reset Control and Status Register - ORCSR.................................................

420

276

MSI Inbound Message Register - MIMR .....................................................................

421

277

MU Configuration Register - MUCR............................................................................

422

278

MU Base Address Register - MUBAR..........................................................................

423

279

MU Upper Base Address Register - MUUBAR ..............................................................

424

280

MU MSI-X Table Message Address Registers - M_MT_MAR [0:7] ...................................

425

281

MU MSI-X Table Message Upper Address Registers - M_MT_MUAR [0:7]........................

426

282

MU MSI-X Table Message Upper Address Registers - M_MT_MUAR [0:7]........................

427

283

MU MSI-X Table Message Vector Control Registers - M_MT_MVCR [0:7] ........................

428

284

MU MSI-X Pending Bits Array Register - M_MPBAR......................................................

429

285

MSI Capability Identifier Register - MSI_Cap_ID.........................................................

429

286

MSI Next Item Pointer Register - MSI_Next_Ptr .........................................................

430

287

Message Control Register - Message_Control .............................................................

431

288

Message Address Register - Message_Address ...........................................................

432

289

Message Upper Address Register - Message_Upper_Address ........................................

433

290

Message Data Register - Message_Data ....................................................................

434

291

MSI-X_Capability Identifier Register - MSI-X_Cap_ID..................................................

435

292

MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr ...........................................

436

293

MSI-X Message Control Register - MSI-X_MCR ...........................................................

437

294

MSI-X Table Offset Register - MSI-X_Table_Offset......................................................

438

295

MSI-X Pending Bit Array Offset Register - MSI-X_PBA Offset ........................................

439

296

MU MSI-X Control Register X — MMCRx ....................................................................

440

297

Inbound MSI Interrupt Pending Registers — IMIPR [0:3] .............................................

441

298

SDMA Controller Unit Registers ................................................................................

446

299

LocalToHost Destination Lower Address Register - L2H_DLAR.......................................

447

300

LocalToHost Destination Upper Address Register - L2H_DUAR ......................................

447

301

LocalToHost Source Lower Address Register - L2H_SLAR .............................................

448

302

LocalToHost Byte Count Register - L2H_BCR..............................................................

449

303

LocalToHost Interrupt Counter/Acknowledge Register - L2H_ICAR ................................

450

304

LocalToHost Control/Status Register - L2H_CSR .........................................................

451

305

LocalToHost Byte Swap Control Register - L2H_BSCR..................................................

452

306

HostToLocal Destination Lower Address Register - H2L_DLAR.......................................

452

307

HostToLocal Source Upper Address Register - H2L_SUAR.............................................

453

308

HostToLocal Source Lower Address Register - H2L_SLAR .............................................

453

309

HostToLocal Byte Count Register - H2L_BCR..............................................................

454

310

HostToLocal Interrupt Counter/Acknowledge Register - H2L_ICAR ................................

455

311

HostToLocal Control/Status Register - H2L_CSR .........................................................

456

312

HostToLocal Byte Swap Control Register - H2L_BSCR..................................................

457

313

SGPIO Input Mapping .............................................................................................

465

314

Example 1: Multiplexer Block Outputs for SGPIO Unit 0 in Direct LED Mode....................

470

315

Example 2: Multiplexer Block Outputs for SGPIO Unit 1 in SGPIO Mode .........................

470

316

SGPIO Unit 0 Multiplexer Block Outputs for Example 2 ................................................

471

317

SGPIO Unit 1 Multiplexer Block Outputs for Example 2 ................................................

471

318

SGPIO Unit 0 Pin Multiplexing ..................................................................................

472

319

SGPIO Unit 1 Pin Multiplexing ..................................................................................

473

320

SGPIO Memory-Mapped Rejecters ............................................................................

474

321

SGPIO Interface Control Register x - SGICRx .............................................................

475

322

SGPIO Programmable Blink Register x - SGPBRx ........................................................

476

323

SGPIO Start Drive Lower Register x — SGSDLRx ........................................................

478

324

SGPIO Start Drive Upper Register x — SGSDURx........................................................

480

325

SGPIO Serial Input Data Lower Register x - SGSIDLRx................................................

482

326

SGPIO Serial Input Data Upper Register x - SGSIDURx ...............................................

483

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

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Intel® 413808 and 413812—Contents

327

SGPIO Vendor Specific Code Register x - SGVSCRx .....................................................

483

328

SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x .........................................

484

329

Intel® 413808 and 413812 I/O Controllers in TPER Mode Initiator IDs ...........................

487

330

Address and Data Parity Testing Initiator IDs .............................................................

489

331

Data Parity Testing Completer IDs ............................................................................

489

332

Bridge supported Internal Bus Commands ................................................................

491

333

Ordering and Passing Rules for both Inbound and Outbound Transactions ......................

493

334

Internal Bus Arbitration Control Register — IBACR ......................................................

499

335

South Internal Bus Address Test Control Register — SIBATCR ......................................

501

336

South Internal Bus Data Test Control Register — SIBDTCR...........................................

502

337

Peripheral Memory-Mapped Register Base Address Register — PMMRBAR .......................

503

338

Memory Block Size Limit Register Value.....................................................................

504

339

Bridge Window Base Address Register — BWBAR ........................................................

505

340

Bridge Window Upper Base Address Register — BWUBAR.............................................

506

341

Bridge Limit Register — BWLR..................................................................................

507

342

Bridge Error Control and Status Register — BECSR......................................................

508

343

Bridge Error Address Register — BERAR ....................................................................

510

344

Bridge Error Upper Address Register — BERUAR .........................................................

510

345

Commonly Used Terms ...........................................................................................

512

346

Syndrome Decoding................................................................................................

522

347

Data Parity Checking/Generation ..............................................................................

529

348

SMCU Error Response .............................................................................................

531

349

Memory Controller Register......................................................................................

535

350

SRAM Base Address Register — SRAMBAR .................................................................

536

351

SRAM Upper Base Address Register — SRAMUBAR ......................................................

536

352

SRAM ECC Control Register — SECR..........................................................................

537

353

SRAM ECC Log Register — SELOG.............................................................................

538

354

SRAM ECC Address Register — SEAR.........................................................................

540

355

SRAM ECC Context Address Register — SECAR ...........................................................

540

356

SRAM ECC Test Register — SECTST ..........................................................................

541

357

SRAM Parity Control and Status Register — SPARCSR..................................................

542

358

SRAM Parity Address Registers — SPAR .....................................................................

543

359

SRAM Parity Upper Address Register — SPUAR ...........................................................

543

360

SRAM Memory Controller Interrupt Status Register — SMCISR......................................

544

361

Bus Signal Descriptions ...........................................................................................

549

362

Flash Wait State Profile Programming1 ......................................................................

552

363

Peripheral Bus Interface Registers ............................................................................

554

364

PBI Control Register — PBCR ...................................................................................

555

365

PBI Status Register — PBISR ...................................................................................

555

366

Memory Block Size Limit Register Values ...................................................................

556

367

PBI Base Address Register 0 — PBBAR0.....................................................................

557

368

PBI Limit Register 0 — PBLR0...................................................................................

558

369

PBI Base Address Register 1 — PBBAR1.....................................................................

559

370

PBI Limit Register 1 — PBLR1...................................................................................

560

371

PBI Drive Strength Control Register — PBDSCR ..........................................................

561

372

Processor Frequency Register - PFR ..........................................................................

562

373

External Strap Status Register 0 — ESSTS0 ...............................................................

563

374

Unique ID Register 0 — UID0 ...................................................................................

564

375

Unique ID Register 1 — UID1 ...................................................................................

564

376

Exception Priorities And Vectors ...............................................................................

568

377

Interrupt Input Pin Descriptions................................................................................

570

378

Interrupt Output Pin Descriptions .............................................................................

571

379

Normal Interrupt Sources ........................................................................................

577

380

Error Interrupt Sources ...........................................................................................

578

381

Default Interrupt Routing and Status Values...............................................................

580

Intel® 413808 and 413812 I/O Controllers in TPER Mode

 

Developer’s Manual

October 2007

30

Order Number: 317805-001US

Contents—Intel® 413808 and 413812

382

Interrupt Controller Co-Processor Register Addresses..................................................

581

383

Interrupt Base Register — INTBASE..........................................................................

583

384

Interrupt Size Register — INTSIZE ...........................................................................

584

385

IRQ Interrupt Vector RegisterIINTVEC ....................................................................

585

386

FIQ Interrupt Vector RegisterFINTVEC ....................................................................

586

387

Interrupt Pending Register 0 — INTPND0 ..................................................................

587

388

Interrupt Pending Register 1 — INTPND1 ..................................................................

588

389

Interrupt Pending Register 2 — INTPND2 ..................................................................

589

390

Interrupt Pending Register 3 — INTPND3 ..................................................................

590

391

Interrupt Control Register 0 — INTCTL0 ....................................................................

591

392

Interrupt Control Register 1 — INTCTL1 ....................................................................

593

393

Interrupt Control Register 2 — INTCTL2 ....................................................................

595

394

Interrupt Control Register 3 — INTCTL3 ....................................................................

596

395

Interrupt Steering Register 0 — INTSTR0 ..................................................................

598

396

Interrupt Steering Register 1 — INTSTR1 ..................................................................

600

397

Interrupt Steering Register 2 — INTSTR2 ..................................................................

602

398

Interrupt Steering Register 3 — INTSTR3 ..................................................................

603

399

IRQ Interrupt Source Register 0 — IINTSRC0.............................................................

605

400

IRQ Interrupt Source Register 1 — IINTSRC1.............................................................

607

401

IRQ Interrupt Source Register 2 — IINTSRC2.............................................................

609

402

IRQ Interrupt Source Register 3 — IINTSRC3.............................................................

610

403

FIQ Interrupt Source Register 0 — FINTSRC0.............................................................

612

404

FIQ Interrupt Source Register 1 — FINTSRC1.............................................................

614

405

FIQ Interrupt Source Register 2 — FINTSRC2.............................................................

616

406

FIQ Interrupt Source Register 3 — FINTSRC3.............................................................

617

407

Interrupt Priority Register 0 — IPR0..........................................................................

619

408

Interrupt Priority Register 1 — IPR1..........................................................................

620

409

Interrupt Priority Register 2 — IPR2..........................................................................

621

410

Interrupt Priority Register 3 — IPR3..........................................................................

622

411

Interrupt Priority Register 4 — IPR4..........................................................................

623

412

Interrupt Priority Register 5 — IPR5..........................................................................

624

413

Interrupt Priority Register 6 — IPR6..........................................................................

625

414

Interrupt Priority Register 7 — IPR7..........................................................................

626

415

Timer Performance Ranges......................................................................................

627

416

Timer Mode Register Control Bit Summary ................................................................

628

417

Timer Responses to Register Bit Settings...................................................................

630

418

Timer Registers .....................................................................................................

633

419

Timer Power Up Mode Settings ................................................................................

633

420

Timer Mode Register – TMRx ...................................................................................

634

421

Timer Input Clock (TCLOCK) Frequency Selection .......................................................

636

422

Timer Count Register – TCRx...................................................................................

637

423

Timer Reload Register – TRRx..................................................................................

637

424

Timer Interrupt Status Register – TISR .....................................................................

638

425

Watch Dog Timer Control Register — WDTCR.............................................................

639

426

Watch Dog Timer Setup Register — WDTSR...............................................................

639

427

Uncommon TMRx Control Bit Settings .......................................................................

640

428

SMBus Interface Pins..............................................................................................

641

429

SMBus Command Encoding .....................................................................................

643

430

SMBus Interface Registers for Configuration Space Access...........................................

647

431

SMBus Interface Registers for Memory Space Access ..................................................

647

432

SMBus Status Byte Encoding ...................................................................................

649

433

SMBus Register Summary .......................................................................................

655

434

SMBus Controller Command Register — SM_CMD .......................................................

655

435

SMBus Controller Byte Count Register — SM_BC ........................................................

656

436

SMBus Controller ADDR3 Register — SM_ADDR3........................................................

656

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

31

Intel® 413808 and 413812—Contents

437

SMBus Controller ADDR2 Register — SM_ADDR2 ........................................................

656

438

SMBus Controller ADDR1 Register Number — SM_ADDR1 ............................................

657

439

SMBus Controller ADDR0 Register Number — SM_ADDR0 ............................................

657

440

SMBus Controller Data Register — SM_DATA..............................................................

658

441

SMBus Controller Status Register — SM_STS .............................................................

658

442

UART Signal Descriptions.........................................................................................

661

443

Divisor Values for Typical Baud Rates ........................................................................

666

444

UART Register Addresses as Offsets of a Base ............................................................

668

445

UART Unit Registers................................................................................................

668

446

UART Register MMR Addresses .................................................................................

669

447

UART x Receive Buffer Register - (UxRBR) .................................................................

670

448

UART x Transmit Holding Register - (UxTHR)..............................................................

670

449

UART x Interrupt Enable Register - (UxIER) ...............................................................

671

450

UART x Interrupt Identification Register - (UxIIR) .......................................................

672

451

Interrupt Identification Register Decode ....................................................................

673

452

UART x FIFO Control Register - (UxFCR) ....................................................................

674

453

UART x Line Control Register - (UxLCR).....................................................................

676

454

UART x Modem Control Register - (UxMCR)................................................................

678

455

UART x Line Status Register - (UxLSR) ......................................................................

680

456

UART x Modem Status Register ................................................................................

683

457

UART x Modem Status Register - (UxMSR).................................................................

683

458

UART x Scratchpad Register - (UxSCR)......................................................................

684

459

UART x Divisor Latch Low Register - (UxDLL) .............................................................

685

460

UART x Divisor Latch High Register - (UxDLH) ............................................................

685

461

UART x FIFO Occupancy Register - (UxFOR)...............................................................

686

462

UART x Auto-Baud Control Register - (UxABR)............................................................

687

463

UART x Auto-Baud Count Register - (UxACR) .............................................................

688

464

I2C Bus Definitions .................................................................................................

690

465

Modes of Operation.................................................................................................

694

466

START and STOP Bit Definitions................................................................................

695

467

Master Transactions................................................................................................

702

468

Slave Transactions..................................................................................................

705

469

General Call Address Second Byte Definitions .............................................................

707

470

I2C Register Summary ............................................................................................

714

471

I2C Control Register x — ICRx..................................................................................

715

472

I2C Status Register x — ISRx ...................................................................................

717

473

I2C Slave Address Register x — ISARx.......................................................................

719

474

I2C Data Buffer Register x — IDBRx ..........................................................................

720

475

I2C Bus Monitor Register x — IBMRx .........................................................................

721

476

I2C Manual Bus Control Register x — IMBCRx.............................................................

722

477

General Purpose I/O Registers Addresses...................................................................

724

478

GPIO Output Enable Register — GPOE .......................................................................

725

479

GPIO Input Data Register — GPID ............................................................................

726

480

GPIO Output Data Register — GPOD .........................................................................

728

481

Simple Time Based Counting of Events Example .........................................................

733

482

Hardware Event Based Event Counting Example .........................................................

735

483

Hardware Event Based Event Counting Example .........................................................

737

484

Queue Depth Histogram Example .............................................................................

738

485

Head of Queue Histogram Example ...........................................................................

739

486

PMON Internal Bus Memory Mapped Register Range Offsets ........................................

745

487

PMON Register Summaries .....................................................................................

745

488

PMON Feature Enable Register - PMONEN ................................................................

746

489

PMON Status Register - PMONSTAT ........................................................................

746

490

PMON Internal Bus Memory Mapped Register Range Offsets ........................................

747

491

PMON Register Summaries .....................................................................................

748

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492

PMON Command Register 0-7 - PMON_CMD[0:7].....................................................

 

749

493

PMON Event Register 0-7 - PMON_EVR[0:7] ............................................................

 

753

494

PMON Status Register 0-7 - PMON_STS[0:7] ...........................................................

 

754

495

PMON DATA Register 7-0 - PMON_DATA[7:0] ..........................................................

 

756

496

Event Selection Code Summary ...............................................................................

 

757

497

Intel® 413808 and 413812 I/O Controllers in TPER Mode PMON Clock Events ...............

 

757

498

Intel® 413808 and 413812 I/O Controllers PMON Clock Events ...................................

 

758

499

Intel® 413808 and 413812 I/O Controllers PMON Threshold Events .............................

 

758

500

PCI Interface Events...............................................................................................

 

759

501

PCI Express Interface Summary...............................................................................

 

760

502

North Internal Bus Source Select Summary ...............................................................

 

761

503

North Internal Bus Initiator Events ...........................................................................

 

761

504

South Internal Bus Source Select Summary...............................................................

 

762

505

South Internal Bus Initiator Events...........................................................................

 

762

506

PCI Bus Frequency Initialization ...............................................................................

 

765

507

CR_FREQ[1:0] Encoding .......................................................................................

 

765

508

HS_FREQ Encoding ................................................................................................

 

766

509

PCI-X Initialization Pattern1 .....................................................................................

 

766

510

Secondary Clock Output Control...............................................................................

 

767

511

Clock Pin Summary ................................................................................................

 

769

512

Core Reset Control Bit Locations ..............................................................................

 

773

513

Internal Bus Reset Control Bit Locations....................................................................

 

775

514

Internal Bus Reset Summary ...................................................................................

 

775

515

Reset Pin Summary................................................................................................

 

777

516

TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=1) ................

 

778

517

Non-TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=0) .........

778

518

Reset Strap Signals ................................................................................................

 

780

519

TLU TAP Controller Instruction Set............................................................................

 

791

520

IOP Device ID Register Field Definitions ...................................................................

 

792

521

IOP Device ID Register Settings ...............................................................................

 

792

522

PMMR Base Address Register (PMMRBAR) Default Value ..............................................

 

798

523

Local Addresses for Integrated Peripherals ................................................................

 

798

524

PBI Base Address Offset..........................................................................................

 

801

525

Peripheral Bus Interface Unit ...................................................................................

 

801

526

SC Base Address Offset...........................................................................................

 

802

527

System Controller Unit............................................................................................

 

802

528

Internal Bus Bridge Base Address Offset....................................................................

 

802

529

Internal Bus Bridge ................................................................................................

 

802

530

I/O Pad Control Base Address Offset.........................................................................

 

803

531

I/O Pad Control Unit ...............................................................................................

 

803

532

UART 0-1 Offset.....................................................................................................

 

804

533

UART....................................................................................................................

 

804

534

GPIO Offset...........................................................................................................

 

805

535

GPIO ....................................................................................................................

 

805

536

I2C 0-2 Offset........................................................................................................

 

805

537

I2C Unit................................................................................................................

 

805

538

Messaging Unit Offset. ............................................................................................

 

806

539

Messaging Unit ......................................................................................................

 

806

540

PMON Unit Base Address Offset. .............................................................................

 

808

541

PMON Unit ...........................................................................................................

 

808

542

PCI Function MMR Locations ....................................................................................

 

809

543

Intel® 413808 and 413812 I/O Controllers ATUX Configuration Space Base Address Offset ...

 

810

 

 

544

Address Translation Unit Registers — ATUX ...............................................................

 

811

 

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Intel® 413808 and 413812—Contents

545

Intel® 413808 and 413812 I/O Controllers ATUE Configuration Space Base Address Offset...

 

814

 

546

Address Translation Unit Registers — ATUE ................................................................

815

547

Intel® 413808 and 413812 I/O Controllers in TPER Mode PCI Function Visibility..............

819

548

Coprocessor Registers Assigned to Integrated Peripherals ............................................

819

549

Coprocessor Register Locations ................................................................................

820

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Contents—Intel® 413808 and 413812

Revision History

Date

Revision

Description

 

 

 

October 2007

001

Initial Release.

 

 

 

 

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Intel® 413808 and 413812—Introduction

1.0Introduction

This document covers the Intel® 413808 and 413812 I/O Controllers (4138xx). Note that the 4138xx operates in multiple modes, depending on which mode, determines when this manual is applicable. (In part or whole)

With 4138xx in I/O Controller Mode, the 4138xx is a stand-alone SAS/SATA I/O Controller, the host driver interface to the 4138xx is via SLI protocol through the TPMI1 unit. When in Operational Mode as an I/O Controller, there is no direct access to other internal units such as PBI, GPIOs, UARTs etc., all access must be done via SLI (note that some units have no SLI access API). In order to facilitate the programming of the Flash device, the PBI may be accessed via the TPMI1 when the transport firmware is not running (cores in reset). This document is generally not applicable when in IOC mode except for those situations where access to internal registers is required. (Flash programming)

With 4138xx in TPER Mode, Third Party Embedded RAID (TPER) mode. The term “TPER”can refer to a usage model, a silicon SKU, or a version of the transport firmware. Using the term to describe a Usage Model simply means running intelligent RAID (non host-based, typically simple levels such as 0/1/10 due to limited resources) without burdening the I/O processor with external DDR2 costs. From the silicon view it is essentially a DDR2-less 81348 (4138xx/4138xx ‘A’ version); a SKU where the memory controller cannot be used. Because TPER mode is very similar to the 81348 from a programming model perspective, the 81348 is sometimes referenced in collateral discussing the 4138xx in TPER mode.

This manual is primarily intended for those using the 4138xx in TPER mode and much of the content is identical to that of the 81348.

See Table 11 for how the silicon and transport firmware are combined. See Figure 1, “TPER Architecture Overview” on page 37 for an Architectural Overview.

Table 1. Intel® 413808 and 413812 I/O Controllers in TPER Mode/Firmware Mapping

 

Transport Firmware

Silicon

 

 

 

Standard Transport FW

TPER Transport FW

 

 

 

 

 

Functional as a limited capability

 

Functional as a full featured I/O

I/O Processor and can be upgraded

81348

to a full featured I/O Processor via

Processor

 

firmware upgrade (aka In Place

 

 

 

 

Upgrade).

 

 

 

4138xx in IOC mode

Functional as a full featured I/O

Not Supported

Controller

 

 

 

 

 

4138xx in TPER mode

Not Supported

Functional as a limited capability

I/O Processor

 

 

 

 

 

1. The TPMI specification is available through your Intel representative.

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Introduction—Intel® 413808 and 413812

The overall high-level architecture is shown in Figure 1.

Figure 1. TPER Architecture Overview

Driver

MU

Application

TPMI

Transport

Core

Core

 

 

 

 

 

 

SLI Host PTRs

 

 

 

 

SLIM (BAR 0)

 

 

 

 

SLI CMD Wings

 

 

 

 

SLI RSP Wings

 

 

 

 

SLI PORT PTRs

 

 

 

 

Application Core Memory

 

 

 

 

Transport Memory

 

 

 

 

SRAM

 

When the 4138xx is in TPER mode, the interface to the host driver is under the control of the Application Core, and as with the 81348, the MU provides the hardware for the messaging interface. Note however, that since there is no DDR2 the MU is unable to make use of the Index Registers or Circular Queues, since these rely upon DDR2. However, the rest of the MU functionality is available.

The interface between the Application Core and the Transport Core continues to be SLI with the support of the TPMI registers. The Application Core is assigned a total of 256KB of SRAM for its use. The SLI IOCB Command and Response Rings and the SLI Port Pointers must reside in SRAM instead of DDR2. This comes out of the 256KB region assigned to the Application Core as specified by the PCB structure as communicated by the SLI Configuration Port (CONFIG_SLI_PORT) command. Complete details on the Application Core section of SRAM, including alignment requirements, addresses, etc., can be found in the SCDL Architecture Specification, Firmware Release Notes, Sample Code which is included in the Software Developer’s Kit package.

The following is a list of other features, both silicon and firmware that are not available with the TPER usage model.

4138xx in TPER mode (when using 81348 silicon these features are available):

ADMA

MU circular queues, index registers.

TPER Transport Firmware (differences from 81348 1.0 firmware features):

CONFIG_SAS_GPIO is not available when running TPER firmware.

Fewer addressable targets and outstanding I/Os supported, refer to the firmware release notes for the version in question for specifics.

Ring memory and port pointers allocated from application core SRAM region.

Any application core host messaging interface memory required allocated from application core SRAM.

 

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Intel® 413808 and 413812—Introduction

1.1Design-in Considerations

For In Place Upgrade, the 81348 SKU must be used. The 4138xx SKU cannot be upgraded to full featured RAID. In place upgrade simply means using an 81348 SKU in IOC mode and then at some later point in time, updating the firmware and reset straps to put the 81348 into IOP mode. From the end user perspective it will appear as an in place upgrade from an I/O controller for a fully featured Intelligent RAID Subsystem.

The following are reset straps associated with putting the 4138xx in TPER mode (additionally, of course, TPER firmware must be used for the 4138xx to operate in TPER mode). (see datasheet for complete listing of reset straps and their descriptions)

4138xx mode:

-CONTROLLER_ONLY#: 0

-DF_SEL[2:0]: 000 (no other combinations are currently valid)

-HOLD_X0_IN_RST#: 1

-HOLD_X1_IN_RST#: 0

-CFG_CYCLE_EN#: 1

4138xx in TPER mode:

-CONTROLLER_ONLY#: 1

-DF_SEL[2:0]: 000 (no other combinations are currently valid)

-HOLD_X0_IN_RST#: 1

-HOLD_X1_IN_RST#: 1

-CFG_CYCLE_EN#: 1

The design must comprehend the additional hardware requirements needed by the full featured RAID solution. The specific hardware requirements, and the mechanism to add them, are dependent on the RAID ISV but include items such as:

DDR2 (connector and/or memory) and supporting components.

PBI modules required by the full featured RAID such as journaling NVSRAM, buzzers, additional Flash, etc.

Hardware Key for software/firmware feature enabling.

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1.1.1Software

PCI Configuration Space: For 4138xx in TPER mode (as with 81348), the PCI configuration space presented is that of the Address Translation Unit (ATU) and it is the responsibility of the Application Core firmware to setup things such as the device ID per their design. When designing a system for In-place Upgrade, the RAID ISV must determine if/how they will have host driver compatibility between their stack running on 81348 with TPER firmware and their stack running on IOP348 with standard firmware.

RAID MetaData Format: The RAID ISV is responsible for meeting any requirements with regards to Metadata format compatibility between their stack running on 81348 with TPER firmware and their stack running on 81348 with standard firmware.

Host interface: Defined by the ISV, just as in 81348. When using TPER Silicon, MU Circular queues and index registers are not available. SLI interface is only relevant/available between the Application Core and Transport Core. With the same interface as 81348, with the exception that the IOCB command and response rings must be located in the Application Core SRAM space as opposed to DDR2 memory.

For full details on SLI interface requirements for TPER, please refer to the SCDL Architecture Specification listed in Table 2, “Documentation References” on page 40.

SDMA (SRAM DMA) Engine: Since there is no ADMA without DDR2, a separate DMA engine, the SRAM DMA, is provided to allow for the Application Core the ability to DMA command/status as part of its host messaging interface. The engine is different from ADMA, no chaining or special features. All access is direct register (no coprocessor access) as opposed to DDR2 memory descriptor based processing for ADMA. The SDMA chapter is found in this manual.

SRAM ECC: The SRAM is a shared resource between the Application Core and the Transport Core in TPER. The Ttransport Core handles the initial enabling of ECC and scrubbing of SRAM for the entire region before the common boot code allows transfers execution to the Application Core. However, the Transport Core ignores ECC errors in the Application Core SRAM region and expects that the Application Core handles and clears ECC interrupts per specification. Similarly, the Transport Core handles all ECC interrupts for the Transport Core region of SRAM and asserts (hanger/dump) in the event that a multi-bit error occurs in its region. The SRAM chapter is found in this manual.

Important Notes:

-The Application Core must ignore all ECC interrupts until after it has successfully completed CONFIG_SLI_PORT since up until that time, theTransport Firmware monitors ECC errors for the entire SRAM region.

-In the event that the Application Ccore uses a PRG other than the TPER firmware (diagnostic overlay for internal test purposes when available), the Application Ccore must ignore the ECC interrupt for the entire SRAM region.

 

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Intel® 413808 and 413812—Introduction

1.2Documentation References

For available documentation references please refer to the following URLs:

http://developer.intel.com/design/storage/controller/docs/ioc340.htm

http://developer.intel.com/design/iio/docs/iop348.htm

Table 2 is a list of the available documentation for the 4138xx that is referenced for a TPER design.

Table 2.

Documentation References

 

 

 

 

 

Document

Reference #

 

 

 

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode Developer’s Manual

317805a

 

Intel® 413808 and 413812 I/O Controllers Developer’s Manual

315036a

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode Datasheet

317806a

 

Intel® 413808 and 413812 I/O Controllers Datasheet

315040a

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode Design Guide

317807a

 

Intel® 413808 and 413812 I/O Controllers Design Guide

315055a

 

Intel® 413808 and 413812 I/O Controllers Design Review Checklist

315046a

 

Intel® 413808 and 413812 I/O Controllers Thermal Design Considerations

315052a

 

Application Note

 

 

 

 

 

Intel® 413808 and 413812 I/O Controllers in TPER Mode Specification Update

317808a

 

Intel® 413808 and 413812 I/O Controllers Specification Update

315043a

 

Intel® 81348 I/O Processor - Intel® 413808 and 413812 SAS/SATA I/O Controllers

356369b (643939c)

 

SSAS

 

 

 

 

 

SAS/SATA Command Summary (SSCS)

351156 (645843)

 

 

 

 

SCDL Architecture Specification, Firmware Release Notes, Sample Code

Delivered with firmware

 

 

 

 

TPMI Specification

TBD

 

 

 

a. Web document number (http://developer.intel.com/design/storage/controller/docs/ioc340.htm). b. My SMG document number.

c. FDBL document number.

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Introduction—Intel® 413808 and 413812

1.3About This Document

This document is the authoritative and definitive reference for the external architecture of the Intel® 413808 and 413812 I/O Controllers in TPER Mode (4138xx), with Intel XScale® microarchitecture2.

Intel Corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any time, without notice. In particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment to implement them. In fact, this specification does not imply a commitment by Intel to design, manufacture, or sell the product described herein.

1.3.1How To Read This Document

This document describes the product-specific features of the 4138xx. Each chapter describes a different feature and starts with an overview followed by the theory of operation.

The reader should have a working understanding of the Peripheral Component Interconnect (PCI) Local Bus Specification, the PCI-X Addendum to the PCI Local Bus Specification and the PCI Express Specification. For more information, refer to the PCI Local Bus Specification, Revision 2.3, the PCI-X Addendum to the PCI Local Bus Specification, Revision 2.0a, and the PCI Express Specification, Revision 1.0a.

1.3.2Other Relevant Documents

1.Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Developer’s Manual (Order Number: 273411), Intel Corporation

2.PCI Local Bus Specification, Revision 2.3 - PCI Special Interest Group

3.PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Special Interest Group

4.PCI Express Specification, Revision 1.0a - PCI Special Interest Group

2. ARM architecture compliant.

 

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Intel® 413808 and 413812—Introduction

1.4About the Intel® 413808 and 413812 I/O Controllers in TPER Mode

The 4138xx is a single-function PCI devices that integrates two Intel XScale® processors with intelligent peripherals including a PCI bus application bridge and eight Serial-Attached SCSI (SAS) Engines. The SAS Engines on the 4138xx also support direct-attached Serial ATA (SATA) targets. The 4138xx also supports two internal busses: north internal bus and south internal bus. With the two internal busses, transactions can take place simultaneously on each bus. The north internal bus generates large burst transactions are located on the south internal bus, thus allowing the two Intel XScale® processors exclusive access to the north internal bus.

The 4138xx consolidates, into a single system:

Two Intel XScale® processors

Eight Serial-Attached SCSI Links - also capable of supporting direct-attached SATA targets

PCI - Local Memory Bus Address Translation Unit - PCI function 0

Messaging Unit

Inter-Processor Communication

Inter-Processor Messaging Unit

Third Party Messaging Interface (TPMI)

Peripheral Bus Interface Unit (PBI)

Integrated SRAM Memory Controller

Performance Monitor (PMON)

Two Programmable Timers per Intel XScale® processor

Watchdog Timer per Intel XScale® processor

Three I2C Bus Interface Units

Two Serial Port Units

Sixteen General Purpose Input Output (GPIO) ports

Two SGPIO busses

Internal North Bus-South Bus Bridge

It is an integrated processor that addresses the needs of intelligent I/O Storage applications and helps reduce intelligent I/O system costs.

Both the address and data busses on the 4138xx south internal bus are byte-wise parity protected.

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Introduction—Intel® 413808 and 413812

Figure 2 is a block diagram of the 4138xx.

Figure 2. Intel® 413808 and 413812 I/O Controllers in TPER Mode Functional Block Diagram

 

Intel

Timers

Timers

Intel

 

 

 

 

XScale®

Interrupt

Interrupt

XScale®

 

 

 

 

Processor

Processor

 

 

 

 

Controller

Controller

 

 

 

 

(coreID = 1H)

Inter-Core

Inter-Core

(coreID = 0H)

 

 

 

 

512K L2 Cache

512K L2 Cache

 

 

 

 

Interrupt

Interrupt

 

 

SAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial Bus

 

 

128-Bit North Internal Bus

 

SAS 0

PHY

 

 

 

 

 

 

 

 

 

IMU

 

 

SAS 1

PHY

 

 

 

 

 

 

 

 

 

 

 

Multi-Port

 

 

SAS

 

 

 

 

SRAM

 

 

 

 

DDR

 

 

 

Serial Bus

 

 

 

Memory

 

 

72-Bit

 

 

 

 

 

 

not available in

Controller

SAS 7

PHY

 

I/F

 

 

 

TPER

 

 

 

 

 

 

 

 

 

 

 

 

 

Bridge

 

One TDMA

 

 

 

 

 

 

and

 

 

 

 

 

 

 

 

 

 

 

 

 

One SDMA

 

 

 

 

Host Interface

 

 

 

 

 

 

PCI-X

(ATU)

128-Bit South Internal Bus

 

 

 

 

 

Host Interface

PBI

SMBus

 

 

 

 

 

Unit

APB

 

 

 

PCI-E

(ATU)

Unit

 

 

 

(Flash)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Three I 2 C

Two

 

 

 

 

 

 

Bus

 

 

 

 

 

 

UARTs

 

 

 

 

 

 

Interface

 

 

Intel® 413808 and 413812 I/O Controllers

 

 

 

 

 

 

 

 

 

 

 

 

16-Bit I/F

SMBus

 

I2 C Bus

Serial Bus

B6617-01

 

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Intel® 413808 and 413812—Introduction

1.5Intel® 413808 and 413812 I/O Controllers in TPER Mode Features

The 81348 combines two Intel XScale® processors with powerful new features to create an intelligent I/O storage processor. This singleor multi-function PCI device is fully compliant with the PCI-X 2.0a and PCI Express 1.0a specifications. The 81348-specific features include:

Address Translation Unit

Performance Monitoring Unit

Messaging Unit

Two Serial Port Units (UARTs)

Peripheral Bus Interface Unit (PBI)

Inter-Processor Communication

Three I2C Bus Interface Units

Two Programmable Timers per core

Two SGPIO Busses

Watchdog Timers

Internal Bus Bridge

Third Party Messaging Interface (TMPI)

The 81348 microarchitecture is based upon two Intel XScale® processors. When in TPER mode, one processor is available for general application purposes (RAID). When in IOC mode, there are no processors available. The microarchitecture operates at a maximum frequency of 1.5 GHz. The instruction cache is 32 Kbytes in size and is 32-way set associative. Also, the microarchitecture includes a data cache that is

32 Kbytes and is 32-way set associative and a mini data cache that is 2 Kbytes and is 2-way set associative. Both Intel XScale® processors support unified 512-KByte Level 2 (L2) cache and is 8-way set associative.

The 81348 includes sixteen General Purpose I/O (GPIO) pins, which are used for SAS Links for activity and status indicators. Each SAS link uses two LSO pins. The 81348 also supports two SGPIO busses.

The subsections that follow briefly overview each feature. Refer to the appropriate chapter for full technical descriptions.

1.5.1Host Interface

The 4138xx present a single function to the host When in IOC mode, the TPMI is exposed to the host and PCI configuration parameters are setup by the Transport Firmware. Some parameters are changed via use of the OEM Parameter Tool. When in TPER mode, the TPMI is not exposed to the host, the ATU is. Thus, Application Core firmware is fully responsible for setting up PCI configuration space.

1.5.2Intel XScale® Processor

The Intel XScale® processor operates at a maximum frequency of 1.5 GHz. The instruction cache is 32 Kbytes in size and is 32-way set associative. Also, the processor includes a data cache that is 32 Kbytes and is 32-way set associative. The Intel XScale® processor supports a unified 512-KByte Level 2 (L2) cache and is 8-way set associative.

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1.5.3Internal Busses

The 4138xx is architected around two internal busses: north internal bus and south internal bus. The two busses use the same bus protocol. The north internal bus is 128-bit wide and operates at speed up to 400 MHz.

The south internal bus is 128-bits wide and operates at speeds up to 400 MHz. The south internal bus provides data paths for large DMA generated burst transactions.

Both the internal address and data busses on the south internal bus are parity protected on a byte-wise basis.

1.5.4Application DMA Controller

ADMA is not available in the 4138xx in any mode.

1.5.5Address Translation Unit

The Address Translation Unit (ATU) allows PCI transactions direct access to the local memory. The ATU provides the interface for the RAID Controller PCI function. The ATU supports transactions between PCI address space and the internal address space. Address translation is controlled through programmable registers accessible from both the PCI interface and the Intel XScale® processor. Dual access to registers allows flexibility in mapping the two address spaces. The ATU also supports the extended capability configuration headers.

 

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Intel® 413808 and 413812—Introduction

1.5.6Messaging Unit

The Messaging Unit (MU) provides data transfer between the PCI system and the 4138xx. It uses interrupts to notify each system when new data arrives. The MU has the following messaging mechanisms:

Message Registers

Doorbell Registers

Each allows a host processor or external PCI device and the 4138xx to communicate through message passing and interrupt generation. The MU in conjunction with the ATU in TPER mode.

1.5.7DDR Memory Controller

DDR is not available on the 4138xx.

1.5.8Peripheral Bus Interface

The Peripheral Bus Interface Unit is a data communication path to the Flash memory components or other peripherals of 4138xx hardware system. Note, that Flash parts must be compatible with the transport firmware. See the System/Software Architecture Specfication and Design Guide Checklist for more information on supported Flash parts. The PBI includes support for either 8/16 bit devices. To perform these tasks at high bandwidth, the bus features a burst transfer capability which allows successive 8/16-bit data transfers.

1.5.9Performance Monitoring Unit

The Performance Monitoring Unit allows various events on the 4138xx to be monitored.

1.5.10I2C Bus Interface Unit

There are three I2C (Inter-Integrated Circuit) Bus Interface Units that allow the Intel XScale® processor to serve as a master and slave device residing on the I2C bus. The I2C unit uses a serial bus developed by Philips Semiconductor consisting of a two-pin interface. The bus allows 4138xx to interface to other I2C peripherals and microcontrollers for system management functions. It requires a minimum of hardware for an economical system to relay status and reliability information on the I/O subsystem to an external device. Also refer to I2C Peripherals for Microcontrollers (Philips Semiconductor).

1.5.11UART Unit

The 4138xx includes two UART units. The UART Unit allows the two Intel XScale® processors to serve as a master and slave device residing on the UART bus. The UART unit uses a serial bus consisting of a two-pin interface. The bus allows 4138xx to interface to other peripherals and microcontrollers. Also refer to 16550 Device spec (National Semiconductor).

1.5.12Interrupt Controller Unit

Each Intel XScale® processor supports an Interrupt Controller Unit. The Interrupt Controller Unit (ICU) aggregates interrupt sources both external and internal of sources of 4138xx to the Intel XScale® processor. The ICU supports high performance interrupt processing with direct interrupt service routine vector generation on a per source basis. Each source has programmability for masking, core processor interrupt input, and priority.

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1.5.13Internal Bus System Controller

Each internal bus (north and south) employs a internal System Controller. The internal System Controller observes all the address or data bus request from requestors and completors connected to the internal bus. The internal System Controller includes features to handle: internal address bus arbitration, internal data bus arbitration, framing Address bus cycles, framing Data bus cycles, and provides the shared address and shared data paths from/to units.

1.5.14Inter-Processor Communication

All intern processor communications on the 4138xx are over the internal bus.

1.5.15Inter-Processor Messaging Unit

The IPMU is not available on the 4138xx.

1.5.16Timers

The 4138xx supports two programmable 32-bit timers per processor. The 4138xx also supports one watchdog timer per processor.

1.5.17GPIO

The 4138xx includes sixteen General Purpose I/O (GPIO) pins.

1.5.18FSENG

The FSENG block contains the Serial-Attached SCSI(SAS) and SATA engines. The 81348 contains up to eight engines. And each engine is composed of the transport, link, PHY and physical layers. This unit is for use by the Transport Firmware only.

 

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Intel® 413808 and 413812—Introduction

1.6Terminology and Conventions

1.6.1Representing Numbers

All numbers in this document can be assumed to be Base10 unless designated otherwise. In text, numbers in Base16 are represented as “nnnH”, where the “H” signifies hexadecimal. In pseudo code descriptions, hexadecimal numbers are represented in the form 0x1234ABCD. Binary numbers are not explicitly identified but are assumed when bit operations or bit ranges are used.

1.6.2Fields

A reserved field is a field that may be used by an implementation. When the initial value of a reserved field is supplied by software, this value must be zero. Software should not modify reserved fields or depend on any values in reserved fields.

A read/write field can written to a new value following initialization. This field can always be read to return the current value.

A read only field can be read to return the current value. Writes to read only fields are treated as no-op operations and does not change the current value nor result in an error condition.

A read/clear field can also be read to return the current value. A write to a read/clear field with the data value of 0 causes no change to the field. A write to a read/clear field with a data value of 1 causes the field to be cleared (reset to the value of 0). For example, when a read/clear field has a value of F0H, and a data value of 55H is written, the resultant field is A0H.

A read/set field can also be read to return the current value. A write to a read/set field with the data value of 0 causes no change to the field. A write to a read/set field with a data value of 1 causes the field to be set (set to the value of 1). For example, when a read/set field has a value of F0H, and a data value of 55H is written, the resultant field ia F5H.

A writeonce/readonly field can be written to a new value once following initialization. After the this write has occurred, the writeonce/readonly field treats all subsequent writes as no-op operations and does not change the current value or result in an error condition. The field can always be read to return the current value.

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1.6.3Specifying Bit and Signal Values

The terms set and clear in this specification refer to bit values in register and data structures. When a bit is set, its value is 1; when the bit is clear, its value is 0. Likewise, setting a bit means giving it a value of 1 and clearing a bit means giving it a value of 0.

The terms assert and deassert refer to the logically active or inactive value of a signal or bit, respectively.

1.6.4Signal Name Conventions

All signal names use the PCI signal name convention of using the “#” symbol at the end of a signal name to indicate that the signal’s active state occurs when it is at a low voltage. The absence of the “#” symbol indicates that the signal’s active state occurs when it is at a high voltage.

1.6.5Terminology

To aid the discussion of the 81348 architecture, the following terminology is used:

Downstream

At or toward a PCI bus with a higher number (after

 

configuration)

DWORD

32-bit data word

QWORD

64-bit data word

word

32-bit data word

Host processor

Processor located upstream from the 81348

Local processor

Intel XScale® processor within the 81348

Local bus

81348 Internal Bus

Local memory

Memory subsystem on the Intel XScale® processor DDR SDRAM

 

or Peripheral Bus Interface busses

Upstream

At or toward a PCI bus with a lower number (after configuration)

 

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Intel® 413808 and 413812—Address Translation Unit (PCI-X)

2.0Address Translation Unit (PCI-X)

This chapter describes the operation modes, setup, and implementation of the module which interfaces between the PCI bus and the Intel® 413808 and 413812 I/O Controllers in TPER Mode (4138xx) internal bus.

2.1Overview

As indicated in Figure 3, the Address Translation Unit (ATU) — the interface between the PCI bus and the on-chip internal bus — consists of the Address Translation Unit (ATU) and the Expansion ROM Unit.

The ATU supports both inbound and outbound address translation. The ATU provides access between the PCI bus and the 4138xx internal bus.

Transactions initiated on the PCI bus and targeted at the 4138xx internal bus are referred to as inbound transactions (PCI to internal bus). Transactions initiated on the 4138xx internal bus and targeted at the PCI bus are referred to as outbound transactions (internal bus to PCI). The ATU accepts multiple inbound or outbound transactions and processes them simultaneously.

During inbound transactions, the ATU converts PCI addresses (initiated by a PCI bus master) to Internal Bus Addresses and initiates the data transfer on the 4138xx internal bus. During outbound transactions, the ATU converts internal bus addresses to PCI addresses and initiates the data transfer on the PCI bus.

The Expansion ROM provides the PCI mechanism for downloading device/board driver code during system boot sequence. It consists of a separate inbound address range which accesses a Flash EPROM device connected through the 4138xx memory controller. Refer to the PCI Local Bus Specification, Revision 2.3 for details of Expansion ROM usage.

The Address Translation Unit and the Expansion ROM Translation Unit represent a single function of the multi-function 4138xx PCI device.

The ATU supports the following PCI operating modes and bus widths delivering up to 2133 Mbytes/sec of bandwidth:

Conventional Modes: PCI 33, PCI 66

PCI-X Modes: Mode 1 (PCI-X 66, PCI-X 133), Mode 2 (PCI-X 266)3

Bus Widths: 64-bit, 32-bit

In Mode 2, all transaction phases are ECC protected (when enabled). In the remaining PCI-X and Conventional modes supported by 4138xx, all transaction phases are parity protected (when enabled).

On the internal interface, the ATU implements the 4138xx internal bus protocol which provides for a maximum of 4800 Mbytes/sec of bandwidth.

3. PCIX is not supported in TPER mode.

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