Intel SL6VU - Celeron 2.40GHz 400MHz 128KB Socket 478 CPU, Celeron Series Specification

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Intel® Celeron® Processor in the
478-Pin Package

Specification Update

October 2006

Notice: The Intel
defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are documented in this
Specification Update.

®

Celeron® Processor in the 478-Pin Package may contain design

Document Number: 290749-030

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining
applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

®

The Intel
deviate from published specifications. Current characterized errata are available on request.

The Specification Update should be publicly available following the last shipment date for a period of time equal to the specific product’s warranty
period. Hardcopy Specification Updates will be available for one (1) year following End of Life (EOL). Web access will be available for three (3)
years following EOL.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Celeron Pentium, Intel Xeon, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United
States and other countries.

*Other names and brands may be claimed as the property of others.
Copyright © 2003–2005, Intel Corporation

Celeron® Processor in the 478-Pin Package may contain design defects or errors known as errata which may cause the product to

2 Intel

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Celeron® Processor in the 478-Pin Package Specification Update

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Contents

Revision History..................................................................................................................4

Preface................................................................................................................................6

Summary Tables of Changes .............................................................................................8

General Information ..........................................................................................................14

Component Identification Information...............................................................................15

Errata.................................................................................................................................19

Specification Changes ......................................................................................................46

Specification Clarifications................................................................................................47

Documentation Changes ..................................................................................................50

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Intel

Celeron® Processor in the 478-Pin Package Specification Update 3

Revision History

Revision History

Version Description Date

-001 Initial release. May 2002

-002 Added erratum AC35. Added Documentation Changes AC4- AC5.
Updated processor identification information table.

-003 Added erratum AC37. Added Documentation Changes AC3- AC12. July 2002

-004 Updated with Intel® Celeron® Processor on 0.13 Micron Process and in
the 478-Pin Package. Added erratum AC38. Updated Erratum AC17.
Added Documentation Changes AC3- AC24.

-005 Added erratum AC39. Added Documentation Changes AC25- AC32. October 2002

-006 Added Erratum AC40. Added Spec Change V1. Added Documentation
Changes AC1- AC10. Updated processor identification information table.

-007 Added Erratum AC41. January 2003

-008 Added Erratum AC42. February 2003

-009 Updated Erratum AC41. Added erratum AC43.
Updated processor identification information table

-010 Added Specification clarification AC1. Updated processor identification
information table. Added Errata AC44 and AC45.

-011 Updated processor identification information table. Updated Erratum
AC40.

-012 Updated processor identification information table. Added D1 step
update.

-013 Added Erratum AC46, AC47 and AC49. Updated processor identification
information table.

-014 Added Erratum AC49, AC50 and AC51. Updated processor identification
information table.

-015 Updated Erratum AC51. Updated processor identification information
table.

-016 Added Errata AC52- AC56. March 2004

-017 Updated Erratum AC16. Added Erratum AC57. April 2004

-018 Removed Errata that were previously called AC54 & AC55. Added Errata
AC56 and AC57.

-019 Updated Erratum AC11 & added Erratum AC58. August 2004

-020

-021

-022

Added Errata AC59- AC61.

Added Erratum AC62- AC63
Updated processor identification information table. Added Erratum V64

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June 2002

September

2002

November

2002

March 2003

May 2003

June 2003

June 2003

August 2003

September

2003

November

2003

June 2004

September

2004

October 2004

November

2004

4 Intel

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Celeron® Processor in the 478-Pin Package Specification Update

Revision History

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Version Description Date

-023

-024 • Added specification clarification AC1. April 2005

-025 • Changed the Errata ID tag from “V” to “AC”. Updated Summary table of

-026 • Updated erratum AC40. January 2006

-027 • Updated document numbers for Software Developers Manuals. March 2006

-028 • Added erratum AC67 and AC68. Updated Summary Table of Changes. April 2006

-029 • Added erratum AC69. Updated Summary Table of Changes. June 2006

-030 • Updated the names of the Software Developer Manuals. Updated

Added Erratum AC65

changes. Updated Microcode Update Guide and .PDB file guide.
Added Erratum AC66.

Summary Table of Changes. Updated Links.

December

October 2005

October 2006

2004

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Intel

Celeron® Processor in the 478-Pin Package Specification Update 5

Preface

Preface

This document is an update to the specifications contained in the documents listed in the
following Affected Documents/Related Documents table. It is a compilation of device and
document errata and specification clarifications and changes, and is intended for hardware system
manufacturers and for software developers of applications, operating system, and tools.

Information types defined in the Nomenclature section of this document are consolidated into this
update document and are no longer published in other documents. This document may also
contain information that has not been previously published.

Affected Documents

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Document Title Document Number

Intel® Celeron® Processor in the 478-Pin Package up to 1.80 GHz
Datasheet

Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin
Package

Related Documents

Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 1: Basic Architecture

Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 2A: Instruction Set Reference, A-M

Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 2B: Instruction Set Reference, N-Z

Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 3A: System Programming Guide

Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 3B: System Programming Guide

http://developer.intel.com/design/

celeron/datashts/251748.htm

http://developer.intel.com/support

/processors/celeron/478/

Document Title Document Number

253665

253666

253667

253668

253669

6 Intel

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Celeron® Processor in the 478-Pin Package Specification Update

Preface

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Nomenclature

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their

unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the
processor identification information table. Care should be taken to read all notes associated with
each S-Spec number

®

Errata are design defects or errors. Errata may cause the Intel

package behavior to deviate from published specifications. Hardware and software designed to be
used with any given stepping must assume that all errata documented for that stepping are present
on all devices.

Specification Changes are modifications to the current published specifications. These changes

will be incorporated in the next release of the specifications.

Specification Clarifications describe a specification in greater detail or further highlight a

specification’s impact to a complex design situation. These clarifications will be incorporated in
the next release of the specifications.

Celeron® processor in the 478-pn

Documentation Changes include typos, errors, or omissions from the current published

specifications. These changes will be incorporated in the next release of the specifications.

®

Intel

Celeron® Processor in the 478-Pin Package Specification Update 7

Summary Tables of Changes

Summary Tables of Changes

The following table indicates the Specification Changes, Errata, Specification Clarifications, or
Documentation Changes that apply to the listed component steppings. Intel intends to fix some of
the errata in a future stepping of the component, and to account for the other outstanding issues
through documentation or Specification Changes as noted. This table uses the following
notations:

Codes Used in Summary Table

Stepping

X: Erratum, Specification Change or Clarification that applies

to this stepping.

R

(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification

Status

Doc: Document change or update that will be implemented.

PlanFix: This erratum may be fixed in a future stepping of the

Fixed: This erratum has been previously fixed.

NoFix: There are no plans to fix this erratum.

PKG: This column refers to errata on the Celeron processor in

AP: APIC related erratum.

Shaded: This item is either new or modified from the previous

change does not apply to listed stepping.

product.

the 478-pin package substrate

version of the document.

8 Intel

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Celeron® Processor in the 478-Pin Package Specification Update

Summary Tables of Changes

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Note: Each Specification Update item is prefixed with a capital letter to distinguish the product. The key

below details the letters that are used in Intel’s microprocessor Specification Updates:

A = Dual-Core Intel® Xeon® processor 7000 sequence
B = Mobile Intel ® Pentium ® II processor
C = Intel ® Celeron ® processor
E = Intel ® Pentium ® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
G = Intel ® Pentium ® III Xeon™ processor
H = Mobile Intel ® Celeron ® processor at 466/433/400/366/333/300 and 266 MHz
J = 64-bit Intel® Xeon™ processor MP with 1MB L2 Cache
K = Mobile Intel ® Pentium ® III processor
L = Intel ® Celeron ® D processor
M = Mobile Intel ® Celeron ® processor
N = Intel ® Pentium ® 4 processor
O = Intel ® Xeon™ processor MP
P = Intel ® Xeon™ processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90-

nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon™ processor with 800 MHz system bus (1 MB and 2 MB L2

cache versions)
T = Mobile Intel® Pentium® 4 processor-M
V = Mobile Intel® Celeron® processor on .13 Micron Process in Micro-FCPGA

Package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90nm process with 2-MB L2 Cache
Y = Intel® Pentium® M processor
Z = Mobile Intel ® Pentium ® 4 processor with 533 MHz system bus
AA = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor on
65nm
AB = Intel® Pentium® 4 processor on 65 nm process
AC = Intel® Celeron® processor in 478 Pin Package
AD = Intel® Celeron® D processor on 65nm process
AE = Intel

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CoreTM Duo Processor and Intel® CoreTM Solo processor on 65nm process
AF = Dual-Core Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® Processor 5100 Series
AH = Intel® Core™2 Duo mobile processor
AI = Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop
Processor E6000Δ Sequence
AL = Dual-Core Intel® Xeon® Processor 7100 Series

NO. E0 nC1 nD1 Plans ERRATA

AC1 X X X NoFix

AC2 X X X NoFix

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Intel

Celeron® Processor in the 478-Pin Package Specification Update 9

I/O restart in SMM may fail after simultaneous machine check
exception (MCE)

MCA registers may contain invalid information if RESET#
occurs and PWRGOOD is not held asserted

Summary Tables of Changes

NO. E0 nC1 nD1 Plans ERRATA

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AC3 X Fixed

AC4 X X X NoFix Transaction is not retried after BINIT#
AC5 X X X NoFix Invalid opcode 0FFFh requires a ModRM byte

AC6 X X X NoFix

AC7 X X X NoFix

AC8 X X X NoFix

AC9 X X X NoFix

AC10 X Fixed Writing a performance counter may result in incorrect value
AC11 X X X NoFix IA32_MC0_STATUS register overflow bit not set correctly

AC12 X Fixed

AC13 X NoFix

AC14 X NoFix

AC15 X X X NoFix Debug mechanisms may not function as expected

AC16 X X X NoFix

AC17 X Fixed

AC18 X X X NoFix

AC19 X Fixed

AC20 X X X NoFix EMON event counting of x87 loads may not work as expected

AC21 X Fixed

AC22 X Fixed

AC23 X X X PlanFix

AC24 X X X PlanFix

AC25 X Fixed

AC26 X PlanFix Buffer on resistance may exceed specification

AC27 X X X NoFix

Uncacheable (UC) code in same line as write back (WB) data
may lead to data corruption

FSW may not be completely restored after page fault on
FRSTOR or FLDENV instructions

The processor flags #PF instead of #AC on an unlocked
CMPXCHG8B instruction

When in no-fill mode the memory type of large pages are
incorrectly forced to uncacheable

Processor may hang due to speculative page walks to non­existent system memory

Performance counter may contain incorrect value after being
stopped

MCA error code field in IA32_MC0_STATUS register may
become out of sync with the rest of the register

The IA32_MC1_STATUS register may contain incorrect
information for correctable errors

Machine check architecture error reporting and recovery may
not work as expected

Processor may timeout waiting for a device to respond after
~0.67 seconds

Cascading of performance counters does not work correctly
when forced overflow is enabled

IA32_MC1_STATUS MSR ADDRESS VALID bit may be set
when no valid address is available

Software controlled clock modulation using a 12.5% or 25%
duty cycle may cause the processor to hang

SQRTPD and SQRTSD may return QnaN indefinite instead of
negative zero

Bus Invalidate Line requests that return unexpected data may
result in L1 cache corruption

Write Combining (WC) load may result in unintended address
on system bus

Incorrect data may be returned when page tables are in Write
Combining (WC) memory space

Processor issues inconsistent transaction size attributes for
locked operation

10 Intel

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Celeron® Processor in the 478-Pin Package Specification Update

Summary Tables of Changes

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NO. E0 nC1 nD1 Plans ERRATA

AC28 X Fixed

AC29 X Fixed Processor may hang when resuming from Deep Sleep state

AC30 X X X NoFix

AC31 X X X NoFix

AC32 X X X NoFix

AC33 X Fixed

AC34 X X X NoFix

AC35 X Fixed

AC36 X Fixed L2 cache may contain stale data in the Exclusive state

AC37 X X X NoFix

AC38

S

AC39 X Fixed CPUID Returns Incorrect Number of ITLB Entries

AC40 X X X NoFix

AC41 X Fixed

AC42 X X NoFix

AC43 X Fixed

AC44 X X Fixed

X X X NoFix

Multiple accesses to the same S-state L2 cache line and ECC
error combination may result in loss of cache coherency

When the processor is in the System Management Mode
(SMM), debug registers may be fully writeable

Associated counting logic must be configured when using
Event Selection Control (ESCR) MSR

IA32_MC0_ADDR and IA32_MC0_MISC registers will contain
invalid or stale data following a Data, Address, or Response
Parity Error

CR2 may be incorrect or an incorrect page fault error code
may be pushed onto stack after execution of an LSS
instruction

System may hang if a fatal cache error causes Bus Write Line
(BWL) transaction to occur to the same cache line address as
an outstanding Bus Read Line (BRL) or Bus Read-Invalidate
Line (BRIL)

Processor Does not Flag #GP on Non-zero Write to Certain
MSRs

Simultaneous assertion of A20M# and INIT# may result in
incorrect data fetch

Glitches on Address and Data Strobe Signals May Cause
System Shutdown

A Write to an APIC Register Sometimes May Appear to Have
Not Occurred

Store to Load Data Forwarding may Result in Switched Data
Bytes

Parity Error in the L1 Cache may Cause the Processor to
Hang

The TCK Input in the Test Access Port (TAP) is Sensitive to
Low Clock Edge Rates and Prone to Noise Coupling Onto
TCK's Rising or Falling Edges

Re-mapping the APIC base address to a value less than or
equal to 0xDC001000 may cause IO and Special Cycle failure

AC45 X X Fixed Erroneous BIST result found in EAX register after reset

AC46 X X X NoFix

AC47 X X X NoFix

AC48 X X X NoFix

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Intel

Celeron® Processor in the 478-Pin Package Specification Update 11

The State of the Resume Flag (RF Flag) in a Task-State
Segment (TSS) May be Incorrect

Changes to CR3 Register do not Fence Pending Instruction
Page Walks

Processor Provides a 4-Byte Store Unlock After an 8-Byte
Load Lock

Summary Tables of Changes

NO. E0 nC1 nD1 Plans ERRATA

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AC49 X X X NoFix

AC50 X X X NoFix

AC51 X X X NoFix

AC52 X X NoFix

AC53 X X PlanFix

AC54 X X NoFix

AC55 X X X NoFix xAPIC May Not Report Some Illegal Vector Errors

AC56 X PlanFix

AC57 X X X NoFix

AC58 X X NoFix

AC59 X X X No Fix

AC60 X X No Fix

AC61 X PlanFix

AC62 X X X NoFix

AC63 X X X PlanFix

AC64 X X X NoFix

AC65 X X X NoFix

AC66 X X X NoFix

AC67 X X X NoFix

AC68 X X X NoFix

System Bus Interrupt Messages Without Data Which Receive
a HardFailure Response May Hang the Processor

Memory Type of the Load Lock Different from its
Corresponding Store Unlock

A 16-bit Address Wrap Resulting from a Near Branch (Jump or
Call) May Cause an Incorrect Address to Be Reported to the
#GP Exception Handler

ITP Cannot Continue Single Step Execution after the First
Breakpoint

PWRGOOD and TAP Signals Maximum Input Hysteresis
Higher Than Specified

Incorrect Debug Exception (#DB) May Occur When a Data
Breakpoint is set on an FP Instruction

A Timing Marginality in the Instruction Decoder Unit May
Cause an Unpredictable Application Behavior and/or System
Hang

Memory Aliasing of Pages as Uncacheable Memory Type and
Write Back (WB) May Hang the System

Using STPCLK and Executing Code From Very Slow Memory
Could Lead to a System Hang

Machine Check Exceptions May not Update Last-Exception
Record MSRs (LERs)

Stores to Page Tables May Not Be Visible to Pagewalks for
Subsequent Loads Without Serializing or Invalidating the Page
Table Entry

A Timing Marginality in the Arithmetic Logic Unit (ALU) May
Cause Indeterminate Behavior

With TF (Trap Flag) Asserted, FP Instruction That Triggers an
Unmasked FP Exception May Take Single Step Trap Before
Retirement of Instruction

BTS(Branch Trace Store) and PEBS(Precise Event Based
Sampling) May Update Memory outside the BTS/PEBS Buffer

Memory Ordering Failure May Occur with Snoop Filtering
Third Party Agents after Issuing and Completing a BWIL (Bus
Write Invalidate Line) or BLW (Bus Locked Write) Transaction

Control Register 2 (CR2) Can be Updated during a REP
MOVS/STOS Instruction with Fast Strings Enabled

Writing the Local Vector Table (LVT) when an Interrupt is
Pending May Cause an Unexpected Interrupt

Using 2M/4M Pages When A20M# Is Asserted May Result in
Incorrect Address Translations

Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a
Memory Ordering Issue

12 Intel

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Celeron® Processor in the 478-Pin Package Specification Update

Summary Tables of Changes

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NO. E0 nC1 nD1 Plans ERRATA

AC69 X X X NoFix

Debug Status Register (DR6) Breakpoint Condition Detected
Flags May be set Incorrectly

NO. E0 nC1 nD1 SPECIFICATION CHANGES

No update for this Month

NO. E0 nC1 nD1 SPECIFICATION CLARIFICATIONS

No Update for this month.

NO. E0 nC1 nD1 DOCUMENTATION CHANGES

Refer to Documentation Changes section

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Intel

Celeron® Processor in the 478-Pin Package Specification Update 13

General Information

©

©

f

f

General Information

This section contains top marking information for the Intel® Celeron® processor in the 478-pn
package.

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Figure 1. Example Markings for the Intel

in the 478-Pin Package

Celeron® Processor on 0.13 Micron Process and/or

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S-

Spec/Country o

Spec/Country o

FPO

FPO

2-

D Matrix Mark

D Matrix Mark

m

‘03

i
Celeron®

S-

Assy

Assy

-

-

2-

2A GHZ/512/400/1.50V

2 GHZ/128/400

SYYYY XXXXXX

SYYYY XXXXXX

FFFFFFFF-NNNN

FFFFFFFF

i

-

m

‘01
ATPO LOT N
NNNN

Frequency/Cache/Bus

Frequency/Cache/Bus

§

14 Intel

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Celeron® Processor in the 478-Pin Package Specification Update

Component Identification Information

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Component Identification Information

The Intel® Celeron® processor in the 478-pn package processor may be identified by the
following values.

Family1 Model2 Brand3

1111b 0001b 00001010b
1111b 0010b 00001010b

NOTES:

1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register
after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the
Device ID register accessible through Boundary Scan.

2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after
the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID
register accessible through Boundary Scan.

3. The Brand ID corresponds to bits [7:0] of the EBX register after the CPUID instruction is executed with a
1 in the EAX register.

®

Table 1. Intel
Identification Information

S-Spec

SL69Z E0 128K 0F13h 1.70 GHz/

SL68C E0 128K 0F13h 1.70 GHz/

SL6A2 E0 128K 0F13h 1.80 GHz/

SL68D E0 128K 0F13h 1.80 GHz/

SL6SW C1 128K 0F27h 2 GHz/

SL6LC C1 128K 0F27h 2 GHz/

SL6HY C1 128K 0F27h 2 GHz/

Celeron® Processor in the 478-Pin Package Processor

Core

Stepping

L2 Cache

Size

(bytes)

Processor

Signature Speed Core/Bus

400 MHz

400 MHz

400 MHz

400 MHz

400 MHz

400 MHz

400 MHz

Package and

Revision Notes

FC-PGA2

35.0 mm, Rev
02

FC-PGA2

35.0 mm, Rev
02

FC-PGA2

35.0 mm, Rev
02

FC-PGA2

35.0 mm, Rev
02

FC-PGA2

31.0 mm , rev

1.0

FC-PGA2

31.0 mm , rev

1.0

FC-PGA2

31.0 mm , rev

1.0

2, 4, 8

1, 2

1

2, 3

3

2, 4

4

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Intel

Celeron® Processor in the 478-Pin Package Specification Update 15