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Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

Specification Update

December 2013

Revision 007

Reference Number: 328899-007

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

A “Mission Critical Application” is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800- 548-4725, or go to: http://www.intel.com/design/literature.htm.

Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user.

Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM). Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all operating systems. Consult your PC manufacturer. For more information, visit: http://www.intel.com/go/virtualization.

Intel® Turbo Boost Technology requires a system with Intel® Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology 2.0 are only available on select Intel® processors. Consult your PC manufacturer. Performance varies depending on hardware, software, and system configuration. For more information, visit: http://www.intel.com/go/turbo.

Intel® Hyper-Threading Technology requires an Intel® HT Technology enabled system, check with your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on Intel® Core™ i5-750. For more information including details on which processors support HT Technology, visit http://www.intel.com/info/hyperthreading.

Intel® 64 architecture requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary depending on the specific hardware and software you use. Consult your PC manufacturer for more information. For more information, visit: http://www.intel.com/info/em64t.

Intel, Intel Core, Intel386, Intel486, Pentium, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others.

Copyright © 2013, Intel Corporation. All rights reserved.

2

Specification Update

 

 

Contents

 

Contents

 

Revision History...............................................................................................................

5

Preface ..............................................................................................................................

6

Summary Tables of Changes..........................................................................................

8

Identification Information ..............................................................................................

14

Errata...............................................................................................................................

17

Specification Changes...................................................................................................

47

Specification Clarifications ...........................................................................................

48

Documentation Changes...............................................................................................

49

§ §

Specification Update

3

Contents

4

Specification Update

Revision History

Revision

 

Description

Date

 

 

 

 

001

Initial Release.

June 2013

 

 

 

002

• No Updates. Revision number added to Revision History to maintain

N/A

 

consistency with NDA Specification Update numbering.

 

 

 

 

 

 

 

 

Errata

 

003

 

— Added HSD59-99

August 2013

 

Updated Identification Information

 

 

 

 

004

• No Updates. Revision number added to Revision History to maintain

N/A

 

consistency with NDA Specification Update numbering.

 

 

 

 

 

 

 

 

Errata

 

005

 

— Moved previous HSD99 to HSD108

November 2013

 

— Added HSD99-107 and HSD109-115

 

 

 

 

Updated Identification Information

 

 

 

 

 

006

Identification Information

December 2013

 

— Updated Desktop Processor Identification table

 

 

 

 

 

 

 

007

Errata

December 2013

 

— Added HSD116-118

 

 

 

 

 

 

 

Specification Update

5

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents

Document Title

Document Number

 

 

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family,

328897

and Desktop Intel® Celeron® Processor Family Datasheet – Volume 1 of 2

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family,

328898

and Desktop Intel® Celeron® Processor Family Datasheet – Volume 2 of 2

Related Documents

Document Title

Document Number/

Location

 

 

 

AP-485, Intel® Processor Identification and the CPUID Instruction

http://www.intel.com/

design/processor/

 

applnots/241618.htm

 

 

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture

 

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set

 

Reference Manual A-M

 

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: Instruction Set

http://www.intel.com/

Reference Manual N-Z

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming

products/processor/

manuals/index.htm

Guide

 

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B: System Programming

 

Guide

 

Intel® 64 and IA-32 Intel Architecture Optimization Reference Manual

 

Intel® 64 and IA-32 Architectures Software Developer’s Manual Documentation Changes

http://www.intel.com/

design/processor/

 

specupdt/252046.htm

 

 

ACPI Specifications

www.acpi.info

 

 

6

Specification Update

Nomenclature

Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so on).

Specification Update

7

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations.

Codes Used in Summary Tables

Stepping

X:

Errata exists in the stepping indicated. Specification Change or

 

Clarification that applies to this stepping.

(No mark)

 

or (Blank box):

This erratum is fixed in listed stepping or specification change

 

does not apply to listed stepping.

Page

(Page): Page location of item in this document.

Status

Doc:

Document change or update will be implemented.

Plan Fix:

This erratum may be fixed in a future stepping of the product.

Fixed:

This erratum has been previously fixed.

No Fix:

There are no plans to fix this erratum.

Row

 

Change bar to left of a table row indicates this erratum is either new or modified from the previous version of the document.

8

Specification Update

Errata (Sheet 1 of 5)

Number

Steppings

Status

ERRATA

 

C-0

 

 

 

 

 

 

 

HSD1

X

No Fix

LBR, BTS, BTM May Report a Wrong Address when an Exception/

Interrupt Occurs in 64-bit Mode

 

 

 

 

 

 

 

HSD2

X

No Fix

EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after

a Translation Change

 

 

 

 

 

 

 

HSD3

X

No Fix

MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a

DTLB Error

 

 

 

 

 

 

 

HSD4

X

No Fix

LER MSRs May Be Unreliable

 

 

 

 

HSD5

X

No Fix

MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in

Hang

 

 

 

 

 

 

 

HSD6

X

No Fix

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also

Result in a System Hang

 

 

 

 

 

 

 

HSD7

X

No Fix

#GP on Segment Selector Descriptor that Straddles Canonical Boundary

May Not Provide Correct Exception Error Code

 

 

 

 

 

 

 

HSD8

X

No Fix

FREEZE_WHILE_SMM Does Not Prevent Event From Pending

PEBS During SMM

 

 

 

 

 

 

 

HSD9

X

No Fix

APIC Error “Received Illegal Vector” May be Lost

 

 

 

 

HSD10

X

No Fix

Changing the Memory Type for an In-Use Page Translation May Lead to

Memory-Ordering Violations

 

 

 

 

 

 

 

HSD11

X

No Fix

Performance Monitor Precise Instruction Retired Event May Present

Wrong Indications

 

 

 

 

 

 

 

HSD12

X

No Fix

CR0.CD Is Ignored in VMX Operation

 

 

 

 

HSD13

X

No Fix

Instruction Fetch May Cause Machine Check if Page Size and Memory

Type Was Changed Without Invalidation

 

 

 

 

 

 

 

HSD14

X

No Fix

Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value

for VEX.vvvv May Produce a #NM Exception

 

 

 

 

 

 

 

HSD15

X

No Fix

Processor May Fail to Acknowledge a TLP Request

 

 

 

 

HSD16

X

No Fix

Interrupt From Local APIC Timer May Not Be Detectable While Being

Delivered

 

 

 

 

 

 

 

HSD17

X

No Fix

PCIe* Root-port Initiated Compliance State Transmitter Equalization

Settings May be Incorrect

 

 

 

 

 

 

 

HSD18

X

No Fix

PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s

 

 

 

 

HSD19

X

No Fix

Unused PCIe* Lanes May Report Correctable Errors

 

 

 

 

HSD20

X

No Fix

Accessing Physical Memory Space 0-640K through the Graphics

Aperture May Cause Unpredictable System Behavior

 

 

 

 

 

 

 

HSD21

X

No Fix

PCIe Root Port May Not Initiate Link Speed Change

 

 

 

 

HSD22

X

No Fix

Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than

Expected

 

 

 

 

 

 

 

HSD23

X

No Fix

DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP

SS is Followed by a Store or an MMX Instruction

 

 

 

 

 

 

 

HSD24

X

No Fix

VEX.L is Not Ignored with VCVT*2SI Instructions

 

 

 

 

HSD25

X

No Fix

Certain Local Memory Read / Load Retired PerfMon Events May

Undercount

 

 

 

 

 

 

 

Specification Update

9

Errata (Sheet 2 of 5)

Number

Steppings

Status

ERRATA

 

C-0

 

 

 

 

 

 

 

HSD26

X

No Fix

Specific Graphics Blitter Instructions May Result in Unpredictable

Graphics Controller Behavior

 

 

 

 

 

 

 

HSD27

X

No Fix

Processor May Enter Shutdown Unexpectedly on a Second

Uncorrectable Error

 

 

 

 

 

 

 

HSD28

X

No Fix

Modified Compliance Patterns for 2.5 GT/s and 5 GT/s Transfer Rates Do

Not Follow PCIe* Specification

 

 

 

 

 

 

 

HSD29

X

No Fix

Performance Monitor Counters May Produce Incorrect Results

 

 

 

 

HSD30

X

No Fix

Performance Monitor UOPS_EXECUTED Event May Undercount

 

 

 

 

HSD31

X

No Fix

MSR_PERF_STATUS May Report an Incorrect Core Voltage

 

 

 

 

HSD32

X

No Fix

PCIe* Atomic Transactions From Two or More PCIe Controllers May

Cause Starvation

 

 

 

 

 

 

 

HSD33

X

No Fix

The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not

Updated After a UC Error is Logged

 

 

 

 

 

 

 

HSD34

X

No Fix

An AVX Gather Instruction That Causes an EPT Violation May Not

Update Previous Elements

 

 

 

 

 

 

 

HSD35

X

No Fix

PLATFORM_POWER_LIMIT MSR Not Visible

 

 

 

 

HSD36

X

No Fix

LPDDR Memory May Report Incorrect Temperature

 

 

 

 

HSD37

X

No Fix

PCIe* Host Bridge DID May Be Incorrect

 

 

 

 

HSD38

X

No Fix

TSC May be Incorrect After a Deep C-State Exit

 

 

 

 

HSD39

X

No Fix

PCIe* Controller May Initiate Speed Change While in DL_Init State

Causing Certain PCIe Devices to Fail to Train

 

 

 

 

 

 

 

HSD40

X

No Fix

Spurious VT-d Interrupts May Occur When the PFO Bit is Set

 

 

 

 

HSD41

X

No Fix

N/A. Erratum has been removed.

 

 

 

 

HSD42

X

No Fix

AVX Gather Instruction That Causes a Fault or VM Exit May Incorrectly

Modify Its Destination Register

 

 

 

 

 

 

 

HSD43

X

No Fix

Inconsistent NaN Propagation May Occur When Executing (V)DPPS

Instruction

 

 

 

 

 

 

 

HSD44

X

No Fix

Display May Flicker When Package C-States Are Enabled

 

 

 

 

HSD45

X

No Fix

Certain Combinations of AVX Instructions May Cause Unpredictable

System Behavior

 

 

 

 

 

 

 

HSD46

X

No Fix

Processor May Incorrectly Estimate Peak Power Delivery Requirements

 

 

 

 

HSD47

X

No Fix

IA32_PERF_CTL MSR is Incorrectly Reset

 

 

 

 

HSD48

X

No Fix

Processor May Hang During a Function Level Reset of the Display

 

 

 

 

HSD49

X

No Fix

AVX Gather Instruction That Should Result in #DF May Cause

Unexpected System Behavior

 

 

 

 

 

 

 

HSD50

X

No Fix

Throttling and Refresh Rate Maybe be Incorrect After Exiting Package C-

State

 

 

 

 

 

 

 

HSD51

X

No Fix

Processor May Livelock During On Demand Clock Modulation

 

 

 

 

HSD52

X

No Fix

IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI is Incorrectly Cleared

by SMI

 

 

 

 

 

 

 

HSD53

X

No Fix

The From-IP for Branch Tracing May be Incorrect

 

 

 

 

HSD54

X

No Fix

TM1 Throttling May Continue indefinitely

 

 

 

 

10

Specification Update

Errata (Sheet 3 of 5)

Number

Steppings

Status

ERRATA

 

C-0

 

 

 

 

 

 

 

HSD55

X

No Fix

Internal Parity Errors May Incorrectly Report Overflow in The

IA32_MCi_STATUS MSR

 

 

 

 

 

 

 

HSD56

X

No Fix

Performance Monitor Events OTHER_ASSISTS.AVX_TO_SSE And

OTHER_ASSISTS.SSE_TO_AVX May Over Count

 

 

 

 

 

 

 

HSD57

X

No Fix

Processor May Run at Incorrect P-State

 

 

 

 

HSD58

X

No Fix

Performance Monitor Event DSB2MITE_SWITCHES.COUNT May Over

Count

 

 

 

 

 

 

 

HSD59

X

No Fix

Performance Monitor Register UNC_PERF_GLOBAL_STATUS Not

Restored on Package C7 Exit

 

 

 

 

 

 

 

HSD60

X

No Fix

Processor May Not Enter Package C6 or Deeper C-states When PCIe*

Links Are Disabled

 

 

 

 

 

 

 

HSD61

X

No Fix

Performance Monitor Event For Outstanding Offcore Requests And

Snoop Requests May Over Count

 

 

 

 

 

 

 

HSD62

X

No Fix

Some Performance Monitor Event Counts May be Inaccurate During SMT

Mode

 

 

 

 

 

 

 

HSD63

X

No Fix

Timed MWAIT May Use Deadline of a Previous Execution

 

 

 

 

HSD64

X

No Fix

The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging

 

 

 

 

HSD65

X

No Fix

Performance Monitor Events HLE_RETIRED.ABORTED_MISC4 And

RTM_RETIRED.ABORTED_MISC4 May Over Count

 

 

 

 

 

 

 

HSD66

X

No Fix

A PCIe* LTR Update Message May Cause The Processor to Hang

 

 

 

 

HSD67

X

No Fix

GETSEC Does Not Report Support For S-CRTM

 

 

 

 

HSD68

X

No Fix

EPT Violations May Report Bits 11:0 of Guest Linear Address Incorrectly

 

 

 

 

HSD69

X

No Fix

APIC Timer Might Not Signal an Interrupt While in TSC-Deadline Mode

 

 

 

 

HSD70

X

No Fix

IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The

Highest Index Value Used For VMCS Encoding

 

 

 

 

 

 

 

HSD71

X

No Fix

Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be

Observed

 

 

 

 

 

 

 

HSD72

X

No Fix

VT-d Hardware May Perform STRP And SIRTP Operations on a Package

C7 Exit

 

 

 

 

 

 

 

HSD73

X

No Fix

General-Purpose Performance Counters Can Unexpectedly Increment

 

 

 

 

HSD74

X

No Fix

Performance Monitoring Events May Report Incorrect Number of Load

Hits or Misses to LLC

 

 

 

 

 

 

 

HSD75

X

No Fix

Performance Monitoring Event INSTR_RETIRED.ALL May Generate

Redundant PEBS Records For an Overflow

 

 

 

 

 

 

 

HSD76

X

No Fix

Locked Load Performance Monitoring Events May Under Count

 

 

 

 

HSD77

X

No Fix

Graphics Processor Ratio And C-State Transitions May Cause a System

Hang

 

 

 

 

 

 

 

HSD78

X

No Fix

Certain Performance Monitoring Events May Over Count Software

Demand Loads

 

 

 

 

 

 

 

HSD79

X

No Fix

Accessing Nonexistent Uncore Performance Monitoring MSRs May Not

Signal a #GP

 

 

 

 

 

 

 

HSD80

X

No Fix

Call Stack Profiling May Produce Extra Call Records

 

 

 

 

HSD81

X

No Fix

Warm Reset May Fail or Lead to Incorrect Power Regulation

 

 

 

 

Specification Update

11

Errata (Sheet 4 of 5)

Number

Steppings

Status

ERRATA

 

C-0

 

 

 

 

 

 

 

HSD82

X

No Fix

PCIe* Host Bridge DID May Be Incorrect

 

 

 

 

HSD83

X

No Fix

Transactional Abort May Produce an Incorrect Branch Record

 

 

 

 

HSD84

X

No Fix

SMRAM State-Save Area Above the 4GB Boundary May Cause

Unpredictable System Behavior

 

 

 

 

 

 

 

HSD85

X

No Fix

DMA Remapping Faults for the Graphics VT-d Unit May Not Properly

Report Type of Faulted Request

 

 

 

 

 

 

 

HSD86

X

No Fix

AVX Gather Instructions Page Faults May Report an Incorrect Faulting

Address

 

 

 

 

 

 

 

HSD87

X

No Fix

Intel® TSX Instructions May Cause Unpredictable System behavior

 

 

 

 

HSD88

X

No Fix

Event Injection by VM Entry May Use an Incorrect B Flag for SS

 

 

 

 

HSD89

X

No Fix

A Fault in SMM May Result in Unpredictable System Behavior

 

 

 

 

HSD90

X

No Fix

Processor Frequency is Unexpectedly Limited Below Nominal P1 When

cTDP Down is Enabled

 

 

 

 

 

 

 

HSD91

X

No Fix

PMI May be Signaled More Than Once For Performance Monitor Counter

Overflow

 

 

 

 

 

 

 

HSD92

X

No Fix

Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a

#NM Exception

 

 

 

 

 

 

 

HSD93

X

No Fix

RDRAND Execution in a Transactional Region May Cause a System

Hang

 

 

 

 

 

 

 

HSD94

X

No Fix

Uncore Clock Frequency Changes May Cause Audio/Video Glitches

 

 

 

 

HSD95

X

No Fix

Processor May Experience a Spurious LLC-Related Machine Check

During Periods of High Activity

 

 

 

 

 

 

 

HSD96

X

No Fix

The Processor May Not Enter Package C7 When Using a PSR Display

 

 

 

 

HSD97

X

No Fix

Video/Audio Distortion May Occur

 

 

 

 

HSD98

X

No Fix

System May Hang When Audio is Enabled During Package C3

 

 

 

 

HSD99

X

No Fix

INVPCID May Not Cause #UD in VMX Non-Root Operation

 

 

 

 

HSD100

X

No Fix

Non-Compliant PFAT Module Base Address May Cause Unpredictable

System Behavior

 

 

 

 

 

 

 

HSD101

X

No Fix

Incorrect LBR Source Address May be Reported For a Transactional

Abort

 

 

 

 

 

 

 

HSD102

X

No Fix

Address Translation Faults for Intel® VT-d May Not be Reported for

Display Engine Memory Accesses

 

 

 

 

 

 

 

HSD103

X

No Fix

L3 Cache Corrected Error Count May be Inaccurate After Package C7

Exit

 

 

 

 

 

 

 

HSD104

X

No Fix

PCIe* Device’s SVID is Not Preserved Across The Package C7 C-State

 

 

 

 

HSD105

X

No Fix

Warm Reset Does Not Stop GT Power Draw

 

 

 

 

HSD106

X

No Fix

Unused PCIe* Lanes May Remain Powered After Package C7

 

 

 

 

HSD107

X

No Fix

BMI1 And BMI2 Instruction Groups Are Not Available

 

 

 

 

HSD108

X

No Fix

Virtual-APIC Page Accesses With 32-Bit PAE Paging May Cause a

System Crash

 

 

 

 

 

 

 

HSD109

X

No Fix

Processor Energy Policy Selection May Not Work as Expected

 

 

 

 

12

Specification Update

Errata (Sheet 5 of 5)

 

Steppings

 

Number

 

Status

ERRATA

 

 

C-0

 

HSD110

X

No Fix

A PEBS Record May Contain Processor State for an Unexpected

Instruction

 

 

 

 

 

 

 

HSD111

X

No Fix

MSR_PP1_ENERGY_STATUS Reports Incorrect Energy Data

 

 

 

 

HSD112

X

No Fix

x87 FPU DP May be Incorrect After Instructions That Save FP State to

Memory

 

 

 

 

 

 

 

HSD113

X

No Fix

Processor May Hang During Package C7 Exit

 

 

 

 

HSD114

X

No Fix

Intel® TSX Instructions May Cause Unpredictable System behavior

 

 

 

 

HSD115

X

No Fix

Spurious LLC Machine Check May Occur

 

 

 

 

HSD116

X

No Fix

Page Fault May Report Incorrect Fault Information

 

 

 

 

HSD117

X

No Fix

CATERR# Pin Assertion is Not Cleared on a Warm Reset

 

 

 

 

HSD118

X

No Fix

Uncorrectable Machine Check Error During Core C6 Entry May Not be

Signaled

 

 

 

Specification Changes

Number

SPECIFICATION CHANGES

None for this revision of this specification update.

Specification Clarifications

Number

SPECIFICATION CLARIFICATIONS

None for this revision of this specification update.

Documentation Changes

Number

DOCUMENTATION CHANGES

HSD1 ”On-Demand Clock Modulation Feature Clarification”

Specification Update

13

Identification Information

Component Identification using Programming Interface

The processor stepping can be identified by the following register contents.

Table 1. Desktop 4th Generation Intel® Core™ Processor Family Component Identification

Reserved

Extended

Extended

Reserved

Processor

Family

Model

Stepping

Family

Model

Type

Code

Number

ID

 

 

 

 

 

 

 

 

 

 

31:28

27:20

19:16

15:14

13:12

11:8

7:4

3:0

 

 

 

 

 

 

 

 

 

00000000b

0011b

 

00b

0110b

1100b

xxxxb

 

 

 

 

 

 

 

 

Notes:

1.The Extended Family, Bits [27:20] are used in conjunction with the Family Code, specified in Bits[11:8], to indicate whether the processor belongs to the Intel386™, Intel486™, Pentium®, Pentium 4, or Intel® Core™ processor family.

2.The Extended Model, Bits [19:16] in conjunction with the Model Number, specified in Bits [7:4], are used to identify the model of the processor within the processor’s family.

3.The Family Code corresponds to Bits [11:8] of the EDX register after RESET, Bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.

4.The Model Number corresponds to Bits [7:4] of the EDX register after RESET, Bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.

5.The Stepping ID in Bits [3:0] indicates the revision number of that model. See the processor Identification table for the processor stepping ID number in the CPUID information.

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

The processor can be identified by the following register contents.

Stepping

Vendor ID

1

Host Device

Processor Graphics

Revision ID

4

CRID

 

ID2

Device ID3

 

 

 

 

 

 

 

 

 

C-0

8086h

 

0C04h

GT2 = 0416h

06h

 

06h

 

 

 

 

 

 

 

 

Notes:

1.The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00h–01h in the PCI function 0 configuration space.

2.The Host Device ID corresponds to bits 15:0 of the Device ID Register located at Device 0 offset 02h– 03h in the PCI function 0 configuration space.

3.The Processor Graphics Device ID (DID2) corresponds to bits 15:0 of the Device ID Register located at Device 2 offset 02h–03h in the PCI function 0 configuration space.

4.The Revision Number corresponds to bits 7:0 of the Revision ID Register located at offset 08h in the PCI function 0 configuration space.

14

Specification Update

Component Marking Information

The processor stepping can be identified by the following component markings.

Figure 1. Desktop 4th Generation Intel® Core™ Processor Family Top-Side Markings

Table 2.

Desktop Processor Identification (Sheet 1 of 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cache

Func-

Integrated

Max

 

 

Thermal

S-Spec

Processor

 

Turbo

Memory

Core

 

Design

Stepping

Size

tional

Graphics

Freq.

Freq.

Number

Number

(MHz)

Power

 

(MB)

Core

Cores

Rate

(GHz)

 

 

 

 

(W)

 

 

 

 

 

 

(GHz)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SR147

I7-4770K

C-0

8

4

2

3.9

1600

3.5

95

 

 

 

 

 

 

 

 

 

 

SR149

I7-4770

C-0

8

4

2

3.9

1600

3.4

95

 

 

 

 

 

 

 

 

 

 

SR14A

I5-4670K

C-0

6

4

2

3.8

1600

3.4

95

 

 

 

 

 

 

 

 

 

 

SR14D

I5-4670

C-0

6

4

2

3.8

1600

3.4

95

 

 

 

 

 

 

 

 

 

 

SR14E

I5-4570

C-0

6

4

2

3.6

1600

3.2

95

 

 

 

 

 

 

 

 

 

 

SR14F

I5-4440

C-0

6

4

2

3.3

1600

3.1

95

 

 

 

 

 

 

 

 

 

 

SR14G

I5-4430

C-0

6

4

2

3.2

1600

3

95

 

 

 

 

 

 

 

 

 

 

SR14H

I7-4770S

C-0

8

4

2

3.9

1600

3.1

65

 

 

 

 

 

 

 

 

 

 

SR14J

I5-4570S

C-0

6

4

2

3.6

1600

2.9

65

 

 

 

 

 

 

 

 

 

 

SR14K

I5-4670S

C-0

6

4

2

3.8

1600

3.1

65

 

 

 

 

 

 

 

 

 

 

SR14L

I5-4440S

C-0

6

4

2

3.3

1600

2.8

65

 

 

 

 

 

 

 

 

 

 

SR14M

I5-4430S

C-0

6

4

2

3.2

1600

2.7

65

 

 

 

 

 

 

 

 

 

 

SR14N

I7-4770T

C-0

8

4

2

3.7

1600

2.5

45

 

 

 

 

 

 

 

 

 

 

SR14P

I5-4670T

C-0

6

4

2

3.3

1600

2.3

45

 

 

 

 

 

 

 

 

 

 

SR14Q

I7-4765T

C-0

8

4

2

3

1600

2

35

 

 

 

 

 

 

 

 

 

 

Specification Update

15

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